NCL30488A3_技术文档

Power Factor Corrected

LED Driver with Primary

Side CC/CV

NCL30488

The NCL30488 is a power factor corrected flyback controller

targeting isolated constant current LED drivers. The controller

operates in a quasi−resonant mode to provide high efficiency. Thanks

to a novel control method, the device is able to tightly regulate a

constant LED current from the primary side. This removes the need

for secondary side feedback circuitry, its biasing and for an

optocoupler.

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SOIC−7

The device is highly integrated with a minimum number of external

components. A robust suite of safety protection is built in to simplify

the design.

CASE 751U

MARKING

DIAGRAM

Features

8

• High Voltage Startup

L30488XX

ALYWX

G

• Quasi−resonant Peak Current−mode Control Operation

• Primary Side Feedback

• CC / CV Accurate Control V up to 320 V rms

in

• Tight LED Constant Current Regulation of 2% Typical

• Digital Power Factor Correction

1

L30488

XX

A

= Specific Device Code

= Version

= Assembly Location

= Wafer Lot

= Assembly Start Week

= Pb−Free Package

• Analog and Digital Dimming

• Cycle by Cycle Peak Current Limit

L

• Wide Operating V Range

CC

YW

G

• −40 to + 125°C

• Robust Protection Features

PIN CONNECTIONS

♦ Brown−Out

♦ OVP on V

CC

♦ Constant Voltage / LED Open Circuit Protection

♦ Winding Short Circuit Protection

♦ Secondary Diode Short Protection

♦ Output Short Circuit Protection

♦ Thermal Shutdown

COMP

ZCD

CS

HV

1

8

2

VCC

DRV

3

4

6

♦ Line over Voltage Protection

• This is a Pb−Free Device

5

GND

Typical Applications

• Integral LED Bulbs

• LED Power Driver Supplies

• LED Light Engines

ORDERING INFORMATION

See detailed ordering and shipping information on page 21 of

this data sheet.

1

Publication Order Number:

August, 2020 − Rev. 0

NCL30488/D

NCL30488

.

NCL30488

1

2

3

4

7

6

5

Figure 1. Typical Application Schematic for NCL30488

PIN FUNCTION DESCRIPTION NCL30488

Pin N5

1

Pin Name

Function

Pin Description

COMP

OTA output for CV loop

This pin receives a compensation network (capacitors and resistors) to stabilize the

CV loop

2

ZCD

Zero crossing Detection

This pin connects to the auxiliary winding and is used to detect the core reset event.

This pin also senses the auxiliary winding voltage for accurate output voltage control.

V

sensing

aux

3

4

5

6

7

8

CS

GND

DRV

VCC

NC

Current sense

−

This pin monitors the primary peak current.

The controller ground

Driver output

The driver’s output to an external MOSFET

This pin is connected to an external auxiliary voltage.

Supplies the controller

creepage

HV

High Voltage sensing

This pin connects after the diode bridge to provide the startup current and internal

high voltage sensing function.

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2

NCL30488

INTERNAL CIRCUIT ARCHITECTURE

STOP

VCC

L_OVP

Aux_SCP

UVLO

Fault

Management

COMP

VCC Management

OFF

Fast_OVP

Standby

V_CV

Thermal

Shutdown

VCC

OVP

HV

Startup

VCC_OVP

Constant Voltage

Control

CS_short

Slow_OVP

Fast_OVP

Slow_OVP

V_REFXV_VS

HV

BO_NOK

L_OVP

V_HVdiv

Brown−out

Line OVP

Zero crossing detection Logic

(ZCD blanking, Time−Out, …)

ZCD

Valley Selection

Frequency foldback

Aux . Winding Short Circuit Prot.

Aux_SCP

Q_drv

V_HVdiv

Line

feed−forward

S

R

Q

V_HVdiv

Standby

DRV

Driver

and

Clamp

CS

V_REFX

CS_reset

Leading

Edge

Blanking

Power factor and

Constant−current control

STOP

Ipk_max

Maximum

on−time

Max. Peak

Current Limit

STOP

Winding /

Output diode

SCP

WOD_SCP

CS Short

Protection

CS_short

GND

Figure 2. Internal Circuit Architecture NCL30488

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3

NCL30488

MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

V

Maximum Power Supply voltage, VCC pin, continuous voltage

Maximum current for VCC pin

−0.3 to 30

Internally limited

V

mA

CC(MAX)

I

V

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3, V

(Note 1)

V

mA

DRV(MAX)

DRV

I

−300, +500

V

Maximum voltage on HV pin

Maximum current for HV pin (dc current self−limited if operated within the allowed range)

−0.3, +700

V

mA

HV(MAX)

I

20

V

Maximum voltage on low power pins (except pins DRV and VCC)

Current range for low power pins (except pins DRV and VCC)

−0.3, 5.5 (Note 2)

−2, +5

V

mA

MAX

I

R

Thermal Resistance Junction−to−Air

Maximum Junction Temperature

200

°C/W

°C

θ

J−A

T

150

J(MAX)

Operating Temperature Range

−40 to +125

°C

Storage Temperature Range

−60 to +150

°C

ESD Capability, HBM model except HV pin (Note 3)

ESD Capability, HBM model HV pin

ESD Capability, CDM model (Note 3)

4

1.5

1

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. V

is the DRV clamp voltage V

when V is higher than V

. V

is V otherwise.

DRV

DRV(high)

CC

DRV(high) DRV CC

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages

can be applied if the pin current stays within the −2 mA / 5 mA range.

3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.

Charged Device Model 1000 V per JEDEC Standard JESD22−C101D.

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

HIGH VOLTAGE SECTION

High voltage current source

V

= V

– 200 mV

I

3.9

−

5.1

300

0.8

15

6.2

−

mA

CC

CC(on)

HV(start2)

I

HV(start1)

= 0 V

CC

V

CC

level for I

to I

transition

V

CC(TH)

−

V

HV(start1)

HV(start2)

Minimum startup voltage

HV source leakage current

V

= 0 V

V

−

V

CC

HV(MIN)

HV(leak)

= 450 V

I

−

4.5

−

10

−

mA

HV

Maximum input voltage (rms) for correct operation of

the PFC loop

V

320

V rms

HV(OL)

SUPPLY SECTION

Supply Voltage

V

Startup Threshold

V

CC

V

CC

V

CC

increasing

decreasing

V

16

9.3

7.6

4

18

20

10.7

−

CC(on)

CC(off)

Minimum Operating Voltage

10.2

−

Hysteresis V

– V

V

CC(on)

CC(off)

CC(HYS)

CC(reset)

Internal logic reset

V

5

6

Over Voltage Protection

VCC OVP threshold

V

25

26.5

28

V

CC(OVP)

V

noise filter (Note 5)

CC(reset)

t

−

5

20

−

ms

CC(off)

VCC(off)

noise filter (Note 5)

t

VCC(reset)

Supply Current

mA

Device Disabled/Fault

V

> V

I

1.2

–

1.35

3.0

3.5

1.7

1.6

3.5

CC

sw

CC(off)

CC1

CC2

CC3

CC4

Device Enabled/No output load on pin 5

F

= 65 kHz

Device Switching (F = 65 kHz)

C

= 470 pF, F = 65 kHz

−

4.0

sw

DRV

sw

Device switching (F = 700 Hz)

V

COMP

v 0.9 V

−

1.88

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NCL30488

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

CURRENT SENSE

Maximum Internal current limit

V

1.33

283

−

1.40

345

100

1.47

407

150

V

ILIM

LEB

ILIM

Leading Edge Blanking Duration for V

t

ns

ILIM

Propagation delay from current detection to gate

off−state

t

Maximum on−time (option 1)

Maximum on−time (option 2)

t

29

16

39

20

49

24

ms

V

on(MAX)

Threshold for immediate fault protection activation

(140% of V

V

1.9

2.0

2.1

CS(stop)

)

ILIM

Leading Edge Blanking Duration for V

t

−

170

500

60

−

ns

mA

CS(stop)

BCS

Current source for CS to GND short detection

I

400

20

600

90

CS(short)

Current sense threshold for CS to GND short

detection

V

CS

rising

V

mV

CS(low)

GATE DRIVE

Drive Resistance

DRV Sink

DRV Source

W

R

SNK

R

SRC

−

13

30

−

Drive current capability

DRV Sink (Note GBD)

DRV Source (Note GBD)

mA

I

−

500

300

−

SNK

SRC

I

Rise Time (10% to 90%)

Fall Time (90 %to 10%)

DRV Low Voltage

C

= 470 pF

t

–

8

30

20

–

−

ns

V

DRV

CC

r

t

f

V

C

= V +0.2 V

CC(off)

V

DRV(low)

= 470 pF, R

= 33 kW

DRV

DRV High Voltage

V

= V

DRV

V

10

12

14

V

CC

CC(MAX)

DRV(high)

C

= 470 pF, R

= 33 kW

DRV

ZERO VOLTAGE DETECTION CIRCUIT

Upper ZCD threshold voltage

V

rising

falling

V

−

35

−

90

55

0.7

−

150

−

mV

V

ZCD

ZCD(rising)

V

ZCD(falling)

Lower ZCD threshold voltage

Threshold to force V

ZCD hysteresis

maximum during startup

V

−

REFX

ZCD(start)

ZCD(HYS)

ZCD(DEM)

V

15

−

mV

ns

Propagation Delay from valley detection to DRV high

(no t

V

decreasing

t

−

150

ZCD

)

LEB4

Additional delay from valley lockout output to DRV

latch set (programmable option)

T

t

125

250

375

ns

ZCD

LEB4

Equivalent time constant for ZCD input (GBD)

Blanking delay after on−time (option 1)

Blanking delay after on−time (option 2)

Blanking Delay at light load (option 1)

Blanking Delay at light load (option 2)

Timeout after last DEMAG transition

Pulling−down resistor

−

1.1

0.75

0.6

0.45

5

20

1.5

1.0

0.8

0.6

6.5

200

−

1.9

1.25

1.0

0.75

8

ns

ms

kW

PAR

V

REFX

V

REFX

V

REFX

V

REFX

> 0.35 V

< 0.25 V

t

ZCD(blank1)

ZCD(blank2)

t

TIMO

V

ZCD

= V

R

ZCD(pd)

−

ZCD(falling)

CONSTANT CURRENT CONTROL

Reference Voltage

T = 25°C − 85°C

V

327.9 334.2 341.2

mV

j

REF/3

Reference Voltage

T = −40°C to 125°C

j

V

REF/3

324

20

334.2

50

346

100

Current sense lower threshold for detection of the

leakage inductance reset time

V

CS

falling

V

CS(low)

Blanking time for leakage inductance reset detection

t

−

120

−

ns

CS(low)

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NCL30488

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

POWER FACTOR CORRECTION

Clamping value for V

T = 0°C to 125°C

V

2.06

−

2.2

240

230

2.34

−

V

REF(PFC)

J

REF(PFC)CLP

Line range detector for PFC loop

CONSTANT VOLTAGE SECTION

V

HV

increases

decreases

V

Vdc

HL(PFC)

V

−

LL(PFC)

Internal voltage reference for constant voltage

regulation

V

3.41

3.52

3.63

V

REF(CV)

CV Error amplifier Gain

G

40

−

50

60

−

mS

mA

V

EA

Error amplifier current capability

COMP pin lower clamp voltage

COMP pin higher clamp voltage

V

= V

(no dimming)

I

EA

REFX

REF

V

−

0.6

4.12

4

−

CV(clampL)

CV(clampH)

T = 0°C to 125°C

J

V

4.05

4.01

−

4.25

−

V

T = −40°C to 125°C

J

V

Internal divider V

to V

K

COMP

REFX

Internal ZCD voltage below which the CV OTA is

boosted

V

* 85%

* 90%

V

2.796 2.975 3.154

V

REF(CV)

boost(CV)

Threshold for releasing the CV boost

V

2.96

3.15

140

3.34

V

mA

V

REF(CV)

boost(CV)RST

Error amplifier current capability during boost phase

I

−

EAboost

st

ZCD OVP 1 level (slow OVP) option 1

V

* 115%

* 105%

V

OVP1

3.783 4.025 4.267

REF(CV)

ZCD voltage at which slow OVP is exit (option 1)

Switching period during slow OVP

ZCD fast OVP option 1

V

−

3.675

1.5

−

V

REF(CV)

OVP1rst

T

ms

V

sw(OVP1)

V

ref(CV)

* 125% + 150 mV

V

4.253 4.525 4.797

OVP2

OVP2_CNT

Number of switching cycles before fast OVP

confirmation

T

−

4

−

Duration for disabling DRV pulses during ZCD fast

OVP

T

4

s

recovery

COMP pin internal pullup resistor (SSR option)

R

15

kW

pullup

LINE FEED FORWARD

V

to I

conversion ratio

K

0.189

76

0.21

95

0.231 mA/V

HV

CS(offset)

LFF

Offset current maximum value

Line feed−forward current

V

> (450 V or 500 V)

I

114

45

mA

HV

offset(MAX)

DRV high, V = 200 V

I

35

40

HV

FF

VALLEY LOCKOUT SECTION

Threshold for line range detection V increasing

V

increases

decreases

V

HL

228

218

15

240

230

25

252

242

35

V

HV

> 80% V

HV

st

nd

(1 to 2 valley transition for V

)

REFX

REF

st

rd

(prog. option: 1 to 3 valley transition)

Threshold for line range detection V decreasing

V

LL

HV

REFX

nd

st

(2 to 1 valley transition for V

> 80% V

)

REF

rd

st

(prog. option: 3 to 1 valley transition)

Blanking time for line range detection

t

ms

HL(blank)

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NCL30488

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

VALLEY LOCKOUT SECTION

Valley thresholds

V

st

nd

th

rd

th

rd

1

to 2 valley transition at LL and 2 to 3 valley

V

REF

V

REF

V

REF

V

REF

V

REF

V

REF

V

REF

V

REF

decreases

increases

decreases

increases

decreases

increases

decreases

increases

V

−

0.80

0.90

0.65

0.75

0.50

0.60

0.35

0.45

−

VLY1−2/2−3

VLY2−1/3−2

VLY2−3/3−4

VLY3−2/4−3

VLY3−4/4−5

VLY4−3/5−4

VLY4−5/5−6

VLY5−4/6−5

rd

HL, V

decr. (prog. option: 3 to 4 valley HL)

REF

nd

st

nd

2

to 1 valley transition at LL and 3 to 2 valley

th

HL, V

incr. (prog. option: 4 to 3 valley HL)

REF

nd

rd

th

2

to 3 valley transition at LL and 3 to 4 valley

th

HL, V

decr. (prog. option: 4 to 5 valley HL)

REF

rd

nd

rd

3

to 2 valley transition at LL and 4 to 3 valley

th

HL, V

incr. (prog. option: 5 to 4 valley HL)

REF

rd

th

3

to 4 valley transition at LL and 4 to 5 valley

th

HL, V

decr. (prog. option: 5 to 6 valley HL)

REF

th

4

to 3 valley transition at LL and 5 to 4 valley

th

HL, V

incr. (prog. option: 6 to 5 valley HL)

REF

th

4

to 5 valley transition at LL and 5 to 6 valley

th

HL, V

decr. (prog. option: 6 to 7 valley HL)

REF

th

5

to 4 valley transition at LL and 6 to 5 valley

th

HL, V

incr. (prog. option: 7 to 6 valley HL)

REF

V

REF

V

REF

value at which the FF mode is activated

value at which the FF mode is removed

V

decreases

increases

V

−

0.25

0.35

−

V

REF

FFstart

REF

FFstop

FREQUENCY FOLDBACK

Added dead time

V

REFX

V

REFX

V

REFX

V

REFX

V

REFX

V

REFX

= 0.25 V

= 0.08 V

< 3 mV

< 11.2 mV

= 0

t

0.8

−

1.0

40

1.2

−

ms

FF1LL

Added dead time

t

FFchg

Dead−time clamp ( option 1)

Dead−time clamp ( option 2)

Minimum added dead−time in standby

Maximum added dead−time in standby (option 2)

FAULT PROTECTION

t

−

675

250

650

1.8

−

FFend1

FFend2

t

−

t

−

DT(min)SBY

= 0, V

< 0.7 V

t

−

COMP

DT(max)SBY2

Thermal Shutdown (Note 5)

Device switching (F

around 65 kHz)

T

SHDN

130

150

170

°C

SW

Thermal Shutdown Hysteresis

T

−

20

–

°C

SHDN(HYS)

Threshold voltage for output short circuit or aux.

winding short circuit detection

V

0.6

0.65

0.7

V

ZCD(short)

Short circuit detection Timer

V

ZCD

< V

t

OVLD

70

3

90

4

110

5

ms

s

ZCD(short)

Auto−recovery Timer

t

recovery

Line OVP threshold

V

increasing

decreasing

V

457

430

15

469

443

25

485

465

35

Vdc

ms

HV

HV(OVP)

HV pin voltage at which Line OVP is reset

Blanking time for line OVP reset

V

HV

HV(OVP)RST

T

LOVP(blank)

BROWN−OUT AND LINE SENSING

Brown−Out ON level (IC start pulsing)

Brown−Out ON level (IC start pulsing) option 2

Brown−Out OFF level (IC stops pulsing)

Brown−Out OFF level (IC stops pulsing) option 2

V

increasing

decreasing

V

101.5

129.7

92

108

138

98

114.5

146.3

104

137

−

Vdc

V

HV

HVBO(on)

V

HVBO(on)2

V

HVBO(off)

V

121

−

129

55

HVBO(off)2

HV pin voltage above which the sampling of ZCD is

enabled low line

decreasing, low line

decreasing, highline

increasing

V

sampENLL

HV pin voltage above which the sampling of ZCD is

enabled highline

V

HV

V

HV

V

−

105

−

V

sampENHL

ZCD sampling enable comparator hysteresis

BO comparators delay

V

−

5

−

V

sampHYS

BO(delay)

BO(blank)

t

30

25

ms

Brown−Out blanking time

15

35

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Guaranteed by design.

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NCL30488

TYPICAL CHARACTERISTICS

5,4

5,3

5,2

5,1

5

309

304

299

294

289

284

4,9

4,8

4,7

4,6

4,5

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 3. I_HV(start2)vs. Temperature

Figure 4. I_HV(start1)vs. Temperature

361

359

357

355

353

351

349

18,34

18,29

18,24

18,19

18,14

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 5. V_HV(OL)vs. Temperature

Figure 6. V_CC(on)vs. Temperature

10,25

10,23

10,21

10,19

10,17

10,15

10,13

10,11

26,96

26,91

26,86

26,81

26,76

26,71

26,66

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 7. V_CC(off)vs. Temperature

Figure 8. V_CC(OVP)vs. Temperature

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NCL30488

TYPICAL CHARACTERISTICS (continued)

1,7

1,69

1,68

1,67

1,66

1,65

1,64

1,63

1,62

1,41

1,39

1,37

1,35

1,33

1,31

1,29

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 9. I_CC1vs. Temperature

Figure 10. I_CC4vs. Temperature

1,2

1,15

1,1

54

53,5

53

1,05

1

52,5

52

0,95

0,9

51,5

51

0,85

0,8

50,5

50

0,75

0,7

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 11. V_ILIMvs. Temperature

Figure 12. V_CS(low)Fvs. Temperature

2,06

2,04

2,02

2

20,24

20,19

20,14

20,09

20,04

19,99

19,94

19,89

19,84

1,98

1,96

1,94

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 13. V_CS(stop)vs. Temperature

Figure 14. t_on(MAX)2vs. Temperature

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9

NCL30488

TYPICAL CHARACTERISTICS (continued)

359

354

349

344

339

334

180

179

178

177

176

175

174

173

172

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 15. t_LEBvs. Temperature

Figure 16. t_BCSvs. Temperature

120

110

100

90

10,5

9,5

8,5

7,5

6,5

5,5

4,5

3,5

80

70

60

50

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 17. t_ILIMvs. Temperature

Figure 18. R_SNKvs. Temperature

34

32

30

28

26

24

22

20

15,5

13,5

11,5

9,5

7,5

5,5

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 19. R_SRCvs. Temperature

Figure 20. t_rvs. Temperature

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10

NCL30488

TYPICAL CHARACTERISTICS (continued)

21,5

20,5

19,5

18,5

17,5

16,5

15,5

14,5

13,5

12,5

83

82,5

82

81,5

81

80,5

80

79,5

79

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 21. t_fvs. Temperature

Figure 22. V_ZCD(rising)vs. Temperature

0,672

0,67

54,5

53,5

52,5

51,5

50,5

49,5

0,668

0,666

0,664

0,662

0,66

0,658

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 23. V_ZCD(falling)vs. Temperature

Figure 24. V_ZCD(short)vs. Temperature

116

111

106

101

96

1,605

1,595

1,585

1,575

1,565

1,555

91

86

81

76

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 25. t_ZCD(dem)vs. Temperature

Figure 26. t_{ZCD(blank1)OPN1}vs. Temperature

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11

NCL30488

TYPICAL CHARACTERISTICS (continued)

0,861

0,856

0,851

0,846

0,841

0,836

1,072

1,067

1,062

1,057

1,052

1,047

1,042

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 27. t_{ZCD(blank1)OPN2}vs. Temperature

Figure 28. t_{ZCD(blank2)OPN1}vs. Temperature

0,584

0,579

0,574

0,569

0,564

6,92

6,87

6,82

6,77

6,72

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 29. t_{ZCD(blank2)OPN2}vs. Temperature

Figure 30. t_TIMOvs. Temperature

336,8

336,3

335,8

335,3

334,8

334,3

333,8

333,3

332,8

332,3

331,8

3,545

3,535

3,525

3,515

3,505

3,495

3,485

3,475

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 31. V_REF/3vs. Temperature

Figure 32. V_REF(CV)vs. Temperature

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12

NCL30488

TYPICAL CHARACTERISTICS (continued)

4,15

4,14

4,13

4,12

4,11

4,1

4,075

4,065

4,055

4,045

4,035

4,025

4,015

4,005

3,995

4,09

4,08

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 33. V_CV(clampH)vs. Temperature

Figure 34. V_OVP1vs. Temperature

0,2095

0,2085

0,2075

0,2065

0,2055

0,2045

0,2035

0,2025

0,2015

0,2005

4,54

4,53

4,52

4,51

4,5

4,49

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 35. V_OVP2vs. Temperature

Figure 36. K_LFFvs. Temperature

104

103

102

101

100

99

41,7

41,5

41,3

41,1

40,9

40,7

40,5

40,3

40,1

98

97

96

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 37. I_offset(MAX)vs. Temperature

Figure 38. I_FFvs. Temperature

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13

NCL30488

TYPICAL CHARACTERISTICS (continued)

1,0395

1,0385

1,0375

1,0365

1,0355

1,0345

1,0335

1,0325

1,0315

1,0305

2,208

2,203

2,198

2,193

2,188

2,183

2,178

2,173

2,168

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 39. t_FF1LLvs. Temperature

Figure 40. V_REF(PFC)CLPvs. Temperature

108,9

108,7

108,5

108,3

108,1

107,9

107,7

107,5

107,3

107,1

106,9

99,6

99,4

99,2

99

98,8

98,6

98,4

98,2

98

97,8

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 41. V_HVBO(on)ONP1vs. Temperature

Figure 42. V_HVBO(off)vs. Temperature

472

471

470

469

468

467

466

465

464

446

445

444

443

442

441

440

439

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 43. V_HV(OVP)vs. Temperature

Figure 44. V_HV(OVP)RSTvs. Temperature

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14

NCL30488

Application Information

if V reaches 1.5 x V

(after a reduced LEB of t ).

BCS

CS

ILIM

The NCL30488 implements a current−mode architecture

operating in quasi−resonant mode. Thanks to proprietary

circuitry, the controller is able to accurately regulate the

secondary side current and voltage of the fly−back converter

without using any opto−coupler or measuring directly the

secondary side current or voltage. The controller provides

near unity power factor correction

This additional comparator is enabled only during the

main LEB duration t , for noise immunity reason.

LEB

• Output Under Voltage Protection: If a too low voltage is

applied on ZCD pin for 90 ms time interval, the

controllers assume that the output or the ZCD pin is

shorted to ground and shutdown. After waiting 4 seconds,

the IC restarts switching.

• Thermal Shutdown: an internal circuitry disables the gate

drive when the junction temperature exceeds 150°C

(typically). The circuit resumes operation once the

temperature drops below approximately 140°C.

• Quasi−Resonance

Current−Mode

Operation:

implementing quasi−resonance operation in peak

current−mode control, the NCL30488 optimizes the

efficiency by switching in the valley of the MOSFET

drain−source voltage. Thanks to an internal algorithm

control, the controller locks−out in a selected valley and

remains locked until the input voltage or the output

current set point significantly changes.

POWER FACTOR AND CONSTANT CURRENT

CONTROL

The NCL30488 embeds an analog/digital block to control

the power factor and regulate the output current by

monitoring the ZCD, CS and HV pin voltages (signals

• Primary Side Constant Current Control: thanks to a

proprietary circuit, the controller is able to take into

account the effect of the leakage inductance of the

transformer and allows an accurate control of the

secondary side current regardless of the input voltage and

output load variation.

• Primary Side Constant Voltage Regulation: By

monitoring the auxiliary winding voltage, it is possible to

regulate accurately the output voltage. The output voltage

regulation is typically within 2%.

• Load Transient Compensation: Since PFC has low loop

bandwidth, abrupt changes in the load may cause

excessive over or under−shoot. The slow Over Voltage

Protection contains the output voltage when it tends to

become excessive. In addition, the NCL30488 speeds up

the constant voltage regulation loop when the output

voltage goes below 85% of its regulation level.

• Power Factor Correction: A proprietary concept allows

achieving high power factor correction and low THD

while keeping accurate constant current and constant

voltage control.

V

, V

, V ). This circuit generates the current

HV_DIV CS

ZCD

setpoint signal and compares it to the current sense signal to

turn the MOSFET off. The HV pin provides the sinusoidal

reference necessary for shaping the input current. The

obtained current reference is further modulated so that when

averaged over a half line period, it is equal to the output

current reference (V

). The modulation and averaging

REFX

process is made internally by a digital circuit. If the HV pin

properly conveys the sinusoidal shape, power factor will be

close to 1. Also, the Total Harmonic Distortion (THD) will

be low especially if the output voltage ripple is small.

V_REF

(eq. 1)

I_OUT

+

2N_spR_sense

Where:

• N is the secondary to primary transformer turns ratio:

sp

N

• R

• V

= N / N

S P

sp

is the current sense resistor

sense

is the output current reference: V

= V

if

REFX

REF

no dimming

• Line Feed−forward: allows compensating the variation of

the output current caused by the propagation delay.

• V Over Voltage Protection: if the V pin voltage

The output current reference (V

) is V

unless the

REFX

REF

controller operates in constant voltage mode.

CC

exceeds an internal limit, the controller shuts down and

waits 4 seconds before restarting pulsing.

PRIMARY SIDE CONSTANT VOLTAGE CONTROL

The auxiliary winding voltage is sampled internally

through the ZCD pin.

• Fast Over Voltage Protection: If the voltage of ZCD pin

exceeds 130% of its regulation level, the controller shuts

down and waits 4 s before trying to restart.

• Brown−Out: the controller includes a brown−out circuit

which safely stops the controller in case the input voltage

is too low. The device will automatically restart if the line

recovers.

A precise internal voltage reference V

voltage target for the CV loop.

sets the

REF(CV)

The sampled voltage is applied to the negative input of the

constant voltage (CV) operational transconductance

amplifier (OTA) and compared to V

.

REFCV

A type 2 compensator is needed at the CV OTA output to

stabilize the loop. The COMP pin voltage modify the the

output current internal reference in order to regulate the

output voltage.

• Cycle−by−cycle peak current limit: when the current

sense voltage exceeds the internal threshold V

, the

ILIM

MOSFET is turned off for the rest of the switching cycle.

• Winding Short−Circuit Protection: an additional

comparator senses the CS signal and stops the controller

When V

≥ 4 V, V

= V

.

COMP

REFX

< 0.9 V, V

REF

= 0 V.

REFX

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15

NCL30488

G_m

R

ZCD

ZCDU

V

ZCDsamp

ZCD & signal

sampling

COMP

.

R₁

C₁

R

OTA

ZCDL

V_REF(CV)

C₂

Aux.

Figure 45. Constant Voltage Feedback Circuit

Secondary Side Regulation Compatible

The NCL30488 is able to support secondary−side

regulation as well. The controller features an option to

The HV startup circuitry is made of two startup current

levels, I and I . This helps to protect the

HV(start1)

controller against short−circuit between V and GND. At

CC

provide a pullup resistor R

on COMP pin instead of the

power−up, as long as V is below V

, the source

pullup

CC

CC(TH)

CV OTA output. This allows connecting directly an

optocoupler collector and properly biases it. The internal

delivers I

(around 300 mA typical). Then, when

HV(start1)

V

I

reaches V

, the source smoothly transitions to

CC(TH)

CC

voltage biasing R

is around 5 V.

and delivers its nominal value. As a result, in case

pullup

HV(start2)

In secondary side regulation, the slow and fast OVP on

ZCD pin are still active thus providing an additional over

voltage protection. In this case, the ZCD pin resistors should

of short−circuit between V and GND occurring at high

CC

line (V = 305 V rms), the maximum power dissipation will

in

be 431 x 300 m = 130 mW instead of 1.5 W if there was only

one startup current level.

To speed−up the output voltage rise, the following is

implemented:

be calculated to trigger V

interest.

at the output voltage of

OVP2

• The digital OTA output is increased until V

REF(PFC)

. Again, this is to speed−up the

CV OTA Boost

signal reaches V

V_DD

REFX

control signal rise to their steady state value.

R_pullup

• At the beginning of each operating phase of a V cycle,

CC

COMP

the digital OTA output is set to 0. Actually, the digital

OTA output is set to 0 in the case of a cold start−up or in

the case of a start−up sequence following an operation

−

+

V_REF(CV)

interruption due to a fault. On the other hand, if the V

CC

hiccups just because the system fails to start−up in one

cycle, the digital OTA output is not reset to ease the

V

CC

second (or more) attempt.

• If the load is shorted, the circuit will operate in hiccup

Figure 46. COMP Pin Configuration for Secondary

Side Regulation

mode with V oscillating between V

and V

CC(on)

CC

CC(off)

until the output under voltage protection (UVP) trips.

UVP is triggered if the ZCD pin voltage does not exceed

STARTUP PHASE (HV STARTUP)

It is generally requested that the LED driver starts to emit

light in less than 1 s and possibly within 300 ms. It is

challenging since the start−up consists of the time to charge

V

within a 90 ms operation of time. This

ZCD(short)

indicates that the ZCD pin is shorted to ground or that an

excessive load prevents the output voltage from rising.

the V capacitor and that necessary to charge the output

CC

capacitor until sufficient current flows into the LED string.

This second phase can be particularly long in dimming cases

where the secondary current is a portion of the nominal one.

The NCL30488 features a high voltage startup circuit that

allows charging VCC pin capacitor very fast.

HV Startup Power Dissipation

At high line (305 V rms and above) the power dissipated

by the HV startup in case of fault becomes high. Indeed, in

case of fault, the NCL30488 is directly supplied by the HV

rail. The current flowing through the HV startup will heat the

controller. It is highly recommended adding enough copper

When the power supply is first connected to the mains

outlet, the internal current source is biased and charges up

the V capacitor. When the voltage on this V capacitor

around the controller to decrease the R

of the controller.

qJA

2

Adding a minimum pad area of 215 mm of 35 mm copper

(1 oz) drops the R to around 120°C/W (no air flow, R

CC

reaches the V

level, the current source turns off. At this

CC(on)

qJA

time, the controller is only supplied by the V capacitor,

measured at ADIM pin)

The PCB layout shown in Figure 47 is a layout example

to achieve low R

CC

and the auxiliary supply should take over before V

CC

collapses below V

.

CC(off)

qJA

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16

NCL30488

Winding and Output Diode Short−Circuit Protection

In parallel to the cycle−by−cycle sensing of the CS pin,

another comparator with a reduced LEB (t ) and a

BCS

threshold of (V

= 140% x V

) monitors the CS pin

CS(stop)

ILIM

to detect a winding or an output diode short circuit. The

controller shuts down if it detects 4 consecutives pulses

during which the CS pin voltage exceeds V

CS(stop).

The controller goes into auto−recovery mode.

Valley Lockout

Quasi−Square wave resonant systems have a wide

switching frequency excursion. The switching frequency

increases when the output load decreases or when the input

voltage increases. The switching frequency of such systems

must be limited.

Figure 47. PCD Layout Example

The NCL30488 changes valley as V

decreases and as

REFX

the input voltage increases and as the output current setpoint

is varied during dimming. This limits the frequency

excursion.

By default, when the output current is not dimmed, the

controller operates in the first valley at low line and in the

second valley at high line.

The application note ANDXXXX gives more details about

strategies to decrease the power dissipation of the HV

startup circuit.

Cycle−by−Cycle Current Limit

When the current sense voltage exceeds the internal

(prog. option to have the operating valley incremented by

threshold V , the MOSFET is turned off for the rest of the

ILIM

1 at high line for better I control at 305 V rms.)

out

switching cycle.

Table 1. VALLEY SELECTION

V

Voltage for Valley Change

HV_DIV

V

REFX

value at which the Controller

V

REFX

Value at Which the Controller

0

−−LL−−

2.3 V

−−HL−−

5 V

Changes Valley (I

Decreasing)

Changes Valley(I

Increasing)

out

st

nd rd

100%

80%

1

2

3

4

5

6

(3 )

80%

65%

50%

35%

nd

rd th

2

(4 )

65%

50%

35%

rd

th th

3

(5 )

th

th th

4

(6 )

th

th th

5

(7 )

25%

0%

25%

0%

FF mode

0

−−LL−−

2.3 V

−−HL−−

5 V

Internal V

Voltage for Valley Change

HV_DIV

Zero Crossing Detection Block

The Time−out also acts as a substitute clock for the valley

detection and simulates a missing valley in case of too

damped free oscillations.

The ZCD pin allows detecting when the drain−source

voltage of the power MOSFET reaches a valley.

A valley is detected when the ZCD pin voltage crosses

below the 55 mV internal threshold.

At startup or in case of extremely damped free

oscillations, the ZCD comparator may not be able to detect

the valleys. To avoid such a situation, Optimus Prime

features a Time−Out circuit that generates pulses if the

voltage on ZCD pin stays below the 55 mV threshold for

6.5 ms.

At startup, the output voltage reflected on the auxiliary

winding is low. Because of the ZCD resistor bridge setting

the constant voltage regulation target, the voltage on the

ZCD pin is very low and the ZCD comparator might be

unable to detect the valleys. In this condition, setting the

DRV Latch with the 6.5 ms time−out leads to a continuous

conduction mode operation (CCM) at the beginning of the

soft−start. This CCM operation only last a few cycles until

the voltage on ZCD pin becomes high enough and trips the

ZCD comparator.

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17

NCL30488

V_ZCD

V_ZCD(th)

low

3

4

high

14

12

I

decreases or V

out

in

high

increases

ZCD comp

high

low

15

low

TimeOut

16

17

2^nd, 3 ^rd

high

V_VIN

increases

Clock

low

Figure 48. Valley Detection and Time−out Chronograms

If the ZCD pin or the auxiliary winding happen to be

shorted the time−out function would normally make the

controller keep switching and hence lead to improper

regulation of the LED current.

The Under Voltage Protection (UVP) is implemented to

avoid these scenarios: a secondary timer starts counting

Slow OVP

If ZCD voltage exceeds V

switching cycles, the controller stops switching during

1.4 ms. The PFC loop is not reset. After 1.4 ms, the

controller initiates a new DRV pulse to refresh ZCD

for 4 consecutive

OVP1

sampling voltage. If V

is still too high (V

> 115%

ZCD

when the ZCD voltage is below the V

threshold. If

V

), the controller continues to switch with a 1.4 ms

ZCD(short)

REF(CV)

this timer reaches 90 ms, the controller detects a fault and

enters the auto−recovery fault mode.

period. The controller resumes its normal operation when

< 115% V

V

ZCD

.

REF(CV)

During slow OVP, the peak current setpoint is COMP pin

voltage scaled down by a fixed ratio.

ZCD Over Voltage Protection

Because of the power factor correction, it is necessary to

set the crossover frequency of the CV loop very low (target

10 Hz, depending on power stage phase shift). Because the

loop is slow, the output voltage can reach high value during

startup or during an output load step. It is necessary to limit

the output voltage excursion. For this, the NCL30488

features a slow OVP and a fast OVP on ZCD pin.

Fast OVP

If ZCD voltage exceeds V

4 consecutive switching cycles (slow OVP not triggered) or

for 2 switching cycles if the slow OVP has already been

triggered, the controller detects a fault and starts the

auto−recovery fault mode (cf: Fault Management Section)

(130% of V

) for

REF(CV)

OVP2

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18

NCL30488

Line Feedforward

HV

v _DD

v _VS

CS

R_LFF

I _CS(offset)

K _LFF

R _sense

Q_drv

+

25 ms

BO_NOK

Blanking

−

1 V / 0.9 V

Figure 49. Line Feed−Forward and Brown−out Schematic

The line voltage is sensed by the HV pin and converted

into a current. By adding an external resistor in series

between the sense resistor and the CS pin, a voltage offset

proportional to the line voltage is added to the CS signal. The

offset is applied only during the MOSFET on−time in order

to not influence the detection of the leakage inductance

reset.

below V

for 25 ms typical. Exiting a brown−out

HVBO(off)

condition overrides the hiccup on V (V does not wait

to reach V

mode.

An option with higher brown−out levels is also available

(see ordering table and electricals parameters)

CC

) and the IC immediately goes into startup

CC(off)

Line OVP

The offset is always applied even at light load in order to

improve the current regulation at low output load.

In order to protect the power supply in case of too high

input voltage, the NCL30488 features a line over voltage

protection. When the voltage on HV pin exceeds V

Brown−out

HV(OVP)

In order to protect the supply against a very low input

voltage, the controller features a brown−out circuit with a

fixed ON/OFF threshold. The controller is allowed to start

the controller stops switching; V hiccups.

CC

When V becomes lower than V

for more

HV

HV(OVP)RST

than 25 ms, the controller initiates a clean startup sequence

if a voltage higher than V

is applied to the HV pin

and re−starts switching.

HVBO(on)

and shuts−down if the HV pin voltage decreases and stays

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19

NCL30488

V_HV

V_HV(OVP)

V_HV(OVP)RST

t _LOVP(blank)

V_CC

V_CC(on)

V_CC(off)

V_DRV

I_out

Figure 50. Line OVP Chronograms

Protections

The circuit incorporates a large variety of protections to

make the LED driver very rugged.

Among them, we can list:

• Winding or Output Diode Short Circuit protection

The circuit detects this failure when 4 consecutive DRV

pulses occur within which the CS pin voltage exceeds

• Fault of the GND connection

(V

= 140% x V

). In this case, the controller

CS(stop)

ILIM

If the GND pin is properly connected, the supply current

enters auto−recovery mode (4−s operation interruption

drawn from the positive terminal of the V capacitor,

between active bursts).

CC

flows out of the GND pin to return to the negative terminal

• V Over Voltage Protection

CC

of the V capacitor. If the GND pin is not connected, the

CC

The circuit stops generating pulses if the V exceeds

CC

circuit ESD diodes offer another return path. The

accidental non connection of the GND pin can hence be

detected by detecting that one of this ESD diode is

conducting. Practically, the ESD diode of CS pin is

monitored. If such a fault is detected for 200 ms, the circuit

stops generating DRV pin.

V

and enters auto−recovery mode. This feature

CC(OVP)

protects the circuit if output LEDs happen to be

disconnected.

• ZCD fast OVP

If ZCD voltage exceeds V

for 4 consecutive

ZCD(OVP2)

switching cycles (slow OVP not triggered) or for 2

switching cycles if the slow OVP has already been

triggered, the controller detects a fault and enters

auto−recovery mode (4 s operation interruption between

active bursts).

• Output short circuit situation (Output Under Voltage

Protection)

Overload is detected by monitoring the ZCD pin voltage:

if it remains below V

for 90 ms, an output short

ZCD(short)

circuit is detected and the circuit stops generating pulses

for 4 s. When this 4 s delay has elapsed, the circuit

attempts to restart.

• Die Over Temperature (TSD)

The circuit stops operating if the junction temperature

(T ) exceeds 150°C typically. The controller remains off

until T goes below nearly 130°C.

J

• ZCD pin incorrect connection:

J

♦ If the ZCD pin grounded, the circuit will detect an

output short circuit situation when 90 ms delay has

elapsed.

• Brown−Out Protection (BO)

The circuit prevents operation when the line voltage is too

low to avoid an excessive stress of the LED driver.

Operation resumes as soon as the line voltage is high

♦ A 200 kW resistor pulls down the ZCD pin so that

the output short circuit detection trips if the ZCD pin

is not connected (floating).

enough and V is higher than V

.

CC

CC(on)

www.onsemi.com

20

NCL30488

250W to take into account possible parametric deviations.

• CS pin short to ground

Also, along the circuit operation, the CS pin could happen

to be grounded. If it is grounded, the MOSFET

conduction time is limited by the 20 ms maximum

on−time. If such an event occurs, a new pin impedance

test is made.

The CS pin is checked at start−up (cold start−up or after

a brown−out event). A current source (I

) is applied

cs(short)

to the pin and no DRV pulse is generated until the CS pin

exceeds V . I and V are 500 mA and

cs(low) cs(short)

cs(low)

60 mV typically (V rising). The typical minimum

CS

• Line overvoltage protection

impedance to be placed on the CS pin for operation is then

120 W. In practice, it is recommended to place more than

(see Line OVP section)

ORDERING TABLE OPTION

Valley

Transition

from LL to HL

Line Range

Detector

Maximum Dead−time

V

REF

Max. On−time

ZCD Blanking

Standby Mode

st

OPN #

NCL30488_ _

1.4 ms 200 mV 333 mV

1

to

1

to

On

Off

On

Off

250 ms 687 ms

20 ms

33 ms

1 ms

1.5 ms

nd

rd

2

3

NCL30488A2

NCL30488A3

x

Line OVP

Frozen Peak Current During Standby Mode V

Brown−out Levels

CS(SBY)

OPN #

NCL30488_ _

On

Off

380 mV

330 mV

280 mV

On: 108 V

Off: 98 V

On: 138 V

Off: 129 V

NCL30488A2

NCL30488A3

x

NA

x

ORDERING INFORMATION

Device

†

Marking

Package type

Shipping

NCL30488A2

L30486A2

SOIC7 – P7 COMP VHV PBFH

2500 / Tape & Reel

(Pb−Free)

NCL30488A3

L30488A3

SOIC7 – P7 COMP VHV PBFH

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

21

NCL30488

PACKAGE DIMENSIONS

SOIC−7

CASE 751U

ISSUE E

−A−

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B ARE DATUMS AND T

IS A DATUM SURFACE.

4. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

S

M

B

−B−

0.25 (0.010)

1

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

G

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189 0.197

4.00 0.150 0.157

1.75 0.053 0.069

0.51 0.013 0.020

0.050 BSC

0.25 0.004 0.010

0.25 0.007 0.010

1.27 0.016 0.050

C

R X 45

_

1.27 BSC

J

0.10

0.19

0.40

0

−T−

SEATING

PLANE

K

8

0

8

_

M

H

D 7 PL

0.25

5.80

0.50 0.010 0.020

6.20 0.228 0.244

M

S

0.25 (0.010)

T

B

A

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

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LITERATURE FULFILLMENT:

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TECHNICAL SUPPORT

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Voice Mail: 1 800−282−9855 Toll Free USA/Canada

Phone: 011 421 33 790 2910

Europe, Middle East and Africa Technical Support:

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◊

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22


型号：	NCL30488A3
厂家：	ONSEMI
描述：	Power Factor Corrected LED Driver with Primary Side CC/CV
文件：	总22页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCL30488A3 [ONSEMI]

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