NCL31000MNITWG [ONSEMI]
Intelligent LED Driver, Visible Light Communication capable, with Precision Dimming, Diagnostics and Power Metrology;
| 型号： | NCL31000MNITWG |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent LED Driver, Visible Light Communication capable, with Precision Dimming, Diagnostics and Power Metrology |
| 文件： | 总44页 (文件大小：1444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductor
Is Now
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www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
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or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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Complete Connected LED
Driver Power Solution
NCL31000, NCL31001
Description
The NCL31000 is a new member of the ON Semiconductor LED
driver family specifically targeting luminaire applications. NCL31000
incorporates a high efficient buck LED driver. The LED driver
supports both high−bandwidth analog dimming and PWM dimming
down to zero current. NCL31000 includes an integrated fixed 3V3
DC−DC and one adjustable DC−DC. A diagnostics block incorporates
an ADC, which measures input and LED output currents, voltages,
LED temperature, DC/DC voltages and currents. Fast safety
mechanisms protect the critical blocks of the chip. The diagnostic
measurements are available together with a flexible status reporting
and interrupt mechanism. NCL31001 is the same as NCL31000 except
that it does not include both DC−DC converters. The combination of
NCL31000 and NCL31001 is ideal for dual channel solutions.
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QFN48 7x7, 0.5P
CASE 485EP
MARKING DIAGRAM
1
NCL31
000x
AWLYYWW
Features
• Wide Input Voltage Range: 21.5 V to 57 V
• Proprietary 100 W+ Applications
• Integrated 3.3 V Buck Convertor (Only for NCL31000)
NCL31000
• Integrated Adjustable Buck Convertor 2.5 − 24 V (Only for
NCL31000)
1
• Integrated High Efficiency Buck LED Driver
• Adjustable Switching Frequency 44.4 kHz to 1 MHz
NCL31
001x
AWLYYWW
• Deep Dimming to Zero with Accuracy of 0.1% Using Internal
Precision 2.4 V Reference
NCL31001
• Best in Class Linearity
• High Modulation Bandwidth (~50 kHz)
♦ Visual Light Communication Capable
♦ Yellow−Dott Compliant
NCL31000x = Specific Device Code (x = I or S)
NCL31001x
A
= Assembly Location
= Wafer Lot
= Year
WL
YY
WW
• Internal DIM DAC for Independent LED Control During
Micro−controller Re−flashing (Warm Boot)
• Low EMI Reference Design
= Work Week
2
• I C/SPI Interface (I/S Suffix)
• High Accuracy Diagnostic Functions to Measure Voltages/Currents
• Protection against LED Shorts & Opens
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• LED Over/Under Voltage & Over Current Protection
• Chip Over Current Protection
• Chip & LED Over Temperature Protection
• Junction Temperature Range of −40°C to +125°C
• Available in 48−pin QFN 7x7
• These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
June, 2021 − Rev. 1
NCL31000/D
NCL31000, NCL31001
DEVICE ORDERING INFORMATION
Device
†
DC−DC Converters
Serial Bus
Shipping
2
NCL31000MNITWG
NCL31000MNSTWG
NCL31001MNITWG
NCL31001MNSTWG
Yes
Yes
No
I C
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
SPI
2
I C
No
SPI
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1
2
36
35
34
33
32
31
30
29
28
27
26
25
NC
N3V3
VBB
UVLO
NC
VDDD
ADDR2_MISO
INTB
3
4
SCL_CLK
SDA_MOSI
ADDR1_CSB
CADC
5
NC
6
NCL31000
NC
7
GNDA
VSS
NC
8
VREF
9
DIM
10
11
12
PSNSN
PSNSP
NC
TLED
VLED
Figure 1. Pin−out NCL31000 in 48−pin QFN (Top View)
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2
NCL31000, NCL31001
1
2
36
35
34
33
32
31
30
29
28
27
26
25
NC
N3V3
VBB
UVLO
NC
VDDD
ADDR2_MISO
INTB
3
4
SCL_CLK
SDA_MOSI
ADDR1_CSB
CADC
5
NC
6
NCL31001
NC
7
GNDA
VSS
NC
8
VREF
9
DIM
10
11
12
PSNSN
PSNSP
NC
TLED
VLED
Figure 2. Pin−out NCL31001 in 48−pin QFN (Top View)
PIN DESCRIPTION
Pin No. Signal Name
Type
Description
1
2
NC
N3V3
VBB
UVLO
NC
Power
Power
Analog
−3V3 LDO output. Decouple to VBB (pin 3) with a 1 mF capacitor.
3
Positive input power. Connect to the positive terminal of the DC power supply.
4
Under−voltage lockout pin. Keep capacitance on this pin versus VSS below 100 pF
5
6
NC
7
NC
8
VSS
NC
Power
Negative input power. Connect to the negative terminal of the DC power supply.
9
10
PSNSN
Input
Input
Negative input current sense line. Connect to VSS at the negative side of the external input
current sense resistor.
11
PSNSP
Positive input current sense line. Connect to the positive side of the external input current
sense resistor.
12
13
14
15
NC
GNDALD
LDSNSN
LDSNSP
Power
Input
Input
Application ground. Return for the LED Buck compensation network.
Negative LED current sense line. Connect to the GND side of LDSNS.
Positive LED current sense line. Connect to the positive side of LDSNS.
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3
NCL31000, NCL31001
PIN DESCRIPTION (continued)
Pin No. Signal Name Type
Description
16
17
18
LDCOMP
RTNPLD
P9V
Analog
Power
Power
Compensation pin for the LED driver.
Application ground. LED Buck power return.
9 V gate drive voltage regulator output. Decouple to GNDPLD with a 1 mF capacitor.
Connect to P9V (pin 45) with a trace on the PCB.
19
20
21
22
23
24
25
26
27
28
29
30
31
LDGB
GNDPLD
LDSW
BST
Output
Power
Power
Power
Output
Input
LED buck convertor bottom switch gate driver.
Application ground. LED Buck power return.
LED buck convertor switching node.
Boost voltage for top switch gate drive. Decouple to LDSW with a 100 nF capacitor.
LED buck convertor bottom switch gate driver.
LDGT
PWM
PWM Dimming input.
VLED
Input
LED string voltage measurement. Connect to GND when not used.
LED string NTC resistor divider measurement point. Connect to GND when not used.
Analog Dimming input.
TLED
Input
DIM
Analog
Analog
Power
Analog
Input
VREF
Reference precision voltage output. Decouple with a 2.2 mF capacitor.
Application ground. Analog return.
RTNA
CADC
ADDR1_CSB
ADC filter capacitor connection. Decouple to GNDA with a 10 nF capacitor.
2
2
2
I C Address for I C mode. Tie to GND, VDDD or leave floating for alternative I C address.
CSB in SPI mode.
2
32
33
34
35
36
37
38
SDA_MOSI
SCL_CLK
INTB
Input/Output
Input
I C Data line. External pull−up resistor required. MOSI in SPI mode.
2
I C Clock line. External pull−up resistor required. CLK in SPI mode.
2
Open Drain
Input
I C Interrupt pin. External pull−up resistor required.
2
2
ADDR2_MISO
VDDD
I C Address. Tie to GND or leave floating for alternative I C address. MISO in SPI mode.
Power
3V3 power input for the NCL31000 digital circuitry.
VDD1
Power
3V3 power output for the chip and external circuitry.
IVDD1
Input
Current measurement for VDD1 regulator. Connect to the positive terminal of the VDD1
sense resistor.
39
40
41
VDD1SW
GND
Power
Power
Power
VDD1 buck convertor switching node.
Application ground. Ground connection for the VDD1 and VDD2 DC/DC convertors.
VBB
Positive input power. Decouple to the GND with a 1 mF capacitor. Connect to the positive
terminal of the DC power supply.
42
43
44
45
VDD2SW
GND
Power
Power
Output
Power
VDD2 buck convertor switching node.
Application ground. Ground connection for the VDD1 and VDD2 DC/DC convertors
VDD2 buck convertor bottom switch gate driver.
VDD2GB
P9V
9 V gate drive voltage input. Decouple to GND with a 100 nF capacitor.
Connect to P9V (pin 18) with a trace on the PCB.
46
47
VDD1GB
IVDD2
Output
Input
VDD1 buck convertor bottom switch gate driver.
Current measurement for VDD2 regulator. Connect to the positive terminal of the VDD2
sense resistor.
48
VDD2
Power
VDD2 power output for external circuitry.
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4
NCL31000, NCL31001
Figure 3. NCL31000 Block Diagram
Figure 4. NCL31001 Block Diagram
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5
NCL31000, NCL31001
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
Max
70
Unit
V
VBB
Input Power Supply vs. VSS
GND, GNDPLD, GNDA, Application Ground vs. VSS
GNDALD
VBB + 0.3
V
BST
LDGT
Analog Output vs. LDSW
Analog Output vs. GND
Analog Output vs. GND
Analog Input vs. VSS
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
11
V
V
V
V
Min (70, VBB + 11)
LDSW
VBB+0.3
3.6
PSNSN, PSNSP
LDSNSN, LDSNSP
VDD1
Analog Input vs. GND
0.3
3.3 V Analog Supply vs. GND
3.3 V Digital Supply vs. GND
Digital Input/Output vs. GND
Digital Input/Output vs. GND
Analog Output vs. GND
Analog Input vs. GND
3.6
V
VDDD
ADDR1_CSB
ADDR2_MISO
VREF
DIM
CADC
Analog Output vs. GND
Compensation Pin vs. GND
Analog Input vs. GND
LDCOMP
IVDD1
−0.3
−0.3
Min (3.6, VDD1 + 0.3)
5.5
V
V
SDA_MOSI
SCL_SCK
INTB
Digital Input/Output vs. GND
Digital Input vs. GND
Open Drain Digital Output vs. GND
Analog Output vs. GND
Analog Output vs. GND
Analog Output vs. GND
Analog Output vs. GND
Analog Input vs. GND
P9V
−0.3
11
V
VDD1GB, VDD2GB
LDGB
N3V3
VBB−3.6
−0.3
VBB + 0.3
VBB + 0.3
V
V
VDD2
VLED
HV tolerant Input vs. GND
HV tolerant Input vs. GND
HV tolerant Input vs. GND
Analog Input vs. GND
PWM
TLED
IVDD2
VDD1SW
VDD2SW
Analog Output vs. GND
Analog Output vs. GND
Storage Temperature
−0.6
VBB + 11
V
T
STRG
−55
−40
2
+150
+125
−
°C
°C
kV
V
T
J
Junction Temperature
ESD−HBM
ESD−CDM
Human Body Model; EIA−JESD−A114
Charged Device Model; ESD−STM5.3.1
500
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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6
NCL31000, NCL31001
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
21.5
0
Max
57
Unit
V
VBB
Input Power Supply (VBB vs. VSS)
V
Digital Inputs SCL, SDA, INTB, PWM vs. GND
Temperature Sense Analog Input vs. GND
Ambient Temperature
5
V
I_D
VTLED
0
VDD1
+85
+125
V
T
−40
−40
°C
°C
A
T
J
Junction Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL CHARACTERISTICS
Symbol
qJC
Characteristic
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Air
Value
38
Unit
°C/W
°C/W
qJA
128
1. qJA is obtained with 1S1P test board (1 signal – 1 plane) and natural convection. Refer to JEDEC JESD51 for details
ELECTRICAL CHARACTERISTICS
Symbol
OSCILLATOR
OSC_FREQ
Parameter
Condition
Min
Typ
Max
Unit
Oscillation Frequency
7.6
8
8.4
MHz
UNDER VOLTAGE LOCK−OUT CHARACTERISTICS
UVLO_H
UVLO_L
VBB UVLO Threshold Voltage (Note 2)
VBB UVLO Threshold Voltage (Note 2)
UVLO Threshold Hysteresis
VBB rising
VBB falling
1.15
1.09
30
1.23
1.17
53
1.3
1.26
75
V
V
UVLO_hyst
mV
CONSUMPTIONS (VBB = 53 V)
Idd_on,0
Idd_on,1
Operating Current
CTRL = 0; VDD1 Non−switching
−
−
2.03
2.12
−
−
mA
mA
Operating Current w. VDD2
CTRL = 1; VDD1, VDD2
Non−switching
Idd_on,2
Idd_on,3
Operating Current w. Metrology
CTRL = 4; VDD1 Non−switching
−
−
2.06
2.15
−
−
mA
mA
Operating Current w. VDD2 & Metrology
CTRL = 5; VDD1, VDD2
Non−switching
VDD1 & VDD2 DCDC ELECTRICAL SPECIFICATIONS
VDD1x_Freq
N3V3
Switching Frequency
JIT_EN = 0
0 ≤ I ≤ 5 mA
0 ≤ I ≤ 20 mA
126.6
3.13
8.55
133.3
3.3
9
140
3.47
9.45
kHz
V
Internal VBB−N3V3 Voltage
P9V
Internal P9V Voltage
(Generated in LED Block)
V
VDD1xGB_Rpu LS Gate Driver Pull−up Resistance
VDD1xGB_Rpd LS Gate Driver Pull−down Resistance
15
2
28
3.25
20
65
6.5
52
16
W
W
VDD1xGB_Tr
VDD1xGB_Tf
LS Gate Driver Rise Time
LS Gate Drive Fall Time
10
3
ns
ns
6
VDD1 MAIN DCDC ELECTRICAL SPECIFICATIONS
DC3V3_VDD1
DC3V3_ILMT
Main Supply Output Voltage
Peak Inductor Current Limit
3.234
230
50
3.3
300
110
88
3.366
370
200
200
7.5
V
mA
ns
R
= 0.75 W
sns
VDD1_Ton,min Minimum ON Time
VDD1_Ton,min Minimum OFF Time
VDD1_HS_Ron Top Switch on Resistance
50
ns
1.5
−
3.3
W
I_VDDD
Operating Current on VDDD
CTRL = 0
3.15
−
mA
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7
NCL31000, NCL31001
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter
VDD1 MAIN DCDC ELECTRICAL SPECIFICATIONS
Condition
Min
Typ
Max
Unit
VDD1_ACRp
VDD1_ACLp
Equivalent AC Parallel Resistance
Equivalent AC Parallel Inductance
R
R
= 0.75 W; CCM
= 0.75 W; CCM
−
−
0.6
−
−
W
sns
sns
149
mH
VDDD RESET ELECTRICAL SPECIFICATIONS
VDD1_POR_LH VDD1(D) Reset Threshold H
VDD1_POR_HL VDD1(D) Reset Threshold L
VDD1_POR_HY VDD1(D) Reset Hysteresis
VDD2 AUXILIARY DCDC ELECTRICAL SPECIFICATIONS
DCAUX_VDD2 Aux Supply Output Voltage
VDD1(D) Rising
VDD1(D) Falling
2.8
2.5
0.2
2.9
2.7
0.3
3.05
2.8
V
V
V
0.4
5V0 (VDD2_SEL = 2)
7V2 (VDD2_SEL = 6)
2V5 (VDD2_SEL = 0)
3V3 (VDD2_SEL = 4)
10V (VDD2_SEL = 1)
12V (VDD2_SEL = 5)
15V (VDD2_SEL = 3)
24V (VDD2_SEL = 7)
4.9
7.056
2.45
3.234
9.8
11.76
14.7
23.52
882
601
811
802
544
544
538
450
50
5
7.2
5.1
7.344
2.55
3.366
10.2
12.24
15.3
24.48
1014
750
933
922
664
664
678
650
150
150
2.65
−
V
V
2.5
V
3.3
V
10
V
12
V
15
V
24
V
DCAUX_ILMT
Peak Inductor Current Limit
948
668
872
862
604
604
598
547
87
mA
mA
mA
mA
mA
mA
mA
mA
ns
ns
W
5V0; R
7V2; R
2V5; R
3V3; R
10V; R
12V; R
15V; R
24V; R
= 0.22 W
= 0.22 W
= 0.20 W
= 0.20 W
= 0.33 W
= 0.33 W
= 0.33 W
= 0.36 W
sns
sns
sns
sns
sns
sns
sns
sns
VDD2_Ton,min Minimum ON Time
VDD2_Ton,min Minimum OFF Time
VDD2_HS_Ron Top Switch on Resistance
50
84
0.5
−
1.1
VDD2_Sx
Slope Compensation
0.073
0.067
0.23
0.53
0.12
0.15
1.22
1.16
0.92
2.09
15V; R
24V; R
5V0; R
7V2; R
2V5; R
3V3; R
10V; R
12V; R
15V; R
24V; R
= 0.33 W
A/ms
A/ms
W
sns
sns
sns
sns
sns
sns
sns
sns
sns
sns
= 0.36 W
0.028
−
−
VDD2_ACRp
Equivalent AC Parallel Resistance
−
= 0.22 W; CCM
= 0.22 W; CCM
= 0.20 W; CCM
= 0.20 W; CCM
= 0.33 W; CCM
= 0.33 W; CCM
= 0.33 W; CCM
= 0.36 W; CCM
−
−
W
−
−
W
−
−
W
−
−
W
−
−
W
−
−
W
−
−
W
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8
NCL31000, NCL31001
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter
VDD2 AUXILIARY DCDC ELECTRICAL SPECIFICATIONS
VDD2_ACLp Equivalent AC Parallel Inductance
Condition
Min
Typ
Max
Unit
5V0; R
7V2; R
2V5; R
3V3; R
10V; R
12V; R
15V; R
24V; R
= 0.22 W; CCM
= 0.22 W; CCM
= 0.20 W; CCM
= 0.20 W; CCM
= 0.33 W; CCM
= 0.33 W; CCM
= 0.33 W; CCM
= 0.36 W; CCM
−
−
−
−
−
−
−
−
60
120
29
−
−
−
−
−
−
−
−
mH
mH
mH
mH
mH
mH
mH
mH
sns
sns
sns
sns
sns
sns
sns
sns
38
275
275
229
514
LED DRIVER ELECTRICAL SPECIFICATIONS
VBB
VLED
Input Voltage Range for Stable Output
21.5
4
−
−
57
38
V
V
LED String Voltage vs. GND
Analog DIM Input vs. GND
LED Current Range
VDIM
0
−
2.4
3
V
ILED (Note 4)
0
−
A
VSNS (Note 5) Sense Resistor Voltage
VCSA_0 (Note 6) Sense Amplifier Output Voltage [Inputs Shorted]
−0.24
197
−0.125
−
0.3
205
0.2
V
200
−
mV
%
ILED_OFFS
(Note 7)
LED Current Regulation Offset Error Relative to VREF
ILED_GAIN
(Note 8)
LED Current Regulation Gain Error
−2
−
2
%
FAST CURRENT−MODE AMPLIFIER
LED_CSNSF_
GAIN
Current−mode Loop Amplifier Gain
2.97
3.0
3.03
LED DRIVER SAWTOOTH SLOPE COMPENSATION ELECTRICAL SPECIFICATIONS
SLP1_1
SLP1_2
SLP1_3
SLP1_4
SLP2_1
SLP2_2
SLP2_3
SLP2_4
Slope Compensation 1 with SLP1<1:0> = 00
Slope Compensation 1 with SLP1<1:0> = 01
Slope Compensation 1 with SLP1<1:0> = 10
Slope Compensation 1 with SLP1<1:0> = 11
Slope Compensation 2 with SLP2<1:0> = 00
Slope Compensation 2 with SLP2<1:0> = 01
Slope Compensation 2 with SLP2<1:0> = 10
Slope Compensation 2 with SLP2<1:0> = 11
0.07
0.14
0.21
0.28
0.21
0.28
0.42
0.63
0.1
0.2
0.3
0.4
0.3
0.4
0.6
0.9
0.13
0.26
0.39
0.52
0.39
0.52
0.78
1.17
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
LED DRIVER INTERNAL DAC ELECTRICAL SPECIFICATIONS
DIM_DNL
DIM_INL
DIM_MAX
DIM_MIN
DIM_RES
Internal DIM Differential Nonlinearity
Internal DIM Integral Nonlinearity
Internal DIM Maximum (Code 0x7F)
Internal DIM Minimum (Code 0x09)
Internal DIM DAC Resolution
−0.5
−0.5
2.376
168.75
−
0
0
0.5
0.5
LSB
LSB
V
2.4
187.5
7
2.424
206.75
−
mV
LSB
LED DRIVER OVER−CURRENT PROTECTION ELECTRICAL SPECIFICATION
OCP_VTH_UP Comparator Threshold
2.95
3
3.04
V
LED DRIVER SOFT−START /OTA/NON−OVERLAPPING ELECTRICAL SPECIFICATION
GM
Error Amplifier Transconductance gm in Operational Mode
Error Amplifier Transconductance gm in Soft Start Mode
0.5
60
1
1.5
mS
GM_SST
100
180
mS
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9
NCL31000, NCL31001
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter
Condition
Min
Typ
Max
Unit
LED DRIVER SOFT−START /OTA/NON−OVERLAPPING ELECTRICAL SPECIFICATION
TON_MIN
TOFF_MIN
TNOV
Minimum ON Time of the HS Driver
Minimum ON Time of the LS Driver
Non−overlapping Time
20
20
10
63
73
25
150
150
50
ns
ns
ns
REFERENCE VOLTAGE CHARACTERISTICS
VREF
IREF
Voltage Reference for DIAG/LED/DCDC [IREF < 2 mA]
Voltage Reference Current Consumption
2.394
2.4
2.406
3
V
−
−
mA
2
I C TIMING CHARACTERISTICS (NCL31000I)
f_SCL Interface Clock Frequency
SPI TIMING CHARACTERISTICS (NCL31000S)
f_SCLK Interface Clock Frequency
DIAGNOSTICS ELECTRICAL SPECIFICATION
−
−
−
−
400
2
kHz
MHz
DIAG_ILED
DIAG_VLED
DIAG_IBB
LED Current Measurement Overall Accuracy
−0.6
−0.8
−1
−
−
−
−
−
−
−
−
−
−
0.6
0.8
1
%
%
%
%
%
%
%
%
%
mA
LED Voltage Measurement Overall Accuracy
Input Current Measurement Overall Accuracy
Input Voltage Measurement Accuracy
DIAG_VBB
−0.9
−2
0.9
2
DIAG_IVDD1
DIAG_IVDD2
DIAG_VDD1
DIAG_VDD2
DIAG_TLED
VDD1 Current Measurement Overall Accuracy
VDD2 Current Measurement Overall Accuracy
VDD1 Voltage Measurement Overall Accuracy
VDD2 Voltage Measurement Overall Accuracy
TLED Voltage Measurement Overall Accuracy
−2
2
−1
1
−1
1
−1
1
DIAG_CONSO DIAG Current Consumption
−
200
THERMAL PROTECTION CHARACTERISTICS
TSD_H
TSD_L
Thermal Shutdown, High Threshold
Thermal Shutdown, Low Threshold
Thermal Warning, High Threshold
Thermal Warning, Low Threshold
141
126
112
101
150
135
120
108
159
143
127
114
°C
°C
°C
°C
TWRN_H
TWRN_L
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Voltage referenced to VSS
3. E.g. after overcurrent timeout
4. This range depends on the sense resistor RSNS.
5. Assume inductor current ripple included. This spec implies that the inductor current ripple size has an upper limit
VSNSmin > RSNS x Ippmax / 2.
6. The VCSA voltage is the output of the LED sense amplifier and is the compare voltage for the DIM input. VCSA_0 is given with the inputs
shorted. The VCSA_0 voltage is the threshold to get exactly zero current.
7. This deviation is the total offset in the loop. It is specified relative to the VREF typical. It is useful for calculating the maximum offset error
when using a VREF based solution for accurate dimming to low currents. It is derived from VCSA_0:
a. ILED_OFFS
= (VCSA_0
– VCSA_0
) / VREF
HIGH
HIGH
TYP
8. This error is a dominant factor in the LED current regulation error at mid and high LED currents. It is specified relative to VREF typical. Assume
RSNS = 100 mW and ideal.
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10
NCL31000, NCL31001
SIMPLIFIED APPLICATION SCHEMATIC
Figure 5. Typical Application Schematic
Figure 6. Typical Application Schematic with Input Current Sense
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11
NCL31000, NCL31001
Figure 7. Typical Application Schematic Dual Channel
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12
NCL31000, NCL31001
Table 1. TYPICAL BILL OF MATERIALS − BASED ON SINGLE CHANNEL WITH INPUT CURRENT SENSE
Symbol
C1
Description
Value
100 pF
1 mF
Rating
10 V
10 V
6.3 V
6.3 V
100 V
100 V
80 V
25 V
100 V
25 V
25 V
10 V
25 V
25 V
25 V
Remark
Reference
Decoupling
(Note 9)
C2
Decoupling, Buffer
C3
Output Capacitor for VDD1
Output Capacitor for VDD2
Fast Filter Capacitor for DC−DC’s and Chip
Fast Filter Capacitor for LED Driver
Buffer Capacitor for Application
LED Bootstrap Capacitor
22 mF
C1206C226K9PAC
C1210C476M9PAC
C4
47 mF
(Note 11)
C5
1 mF
C1210C105K1RAC
C6
2 x 1 mF
56 mF
C1210C105K1RACTU
A759MS566M1KAAE045
C7
C8
100 nF
2 x 470 nF
100 nF
10 nF
C9
LED Driver Output Capacitors
Filtering TLED
C0805C471K1RACTU
C13
C11
C12
C13
C14
C15
R1
LED Driver Compensation Capacitor
Stabilization Capacitor, Buffer VREF
Sample and Hold for ADC
2.2 mF
10 nF
Decoupling, Buffer P9V
1 mF
Decoupling P9V
100 nF
750 mW
200 mW
100 W
VDD1 Sense Resistor
RCWE0603R750FKEA
RL1220S−R20−F
R2
VDD2 Sense Resistor
(Note 11)
(Note 10)
R3
Protection Resistor for Overvoltage on VLED Node
TLED Resistor
RC0603FR−07100RL
R4
10 kW 1%
180 mW 1%
4.7 kW
R5
LED Driver Current Sense Resistor
2 W
2
R6
I C Pull−up
2
R7
I C Pull−up
4.7 kW
R8
Interrupt Pull−up
4.7 kW
R9
UVLO (POR @ 35 V)
470 kW 1%
16 kΩ 1%
100 mW 1%
390 mH
100 mH
68 mH
R10
R11
L1
UVLO (POR @ 35 V)
Sense Resistor for Input Current
VDD1 Buck Inductor
2 W
CRA2512−FZ−R100ELF
744777239
L2
VDD2 Buck Inductor
7447714101
L3
LED Driver Buck Inductor
2 A
(Note 10)
rms
Q1
Q3
Q4
U5
Dual NMOS Bottom Switching Transistor for DC/DCs
NMOS Bottom Switching Transistor for LED Driver
NMOS Top Switching Transistor for LED Driver
FDC8602
FDMA037N08L
NVTFS6H880N
NCL31000
9. Must be smaller than 1 nF.
10.Inductor saturation current and LED current sense resistor depend on the application specifications such as required power, allowed current
ripple. See LED driver section for details.
11. The values for L2, R2 and C4 in the table are specific for the 5 V VDD2 output. Refer to table 6 and 10 for other VDD2 output voltages.
General: The schematic does not show EMI filtering required for some applications.
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13
NCL31000, NCL31001
DUAL STEP−DOWN CONVERTER FUNCTIONAL DESCRIPTION
Bottom Mosfet
The NCL31000 incorporates a dual synchronous
step−down switching converter for generating two voltage
rails. The top mosfets are internal in NCL31000, whereas
the bottom mosfets need to be added externally.
The regulators employ a constant−frequency peak
current−mode control scheme with internal compensation.
The inductor current is sensed trough a resistance in series
with the inductor. This also allows the NCL31000 to
measure the average output current (see Metrology section).
Depending on the load current, the converter operates in
Discontinuous Conduction Mode (DCM) or Continuous
Conduction Mode (CCM).
The bottom mosfets should have the appropriate
drain−source on−resistance and voltage rating (≥80 V) while
maintaining low output capacitance, low gate charge and
good drain−source diode characteristics (reverse recovery).
Preferably, the package(s) should be very small to enable a
compact PCB layout as well.
Based on above considerations, it is obvious that dual
n−channel mosfet FDC8602 seems to be − by far − the best
choice to complement NCL31010.
Table 2. DUAL N−CHANNEL MOSFET
The VDD1 regulator, which is automatically enabled
when the voltage on the UVLO pin rises above the UVLO_H
treshold, generates a 3.3 V output voltage with 150 mA
output current capability to power the system
microcontroller (next to some internal logic on VDDD).
The VDD2 regulator needs to be enabled through the
digital interface. The default output voltage of VDD2 is 5 V
(with 510 mA output current capability), but other output
voltages (and corresponding other output current
capabilities) can be programmed by the digital interface:
2.5 V, 3.3 V, 7.2 V, 10 V, 12 V, 15 V or 24 V.
Product
V
(V)
r
(mW) Package Type
DS(on)
DS
FDC8602
100
350
TSOT−23−6
Switching Frequency
The switching frequency of the NCL31000 DC/DC
regulators is 133.3 kHz. This switching frequency is derived
from the internal accurate 8 MHz master clock which is
divided by 60.
In terms of efficiency and EMI, this low switching
frequency is beneficial and yet it allows a small overall
solution size (small external inductors and capacitors).
VBB
VBB
LS
BUF3V3
N3V3
IVDDx
Current
Sense
L
VDDx
VDDxSW
VDDx
R
IVDDx
P9V
CK
S
VDDxGB
V
REFx
M
VDDx
C
VDDx
BUF9V
R Q
OTA
GND
GND
Figure 8. DCDC Block Diagram
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14
NCL31000, NCL31001
Current Sense Resistor and Peak Current Limit
Maximum Output Current
The inductor current is sensed by a current sense resistor
in series with the inductor. The sense resistor value
configures the gain of the sensed current signal that is
compared to the control voltage to determine when the top
mosfet needs to be switched off to maintain regulation. The
sense resistor value also configures the peak inductor
current limit at which the top mosfet will be switched off −
despite a higher control voltage − in order to protect the
power stage of the converter against overcurrents.
For the VDD1 regulator, a 750 mW sense resistor is
recommended.
The maximum load current that will be available is the
peak inductor current limit minus half the peak−to−peak
inductor ripple current:
(VIN * VOUT) VOUT
IOUT + ILIM
*
(eq. 1)
2 L VIN fSW
To determine the maximum guaranteed output current
above equation should be evaluated with the minimum value
of the peak inductor current limit I , of the inductance L
LIM
(tolerance and saturation) and of the switching frequency
f . For both the VDD1 regulator and all output voltages of
sw
the VDD2 regulator, conversely, the maximum value of the
For the VDD2 regulator with 5 V output voltage, a
200 mW sense resistor is recommended. For the other output
voltages, the recommended sense resistor value can be
found in table 6.
input voltage V (i.e. 57 V) should be used here. Likewise
IN
for the output voltage V
in above equation an equivalent
OUT
value V
can be used here to incorporate the slight
OUT,eq
increase in duty cycle with the output current due to the
(maximum) resistance of the (bottom) mosfet, the inductor
and the sense resistor:
The current sense resistors should have a 1% tolerance.
Inductor
The inductor saturation current should be higher than the
maximum peak switch current of the converter. Within an
inductor series, smaller inductance values have a higher
saturation current rating. Allowing a larger than typically
recommended inductor ripple current enables the use of a
physically smaller inductor.
VOUT,eq (IOUT) + VOUT,typ ) (rDS(on) ) RDC ) RCS) IOUT
(eq. 2)
Based on above considerations, the output current
capability of both converters operated with the
recommended current sense resistance, inductor and bottom
mosfet is given below in table 5 and table 6.
For the VDD1 regulator, a Würth WE−PD Size 7345
Inductor with 390 mH Inductance is recommended.
Table 5. VDD1 CONFIGURATION
V
OUT
(V)
I
(mA)
R (mW)
CS
L (mH)
OUT
Table 3. INDUCTOR FOR VDD1
3.3
150
750
390
Product
L (mH)
390
R
(W)
I
(A)
DC typ.|max.
SAT typ.
744777239
1.25 | 2.85
0.42
20%
Table 6. VDD2 CONFIGURATION
For the VDD2 regulator with 5 V output voltage, the
Würth WE−PD Size 1050 P Inductor with 100 mH
Inductance is recommended. For the other output voltages,
the recommended inductance value from the same inductor
series can be found in table 6.
V
OUT
(V)
I
(mA)
R (mW)
CS
L (mH)
OUT
2.5
560
220
100
3.3
5
515
510
415
335
315
285
230
200
330
7.2
10
12
15
24
330
330
Table 4. INDUCTORS FOR VDD2
Product
L (mH)
R
(mW)
I
(A)
DC typ.|max.
SAT typ.
7447714101
7447714331
7447714471
100
165 | 198
655 | 750
960 | 1100
1.8
20%
20%
20%
330
470
1
390
470
0.82
The listed output current capability still contains some
headroom for a temporarily higher output current after a
load step−up transient (in order not to influence the load
transient response settling time) and for the variation of the
switching frequency due to spread spectrum modulation.
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15
NCL31000, NCL31001
Output Capacitor Selection
The output capacitor is needed to stabilize the control
loop. The gain crossover frequency of the complex open
loop gain can be estimated by:
The VDD1 and VDD2 regulators do not require any series
resistance (ESR) in the output capacitor. Therefore ceramic
capacitors with X5R or X7R dielectric are recommended.
Unfortunately for these capacitors it is usually not sufficient
to only look at the nominal capacitance value: one should
always check the Capacitance versus Bias Voltage chart to
know the actual remaining capacitance with the output
voltage applied!
1
fgc
[
(eq. 3)
2 p ACRp CVDDx
This gain crossover frequency should be significantly
lower than half the switching frequency. This places a
constraint on the minimum output capacitance value.
The recommended output capacitors for the VDD1
regulator are listed in Table 9.
Some recommended capacitors from the Kemet SMD
X5R and X7R series are listed in table 7 (Size 1206) and
table 8 (Size 1210).
Table 9. CAPACITOR(S) FOR VDD1
V
OUT
(V)
C
Component(s)
C
(mF)
VDD1
VDD
Table 7. X5R CAPACITORS SIZE 1206
3.3
19
22 mF / 6.3 V / 1206
C
VDD2
(mF @ V)
20.3 @ 2.5
19 @ 3.3
14.1 @ 5.0
9.9 @ 2.5
9.8 @ 3.3
9.5 @ 5.0
9 @ 7.2
Product
C (mF)
V
(V)
0
Rated
2 x 10 mF / 16 V / 1206
19.6
C1206C226K9PAC
C1206C226M9PAC
22
22
6.3
10%
20%
The minimum output capacitor values for the VDD2
regulator are listed in Table 10 and those listed in bold are
recommended.
C1206C106K4PAC
10
16
10%
Table 10. CAPACITOR(S) FOR VDD2
V
(V)
C
VDD2
OUT
(mF)
79.8
100.1
60.7
79.7
42.2
51.7
56.3
17.1
18
C
Component(s)
VDD
2.5
100μF / 6.3V / 1210
100 mF / 6.3 V / 1210 + 22 mF / 6.3 V / 1206
100 mF / 6.3 V / 1210
8 @ 10
6.7 @ 12
5.3 @ 15
3.1 @ 24
3.3
5
C1206C106K3PAC
C1206C475K5PAC
10
25
50
10%
10%
100 mF / 6.3 V / 1210 + 22 mF / 6.3 V / 1206
47 mF / 6.3 V/ 1210
4.7
47 mF / 6.3 V / 1210 + 10 mF / 16 V / 1206
47 mF / 6.3 V / 1210 + 22 mF / 6.3 V / 1206
22 mF / 10 V / 1210
Table 8. X5R AND X7R CAPACITORS SIZE 1210
C
VDD2
(mF @ V)
79.8 @ 2.5
60.7 @ 3.3
42.2 @ 5.0
17.1 @ 7.2
8 @ 10
Product
C (mF)
0
V
Rated
(V)
7.2
C1210C107M9PAC
100
6.3
2 x 10 mF / 16 V / 1206
20%
22 mF / 10 V / 1210 + 10 mF / 16 V / 1206
3 x 10 mF / 16 V / 1206
26.1
27
C1210C476M9PAC
C1210C226K8PAC
C1210C106K4PAC
C1210C106K3RAC
C1210C106M6PAC
47
6.3
10
16
25
35
20%
22
10
12
15
9.1
10 mF / 35 V / 1210
10%
10
16
2 x 10 mF / 16 V / 1206
10%
10
6.7 @ 15
9.1 @ 10
8.7 @ 12
8 @ 15
8.7
10 mF / 35 V / 1210
10%
10
2 x 10 mF / 16 V / 1206
13.4
8
20%
10 mF / 35 V / 1210
2 x 10 mF / 25 V / 1206
10.6
13.4
15.9
5
5 @ 24
2 x 10 mF / 25 V / 1210
3 x 10 mF / 25 V / 1206
For X5R and X7R dielectric capacitors the change in
capacitance over their operating temperature range is
limited to 15%.
24
10 mF / 35 V / 1210
2 x 4.7 mF / 50 V / 1206
6.2
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16
NCL31000, NCL31001
Transient Response
current−mode controller without compensation ramp in
A first order equivalent circuit of the output impedance of
the NCL31000 DC/DC regulators operating in CCM is
shown in figure 9.
CCM up to 33.5% duty cycle in order to keep the Q of the
p
current−mode double pole up to 1.932 (c ≥ 0.259). For a
p
peak current−mode controller with compensation ramp in
CCM, this rule of thumb for the duty cycle becomes:
0.335
VDDx
D v
L SX
ǒ
Ǔ
1 *
(eq. 7)
VOUT
ACL
ACR
C
VDDx
This duty cycle requirement in CCM can be translated into
a minimum input voltage requirement:
p
p
VIN w 2.985 (VOUT * L SX)
(eq. 8)
GND
Obviously without compensation ramp this equation
simplifies to:
Figure 9. Model for Loop Response
VIN w 2.985 VOUT
(eq. 9)
The output capacitor delivers the initial current for
transient loads. The output voltage undershoot/overshoot
after a load step up/down transient can be estimated by:
Above constraint explains why a compensation ramp is
implemented on the VDD2 regulator for the 15 V and 24 V
output voltage settings. Likewise it explains why there is no
need for a compensation ramp on the VDD1 regulator and
on the VDD2 regulator for the other output voltage settings
with an input voltage above 35 V.
The maximum input voltage is determined by the
maximum recommended operating voltage of the VBBP
pins (i.e. 57 V).
DvVDDx + * ACRp DiVDDx
(eq. 4)
On the other hand, the model explains there is a constraint
on the maximum output capacitance value. This can be
expressed by the damping factor of the parallel RLC circuit:
ACLp
1
Ǹ
c +
(eq. 5)
2 ACRp
CVDDx
Input Capacitor
It is best to keep the damping factor at or above unity. That
it is equivalent to keeping the gain crossover frequency at
least 4 times higher than the compensation network zero:
The VBB pin 41 must be decoupled to the source of the
bottom mosfets (FDC8602) with a ceramic capacitor. The
Kemet X7R Size 1210 Capacitor with 1 mF nominal
capacitance value is a good option, since the capacitance
change over DC bias voltage remains moderate.
ACRp
fz
+
(eq. 6)
2 p ACLp
Otherwise the load step response will become oscillatory.
Table 11. X7R CAPACITOR SIZE 1210
Input Voltage Range
C
VPORTP
The minimum input voltage is determined by the
NCL31000 VBB undervoltage lockout (UVLO). With
appropriate filtering, both the VDD1 and the VDD2
regulators shall continue to operate without interruption in
the presence of transients on the DC power supply.
(nF @ V)
865 @ 41.1
800 @ 50
702 @ 57
Product
C (mF)
V
(V)
0
Rated
C1210C105K1RAC
1
100
10%
VBB
4
Light Load Operation
UVLO
75 kW
820 kW
33 kW
In Discontinuous Conduction Mode (DCM), the square of
the top mosfet on−time is proportional to the output current.
When the load becomes lower than the output current
corresponding with the minimum on−time, the converter
will exhibit pulse skipping behavior.
2.2 nF
VSS
VSS
Figure 10. UVLO Filter
VDD2 Output voltage
The VDD2 output voltage is programmed in the
VDD2_SEL[2:0] bits of Test Register 10 (&TREG10
0x6E):
Eventually another constraint on the minimum input
voltage is related to the subharmonic oscillation
phenomenon that might occur in current−mode controlled
converters. A rule of thumb is to operate a peak
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17
NCL31000, NCL31001
Soft−Start
Table 12.
Both regulators have soft−start implemented in order to
limit the overshoot during start−up.
Bit [2:0]
000b
001b
010b
011b
100b
101b
110b
111b
VDD2 Output Voltage (V)
2.5
10
5
Short Circuit Protection
Besides the peak current limit, the NCL31000 contains
additional short circuit protection. If the voltage drops
significantly below the regulated value during around
15 ms, that specific converter will be shut down. The
converter will be automatically restarted after a cool down
period of around 120 ms.
15
3.3
12
7.2
24
Severe Faults
The NCL31000 monitors the drain−source voltage of a
mosfet that is turned−on: if the voltage becomes too large
due to excessive current flow through the mosfet, the
respective converter will be latched off.
If this occurs on the VDD2 regulator, the VDD2NOK bit
in the Status Positive Register (&STATP) will be set. This
will generate an interrupt on the INTB pin if the VDD2NOK
bit in the Interrupt Positive Mask Register (&INTP) was not
masked.
The default output voltage of VDD2 is 5 V.
Do NOT write to Test Register 10 when the VDD2
regulator is already enabled.
VDD2 Enable and Shutdown
The VDD2 regulator is enabled when the VDD2_EN bit
in the Control Register (&CTRL 0x04) is set.
Table 13.
Bit 0
0b
VDD2EN
Disable VDD2
Enable VDD2
1b
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18
NCL31000, NCL31001
LED DRIVER FUNCTIONAL DESCRIPTION
The NCL31000 incorporates a peak current−mode buck
current between zero and the level defined by the voltage
level on the DIM pin. The duty−cycle of this signal will
define the average LED current. To have a good linear
relationship between the duty−cycle and the LED current the
frequency of this signal must be below 1 − 2 kHz. This
method provides a simple way to use PWM directly to
control the LED current, however it does not give the best
dimming accuracy and linearity and the duty−cycle range is
limited. When the PWM digital input pin is low, the MUX
connects VLS to DIMCTRL. VLS has a steady value just
below VCSA_0 to guarantee that the LED driver is
regulating zero current when PWM = 0. When the PWM pin
is high, the voltage on the DIM pin is connected to
DIMCTRL.
When the INTDIMEN bit in the INTDIM register is set
the internal 7−bit DAC output is connected to DIMCTRL.
In this case, the LED current will depend on the value
programmed in the 7 bits of the INTDIM register. The
relationship between the register value and the DAC output
voltage is given below.
LED controller. The controller operates only in CCM mode
and is designed to drive high power LED loads up to 90 W
and beyond. A block diagram of the concept with the
essential parts is given in figure 11.
LEDEN
CLK
SLPCMP
S
Gi
OTA
LDSNSP
Go
gm
INTDIM
VLS
3:1
MUX
SS
LDCMP
PWM/EN DIM
VREF (INTDIM[7 : 0] ) 1)
VINTDIM
+
(eq. 11)
128
The internal DAC can be useful when, for example, the
host MCU is being re−flashed and the DIM voltage is not
controlled during this period. In this case the MCU can
instruct the internal DAC to take control of DIMCTRL net
moments before the MCU firmware is under maintenance.
This is called ‘Warm Boot’.
Figure 11. LED Driver Block Diagram
The LED driver is enabled when the LEDEN bit in the
CTRL register is set. When the LED driver is enabled it is
switching and regulates a current controlled by the
DIMCTRL voltage shown in figure 11. The relationship
between DIMCTRL and the LED current is given below.
Voltage Reference
The NCL31000 provides a precise ( 0.3%) 2.4 V
reference voltage on the VREF pin, which can be used by
external components, for example, as the reference of an
external PWM to DIM circuit or a DAC that controls the
DIM pin voltage. The load on this pin must be limited to
2 mA to ensure the accuracy of the voltage. The advantage
of using this VREF is that the VREF voltage and the
VCSA_0 voltage (the threshold point for zero current) are
related. If VREF deviates, VCSA_0 will deviate in the same
direction by a proportional factor, thus the LED current
regulation inaccuracy of a circuit that is VREF based does
not suffer from the VREF deviation.
(VDIMCTRL * VCSA_0
)
ILED
+
(eq. 10)
RSNS 7.333
Several sources can be multiplexed to the DIMCTRL
signal, see figure 12.
Sense Resistor
Select an appropriate sense resistor based on the
maximum LED current. The resistor value can be calculated
according to:
Figure 12. DIM Selection
The analog DIM input gives the best dimming
performance in terms of linearity, bandwidth and accuracy.
The DIM pin threshold voltage that provides exactly zero
current is the VCSA_0 voltage. Applying a voltage below
the VCSA_0 lower limit guarantees zero current.
(VREF * VCSA_0)
RS
+
(eq. 12)
7.333 Iledmax
Make sure to select a sense resistor that has a value
between 50 mW and 300 mW. Consider the power rating and
the accuracy. A 1 W or 2 W / 1% sense resistor is sufficient
for most applications.
The PWM pin can be used for PWM dimming. A PWM
signal on the PWM input can be used to switch the LED
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19
NCL31000, NCL31001
Buck Inductor
Slope Compensation
The rule of thumb is to choose the inductor so that the
peak−peak current ripple in the inductor is 20..30% of the
max dc−current. Calculate the required inductance
according to:
Since a peak−current−mode buck convertor is sensitive to
sub−harmonic oscillations for duty−cycles above 33% slope
compensation must be added. There is a minimum amount
of slope needed to damp sub−harmonic oscillations within
one switching cycle. The slope value can be programmed in
the SLPCMP register. The default value is a good setting for
most applications and normally no changes have to be made
to this register. If the phase margin is not sufficient
(<60 degrees), program ‘0’ to SLP1 and SLP2 field in the
SLPCMP register.
The required amount of slope increases with output
voltage and the ratio from output to input voltage
(duty−cycle). A separate slope setting can be programmed
for slopes below 50% duty−cycle (SLP1 field) and above
(SLP2 field). The possibilities for SLP1 and SLP2 fields are
presented in table 14 and 15 respectively. The default value
for SLP1 and SLP2 is set to 0.1 V/ms and 0.3 V/ms. Increase
SLP1 one level if sub−harmonic oscillation is seen below
50% duty−cycle. Increase SLP2 one level if subharmonic
oscillation is seen above 50% duty−cycle.
Vi
L +
(eq. 13)
4 fs Iledmax 0.3
Make sure that the specified RMS current rating of the
inductor (typically the current that results in a temperature
increase of 40°C due to copper losses) is at or above the max
dc−current used in the application. The saturation current
rating minus 20% derating should still be at or above the
largest peak current. Use the formulas below to find
appropriate minimum RMS current and saturation current
values.
Irms u Iledmax
(eq. 14)
Vimax
Irmax*pkpk
+
(eq. 15)
(eq. 16)
4 fs L
Irmax*pkpk
Isat u ǒIledmax )
Ǔ
1.2
2
Table 14. SLP1 VALUES
Output Capacitor
SPL1 Register Value
Slope [V/ms]
The purpose of the output capacitor is to filter the high
frequency inductor ripple current to some extent. This must
be a 100 V rated ceramic capacitor(s) with low ESR. The
required output capacitor depends on the switching
0
1
2
3
0.1
0.2
0.3
0.4
frequency, the expected LED ripple current (Ir
), the
LED−pkpk
dynamic resistance of the LED string (Rd) and the inductor
ripple current (Ir
). The expression is given below:
max−pkpk
Table 15. SLP2 VALUES
Irmax*pkpk
8
p2
CO
+
SPL2 Register Value
Slope [V/ms]
(eq. 17)
2p fs IrLED Rd
0
1
2
3
0.3
0.4
0.6
0.9
Substituting Ir
gives:
max
Vimax
CO
+
31 fs2 L IrLED*pkpk Rd
(eq. 18)
A reasonable output capacitor value would be anything
between 100 nF and 1 − 3 mF. Try to avoid 1608 (metric)
packages or smaller to avoid audible noise. The output
capacitance has no significant effect on stability.
Switching Frequency
All the clocks in the chip are derived from a main 8 MHz
clock. The LED driver’s switching frequency can be
programmed with the LEDFC register. The value in the
register relates to the LED driver switching frequency clock
according to table 16. The default switching frequency is
500 kHz. For most applications that regulate LED currents
below 1.5 A, a switching frequency of 500 kHz is a good
choice. For applications that regulate above 1.5 A, 400 kHz
is recommended.
Bandwidth & Stability
The control loop in this configuration exhibits no poles to
be compensated in the bandwidth area so a single
compensation capacitor connected to LDCMP pin will
th
suffice. This strategy is suitable for a bandwidth up to 1/10
of the switching frequency and provides a phase margin of
60 − 75 degrees. The compensation capacitor can be
calculated as:
GM
CC + 2.44
(eq. 19)
2 p fC
f is the wanted cross−over frequency and G = 1 mS.
C
M
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20
NCL31000, NCL31001
Table 16. SWITCHING FREQUENCY
Table 17. TRANSISTOR SELECTION
LEDFC [5:0]
DIVISOR
8
LED_CLK [kHz]
Product
V
(V)
r
(mW)
DS(on)
DS
Top
NVTFS6H880N
NVTFS6H888N
NVTFS6H860N
FDMA037N08LC
80
32
0
1
1000.00
800.00
666.67
571.43
500.00
444.44
400.00
363.64
333.33
307.69
285.71
250.00
235.29
210.53
190.48
173.91
153.85
142.86
125.00
114.29
105.26
95.24
10
80
80
80
55
2
12
21.1
36.5
3
14
Bottom
4
16
Do not use external gate resistors for the transistors. The
chip uses the voltages at the gate nodes as feedback for
desaturation protection and fast switching.
5
18
6
20
7
22
Thermal Considerations
8
24
Additional copper is needed for good thermal
performance. A typical design with LED currents below 2 A
(<60 W) requires a small (both copper sides) cooling plane
9
26
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
2
with size 2 − 3 cm connected to the drain of the top fet. For
32
2
2 A and above (>60 W), a 3 − 4 cm copper plane is
recommended on both sides. The bottom fet drain
connection should also have a small 0.5 − 1 cm copper
34
2
38
plane.
42
Metrology
46
The NCL31000 incorporates a high accuracy metrology
block that measures several voltages, currents and
temperatures in the system. This is made possible by an
internal 10−bit ADC, which is multiplexed to measure VBB,
VDD11, VDD2, VLED, ILED, IBB, IVDD1, IVDD2 and
TLED. The metrology measurements can be enabled with
the DIAG_EN bit in the CTRL register. The measurements
are referenced to GND and are sampled every 100 ms. The
measurements can be read out from the 16−bit registers. The
52
56
64
70
76
84
102
112
124
150
180
78.43
relationship
between
the
measured
71.43
voltage/current/temperature and the values read in the
registers is given below.
64.52
53.33
5000
201
VREF
216
VBB + VBBreg
(eq. 20)
(eq. 21)
(eq. 22)
(eq. 23)
(eq. 24)
(eq. 25)
(eq. 26)
(eq. 27)
(eq. 28)
44.44
VREF
6 Rs 216
IBB + IBBreg
Switching Transistors
The selection of the switching transistors is a critical
aspect for the correct functioning of the LED driver. It can
significantly impact the power efficiency and thermal
performance. The top fet in particular will dissipate most of
the switching losses. Because this component is essential to
the LED driver performance it is advised to select one of the
validated transistors for top and bottom given in table 17.
The transistors are ranked high−low for efficiency. The
typical LED driver efficiency achievable with the proposed
transistors for 30 − 70 W range is 97%. The best combination
is to use FDMA037N08L as bottom fet and NVTFS6H880N
or NVTFS6H888N as top fet.
3
2
VREF
216
VDD + VDDreg
30
VREF
216
VDD2 + VDD2reg
4
VREF
10 Rs 216
IDD + IDDreg
VREF
IDD2 + IDD2reg
VLED + VLEDreg
10 Rs 216
35
2
VREF
216
3
VREF
ILED + ILEDreg
Rs 216
22
33
VREF
216
TLED + TLEDreg
24
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21
NCL31000, NCL31001
TLED
Status Bits
The NCL31000 has ten status−monitoring bits, spread
over two 8−bit registers. The status bits are active when a
particular condition is met. As an example, STAT1.TW is
active when the internally measured temperature exceeds
the temperature limit set by the TWTH (thermal warning
threshold). When the condition disappears, the
corresponding bit becomes inactive immediately. The
actual, immediate, value of the status bits can be accessed
through the read−only status registers (STAT). Status bits
can become active only very briefly. As such, reading the
STAT is not sufficient to detect the activation of a fault in an
NCL31000 device: between subsequent reads, the fault
could have appeared and disappeared. The read−only
‘Status Positive Transition’ register (STATP) addresses this
problem. It reflects all status bits that have become active
since the last read of the STATP. Thus, by reading STAT and
STATP, the host microcontroller can determine whether a
status bit has been active since the last read, and whether it
is still active. The STATP bits are cleared on read. The
addresses of the STAT and STATP are contiguous. Thus the
microcontroller can read out the STAT and STATP
atomically, ensuring coherent information is received.
In addition to STATP, the ‘Status negative transition’
STATN register activates when the fault disappears
(negative edge STAT register). This register is also cleared
on read. The status signals are grouped in two categories:
warnings and errors. This is discussed below.
LEDTW_H
LEDTW_L
MCU READ
STAT + STATP
MCU READ
STAT + STATN
STAT.LEDTW
STATP.LEDTW
STATN.LEDTW
INTb
LEDTW_H = LEDTWTH + LEDTWHYS
LEDTW_L = LEDTWTH − LEDTWHYS
Figure 13. LEDTW [INTCFG=1 INTP/INTN=1]
TLED
LEDTW_H
LEDTW_L
MCU READ
STAT + STATP
MCU READ
STAT + STATN
STAT.LEDTW
STATP.LEDTW
STATN.LEDTW
INTb
LEDTW_H = LEDTWTH + LEDTWHYS
LEDTW_L = LEDTWTH − LEDTWHYS
Warnings
Figure 14. LEDTW [INTCFG=0 INTP/INTN=1]
Some of the status bits can be considered as a warning
signal meaning there is no need for a very fast response from
the NCL31000 itself and the decision can be left up to the
microcontroller. The NCL31000 takes no action other than
signal that a threshold is crossed using the status bits. The
status bits that are considered as warnings are: TW,
LEDTSD, LEDTW, LEDOV, LEDUV, VDD2OC,
VDD1OC. These warnings are reflected in the STAT1 and
STATP1/STATN1 registers. These analog values are
measured by the metrology block with the internal ADC and
a sampling rate of 100 ms. For the warnings, all the
thresholds and hysteresis values are programmable except
for TW. An example for LEDTW is given in figures 13 and
14.
A warning occurs when a programmable limit is crossed.
For example, when the voltage on the TLED pin exceeds the
LEDTWTH + LEDTWHYS threshold the status LEDTW
bit is set in the STAT register. The threshold and hysteresis
are programmable in the LEDTWTH and LEDTWHYS
registers. Only when the voltage on the TLED pin drops
below LEDTWTH − LEDTWHYS the LEDTW bit in the
STAT is cleared. If the LEDTW bit in the Interrupt Mask
register is set a pulse interrupt will be given on the INTb pin
when the LEDTW bit is set in the STAT. The warnings
except TW are disabled when LEDTWTH + LEDTWHYS
> 1022. All warnings except TW are disabled by default
because they have 1023 in their threshold registers. All the
warnings are explained below.
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22
NCL31000, NCL31001
MCU DISABLES LED
CTRL.LEDEN = 0
TW: Thermal Warning
The TW bit in the STAT is set if the junction temperature
of the NCL31000 goes above TW_H. This warning is active
by default and cannot be de−activated. This threshold is not
programmable.
DESAT LEVEL
MCU READ
MCU RESET LED
STAT + STATP
CTRL.LEDEN = 1
LEDNOK
TH
LEDTW: LED Thermal Warning
This warning will occur if the voltage on TLED pin is
above LEDTWTH + LEDTWHYS. Typically, an NTC is
mounted on the LED load and connected to TLED and
GND. This warning is not active by default and the threshold
and hysteresis are programmable.
STAT.LEDNOK
STATP.LEDNOK
STATP CLEAR ON READ
LED driver DISABLED
LED driver state
LEDTSD: LED Thermal Shutdown
INTb
This warning will occur if the voltage on TLED pin is
above LEDTSD + LEDTSDHYS. Typically, an NTC is
mounted on the LED load and connected to TLED and
GND. This warning is not active by default and the threshold
and hysteresis are programmable.
Figure 15. LEDNOK [INTCFG=1 INTP=1 INTN=X]
MCU DISABLES LED
CTRL.LEDEN = 0
DESAT LEVEL
MCU READ
MCU RESET LED
STAT + STATP
CTRL.LEDEN = 1
LEDOV: LED Overvoltage
LEDNOK
TH
This warning will typically occur if the LED string is an
open circuit. The LEDOV bit in the STAT is set if the VLED
pin voltage goes above LEDOVTH + LEDOVHYS. The
threshold and hysteresis are programmable.
STAT.LEDNOK
STATP.LEDNOK
LEDUV: LED Undervoltage
STATP CLEAR ON READ
LED driver DISABLED
This warning will typically occur if the LED string is a
short circuit. The LEDUV bit is set in the STAT. This
warning is not active by default and the threshold and
hysteresis are programmable.
LED driver state
INTb
VDD1OC and VDD2OC: VDD1x Overcurrent
Figure 16. LEDNOK [INTCFG=0 INTP=1 INTN=X]
A warning is given if the average current is above
VDD1xOCTH + VDD1xOCHYS. Note that the DC−DC’s
also have a current limiting hick−up mode built−in. This
warning is not active by default and the threshold and
hysteresis are programmable.
An error indicates that there is a hardware issue. Further
explanation for each of the errors is given below.
TSD: Thermal Shutdown
When the junction temperature of the NCL31000 reaches
TSD_H, the NCL31000 will shut down all functions and go
into reset state. The device will remain in reset until the
junction temperature drops below TSD_L.
Errors
There are severe error conditions that require NCL31000
to disable the block that triggered the error immediately
before any damage can occur. These are LEDNOK, LEDOC
and VDD2NOK. These errors are reflected in the STAT2
and STATP2/STATN2 registers. The STAT signals behavior
is the same for errors and warnings. Note that typically
STATN has no use for errors because the fault is gone when
the micro−controller reads the registers.
In case of a desaturation fault during the switching of the
transistors in the LED driver a LEDNOK error is triggered
and NCL31000 will disable the LED driver block.
NCL31000 will remain disabled until the LEDEN bit is reset
by the user. Similarly if a desaturation fault occurs in the
DC−DC2 block a VDD2NOK error is triggered and the
DC−DC2 block is disabled. A LEDOC error is triggered if
the LED driver sense resistor voltage crosses the OCP_TH
threshold indicating a LED overcurrent. The LED block is
disabled and resumes after a reset of the LEDEN bit. See
figures 15 and 16 for clarification.
VDD2NOK: Desaturation Error Switching Transistors
NCL31000 will shut−down DC−DC2 if this error occurs.
DC−DC2 can be restarted if VDD2EN bit in CTRL is reset.
LEDNOK: Desaturation Error Switching Transistors
NCL31000 will shut−down LED block if this error
occurs. The LED block can be restarted if LEDEN bit in
CTRL is reset.
LEDOC: LED Overcurrent
This error can occur if the LED load wires are not well
connected to the driver board and contact−bounce occurs. A
sudden failure of the sense resistor can also trigger this error.
NCL31000 will shut−down the LED block if this error
occurs and set the LEDOC bit in the STATP.
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23
NCL31000, NCL31001
Interrupts
The FMOD register value affects the modulation period
(Tmod) of the triangular signal. The default value for fmod
is 400 Hz. The value in the FMOD register relates to fmod
according to table 19.
The NCL31000 has a flexible interrupt mechanism that
obviates the need for frequent polling. With an appropriate
configuration of the two interrupt mask registers (INTP and
INTN), most applications will not require polling at all,
while providing for coherent status awareness in the host
microcontroller. When an interrupt is triggered, INTb is
Table 19. MODULATION FREQUENCY
FMOD [1:0]
fmod (1/Tmod)
200 Hz
2
pulled low. INTb is an open−drain pin to ensure multiple I C
0
1
2
3
bus participants can share the same interrupt line. A pull−up
resistor must be provided externally. The NCL31000
provides an open−drain, active−low interrupt pin that
activates, i.e. pulled low, when any interrupt condition is
satisfied. An interrupt condition is satisfied if any of the bits
in the STATP or STATN register is active and if the
corresponding bit in the INTP and INTN are unmasked
(= set).
400 Hz
800 Hz
1600 Hz
The spread spectrum is illustrated with figure 17.
If CTRL.INTCFG is zero (default) level interrupt is used
and INTb goes low as long as the interrupt condition is
satisfied. If CTRL.INTCFG is set, INTb is configured for
pulsed interrupt and INTb will go low for about 10us every
time the interrupt condition is satisfied.
Ts + DT
Ts (125 ms)
Spread Spectrum
Ts − DT
The purpose of spread spectrum is to continuously change
the clock frequency used by the switching convertors in a
periodic pattern to reduce the detected energy levels at a
given frequency. It will improve the results of conducted
EMI tests, not for radiated EMI. The spread spectrum block
modulates the main 8 MHz clock according to a number of
discrete steps in a triangular pattern as shown in figure 17.
The spread clock signal is used by digital, LED driver and
DC−DC convertors. The spread spectrum is disabled by
default and can be enabled with the JIT_EN bit in the
LEDFC register. The amount of spreading can be configured
with the FDEV register. The deviation (%) is the amplitude
variation towards the main clock. When the main clock is
divided the same amount of spread (%) is still present on the
divided clock. Table 18 relates the value for FDEV register
to the amount of spreading. The default spreading when
spread spectrum is enabled is 3%.
Tmod
t
Figure 17. Spread Spectrum
Both fmod and fdev affect the modulation index of the
frequency modulated clock signal.
fdev
MI +
(eq. 29)
fmod
More suppression is achieved when the modulation index
is higher. This is true if the RBW of the spectrum analyzer
would be infinitely small, instead the RBW is 9 kHz for
conducted emission measurements (150 kHz to 30 MHz)
and 120 kHz for radiated emission measurements (30 MHz
to 1 GHz). When the RBW is 9 kHz the spectrum analyzer
will show better suppression if fmod has the maximum
value.
Address Selection (NCL3100xI)
Table 18. FREQUENCY DEVIATION
The NCL31000 comes in two variants. One with SPI
FDEV [2:0]
D (%)
3
2
interface and one with I C interface. This is defined by OTP
0
1
2
3
4
5
6
7
(One−time programmable memory) in the chip. In case the
2
5
device is configured as I C slave the ADDR1 and ADDR2
2
pins define the I C slave bus address. The device can have
6
2
6 possible I C slave addresses to differentiate devices on the
8
2
same I C−bus. The mapping between the logic level on these
2
10
11
12.5
14
pins and the I C slave address is given in table 20.
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24
NCL31000, NCL31001
Table 20. SLAVE ADDRESS
ADDR1_CSB
GND
ADDR2_MISO
Slave Address
GND
VDD1
GND
0x50 (1010000)
0x52 (1010010)
0x54 (1010100)
0x56 (1010110)
0x58 (1011000)
0x5A (1011010)
VDD1
FLOAT
GND
VDD1
GND
Figure 19. I2C Read Operation (1 byte)
VDD1
FLOAT
VDD1
I2C Interface (NCL3100xI)
2
The I C interface can be used to interface with the
NCL31000I in order to read or write its registers. The
2
NCL3100I operates as an I C slave device. The SDA and
2
SCL lines comply with the I C electrical specification and
Figure 20. I2C Read Operation (2 bytes or More)
should be terminated with external pull−up resistors. The
device supports the maximum bus speed of 400 kbit/s.
Figure 18 shows how an I C write operation is performed.
SPI Interface (NCL3100xS)
2
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
NCL31000S. The device acts always as a Slave and cant
initiate any transmission. The operation of the device is
configured and controlled by means of registers which are
observable for read and/or write from the Master. ’
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (SCL/CLK) synchronizes shifting and
sampling of the information on the two serial data lines,
MOSI (SDA_MOSI pin) and MISO (ADDR2_MISO pin).
The MISO signal is the output from the slave and MOSI is
the master output.
The master gives the Start condition followed by the 7−bit
slave address and the read−write bit. The slave
acknowledges the address. The master then places the
register address on the bus. This is again acknowledged by
the slave. Finally the data byte is placed on the bus by the
master. The slave must acknowledge this. The master can
write more than one byte in one transaction if he wishes.
Writing to the registers in this case is contiguous. As more
data bytes follow, the register address is auto−incremented.
NCL31000S is configured for SPI MODE 2. This means
that the signal on the MOSI/MISO data lines is sampled on
the negative clock edge and that the CLK signal is high when
idle. Note that the NCL31000S expects the first data signal
to be present and stable on the first negative clock edge.
Figure 21 shows how to perform a SPI write operation.
The master pulls the chip select signal low and a little later
the master provides a minimum sequence of 16 clock cycles.
During the first eight clock cycles, the master provides the
register address [A6:A0] and the read−write bit on the MOSI
line. If the read−write bit is high, a read operation is selected.
During the following eight clock cycles, the slave clocks in
the data byte [D7:D0]. If the master provides a multiple of
eight clock cycles, more bytes can be written contiguously.
The register counter is automatically incremented.
Figure 22 demonstrates a SPI read operation. The same
principle applies as with a write operation only now the slave
puts the contents of the addressed register on the MISO line
during the last eight clock cycles. If the master provides a
multiple of eight clock cycles more registers can be read
contiguously.
Figure 18. I2C Write Operation (2 bytes)
2
Figure shows how to perform an I C read operation. The
first part of a read operation is the same as for a write
operation. The master provides the slave address, write bit,
and register address were to read from. It then provides a
repeated start condition which behaves the same as a start
condition. It provides the slave address again, but this time
it uses it makes the read−write bit zero to indicate a read
operation. The slave acknowledges and places the requested
data byte on the bus. If the master responds with a NACK
(not acknowledge) and a STOP condition the message
transaction is terminated. If instead the master uses an ACK
it indicates to the slave that it wants to read more bytes. The
slave will auto−increment the register address to read from
and put the bytes on the bus as shown in Figure 20.
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25
NCL31000, NCL31001
Multiple SPI slaves can be used with one SPI master as
shown in figure 23. A separate CSB signal is required for
each slave. Daisy chaining is not supported.
Figure 21. SPI Write Operation (1 byte)
Figure 22. SPI Read Operation (1 byte)
Figure 23. SPI Multi Slave
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26
NCL31000, NCL31001
REGISTER MAP
Table 21. REGISTER MAP
Addr
Name
RID1
Reset Bits
MSB
LSB
00
H
01
H
02
H
03
H
04
H
05
H
06
H
07
H
08
H
09
H
00
H
75
H
7:0
7:0
MANUF_H
RID2
MANUF_L
PART_L
PART_H
REV
RID3
8C
7:0
H
H
H
H
H
H
H
H
H
H
H
H
H
Rsv.
00
00
00
00
00
00
00
00
00
00
00
00
7:0
Rsv.
CTRL
STAT1
STAT2
STATP1
STATP2
STATN1
STATN2
INTP1
INTP2
INTN1
INTN2
VBB
7:0
INTCFG
Rsv.
Rsv.
DIAG_EN LED_EN VDD2_EN
LEDUV VDD2OC VDD11OC
LEDOC LEDNOK VDD2NOK
LEDUV VDD2OC VDD11OC
LEDOC LEDNOK VDD2NOK
LEDUV VDD2OC VDD11OC
LEDOC LEDNOK VDD2NOK
LEDUV VDD2OC VDD11OC
LEDOC LEDNOK VDD2NOK
LEDUV VDD2OC VDD11OC
LEDOC LEDNOK VDD2NOK
7:0
TW
TW
TW
TW
TW
LEDTSD LEDTW
Rsv.
LEDOV
LEDOV
LEDOV
LEDOV
LEDOV
7:0
7:0
Rsv.
Rsv.
Rsv.
Rsv.
LEDTSD LEDTW
Rsv.
7:0
7:0
LEDTSD LEDTW
Rsv.
0A
H
0B
H
7:0
7:0
LEDTSD LEDTW
Rsv.
0C
0D
7:0
H
H
H
H
7:0
LEDTSD LEDTW
Rsv.
0E
7:0
10
12
14
16
18
0000
0000
0000
0000
0000
0000
0000
0000
0000
15:8
7:0
ADCv
H
H
H
H
H
H
H
H
H
ADCv
Rsv.
IBB
VDD11
15:8
7:0
ADCv
ADCv
ADCv
ADCv
ADCv
ADCv
ADCv
ADCv
val
H
H
H
H
ADCv
ADCv
ADCv
ADCv
ADCv
ADCv
ADCv
ADCv
val
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
15:8
7:0
IDD1
15:8
7:0
VDD2
15:8
7:0
1A
H
IDD2
15:8
7:0
1C
VLED
15:8
7:0
H
H
H
H
H
H
1E
ILED
15:8
7:0
20
22
24
26
TLED
15:8
7:0
VDD11OCTH
VDD2OCTH
TLEDTWTH
FFFF
FFFF
FFFF
15:8
7:0
H
H
H
15:8
7:0
val
val
15:8
7:0
val
val
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27
NCL31000, NCL31001
Table 21. REGISTER MAP (continued)
Addr
28
Name
Reset Bits
MSB
LSB
TLEDTSDTH
FFFF
FFFF
FFFF
15:8
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
val
val
val
H
H
H
H
val
val
val
Rsv.
Rsv.
Rsv.
2A
H
VLEDOVTH
VLEDUVTH
2C
H
30
H
31
H
32
H
33
H
34
H
35
H
40
H
41
H
42
H
50
H
51
H
52
H
VDD11OCTH_HYS 0A
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
Rsv.
EN
val
val
H
H
H
H
H
H
H
H
VDD2OCTH_HYS
TLEDTWTH_HYS
0A
0A
val
TLEDTSDTH_HYS 0A
val
VLEDOVTH_HYS
VLEDUVTH_HYS
INTDIM
0A
0A
val
val
00
04
DACv
FREQ
LEDFC
JIT_EN
SLCMP
0A
Rsv.
SLP2
SLP1
val
H
H
H
H
MPS
84
06
01
EN
DELTA
FDEV
Rsv.
SSLUT_DIS
Rsv.
FDEV
FMOD
Rsv.
REGISTER RID1
Manufacturer, part and revision identification.
7
6
5
4
3
2
1
0
MANUF_H
r
0
Bits 0–7, MANUF_H: Manufacturer ID.
REGISTER RID2
Manufacturer, part and revision identification.
7
6
5
4
3
2
1
0
MANUF_L
PART_H
r
r
7
5
Bits 4–7, MANUF_L: Manufacturer ID
Bits 0–3, PART_H:
Part ID
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28
NCL31000, NCL31001
REGISTER RID3
Manufacturer, part and revision identification.
7
6
5
4
3
2
1
REV
r
0
PART_L
r
11
H
4
Bits 3–7, PART_L: Part ID.
Bits 0–2, REV:
Revision ID.
1: N1A
2: O1A
3: P1A
4: Q1A
REGISTER CTRL
Control register for the major blocks in the system.
7
INTCFG
r/w
6
5
4
3
2
1
0
Rsv.
DIAG_EN LED_EN VDD2_EN
r
r/w
0
r/w
0
r/w
0
0
0
Bit 7, INTCFG:
Bits 3–6:
Define how the interrupt on the INTB line behaves.
0: The INTB pin is pulled low when a interrupt occurs. It stays low until the STATPx registers are read
and provided the alert condition is gone (STATx register bits are cleared).
1: A pulse is given on each interrupt by the INTB pin.
Reserved, do not use.
Bit 2, DIAG_EN: The diagnostics function measures voltages, currents and temperatures in the system using the internal
ADC.
0: Diagnostics block is disabled.
1: Diagnostics block is enabled.
Bit 1, LED_EN:
Enable bit for the LED driver.
0: LED driver is disabled.
1: LED driver is enabled.
Bit 0, VDD2_EN: Enable bit for DC/DC2 converter.
0: DC/DC2 is disabled.
1: DC/DC2 is enabled.
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29
NCL31000, NCL31001
REGISTER STAT1
A signal/alert is currently active.
7
6
5
4
3
2
1
0
Rsv. TW LEDTSD LEDTW
LEDOV
LEDUV VDD2OC VDD11OC
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
Bit 7:
Reserved, do not use.
Bit 6, TW:
Thermal warning of the chip.
0: Alert is not active.
1: Alert is active.
Bit 5, LEDTSD:
Bit 4, LEDTW:
Bit 3, LEDOV:
Bit 2, LEDUV:
Bit 1, VDD2OC:
Bit 0, VDD11OC:
LED Thermal shutdown. Is active if the voltage on the TLED pin is above TLEDTSDTH +
TLED_TSDTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDTSDTH −
TLED_TSDTH_HYST.
0: Alert is not active.
1: Alert is active.
LED Thermal warning. Is active if the voltage on the TLED pin is above TLEDTWTH +
TLED_TWTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDWTH −
TLED_TWTH_HYST.
0: Alert is not active.
1: Alert is active.
LED Overvoltage. Is active if the voltage on the VLED pin is above VLEDOVTH +
VLED_OVTH_HYST threshold. Becomes false if the VLED voltage drops below VLEDOVTH −
VLED_OVTH_HYST.
0: Alert is not active.
1: Alert is active.
LED Undervoltage. Is active if the voltage on the VLED pin is below VLEDUVTH −
VLED_UVTH_HYST threshold. Becomes false if the VLED voltage is above VLEDUVTH +
VLED_UVTH_HYST.
0: Alert is not active.
1: Alert is active.
VDD2 Overcurrent. Is active if the IDD2 current is above VDD2OCTH + VDD2_OCTH_HYST
threshold. Becomes false if the VDD2OCTH current is below VDD2_OCTH_UVTH +
VDD2_OCTH_HYST.
0: Alert is not active.
1: Alert is active.
VDD11 Overcurrent. Is active if the IDD1 current is above a fixed limit.
0: Alert is not active.
1: Alert is active.
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NCL31000, NCL31001
REGISTER STAT2
A signal/alert is currently active.
7
6
5
Rsv.
r
4
3
2
1
0
LEDOC LEDNOK VDD2NOK
r
r
r
0
0
0
0
Bits 3–7:
Bit 2, LEDOC:
Reserved, do not use.
LED Overcurrent. Is active if this condition is true: ILED x Rsns x 22.0 / 3.0 > 3.
In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the
LED driver.
The LED current will drop immediately and the LEDOC bit in this register will be cleared before the
MCU can read it and the LEDOC bit in the STATP register will be set indicating a LED overcurrent event
occured.
0: Alert is not active.
1: Alert is active.
Bit 1, LEDNOK:
LED desaturation error. Is active if a severe error occured in one of the switching transistors of the LED
driver.
In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the
LED driver.
The LED current will drop immediately and the LEDNOK bit in this register will be cleared before the
MCU can read it and the LEDNOK bit in the STATP register will be set indicating there is a severe issue
with the transistors.
This error indicates something is wrong with the hardware of the LED driver.
0: Alert is not active.
1: Alert is active.
Bit 0, VDD2NOK: VDD2 desaturation error. True if a severe error occured in of the switching transistors of the DC/DC2
converter.
In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the
DC/DC1.
The VDD2 current will drop immediately and the VDD2NOK bit in this register will be cleared before
the MCU can read it and the VDD2NOK bit in the STATP register will be set indicating there is a severe
issue with the transistors.
This error indicates something is wrong with the hardware of the VDD2 DC/DC1.
0: Alert is not active.
1: Alert is active.
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NCL31000, NCL31001
REGISTER STATP1
A signal has become active since the last read to this register.
7
6
5
4
3
2
1
0
Rsv. TW LEDTSD LEDTW LEDOV
LEDUV VDD2OC VDD11OC
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
Bit 7:
Bit 6, TW:
Reserved, do not use.
Thermal warning of the chip.
0: Alert is not active.
1: Alert is active.
Bit 5, LEDTSD:
Bit 4, LEDTW:
Bit 3, LEDOV:
Bit 2, LEDUV:
Bit 1, VDD2OC:
Bit 0, VDD11OC:
LED Thermal shutdown. True as long as the voltage on the TLED pin is above TLEDTSDTH +
TLED_TSDTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDTSDTH −
TLED_TSDTH_HYST.
0: Alert is not active.
1: Alert is active.
LED Thermal warning. True as long as the voltage on the TLED pin is above TLEDTWTH +
TLED_TWTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDWTH −
TLED_TWTH_HYST.
0: Alert is not active.
1: Alert is active.
LED Overvoltage. True as long as the voltage on the VLED pin is above VLEDOVTH +
VLED_OVTH_HYST threshold. Becomes false if the VLED voltage drops below VLEDOVTH −
VLED_OVTH_HYST.
0: Alert is not active.
1: Alert is active.
LED Undervoltage. True as long as the voltage on the VLED pin is below VLEDUVTH −
VLED_UVTH_HYST threshold. Becomes false if the VLED voltage is above VLEDUVTH +
VLED_UVTH_HYST.
0: Alert is not active.
1: Alert is active.
VDD2 Overcurrent. True as long as the IDD2 current is above VDD2OCTH + VDD2_OCTH_HYST
threshold. Becomes false if the VDD2OCTH current is below VDD2_OCTH_UVTH +
VDD2_OCTH_HYST.
0: Alert is not active.
1: Alert is active.
VDD11 Overcurrent. True as long as the IDD1 current is above a fixed limit of ....
0: Alert is not active.
1: Alert is active.
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NCL31000, NCL31001
REGISTER STATP2
A signal has become active since the last read to this register.
7
6
5
Rsv.
r
4
3
2
1
0
LEDOC LEDNOK VDD2NOK
r
r
r
0
0
0
0
Bits 3–7:
Bit 2, LEDOC:
Reserved, do not use.
LED Overcurrent. True as long as this condition is true: ILED x Rsns x 22.0 / 3.0 > 3.
In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the
LED driver.
The LED current will drop immediately and the LEDOC bit in this register will be cleared before the
MCU can read it and the LEDOC bit in the STATP register will be set indicating a LED overcurrent
event occured.
0: Alert is not active.
1: Alert is active.
Bit 1, LEDNOK:
LED desaturation error. True if a severe error occured in of the switching transistors of the LED driver.
In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the
LED driver.
The LED current will drop immediately and the LEDNOK bit in this register will be cleared before the
MCU can read it and the LEDNOK bit in the STATP register will be set indicating there is a severe issue
with the transistors.
This error indicates something is wrong with the hardware of the LED driver.
0: Alert is not active.
1: Alert is active.
Bit 0, VDD2NOK: VDD2 desaturation error. True if a severe error occured in of the switching transistors of the DC/DC2
converter.
In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the
DC/DC1.
The VDD2 current will drop immediately and the VDD2NOK bit in this register will be cleared before
the MCU can read it and the VDD2NOK bit in the STATP register will be set indicating there is a severe
issue with the transistors.
This error indicates something is wrong with the hardware of the VDD2 DC/DC1.
0: Alert is not active.
1: Alert is active.
REGISTER STATN1
A signal has become inactive since the last read to this register.
7
6
5
4
3
2
1
0
Rsv. TW LEDTSD LEDTW LEDOV
LEDUV VDD2OC VDD11OC
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
This register has the same structure as STATP1; refer there for more information.
REGISTER STATN2
A signal has become inactive since the last read to this register.
7
6
5
Rsv.
r
4
3
2
1
0
LEDOC LEDNOK VDD2NOK
r
r
r
0
0
0
0
This register has the same structure as STATP2; refer there for more information.
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33
NCL31000, NCL31001
REGISTER INTP1
Interrupt enable register for STATP1. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.
7
6
5
4
3
2
1
0
Rsv. TW LEDTSD LEDTW LEDOV
LEDUV VDD2OC VDD11OC
r
r/w
0
r/w
0
r/w
0
r/w
0
r/w
0
r/w
0
r/w
0
0
Bit 7:
Reserved, do not use.
Bit 6, TW:
Thermal warning.
0: Interrupt disabled/masked.
1: Interrupt enabled.
Bit 5, LEDTSD:
Bit 4, LEDTW:
Bit 3, LEDOV:
Bit 2, LEDUV:
Bit 1, VDD2OC:
Bit 0, VDD11OC:
LED Thermal shutdown.
0: Interrupt disabled/masked.
1: Interrupt enabled.
LED Thermal warning.
0: Interrupt disabled/masked.
1: Interrupt enabled.
LED Overvoltage.
0: Interrupt disabled/masked.
1: Interrupt enabled.
LED Undervoltage.
0: Interrupt disabled/masked.
1: Interrupt enabled.
VDD2 Overcurrent.
0: Interrupt disabled/masked.
1: Interrupt enabled.
VDD11 Overcurrent.
0: Interrupt disabled/masked.
1: Interrupt enabled.
REGISTER INTP2
Interrupt mask register for STATP2. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.
7
6
5
Rsv.
r
4
3
2
1
0
LEDOC LEDNOK VDD2NOK
r/w
0
r/w
0
r/w
0
0
Bits 3–7:
Bit 2, LEDOC:
Reserved, do not use.
LED Overcurrent.
0: Interrupt disabled/masked.
1: Interrupt enabled.
Bit 1, LEDNOK:
LED desaturation error.
0: Interrupt disabled/masked.
1: Interrupt enabled.
Bit 0, VDD2NOK: VDD2 desaturation error.
0: Interrupt disabled/masked.
1: Interrupt enabled.
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34
NCL31000, NCL31001
REGISTER INTN1
Interrupt enable register for STATN1. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.
7
6
5
4
3
2
1
0
Rsv. TW LEDTSD LEDTW LEDOV
LEDUV VDD2OC VDD11O
C
r
r/w
0
r/w
0
r/w
0
r/w
0
r/w
0
r/w
0
r/w
0
0
This register has the same structure as INTP1; refer there for more information.
REGISTER INITN2
Interrupt mask register for STATN2. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.
7
6
5
Rsv.
r
4
3
2
1
0
LEDOC LEDNOK VDD2NOK
r/w
0
r/w
0
r/w
0
0
This register has the same structure as INTP2; refer there for more information.
REGISTER VBB
VBB−GND voltage measurement.
15
14
13
12
11
10
9
9
9
8
8
8
7
7
7
6
6
6
5
4
3
2
2
2
1
1
1
0
ADCv
Rsv.
r
r
0
0
Bits 6–15, ADCv: ADC value.
Bits 0–5:
Reserved, do not use.
REGISTER IBB
IBB current measurement.
15
14
13
12
11
10
5
4
3
0
ADCv
Rsv.
r
r
0
0
Bits 6–15, ADCv: ADC value.
Bits 0–5:
Reserved, do not use.
REGISTER VDD11
VDD11 voltage measurement.
15
14
13
12
11
10
5
4
3
0
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
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35
NCL31000, NCL31001
REGISTER IDD1
IDD1 current measurement.
15
14
13
12
11
10
9
8
7
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
REGISTER VDD2
VDD2 voltage measurement.
15
14
13
12
11
10
9
8
7
6
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
REGISTER IDD2
IDD2 current measurement.
15
14
13
12
11
10
9
8
7
6
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
REGISTER VLED
VLED current measurement.
15
14
13
12
11
10
9
8
7
6
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
REGISTER ILED
ILED current measurement.
15
14
13
12
11
10
9
8
7
6
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
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36
NCL31000, NCL31001
REGISTER TLED
TLED voltage measurement.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCv
Rsv.
r
r
0
0
This register has the same structure as IBB; refer there for more information.
REGISTER VDD110CTH
VDD11 overcurrent threshold register.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
val
r/w
Rsv.
r
3FF
3F
H
H
Bits 6–15, val: value.
1023: The detection is disabled.
Reserved, do not use.
Bits 0–5:
REGISTER VDD2OCTH
VDD2 overcurrent threshold register.
15
14
13
12
11
10
9
8
7
6
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
val
r/w
Rsv.
r
3FF
3F
H
H
This register has the same structure as VDD11OCTH; refer there for more information.
REGISTER TLEDTWTH
TLED thermal warning threshold register.
15
14
13
12
11
10
9
8
7
6
5
val
r/w
Rsv.
r
3FF
3F
H
H
This register has the same structure as VDD11OCTH; refer there for more information.
REGISTER TLEDTSDTH
TLED thermal shutdown threshold register.
15
14
13
12
11
10
9
8
7
6
5
val
r/w
Rsv.
r
3FF
3F
H
H
This register has the same structure as VDD11OCTH; refer there for more information.
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37
NCL31000, NCL31001
REGISTER VLEDOVTH
VLED overvoltage threshold register.
15
14
13
12
11
10
9
8
7
6
5
4
4
4
3
2
2
2
1
1
1
0
0
0
val
r/w
Rsv.
r
3FF
3F
H
H
This register has the same structure as VDD11OCTH; refer there for more information.
REGISTER VLEDUVTH
VLED undervoltage threshold register.
15
14
13
12
11
10
9
8
7
6
5
3
val
r/w
Rsv.
r
3FF
3F
H
H
This register has the same structure as VDD11OCTH; refer there for more information.
REGISTER VDD11OCTH_HYS
Overcurrent threshold hysteresis register.
7
Rsv.
r
6
6
6
5
5
5
3
val
r/w
0
0A
H
Bit 7:
Bits 0–6, val:
Reserved, do not use.
value.
REGISTER VDD2OCTH_HYS
Overcurrent threshold hysteresis register.
7
Rsv.
r
4
3
2
1
0
val
r/w
0
0A
H
Bit 7:
Bits 0–6, val:
Reserved, do not use.
value.
REGISTER TLEDTWTH_HYS
LED thermal warning threshold hysteresis register.
7
Rsv.
r
4
3
2
1
0
val
r/w
0
0A
H
This register has the same structure as VDD2OCTH_HYS; refer there for more information.
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38
NCL31000, NCL31001
REGISTER TLEDTSDTH_HYS
TLED thermal shutdown threshold hysteresis register.
7
Rsv.
r
6
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
val
r/w
0
0A
H
This register has the same structure as VDD2OCTH_HYS; refer there for more information.
REGISTER VLEDOVTH_HYS
VLED overvoltage threshold hysteresis register.
7
Rsv.
r
6
5
4
3
val
r/w
0
0A
H
This register has the same structure as VDD2OCTH_HYS; refer there for more information.
REGISTER VLEDUVTH_HYS
VLED undervoltage threshold hysteresis register.
7
Rsv.
r
6
5
4
3
val
r/w
0
0A
H
This register has the same structure as VDD2OCTH_HYS; refer there for more information.
REGISTER INTDIM
Internal DIM register.
7
EN
r/w
0
6
5
4
3
DACv
r/w
0
Bit 7, EN:
Internal DIM enable.
0: The internal DIM is disabled.
1: The internal DIM is enabled.
Internal DAC value.
Bits 0–6, DACv:
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39
NCL31000, NCL31001
REGISTER LEDFC
LED driver switching frequency register.
7
JIT_EN
r/w
6
5
4
3
FREQ
r/w
2
1
0
0
4
Bit 7, JIT_EN:
Spread spectrum enable.
0:
1:
Spread spectrum disabled.
Spread spectrum enabled.
Bits 0–6, FREQ:
Switching frequency value.
0:
1:
2:
3:
4:
5:
6:
7:
8:
9:
1 MHz switching frequency.
800 kHz switching frequency.
666 kHz switching frequency.
571 kHz switching frequency.
500 kHz switching frequency.
444 kHz switching frequency.
400 kHz switching frequency.
363 kHz switching frequency.
333 kHz switching frequency.
307 kHz switching frequency.
10: 285 kHz switching frequency.
11: 250 kHz switching frequency.
12: 235 kHz switching frequency.
13: 210 kHz switching frequency.
14: 190 kHz switching frequency.
15: 173 kHz switching frequency.
REGISTER SLCMP
LED driver slope compensation register.
7
6
5
4
3
2
1
0
Rsv.
SLP2
SLP1
r/w
2
r
r/w
2
0
Bits 4–7:
Reserved, do not use.
Bits 2–3, SLP2:
Slope compensation applicable when LED driver is operating in 50% to 100% duty−cycle range.
0: 0.3 V/ms
1: 0.4 V/ms
2: 0.6 V/ms
3: 0.9 V/ms
Bits 0–1, SLP1:
Slope compensation applicable when LED driver is operating in 0 to 50% duty−cycle range.
0: 0.1 V/ms
1: 0.2 V/ms
2: 0.3 V/ms
3: 0.4 V/ms
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40
NCL31000, NCL31001
REGISTER MPS
Maintain Power Signature register.
7
EN
r/w
1
6
5
4
3
DELTA
r/w
2
1
0
4
Bit 7, EN:
MPS enable.
0:
1:
MPS disabled.
MPS enabled.
Bits 0–6, DELTA: Define how long the MPS pulse lasts. The minimum MPS pulse is about 7 ms if LCF bit is active and
75 ms if the LCF bit is disabled.
The DELTA value defines how many ms are added to the minimum MPS time.
0:
Add 0 ms to the minimum MPS pulse.
63: Add 63 ms to the minimum MPS pulse.
127: Add 127 ms to the minimum MPS pulse.
REGISTER FDEV
Frequency Deviation register.
7
Rsv.
r
6
5
4
3
2
1
FDEV
r/w
0
SSLUT_DIS
Rsv.
r/w
0
r
0
0
6
Bit 7:
Reserved, do not use.
Bits 5–6, SSLUT_DIS: Spread Spectrum Look−up Table Disable.
0: The FDEV and FMOD field values are directly used for the spread spectrum block (expert mode).
The user is responsible for calculating the amount of spread.
1: The spread spectrum block calculates the needed deviation and modulation values to achieve a certain
amount of spread (%) based on the FDEV and FMOD field values. The relation between
FMOD/FDEV and the amount of spread (%) is given in a lookup table.
Reserved, do not use.
Bits 3–4:
Bits 0–2, FDEV:
Frequency Deviation value.
0: 1.8 MHz deviation.
1: 914 kHz deviation.
2: 479 kHz deviation.
3: 322 kHz deviation.
4: 246 kHz deviation.
5: 165 kHz deviation.
6: 100 kHz deviation.
7: 56 kHz deviation.
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41
NCL31000, NCL31001
REGISTER FMOD
Frequency Modulation register.
7
6
5
4
3
2
1
0
Rsv.
val
r/w
1
r
0
Bits 2–7:
Reserved, do not use.
Bits 0–1, val:
Frequency Modulation value.
0: 200 Hz modulation.
1: 400 Hz modulation.
2: 800 Hz modulation.
3: 1600 Hz modulation.
2
ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
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42
NCL31000, NCL31001
PACKAGE DIMENSIONS
QFN48 7x7, 0.5P
CASE 485EP
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
D
A
B
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINAL AND IS MEASURED ABETWEEN
0.15 AND 0.25 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
PIN 1
LOCATION
L1
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
A3
b
D
0.20 REF
2X
0.20
0.30
EXPOSED Cu
MOLD CMPD
7.00 BSC
0.10
C
D2 4.00
4.20
E
7.00 BSC
E2 4.00
4.20
0.10
C
2X
TOP VIEW
e
L
0.50 BSC
DETAIL B
0.30
0.50
0.15
ALTERNATE
DETAIL B
CONSTRUCTION
L1 0.00
(A3)
0.10
0.08
C
C
A
A1
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 4
SEATING
PLANE
C
SIDE VIEW
D2
2X
48X
0.63
4.40
0.10 C A B
DETAIL A
1
13
12
25
E2
36
0.10 C A B
2X
7.30
PACKAGE
OUTLINE
48X
0.32
1
0.50 PITCH
48
37
DIMENSIONS: MILLIMETERS
48X
b
0.10 C A B
e
48X
L
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
e/2
NOTE 3
C
0.05
BOTTOM VIEW
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
2
ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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◊
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