NCL31010MNITWG_技术文档

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RELATED STANDARDS

Complete PoE Connected

LED Driver Power Solution,

IEEE 802.3bt

IEEE 802.3bt−2018

NCL31010

Description

QFN48 7x7, 0.5P

CASE 485EP

The NCL31010 is a member of the onsemi Power over Ethernet

Powered Device (PoE−PD) product family and integrates an IEEE

802.3bt PoE−PD interface controller, a dual step−down converter and a

buck convertor LED driver. The NCL31010 incorporates all the

required functions for operation within a PoE system such as detection,

classification and current limiting during the inrush phase. The

NCL31010 contains synchronous step−down DC/DC converters for the

main 3.3 V system supply as well as an auxiliary supply. In addition, the

NCL31010 also integrates a current mode buck DC/DC controller

designed to operate as a LED driver. The LED driver supports both

PWM dimming and high−bandwidth analog dimming.

MARKING DIAGRAM

1

NCL31

010x

AWLYYWW

NCL31010x = Specific Device Code (x = I, S)

A

= Assembly Location

= Wafer Lot

= Year

The NCL31010 supports high−power applications (up to 90 W PoE).

WL

YY

WW

Features

= Work Week

• Fully Supports IEEE 802.3af/at and 802.3bt Specifications

• Assigned Power Level Up to 90 W

• Proprietary 100 W+ Applications

• Supports Autoclass

• HV Maintain Power PWM Output (MPS)

• Integrated 3.3 V Buck Convertor

ORDERING INFORMATION

Device

Package

Shipping

NCL31010MNITWG

QFN48

2500 / Tape &

Reel

• Integrated Adjustable Buck Convertor 2.5 − 24 V

• Integrated High Efficiency Buck LED Driver

• Adjustable Switching Frequency 44.4 kHz to 1 MHz

NCL31010MNSTWG

QFN48

2500 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• Deep Dimming to Zero with Accuracy of 0.1% Using Internal

Precision 2.4 V Reference

• Best in Class Linearity

• High Modulation Bandwidth (~50 kHz)

♦ Visual Light Communication Capable

♦ Yellow−Dott Compliant

• Internal DIM DAC for Independent LED Control During

Micro−controller Re−flashing (Warm Boot)

• Low EMI Reference Design

2

• I C/SPI Interface (NCL31010I/NCL31010S)

• High Accuracy Diagnostic Functions to Measure Voltages/Currents

• Protection against LED Shorts & Opens

• LED Over/Under Voltage & Over Current Protection

• Chip Over Current Protection

• Chip & LED Over Temperature Protection

• Junction Temperature Range of −40°C to +125°C

• Available in 48−pin QFN 7x7

• These Devices are Pb−Free and are RoHS Compliant

1

Publication Order Number:

January, 2022 − Rev. 0

NCL31010/D

NCL31010

1

2

36

35

34

33

32

31

30

29

28

27

26

25

MPS

N3V3

VDDD

ADDR2_MISO

INTB

3

VPORTP

COSC

4

SCL_CLK

SDA_MOSI

ADDR1_CSB

CADC

CLASSA

CLASSB

ACS

5

6

NCL31010

7

RTNA

VPORTN

DET

8

VREF

9

DIM

10

11

12

PSNSN

PSNSP

PGATE

TLED

VLED

Figure 1. Pin−out NCL31010 in 48−pin QFN (Top View)

PIN DESCRIPTION

Pin No. Signal Name

Type

Output

Power

Analog

Description

1

2

3

4

MPS

N3V3

Maintain Power Signature PWM output.

−3V3 LDO output. Decouple to VPORTP (pin 3) with a 1 ꢀ F capacitor.

VPORTP

COSC

Positive input power. Connect to the positive terminal of the PoE rectifier bridge.

Connect a 1 nF 2% capacitor between COSC and VPORTN.

This pin is pulled to VPORTP during the detection phase.

5

6

7

CLASSA

CLASSB

ACS

Output

Input

Connect a class signature programming resistor to VPORTN.

See classification section for recommended values.

Autoclass enable/disable input.

Pull to VPORTN to disable Autoclass; leave floating to enable Autoclass.

8

9

VPORTN

DET

Power

Negative input power for PoE. Connect to the negative terminal of the PoE bridge rectifier.

Open Drain

Connect a 26.1 kꢁ detection resistor between DET and COSC.

This pin is pulled to VPORTN during the detection phase.

10

11

12

PSNSN

PSNSP

PGATE

Input

Negative input current sense line. Connect to VPORTN at the negative side of the external

input current sense resistor.

Positive input current sense line. Connect to the positive side of the external input current

sense resistor.

Output

Gate driver for the external pass transistor.

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2

NCL31010

PIN DESCRIPTION (continued)

Pin No. Signal Name Type

Description

13

RTNALD

Power

Application ground. Connect to the drain of the external pass transistor. Return for the LED

Buck compensation network.

14

15

16

17

18

LDSNSN

LDSNSP

LDCOMP

RTNPLD

P9V

Input

Negative LED current sense line. Connect to the RTN side of LDSNS.

Positive LED current sense line. Connect to the positive side of LDSNS.

Compensation pin for the LED driver.

Analog

Power

Application ground. LED Buck power return.

9 V gate drive voltage regulator output. Decouple to RTNPLD with a 1 ꢀ F capacitor.

Connect to P9V (pin 45) with a trace on the PCB.

19

20

21

22

23

24

25

26

27

28

29

30

31

LDGB

RTNPLD

LDSW

BST

Output

Power

Output

Input

LED buck convertor bottom switch gate driver.

Application ground. LED Buck power return.

LED buck convertor switching node.

Boost voltage for top switch gate drive. Decouple to LDSW with a 100 nF capacitor.

LED buck convertor bottom switch gate driver.

LDGT

PWM

PWM Dimming input.

VLED

Input

LED string voltage measurement. Connect to RTN when not used.

LED string NTC resistor divider measurement point. Connect to RTN when not used.

Analog Dimming input.

TLED

Input

DIM

Analog

Power

Analog

Input

VREF

Reference precision voltage output. Decouple with a 2.2 ꢀ F capacitor.

Application ground. Analog return.

RTNA

CADC

ADDR1_CSB

ADC filter capacitor connection. Decouple to RTNA with a 10 nF capacitor.

2

I C Address for I C mode. Tie to RTN, VDDD or leave floating for alternative I C address.

CSB in SPI mode.

2

32

33

34

35

36

37

38

SDA_MOSI

SCL_CLK

INTB

Input/Output

Input

I C Data line. External pull−up resistor required. MOSI in SPI mode.

2

I C Clock line. External pull−up resistor required. CLK in SPI mode.

2

Open Drain

Input

I C Interrupt pin. External pull−up resistor required.

2

ADDR2_MISO

VDDD

I C Address. Tie to RTN or leave floating for alternative I C address. MISO in SPI mode.

Power

3V3 power input for the NCL31010 digital circuitry.

VDD

Power

3V3 power output for the chip and external circuitry.

IVDD

Input

Current measurement for VDD regulator. Connect to the positive terminal of the VDD sense

resistor.

39

40

41

VDDSW

RTN

Power

VDD buck convertor switching node.

Application ground. Ground connection for the VDD and VDD2 DC/DC convertors.

VPORTP

Positive input power. Decouple to the RTN with a 1 ꢀ F capacitor. Connect to the positive

terminal of the PoE rectifier bridge.

42

43

44

45

VDD2SW

RTN

Power

Output

Power

VDD2 buck convertor switching node.

Application ground. Ground connection for the VDD and VDD2 DC/DC convertors

VDD2 buck convertor bottom switch gate driver.

VDD2GB

P9V

9 V gate drive voltage input. Decouple to RTN with a 100 nF capacitor.

Connect to P9V (pin 18) with a trace on the PCB.

46

47

VDDGB

IVDD2

Output

Input

VDD buck convertor bottom switch gate driver.

Current measurement for VDD2 regulator. Connect to the positive terminal of the VDD2

sense resistor.

48

VDD2

Power

VDD2 power output for external circuitry.

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3

NCL31010

Figure 2. NCL31010 Block Diagram

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

70

Unit

V

VPORTP

Input Power Supply vs. VPORTN

Application Ground vs. VPORTN

−0.3

RTN, RTNPLD, RTNA,

RTNALD

VPORTP + 0.3

V

BST

LDGT

Analog Output vs. LDSW

Analog Output vs. RTN

−0.3

11

Min (70, VPORTP + 11)

VPORTP+0.3

3.6

V

LDSW

Analog Output vs. RTN

PSNSN, PSNSP

DET

Analog Input vs. VPORTN

Analog Output vs. VPORTN

Analog Input vs. VPORTN

Analog Output vs. VPORTN

Analog Input vs. VPORTN

Analog Input vs. RTN

PGATE

−0.3

11

V

COSC

VPORTP + 0.3

CLASSA, CLASSB

ACS

LDSNSN, LDSNSP

VDD

−0.3

0.3

3.6

V

3.3 V Analog Supply vs. RTN

3.3 V Digital Supply vs. RTN

Digital Input/Output vs. RTN

Analog Output vs. RTN

VDDD

ADDR1_CSB

ADDR2_MISO

VREF

DIM

Analog Input vs. RTN

CADC

Analog Output vs. RTN

LDCOMP

Compensation Pin vs. RTN

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4

NCL31010

ABSOLUTE MAXIMUM RATINGS (continued)

Symbol

IVDD

Parameter

Min

−0.3

Max

Min (3.6, VDD + 0.3)

5.5

Unit

V

Analog Input vs. RTN

SDA_MOSI

SCL_CKL

INTB

Digital Input/Output vs. RTN

Digital Input vs. RTN

V

Open Drain Digital Output vs. RTN

Analog Output vs. RTN

MPS vs. VPORTN

P9V

−0.3

11

V

VDDGB, VDD2GB

LDGB

N3V3

VPORTP − 3.6

−0.3

VPORTP + 0.3

V

MPS

VDD2

Analog Input vs. RTN

−0.3

VLED

HV Tolerant Input vs. RTN

Analog Input vs. RTN

PWM

TLED

IVDD2

VDDSW

VDD2SW

Analog Output vs. RTN

Storage Temperature

−0.6

VPORTP + 11

V

T

STRG

−55

−40

2

+150

+125

−

°C

kV

V

T

J

Junction Temperature

ESD−HBM

ESD−CDM

Human Body Model; EIA−JESD−A114

Charged Device Model; ESD−STM5.3.1

500

−

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

− V )

PORTN

Min

−

Max

57

Unit

V

PORT

Input Power Supply (V

= V

PORT

PORTP

V

Digital Inputs SCL, SDA, INTB, PWM vs. RTN

Temperature Sense Analog Input vs. RTN

Ambient Temperature

0

5

V

I_D

VTLED

0

VDD

+85

+125

V

T

−40

°C

A

T

Junction Temperature

J

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

THERMAL CHARACTERISTICS

Symbol

ꢂ JC

Characteristic

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Air

Value

38

Unit

°C/W

ꢂ JA

128

1. ꢂ JA is obtained with 1S1P test board (1 signal – 1 plane) and natural convection. Refer to JEDEC JESD51 for details

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5

NCL31010

ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Condition

Min

Typ

Max

Unit

DETECTION CHARACTERISTICS

Rdetect

Equivalent Detection Resistance

Detection Offset Voltage (IC Part)

R

= 26.1 k

PORT

ꢁ

1%

23.7

−

26.3

0.2

kꢁ

DET

1 V ≤ V

≤ 10.1 V

VoffsetIC

−

V

CLASSIFICATION CHARACTERISTICS

Vcl_th

Class/Mark Current Switchover

V

rising or falling

= 12.5 V

10.1

20.5

−

12.5

24.5

V

PORT

Threshold (Note 2)

Vcldis

Classification Current Disable Threshold

(Note 2)

Iclsigq

Vcsr

Quiescent Current During Classification

−

275

−

ꢀ

A

CLASS Driver Voltage (Note 2) During

Class Event

12.5 V ≤ V

≤ 20.5 V

8.5

9.15

9.7

V

PORT

Iclsig0

Iclsig1

Iclsig2

Iclsig3

Iclsig4

Imark

tfce

RclassA,B = 4.5 k

ꢁ

1%

12.5 V ≤ V

≤ 20.5 V

1

9

−

4

mA

ms

PORT

RclassA,B = 909

RclassA,B = 511

RclassA,B = 332

RclassA,B = 232

ꢁ

12

20

30

44

4

ꢁ

17

26

36

1

−

ꢁ

−

IPORTP During Mark Event Range

V

PORT

= 10.1 V

2.3

−

Short/Long First Class Event Threshold

R

C

= 26.1 k

= 1 nF 2%

ꢁ

1%;

75

88

DET

OSC

tacspd

Change to Class Signature ‘0’ Current

Timing

Autoclass enabled

75.5

−

87.5

ms

RC OSCILLATOR CHARACTERISTICS

fosc

duty

Frequency of the Oscillator

Oscillator Duty Cycle

R

= 26.1 kꢁ; C

= 1 nF

−

26.8

50

−

kHz

%

DET

OSC

PASS SWITCH CURRENT CONTROL CHARACTERISTICS

Iinr

Inrush Current

100 mꢁ Sense Resistor

75

97.3

1.0

125

1.1

mA

V

Vdrain_pg

RTN PowerGood Threshold Voltage

(Note 2)

RTN – VPORTN falling

0.9

Vgate_pg

PGATE PowerGood Threshold Voltage

(Note 2)

PGATE − VPORTN rising

6.9

8.5

10.0

V

PASS SWITCH ON−STATE CHARACTERISTICS

Ioc

Over Current Detection Level

100 mꢁ Sense Resistor

5.4

1.1

6.0

1.2

6.7

1.3

A

V

Voc

RTN Overcurrent Detection Voltage

(Note 2)

RTN – VPORTN rising

UNDER VOLTAGE LOCK−OUT CHARACTERISTICS

UVLO_H

UVLO_L

VPORT UVLO Threshold Voltage (Note 2)

UVLO Threshold Hysteresis

V

rising

falling

33

30

35.1

32.3

2.8

37.5

34.5

3.3

V

PORT

UVLO_hyst

2.4

PoE RESET CHARACTERISTICS

Vrst

VPORT Reset Threshold Voltage (Note 2)

V

falling

2.81

−

3.85

260

−

4.9

−

V

PORT

PASS SWITCH OFF−STATE CHARACTERISTICS

Idd_off

THERMAL PROTECTION CHARACTERISTICS

TSD_PoE Thermal Shutdown Threshold

Power−off Current (Note 3)

= 57 V

ꢀ A

°C

PORT

Junction temperature

150

−

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6

NCL31010

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

MAINTAIN POWER TIMER

Tclk_MPT

Timer Clock Cycle Period

= 53 V)

972

1024

1076

ꢀ s

CONSUMPTIONS (V

PORT

Idd_on,0

Idd_on,1

Operating Current

CTRL = 0; VDD Non−switching

−

2.03

2.12

−

mA

Operating Current w. VDD2

CTRL = 1;

VDD, VDD2 Non−switching

Idd_on,2

Idd_on,3

Operating Current w. Metrology

CTRL = 4; VDD Non−switching

−

2.06

2.15

−

mA

Operating Current w. VDD2 & Metrology

CTRL = 5;

VDD, VDD2 Non−switching

VDD & VDD2 DCDC ELECTRICAL SPECIFICATIONS

VDDx_Freq

N3V3

Switching Frequency

JIT_EN = 0

0 ≤ I ≤ 5 mA

0 ≤ I ≤ 20 mA

126.6

3.13

8.55

133.3

3.3

9

140

3.47

9.45

kHz

V

Internal VPORTP−N3V3 Voltage

P9V

Internal P9V Voltage

(Generated in LED Block)

V

VDDxGB_Rpu

VDDxGB_Rpd

VDDxGB_Tr

VDDxGB_Tf

LS Gate Driver Pull−up Resistance

LS Gate Driver Pull−down Resistance

LS Gate Driver Rise Time

15

2

28

3.25

20

65

6.5

52

16

ꢁ

10

3

ns

LS Gate Drive Fall Time

6

VDD MAIN DCDC ELECTRICAL SPECIFICATIONS

DC3V3_VDD

DC3V3_ILMT

VDD_Ton,min

VDD_Toff,min

VDD_HS_Ron

I_VDDD

Main Supply Output Voltage

Peak Inductor Current Limit

Minimum ON Time

3.234

230

50

1.5

−

3.3

300

110

88

3.366

370

200

7.5

−

V

mA

ns

ꢁ

R

= 0.75 ꢁ

sns

Minimum OFF Time

Top Switch on Resistance

Operating Current on VDDD

Equivalent AC Parallel Resistance

Equivalent AC Parallel Inductance

3.3

CTRL = 0

3.15

0.6

mA

ꢁ

VDD_ACRp

VDD_ACLp

R

= 0.75 ꢁ; CCM

−

sns

−

149

−

ꢀ H

VDDD RESET ELECTRICAL SPECIFICATIONS

VDD_POR_LH VDD(D) Reset Threshold H

VDD_POR_HL VDD(D) Reset Threshold L

VDD_POR_HY VDD(D) Reset Hysteresis

VDD2 AUXILIARY DCDC ELECTRICAL SPECIFICATIONS

DCAUX_VDD2 Aux Supply Output Voltage

VDD(D) Rising

VDD(D) Falling

2.8

2.5

0.2

2.9

2.7

0.3

3.05

2.8

V

0.4

5V0 (VDD2_SEL = 2)

7V2 (VDD2_SEL = 6)

2V5 (VDD2_SEL = 0)

3V3 (VDD2_SEL = 4)

10V (VDD2_SEL = 1)

12V (VDD2_SEL = 5)

15V (VDD2_SEL = 3)

24V (VDD2_SEL = 7)

4.9

5

5.1

V

7.056

2.45

7.2

2.5

3.3

10

12

15

24

7.344

2.55

3.234

9.8

3.366

10.2

11.76

14.7

12.24

15.3

23.52

24.48

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7

NCL31010

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Condition

Min

882

601

811

802

544

538

450

50

0.5

−

Typ

948

668

872

862

604

598

547

87

Max

1014

750

933

922

664

678

650

150

2.65

−

Unit

mA

ns

DCAUX_ILMT

Peak Inductor Current Limit

5V0; R

7V2; R

2V5; R

3V3; R

10V; R

12V; R

15V; R

24V; R

= 0.22

= 0.20

= 0.33

= 0.36

ꢁ

sns

VDD2_Ton,min Minimum ON Time

VDD2_Ton,min Minimum OFF Time

VDD2_HS_Ron Top Switch on Resistance

84

ns

1.1

ꢁ

VDD2_Sx

Slope Compensation

0.073

0.067

0.23

0.53

0.12

0.15

1.22

1.16

0.92

2.09

60

15V; R

24V; R

5V0; R

7V2; R

2V5; R

3V3; R

10V; R

12V; R

15V; R

24V; R

5V0; R

7V2; R

2V5; R

3V3; R

10V; R

12V; R

15V; R

24V; R

= 0.33

= 0.36

ꢁ

A/ꢀ s

ꢁ

sns

0.028

−

VDD2_ACRp

Equivalent AC Parallel Resistance

−

= 0.22 ꢁ; CCM

= 0.20 ꢁ; CCM

= 0.33 ꢁ; CCM

= 0.36 ꢁ; CCM

= 0.22 ꢁ; CCM

= 0.20 ꢁ; CCM

= 0.33 ꢁ; CCM

= 0.36 ꢁ; CCM

−

ꢁ

−

ꢁ

−

ꢁ

−

ꢁ

−

ꢁ

−

ꢁ

−

ꢁ

VDD2_ACLp

Equivalent AC Parallel Inductance

−

ꢀ H

−

120

29

−

38

−

275

229

514

−

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8

NCL31010

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Min

Typ

Max

Unit

LED DRIVER ELECTRICAL SPECIFICATIONS

VPORTP

VLED

Input Voltage Range for Stable Output

24

4

−

57

38

V

LED String Voltage vs. RTN

Analog DIM Input vs. RTN

LED Current Range

VDIM

0

−

2.4

V

ILED (Note 4)

0

−

3

A

VSNS (Note 5) Sense Resistor Voltage

VCSA_0 (Note 6) Sense Amplifier Output Voltage [Inputs Shorted]

−0.024

199.05

−0.081

−

0.3

V

201

−

202.95

0.081

mV

%

ILED_OFFS

(Note 7)

LED Current Regulation Offset Error Relative to VREF

ILED_GAIN

(Note 8)

LED Current Regulation Gain Error

−2

−

2

%

LED DRIVER SAWTOOTH SLOPE COMPENSATION ELECTRICAL SPECIFICATIONS

SLP1_1

SLP1_2

SLP1_3

SLP1_4

SLP2_1

SLP2_2

SLP2_3

SLP2_4

Slope Compensation 1 with SLP1<1:0> = 00

Slope Compensation 1 with SLP1<1:0> = 01

Slope Compensation 1 with SLP1<1:0> = 10

Slope Compensation 1 with SLP1<1:0> = 11

Slope Compensation 2 with SLP2<1:0> = 00

Slope Compensation 2 with SLP2<1:0> = 01

Slope Compensation 2 with SLP2<1:0> = 10

Slope Compensation 2 with SLP2<1:0> = 11

0.07

0.14

0.21

0.28

0.21

0.28

0.42

0.63

0.1

0.2

0.3

0.4

0.3

0.4

0.6

0.9

0.13

0.26

0.39

0.52

0.39

0.52

0.78

1.17

V/ꢀ s

LED DRIVER INTERNAL DAC ELECTRICAL SPECIFICATIONS

DIM_DNL

DIM_INL

DIM_MAX

DIM_MIN

DIM_RES

Internal DIM Differential Nonlinearity

Internal DIM Integral Nonlinearity

Internal DIM Maximum (Code 0x7F)

Internal DIM Minimum (Code 0x09)

Internal DIM DAC Resolution

−0.5

2.376

−

0

0.5

2.424

−

LSB

V

2.4

187.5

7

mV

LSB

−

LED DRIVER OVER−CURRENT PROTECTION ELECTRICAL SPECIFICATION

OCP_TH Comparator Threshold

LED DRIVER SOFT−START /OTA/NON−OVERLAPPING ELECTRICAL SPECIFICATION

−

382

−

mV

GM

Error Amplifier Transconductance gm in Operational Mode

Error Amplifier Transconductance gm in Soft Start Mode

Minimum ON Time of the LS and HS Driver

Non−overlapping Time

0.5

60

10

1

1.5

180

50

mS

ꢀ S

ns

GM_SST

TOFF_MIN

TNOV

100

25

50

ns

REFERENCE VOLTAGE CHARACTERISTICS

VREF

IREF

Voltage Reference for DIAG/LED/DCDC [IREF < 2 mA]

Voltage Reference Current Consumption

2.394

2.4

2.406

2

V

−

mA

2

I C TIMING CHARACTERISTICS (NCL31010I)

f_SCL Interface Clock Frequency

SPI TIMING CHARACTERISTICS (NCL31010S)

f_SCLK Interface Clock Frequency

−

400

2

kHz

MHz

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9

NCL31010

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Min

Typ

Max

Unit

DIAGNOSTICS ELECTRICAL SPECIFICATION

DIAG_ILED

DIAG_VLED

DIAG_IPORT

DIAG_VPORT

DIAG_IVDD

DIAG_IVDD2

DIAG_VDD

LED Current Measurement Overall Accuracy

LED Voltage Measurement Overall Accuracy

−0.6

−0.5

−1

−

0.6

0.5

1

%

ꢀ A

Input Current Measurement Overall Accuracy

Input Voltage Measurement Accuracy

−0.7

−2

0.7

2

VDD Current Measurement Overall Accuracy

VDD2 Current Measurement Overall Accuracy

VDD Voltage Measurement Overall Accuracy

VDD2 Voltage Measurement Overall Accuracy

TLED Voltage Measurement Overall Accuracy

−2

2

−1

1

DIAG_VDD2

DIAG_TLED

−1

1

−1

1

DIAG_CONSO DIAG Current Consumption

−

200

THERMAL PROTECTION CHARACTERISTICS

TSD_H

TSD_L

Thermal Shutdown, High Threshold

Thermal Shutdown, Low Threshold

Thermal Warning, High Threshold

Thermal Warning, Low Threshold

141

150

135

120

108

159

°C

126.9

112.8

101.5

143.1

127.2

114.5

TWRN_H

TWRN_L

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Voltage referenced to VPORTN

3. E.g. after overcurrent timeout

4. This range depends on the sense resistor RSNS.

5. Assume inductor current ripple included. This spec implies that the inductor current ripple size has an upper limit

VSNSmin > RSNS x Ippmax / 2.

6. The VCSA voltage is the output of the LED sense amplifier and is the compare voltage for the DIM input. VCSA_0 is given with the inputs

shorted. The VCSA_0 voltage is the threshold to get exactly zero current.

7. This deviation is the total offset in the DIM versus LED current relationship. It is specified relative to the VREF typical. It is useful for calculating

the maximum offset error when using a VREF based solution for accurate dimming to low currents.

8. This error is a dominant factor in the LED current regulation error at mid and high LED currents. It is specified relative to VREF typical. Assume

RSNS = 100 mꢁ and ideal.

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10

NCL31010

SIMPLIFIED APPLICATION SCHEMATIC

Figure 3. Typical Application Schematic

Table 1. TYPICAL BILL OF MATERIALS

Symbol

D1

Description

TVS Protection, unidirectional

Decoupling

Value

58 V

Rating

Remark

Reference

SMBJ58A

RSo

C1

100 nF

ꢀ F

100 V

25 V

10 V

25 V

6.3 V

100 V

80 V

100 V

25 V

1 W

0805B104K101C

C2

Decoupling, buffer

1

C0603C105K3PACTU

GRM1885C1H102GA01

C0603C225K8RACTU

C0603C103K3RACTU

C0603C105K3PACTU

C0603C104K3RACTU

C1206C226K9PAC

C1210C476M9PAC

C1210C105K1RAC

C1210C105K1RACTU

A759MS566M1KAAE045

C0805C471K1RACTU

C0603C103K3RACTU

C0603C104K3RACTU

ERJ−1TNF3091U

C3

RC oscillator

1 nF/2%

2.2 ꢀ F

10 nF

C4

Decoupling

C5

Sample and Hold for ADC

Decoupling, buffer

C6

1 ꢀ F

C7

Decoupling

100 nF

22 ꢀ F

47 ꢀ F

C8

Output capacitor for VDD

Output capacitor for VDD2

Fast filter capacitor for DC−DC’s and chip

Fast filter capacitor for LED driver

Buffer capacitor for application

LED driver output capacitors

LED driver compensation capacitor

Filtering TLED

*

C9

C10

C11

C12

C13

C14

C16

R1

1 ꢀ F

2 x 1 ꢀ F

56 ꢀ F

(Note 12)

*

2 x 470 nF

10 nF

(Note 12)

100 nF

MPS resistor

3.09 k

ꢁ

*

R2

PoE detection

26.1 k

1%

RC0603FR−0726K1L

ERJ8ENF2320V

R3

PoE classification

232

332

ꢁ

1%

(Note 9)

*

R4

PoE classification

ꢁ

1%

ERJ6ENF3320V

R5

Auto−classification resistor

PoE current limiting & sense resistor for diagnostics

0

ꢁ

R6

100 mꢁ

3 W

(Note 11)

CRA2512−FZ−R100ELF

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11

NCL31010

Table 1. TYPICAL BILL OF MATERIALS (continued)

Symbol

R7

Description

Value

Rating

Remark

Reference

2

I C pull−up

4.7 k

ꢁ

2

R8

I C pull−up

R9

Interrupt pull−up

2

R10

R11

R12

R13

R18

I C address selection

0

ꢁ

*

2

I C address selection

ꢁ

*

VDD sense resistor

750 m

200 m

100 m

ꢁ

(Note 11)

RCWE0603R750FKEA

VDD2 sense resistor

RL1220S−R20−F

LED driver current sense resistor

1 W

(Note 10)

(Note 11)

R21

L1

Protection resistor for overvoltage on VLED node

VDD buck inductor

100

ꢁ

RC0603FR−07100RL

744777239

390 ꢀ H

100 ꢀ H

68 ꢀ H

L2

VDD2 buck inductor

7447714101

L3

LED driver buck inductor

3 A

(Note 10)

(Note 12)

rms

Q1

Q2

Q3

Q4

U1

U2

U3

U4

U5

Dual NMOS bottom switching transistor for DC/DCs

Pass switch between VPORTN and RTN domains

NMOS bottom switching transistor for LED driver

NMOS top switching transistor for LED driver

Shielded or unshielded Ethernet RJ−45 connector

3bt PoE Magnetics

FDC8602

FDMC8622

FDMA037N08L

NVTFS6H880N

Rectification bridge

FDMQ8205

NCL31010

Rectification bridge

Integrated PoE PD with LED driver and dc−dc’s

9. Resistance value determines the requested power class.

10.Inductor and LED current sense resistor depend on the application specifications such as required power, allowed current ripple. See LED

driver section for details.

11. The accuracy of the sense resistors is not considered in the specification of the current sense accuracy.

12.Saturation current >3.5 A

13.The values for L2, R13 and C9 in the table are specific for the 5 V VDD2 output. Refer to table 14 and 18 for other VDD2 output voltages.

14.The schematic does not show EMI filtering required for some applications.

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12

NCL31010

POE FUNCTIONAL DESCRIPTION

Classification

The NCL31010 incorporates a Power over Ethernet

Powered Device (PD) interface controller with an external

n−channel MOSFET load switch.

A PD is characterized based upon the maximum power

level it requires at its power interface during operation. The

IEEE 802.3bt standard supports up to 71.3 W PDs and

defines 8 power Classes: Class 1 up to Class 8. The PD must

conform to a Class with a power level that is at or above the

maximum power the PD requires. Table 2 lists the different

Classes and the corresponding power level they stand for.

Based on the Class the PD conforms to, two resistance

values are listed. The R

CLASSA and VPORTN. Likewise, the R

be inserted between CLASSB and VPORTN. Eventually,

whenimplementing a Class 1, 2, 3 or 4 PD, the CLASSA and

CLASSB pins can be shorted together to the same single

resistor.

Powered Device Interface

The NCL31010 is located at the interface of the PD and

will interact with the Power Sourcing Equipment (PSE) over

the Ethernet cable. NCL31010 allows the device to be

powered by an IEEE 802.3af/at or −3bt compliant PSE. It

provides a detection signature, classification handshaking,

inrush current limitation and operational overcurrent

protection. A block diagram is shown in Figure 2. Each

section will be explained in more detail below.

value must be inserted between

classA

value must

classB

Detection

During the detection phase, the PSE will check if a valid

or a non−valid detection signature is present. This will

enable the PSE to differentiate between equipment

supporting PoE requesting power and equipment either not

supporting PoE or not requesting power. In order to be able

to present a valid detection signature to the PSE, a 26.1 kꢁ

resistor must be inserted between the COSC and DET pins

of NCL31010. During the detection phase all blocks of the

chip are in power−down except for an internal reference, a

comparator and two switches.

When the voltage at the PD power interface is within the

detection range, the COSC pin is pulled to VPORTP and the

DET pin is pulled to VPORTN, resulting in the PD

presenting a valid detection signature. The offset voltage of

the input rectifier bridge should be between 0 and 1.7 V in

Table 2. CLASSIFICATION RESISTOR VALUE

R

CLASSB

CLASSA

(Note 16)

PD Class

PD Power

13 W

0 (Note 15)

4.5 kW

1

2

3

4

5

6

7

8

3.84 W

6.49 W

13 W

909

511

332

232

ꢁ

909

511

332

232

ꢁ

25.5 W

40.0 W

51.0 W

62.0 W

71.3 .. 90 W

4.5 k

ꢁ

909

511

332

ꢁ

the detection range (2.7 V ≤ V ≤ 10.1 V).

PD

15.3bt compliant PDs should use Class 1, 2 or 3 instead of Class 0

16.All resistors must be 1% accurate

When the PSE has detected a valid detection signature and

continues towards powering on the PD, the COSC and DET

switches are turned off in order to reduce the current

consumption of the PD.

Once the PSE device has detected the PD device, the

classification process begins. The NCL31010 is fully

capable of responding and completing classification with all

PSE types described in the 802.3af/at and −3bt PoE

Standard. The Class requested by NCL31010 during

classification is determined by the resistors connected to the

CLASSA and CLASSB pins. Depending on the power the

PSE is able to deliver to the PD, the PSE will generate a

different number of class−mark events. This will determine

the amount of power the PD is allowed to use. Next to that,

the NCL31010 is able to distinguish between a 3bt

compliant PSE and a 3af/at compliant PSE. Therefore a 1 nF

capacitor must be inserted between COSC and VPORTN.

The classification results will be written to the Classification

Result Register (&CCR 0x03). The offset voltage of the

input rectifier bridge should be between 0 and 2 V in the

VPORTP

COSC

R_DET

DET

1,2 V

PC20180220.1

VPORTN

detection range (14.5 V ≤ V ≤ 20.5 V).

During a class event, the power dissipation in the R

resistor can be significant (V

PD

Figure 4. Detection Circuit

class

2

/ R

class

) and its package size

csr

must be chosen properly. When the port voltage rises above

the class drivers will be disabled in order to limit the

V

cldis

power dissipation.

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13

NCL31010

Inrush Current Limiting

As an example, it typically takes 80 ms to charge a 145 ꢀ F

capacitor to 50 V. Depending mainly on the chosen port

capacitor value, this 80 ms delay may or may not yet have

passed when the NCL31010 exits the inrush current control

state.

When the PSE has successfully assigned the PD to a

specific Class in correspondence with the power the PSE is

able to deliver, the PSE will increase the voltage at its power

interface up to its internal power supply voltage. NCL31010

will enter the inrush current control state once its port

voltage rises above the UVLO_H threshold.

CLASSEVENT Indicators

The state of the CLASSEVENT bits in the Classification

Result Register (&CRR 0x03) provides information about

the power level that the PSE has assigned to the PD during

classification. These status bits are actually only relevant for

PDs requesting Class 4 or higher as those need to take into

account that they can be underpowered. See table 3 to

determine the assigned power based on the CLASSEVENT

bits and the requested Class. An underpowered PD can

eventually be assigned to Class 3, 4 or 6.

In this state, NCL31010 will control the charging of its

port capacitance C located between VPORTP and RTN by

PD

operating the pass switch transistor in the active region. The

current through the pass switch is regulated by monitoring

the voltage over an external sense resistor R

= 100 mꢁ.

SNS

NCL31010 will limit the inrush current well below the PSE

inrush threshold while charging its port capacitance. The

nominal level of the inrush current is 97.3 mA typ. The

NCL31010 will exit the inrush current control state when the

voltage between RTN and VPORTN is smaller than 1.0 V

and the gate voltage rises above 8.5 V. At this stage, the port

capacitance can be considered to be fully charged, and

NCL31010 will enter the normal operation mode with the

pass switch completely turned on.

If the port capacitance voltage remains low due to an

output short error condition, the inrush current control state

will be aborted to protect the pass−switch. In order not to be

considered as a short, the port capacitance should be chosen

not to have too high a value (above 1.5 mF).

Table 3. CLASSIFICATION RESULT OVERVIEW

Requested

Class

CLASSEVENT

Bit [1:0]

Assigned

Class

Assigned

Power

4

5

6

7

00b

01b

1Xb

00b

01b

1Xb

00b

01b

1Xb

00b

01b

10b

11b

00b

01b

10b

11b

3

4

13 W

25.5 W

3

4

5

3

4

6

3

4

6

7

3

4

6

8

13 W

25.5 W

40 W

Class 1 and 2 PDs should operate according to their power

Class 50 ms after the UVLO_H threshold was crossed.

Therefore it is recommended to limit the port capacitance to

57 ꢀ F for Class1 PDs and to 77 ꢀ F for Class2 PDs.

13 W

25.5 W

51 W

System Start−up

Once NCL31010 exits the inrush current control state, it

will set the PGOOD bit in the CRR register, indicating the

VDD 3V3 DC/DC converter − and eventually the system −

is allowed to start. This also indicates NCL31010 will no

longer actively limit the current and/or the power, as the pass

switch is on and will be left turned on.

PDs requesting Class 4 or higher need to take into account

that they can be underpowered and need to implement some

basic functionality with Class 3 power level. Also, the

microcontroller will only be able to read the classification

result after system startup. Therefore the VDD 3V3 DC/DC

converter and the system must be able to start up with Class

3 power (or lower for Class 1 and Class 2 PDs) and turn on

higher power loads only if this is allowed by the PSE

assigned Class.

13 W

25.5 W

51 W

62 W

8

13 W

25.5 W

51 W

71.3..90 W

PDs assigned to Class 8 may consume greater than 71.3 W

as long as they guarantee not to exceed the 90 W power limit

at the PSE power interface. Operation beyond 71.3 W is,

however, only possible if additional information is available

to the PD regarding the actual link section DC resistance

between the PSE and the PD.

The application should always operate at or below the

assigned power limit. Failing to do so will result in the PSE

disconnecting the PD.

Even when being assigned to Class 4 or higher by the PSE,

the PD is only allowed to use this increased power level 80

ms after the UVLO_H threshold was crossed. The nominal

delay introduced to charge the port capacitance can be

calculated from the formula below.

C_pd

(

ꢀ F) V_pd(V)

t_charge(ms) +

(eq. 1)

91

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14

NCL31010

LCF Indicator

resistance of the cable. This should be taken into account

when generating current pulses for MPS.

The state of the LCF bit in the Classification Result

Register (&CRR 0x03) provides information (retrieved

during classification) about the type of PSE the PD is

connected to:

The PD needs to maintain the MPS as soon as its port

voltage rises above the UVLO_H threshold. Depending on

the amount of port capacitance and the type of PSE it is

connected to, the time duration of the inrush current control

state might or might not be enough (T_{MPS_PD,Min}) to count

as the first valid current pulse. In combination with 3bt PSEs

this will usually not be a problem as it typically takes 7 ms

to charge just a 12.7 ꢀ F cap to 50 V. In combination with

3af/at PSEs the situation is different as it typically takes

75 ms to charge a 154 ꢀ F cap to 44 V.

Table 4. TYPE RESULT OVERVIEW

LCF Bit 2

PSE Categorization

0b

1b

802.3af/at (PSE Type 1 or Type 2)

802.3bt (PSE Type 3 or Type 4)

Maintain Power Signature

There is a minimum amount of current a PD needs to draw

in order to allow the PSE to determine if the PD is still

connected. This is called the Maintain Power Signature

(MPS). If the PD no longer maintains this, the PSE may

disconnect the power.

Maintain Power Timer

The NCL31010 can generate a PWM waveform on the

MPS pin to provide a Maintain Power Signature (MPS) and

yet optimize the standby MPS power draw.

The Maintain Power Timer clock has a 1024 ꢀ s cycle

period. The PWM output on MPS pin will consecutively

I_PORT

remain low during N

clock cycles and remain floating

MPON

7 ms

Short MPS

during N

clock cycles; both numbers depend upon the

MPOFF

16 mA

state of the LCF bit in the Classification Result Register

(&CRR 0x03):

10 mA

MPS

Table 7. NUMBER OF CYCLES

75 ms

250 ms

LCF Bit 2

N

MPOFF

MPON

Figure 5. MPS

0b

1b

77 + MPS_DELTA[6:0]

7 + MPS_DELTA[6:0]

215

255

The current needs to be at or above a certain current

threshold (I_{Port_MPS,Min}) during at least a certain amount of

time (T_{MPS_PD,Min}). If this has been the case, the current may

fall below the threshold for at most a certain dropout period

(T_{MPDO_PD,Max}).

Whether or not the lower power short MPS may be used

depends upon the state of the LCF bit in the Classification

Result Register (&CRR 0x03).

The default value for MPS_DELTA[6:0] is 4. However

the on time can be adjusted by programming the

MPS_DELTA bits in the Maintain Power Signature Register

(&MPS 0x50):

MPS_DELTA Bit [6:0]

Value

0x01 .. 0x7F

1 .. 127

Table 5. MPS TIMING

The Maintain Power timer is enabled by default, but it can

be disabled and re−enabled by the MPS_EN bit in the

Maintain Power Signature Register (&MPS 0x50):

LCF Bit 2

T

MPDO_PD,Max

MPS_PD,Min

0b

1b

75 ms

250 ms

7 ms

310 ms

MPS_EN Bit 7

Meaning

For PDs requesting Class 4 or less the MPS current

threshold will always be 10 mA.

For PDs requesting Class 5 or above the MPS current

threshold will depend upon the assigned Class.

0b

1b

Maintain Power Timer Disable

Maintain Power Timer Enable

The simplest MPS circuit is a power resistor between

VPORTP and the MPS pin. For PDs requesting Class 4 or

less a 4.32 kꢁ 1% MPS resistor should be sufficient to draw

at least 10 mA when V

Class 5 or above a 3.09 kꢁ 1% MPS resistor should be

sufficient to draw at least 16 mA when V = 50 V. While

Table 6. MPS CURRENT

Assigned Class

I

Port_MPS,Min

= 44 V. For PDs requesting

PSE

≤4

≥5

10 mA

16 mA

PSE

generating the Maintain Power Signature, the power

2

dissipation in the MPS resistor will be significant (V

/

An important remark is that the PD load current will be

PD

R

MPS

) and its package size must be chosen properly.

low−pass filtered by its port capacitance and the actual

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15

NCL31010

Autoclass

Under Voltage Lockout

802.3bt foresees an optional extension of classification

known as Autoclass. This allows a 3bt certified PSE to better

allocate its power among different PDs.

If the port voltage falls below the UVLO_L threshold and

remains low for a sufficient amount of time, NCL31010 will

enter the poweroff state and turn off the pass−switch.

When the ACS pin is connected to VPORTN, Autoclass

is disabled.

Once the port voltage falls below the reset threshold V ,

the NCL31010 will re−enter the idle state and can again be

rst

When the ACS pin is left floating, Autoclass is enabled

and NCL31010 will request an Autoclass measurement to a

3bt type of PSE during classification. If both the ACS bit and

the LCF bit in the Classification Result Register (&CRR

0x03) are high, the system must go to the maximum power

state according to its assigned Class no later than 1.35 s after

power has been applied, and keep the maximum load active

until at least 3.65 s after power has been applied. During this

period, the PSE will measure the maximum power draw of

the PD and allocate this amount of power to the PD.

detected as a PD requesting power.

Operational Current Protection

In the normal operation mode, NCL31010 will monitor

the current through the pass switch and provide protection

against soft and hard shorts.

Soft shorts are detected if the current is above the short

circuit threshold I (6.0 A typ) and a time out delay of

OC

960 ꢀ s is passed. After this time−out delay the pass switch

is disabled.

A hard short is detected if the voltage across the

pass−switch and sense resistor is above V (1.2 V typ). The

pass gate is switched off within 18 ꢀ s in this case.

Once an overcurrent condition is detected during the

normal operation mode, the NCL31010 will transition to the

offline state and remain there until the port voltage falls

OC

Table 8. AUTOCLASS

ACS

Bit 3

LCF

Bit 2

Autoclass

Measurement

0b

1b

X

Not requested

Requested

below the reset threshold V .

rst

0b

1b

Thermal Shutdown

The NCL31010 includes a thermal shutdown which

protects the device in the case that the junction temperature

is too high. An on−chip sensor monitors the temperature.

Once the thermal shutdown threshold (TSD_PoE) is

exceeded, all functions are disabled and the device goes into

the offline state.

Peak Power and Transients

Although the PoE standard allows the PD to draw slightly

higher peak power during a short time, making use of this is

not recommended. It is best to keep this additional margin

only to be able to withstand voltage transients on the PSE

side. The required recovery time for transients also limits the

amount of the port capacitance that can be used.

The device will remain in offline until the junction

temperature drops and the port voltage falls below the reset

threshold V .

rst

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16

NCL31010

T_{AUTO_PSE2}

T_PON

0 − 400 ms

3100 − 3500 ms

T_{AUTO_PSE1}

1400 − 1600 ms

PSE

DETECT

CLASSIFICATION

UP

POWER_ON

V_PD

50 − 75 ms

PSE REFERENCE

V_{PORT_PD(min)}

PD REFERENCE

t

T_{AUTO_PD2}

T_LCF

88 −105 ms

≥3650 ms

T_{AUTO_PD1}

I_PORT

80 − 1350 ms

T_ACS

75,5 − 87,5 ms

t

ꢀ C active and starts

the application

V_{(VPORTP−RTN)}

.

t

P_PD,Max

Power Class 8

Power Class 7

Power Class 6

Power Class 5

Power Class 4

Power Class 3

Inrush ≈ Power Class 3

t

80 ms

Figure 6. Complete Start−up Diagram of a Class 8 PD with Autoclass

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17

NCL31010

PoE System Overview

The overall PoE standard distinguishes between four

Types of PSEs and four Types of PDs.

• Type 1 PSEs and PDs behave according to 802.3af/at

• Type 2 PSEs and PDs behave according to 802.3at

• Type 3 and 4 PSEs and PDs behave according to 802.3bt

Table 9 gives an overview of the system parameters that

are allowed and required for operation at a certain power

level (assigned Class).

An important parameter is the cable DC resistance

(determined by cable type and length).

In general a Cat 5 cable is required when using a Type 3

or Type 4 PD or PSE in the system or when both PSE and PD

are of Type 2.

Operation over 4−pair is reserved for Type 3 and 4 PSEs.

PoE Reference

All information regarding Power over Ethernet over

TM

4 Pairs can be found in document IEEE 802.3bt −2018

TM

which is an amendment to IEEE Std 802.3 −2018.

Table 9. SYSTEM PARAMETERS OVERVIEW

Minimum Cabling

Type

Assigned

Class

Number of

Powered Pairs

Requested

Class

PSE Type

PD Type

Standard

1

2

3

1

2

Cat 3 (*) (Note 17)

Cat 3

2p

1

802.3af/at

3, 4

1, 2

3

Cat 3

2p/4p

2p

3

1

3

802.3bt

802.3af/at

802.3bt

Cat 3

2

Cat 5 (*) (Note 18)

Cat 5

2p/4p

4

1

Cat 3

2p

1

2

1

2

3

4

2

3

4

3

4

0,3

4

802.3af

802.3at

1

Cat 3 (*) (Note 19)

2

Cat 3

Cat 5

0,3

4

802.3af/at

802.3at

3, 4

2p/4p

3,4/5/6

7/8

4

802.3bt

4

2

2p

802.3at

802.3bt

3, 4

2p/4p

4/5/6

7/8

5

6

3, 4

Cat 5

4p

802.3bt

6

7,8

7

8

4

Cat 5

4p

802.3bt

8

*Critical for:

17. 44 V / 4 W source connected to 3.84 W load over 20

18. 50 V / 6.7 W source connected to 6.49 W load over 12.5

19. 44 V / 15.4 W source connected to 13 W load over 20

ꢁ

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18

NCL31010

DUAL STEP−DOWN CONVERTER FUNCTIONAL DESCRIPTION

Bottom Mosfet

The NCL31010 incorporates a dual synchronous

step−down switching converter for generating two voltage

rails. The top mosfets are internal in NCL31010, whereas

the bottom mosfets need to be added externally.

The regulators employ a constant−frequency peak

current−mode control scheme with internal compensation.

The inductor current is sensed trough a resistance in series

with the inductor. This also allows the NCL31010 to

measure the average output current (see Metrology section).

Depending on the load current, the converter operates in

Discontinuous Conduction Mode (DCM) or Continuous

Conduction Mode (CCM).

The bottom mosfets should have the appropriate

drain−source on−resistance and voltage rating (≥80 V) while

maintaining low output capacitance, low gate charge and

good drain−source diode characteristics (reverse recovery).

Preferably, the package(s) should be very small to enable a

compact PCB layout as well.

Based on above considerations, it is obvious that dual

n−channel mosfet FDC8602 seems to be − by far − the best

choice to complement NCL31010.

Table 10. DUAL N−CHANNEL MOSFET

The VDD regulator, which is automatically enabled by the

PGOOD signal from the PoE block, generates a 3.3 V output

voltage with 150 mA output current capability to power the

system microcontroller (next to some internal logic on

VDDD).

The VDD2 regulator needs to be enabled through the

digital interface. The default output voltage of VDD2 is 5 V

(with 510 mA output current capability), but other output

voltages (and corresponding other output current

capabilities) can be programmed by the digital interface:

2.5 V, 3.3 V, 7.2 V, 10 V, 12 V, 15 V or 24 V.

Product

V

(V)

r

(mW) Package Type

DS(on)

DS

FDC8602

100

350

TSOT−23−6

Switching Frequency

The switching frequency of the NCL31010 DC/DC

regulators is 133.3 kHz. This switching frequency is derived

from the internal accurate 8 MHz master clock which is

divided by 60.

In terms of efficiency and EMI, this low switching

frequency is beneficial and yet it allows a small overall

solution size (small external inductors and capacitors).

VPORTP

LS

BUF3V3

N3V3

IVDDx

Current

Sense

L

VDDx

VDDxSW

VDDx

R

IVDDx

P9V

CK

S

VDDxGB

V

REFx

M

VDDx

C

VDDx

BUF9V

R Q

OTA

RTN

Figure 7. DCDC Block Diagram

www.onsemi.com

19

NCL31010

Current Sense Resistor and Peak Current Limit

Maximum Output Current

The inductor current is sensed by a current sense resistor

in series with the inductor. The sense resistor value

configures the gain of the sensed current signal that is

compared to the control voltage to determine when the top

mosfet needs to be switched off to maintain regulation. The

sense resistor value also configures the peak inductor

current limit at which the top mosfet will be switched off −

despite a higher control voltage − in order to protect the

power stage of the converter against overcurrents.

For the VDD regulator, a 750 mꢁ sense resistor is

recommended.

The maximum load current that will be available is the

peak inductor current limit minus half the peak−to−peak

inductor ripple current:

(V_IN* V_OUT) V_OUT

I_OUT+ I_LIM

*

(eq. 2)

2 L V_IN f_SW

To determine the maximum guaranteed output current

above equation should be evaluated with the minimum value

of the peak inductor current limit I , of the inductance L

LIM

(tolerance and saturation) and of the switching frequency

f . For both the VDD regulator and all output voltages of the

sw

VDD2 regulator, conversely, the maximum value of the

For the VDD2 regulator with 5 V output voltage, a

200 mꢁ sense resistor is recommended. For the other output

voltages, the recommended sense resistor value can be

found in table 14.

input voltage V (i.e. 57 V) should be used here. Likewise

IN

for the output voltage V

in above equation an equivalent

OUT

value V

can be used here to incorporate the slight

OUT,eq

increase in duty cycle with the output current due to the

(maximum) resistance of the (bottom) mosfet, the inductor

and the sense resistor:

The current sense resistors should have a 1% tolerance.

Inductor

The inductor saturation current should be higher than the

maximum peak switch current of the converter. Within an

inductor series, smaller inductance values have a higher

saturation current rating. Allowing a larger than typically

recommended inductor ripple current enables the use of a

physically smaller inductor.

V_OUT,eq(I_OUT) + V_OUT,typ) (r_DS(on)) R_DC) R_CS) I_OUT

(eq. 3)

Based on above considerations, the output current

capability of both converters operated with the

recommended current sense resistance, inductor and bottom

mosfet is given below in table 13 and table 14.

For the VDD regulator, a Würth WE−PD Size 7345

Inductor with 390 ꢀ H Inductance is recommended.

Table 13. VDD CONFIGURATION

V

OUT

(V)

I

(mA)

R

CS

(mW)

L (mH)

OUT

Table 11. INDUCTOR FOR VDD

3.3

150

750

390

Product

L (mH)

390

R

(W)

I

(A)

DC typ.|max.

SAT typ.

744777239

1.25 | 2.85

0.42

20%

Table 14. VDD2 CONFIGURATION

For the VDD2 regulator with 5 V output voltage, the

Würth WE−PD Size 1050 P Inductor with 100 ꢀ H

Inductance is recommended. For the other output voltages,

the recommended inductance value from the same inductor

series can be found in table 14.

V

OUT

(V)

I

(mA)

R

CS

(mW)

L (mH)

OUT

2.5

560

220

100

3.3

5

515

510

415

335

315

285

230

200

330

7.2

10

12

15

24

330

Table 12. INDUCTORS FOR VDD2

Product

L (mH)

R

(mW)

I

(A)

DC typ.|max.

SAT typ.

7447714101

7447714331

7447714471

100

165 | 198

655 | 750

960 | 1100

1.8

20%

330

470

1

390

470

0.82

The listed output current capability still contains some

headroom for a temporarily higher output current after a

load step−up transient (in order not to influence the load

transient response settling time) and for the variation of the

switching frequency due to spread spectrum modulation.

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20

NCL31010

Output Capacitor Selection

The output capacitor is needed to stabilize the control

loop. The gain crossover frequency of the complex open

loop gain can be estimated by:

The VDD and VDD2 regulators do not require any series

resistance (ESR) in the output capacitor. Therefore ceramic

capacitors with X5R or X7R dielectric are recommended.

Unfortunately for these capacitors it is usually not sufficient

to only look at the nominal capacitance value: one should

always check the Capacitance versus Bias Voltage chart to

know the actual remaining capacitance with the output

voltage applied!

1

f_gc

[

(eq. 4)

2 ꢃ ACR_p C_VDDx

This gain crossover frequency should be significantly

lower than half the switching frequency. This places a

constraint on the minimum output capacitance value.

The recommended output capacitors for the VDD

regulator are listed in Table 17.

Some recommended capacitors from the Kemet SMD

X5R and X7R series are listed in table 15 (Size 1206) and

table 16 (Size 1210).

Table 17. CAPACITOR(S) FOR VDD

V

OUT

(V)

C

Component(s)

C

(mF)

VDD

Table 15. X5R CAPACITORS SIZE 1206

3.3

19

19.6

22 mF / 6.3 V / 1206

C

VDD2

(mF @ V)

20.3 @ 2.5

19 @ 3.3

14.1 @ 5.0

9.9 @ 2.5

9.8 @ 3.3

9.5 @ 5.0

9 @ 7.2

Product

C (mF)

V

(V)

0

Rated

2 x 10 mF / 16 V / 1206

C1206C226K9PAC

C1206C226M9PAC

22

6.3

10%

20%

The minimum output capacitor values for the VDD2

regulator are listed in Table 18 and those listed in bold are

recommended.

C1206C106K4PAC

10

16

10%

Table 18. CAPACITOR(S) FOR VDD2

V

(V)

C

VDD2

OUT

(mF)

79.8

100.1

60.7

79.7

42.2

51.7

56.3

17.1

18

C

Component(s)

VDD

2.5

100μF / 6.3V / 1210

100 mF / 6.3 V / 1210 + 22 mF / 6.3 V / 1206

100 ꢀ F / 6.3 V / 1210

8 @ 10

6.7 @ 12

5.3 @ 15

3.1 @ 24

3.3

5

C1206C106K3PAC

C1206C475K5PAC

10

25

50

10%

100 mF / 6.3 V / 1210 + 22 mF / 6.3 V / 1206

47 ꢀ F / 6.3 V/ 1210

4.7

47 mF / 6.3 V / 1210 + 10 mF / 16 V / 1206

47 ꢀ F / 6.3 V / 1210 + 22 ꢀ F / 6.3 V / 1206

22 ꢀ F / 10 V / 1210

Table 16. X5R AND X7R CAPACITORS SIZE 1210

C

VDD2

(mF @ V)

79.8 @ 2.5

60.7 @ 3.3

42.2 @ 5.0

17.1 @ 7.2

8 @ 10

Product

C (mF)

0

V

Rated

(V)

7.2

C1210C107M9PAC

100

6.3

2 x 10 ꢀ F / 16 V / 1206

20%

22 mF / 10 V / 1210 + 10 mF / 16 V / 1206

3 x 10 mF / 16 V / 1206

26.1

27

C1210C476M9PAC

C1210C226K8PAC

C1210C106K4PAC

C1210C106K3RAC

C1210C106M6PAC

47

6.3

10

16

25

35

20%

22

10

12

15

9.1

10 ꢀ F / 35 V / 1210

10%

10

16

2 x 10 mF / 16 V / 1206

10%

10

6.7 @ 15

9.1 @ 10

8.7 @ 12

8 @ 15

8.7

10 ꢀ F / 35 V / 1210

10%

10

2 x 10 mF / 16 V / 1206

13.4

8

20%

10 ꢀ F / 35 V / 1210

2 x 10 ꢀ F / 25 V / 1206

10.6

13.4

15.9

5

5 @ 24

2 x 10 mF / 25 V / 1210

3 x 10 mF / 25 V / 1206

For X5R and X7R dielectric capacitors the change in

capacitance over their operating temperature range is

limited to 15%.

24

10 ꢀ F / 35 V / 1210

2 x 4.7 mF / 50 V / 1206

6.2

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21

NCL31010

Transient Response

This duty cycle requirement in CCM can be translated into

a minimum input voltage requirement:

A first order equivalent circuit of the output impedance of

the NCL31010 DC/DC regulators operating in CCM is

shown in figure 8.

V_INw 2.985 (V_OUT* L S_X)

(eq. 9)

Obviously without compensation ramp this equation

simplifies to:

VDDx

V_INw 2.985 V_OUT

(eq. 10)

Above constraint explains why a compensation ramp is

implemented on the VDD2 regulator for the 15 V and 24 V

output voltage settings. Likewise it explains why there is no

need for a compensation ramp on the VDD regulator and on

the VDD2 regulator for the other output voltage settings.

The maximum input voltage is determined by the

maximum recommended operating voltage of the VPORTP

pins (i.e. 57 V).

ACL

ACR

C

VDDx

p

RTN

Figure 8. Model for Loop Response

The output capacitor delivers the initial current for

transient loads. The output voltage undershoot/overshoot

after a load step up/down transient can be estimated by:

Input Capacitor

The VPORTP pin 41 must be decoupled to the source of

the bottom mosfets (FDC8602) with a ceramic capacitor.

The Kemet X7R Size 1210 Capacitor with 1 ꢀ F nominal

capacitance value is a good option, since the capacitance

change over DC bias voltage remains moderate.

ꢄ v_VDDx+ * ACR_p

ꢄ i_VDDx

(eq. 5)

On the other hand, the model explains there is a constraint

on the maximum output capacitance value. This can be

expressed by the damping factor of the parallel RLC circuit:

Table 19. X7R CAPACITOR SIZE 1210

ACL_p

1

Ǹ

ꢅ +

C

VPORTP

(eq. 6)

2 ACR_p

C_VDDx

(nF @ V)

865 @ 41.1

800 @ 50

702 @ 57

Product

C (mF)

V

(V)

0

Rated

It is best to keep the damping factor at or above unity. That

it is equivalent to keeping the gain crossover frequency at

least 4 times higher than the compensation network zero:

C1210C105K1RAC

1

100

10%

ACR_p

f_z

+

(eq. 7)

2 ꢃ ACL_p

Light Load Operation

Otherwise the load step response will become oscillatory.

In Discontinuous Conduction Mode (DCM), the square of

the top mosfet on−time is proportional to the output current.

When the load becomes lower than the output current

corresponding with the minimum on−time, the converter

will exhibit pulse skipping behavior.

Input Voltage Range

The minimum input voltage is determined by the

NCL31010 VPORTP undervoltage lockout (UVLO).

However both the VDD and the VDD2 regulators shall

continue to operate without interruption in the presence of

transients lasting less than 250 ꢀ s at the PSE PI according to

IEEE Std 802.3.

Eventually another constraint on the minimum input

voltage is related to the subharmonic oscillation

phenomenon that might occur in current−mode controlled

converters. A rule of thumb is to operate a peak

current−mode controller without compensation ramp in

VDD2 Output voltage

The VDD2 output voltage is programmed in the

VDD2_SEL[2:0] bits of Test Register 10 (&TREG10

0x6E):

Table 20.

Bit [2:0]

000b

001b

010b

011b

100b

101b

110b

111b

VDD2 Output Voltage (V)

CCM up to 33.5% duty cycle in order to keep the Q of the

2.5

10

5

p

current−mode double pole up to 1.932 (ꢅ ≥ 0.259). For a

p

peak current−mode controller with compensation ramp in

CCM, this rule of thumb for the duty cycle becomes:

15

3.3

12

7.2

24

0.335

D v

L S_X

ǒ

Ǔ

1 *

(eq. 8)

V_OUT

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22

NCL31010

Short Circuit Protection

The default output voltage of VDD2 is 5 V.

Do NOT write to Test Register 10 when the VDD2

regulator is already enabled.

Besides the peak current limit, the NCL31010 contains

additional short circuit protection. If the voltage drops

significantly below the regulated value during around

15 ms, that specific converter will be shut down. The

converter will be automatically restarted after a cool down

period of around 120 ms.

VDD2 Enable and Shutdown

The VDD2 regulator is enabled when the VDD2_EN bit

in the Control Register (&CTRL 0x04) is set.

Severe Faults

The NCL31010 monitors the drain−source voltage of a

mosfet that is turned−on: if the voltage becomes too large

due to excessive current flow through the mosfet, the

respective converter will be latched off.

If this occurs on the VDD2 regulator, the VDD2NOK bit

in the Status Positive Register (&STATP 0x07) will be set.

This will generate an interrupt on the INTB pin if the

VDD2NOK bit in the Interrupt Positive Mask Register

(&INTP 0x0B) was not masked.

Table 21.

Bit 0

0b

VDD2EN

Disable VDD2

Enable VDD2

1b

Soft−Start

Both regulators have soft−start implemented in order to

limit the overshoot during start−up.

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23

NCL31010

LED DRIVER FUNCTIONAL DESCRIPTION

The NCL31010 incorporates a peak current−mode buck

define the average LED current. To have a good linear

relationship between the duty−cycle and the LED current the

frequency of this signal must be below 1 − 2 kHz. This

method provides a simple way to use PWM directly to

control the LED current, however it does not give the best

dimming accuracy and linearity and the duty−cycle range is

limited. When the PWM digital input pin is low, the MUX

connects VLS to DIMCTRL. VLS has a steady value just

below VCSA_0 to guarantee that the LED driver is

regulating zero current when PWM = 0. When the PWM pin

is high, the voltage on the DIM pin is connected to

DIMCTRL.

LED controller. The controller operates only in CCM mode

and is designed to drive high power LED loads up to 90 W

and beyond. A block diagram of the concept with the

essential parts is given in figure 9.

LEDEN

CLK

When the INTDIMEN bit in the INTDIM register is set

the internal 7−bit DAC output is connected to DIMCTRL.

In this case, the LED current will depend on the value

programmed in the 7 bits of the INTDIM register. The

relationship between the register value and the DAC output

voltage is given below.

SLPCMP

ꢆ

Gi

OTA

LDSNSP

Go

gm

INTDIM

VLS

3:1

MUX

V_REF (INTDIM[6 : 0] ) 1)

SS

V_INTDIM

+

(eq. 12)

128

LDCMP

PWM/EN DIM

The internal DAC can be useful when, for example, the

host MCU is being re−flashed and the DIM voltage is not

controlled during this period. In this case the MCU can

instruct the internal DAC to take control of DIMCTRL net

moments before the MCU firmware is under maintenance.

This is called ‘Warm Boot’.

Figure 9. LED Driver Block Diagram

The LED driver is enabled when the LEDEN bit in the

CTRL register is set. When the LED driver is enabled it is

switching and regulates a current controlled by the

DIMCTRL voltage shown in figure 9. The relationship

between DIMCTRL and the LED current is given below.

Voltage Reference

The NCL31010 provides a precise ( 0.3%) 2.4 V

reference voltage on the VREF pin, which can be used by

external components, for example, as the reference of an

external PWM to DIM circuit or a DAC that controls the

DIM pin voltage. The load on this pin must be limited to

2 mA to ensure the accuracy of the voltage. The advantage

of using this VREF is that the VREF voltage and the

VCSA_0 voltage (the threshold point for zero current) are

related. If VREF deviates, VCSA_0 will deviate in the same

direction by a proportional factor, thus the LED current

regulation inaccuracy of a circuit that is VREF based does

not suffer from the VREF deviation.

(VDIMCTRL * V_{CSA_0}

)

I_LED

+

(eq. 11)

R_SNS 7.333

Several sources can be multiplexed to the DIMCTRL

signal, see figure 10.

PWM/EN

INTDIM[6:0]

DAC

VLS

DIM

DIMCTRL

3:1

MUX

Sense Resistor

Select an appropriate sense resistor based on the

maximum LED current. The resistor value can be calculated

according to:

Figure 10. DIM Selection

(VREF * VCSA_0)

The analog DIM input gives the best dimming

performance in terms of linearity, bandwidth and accuracy.

The DIM pin threshold voltage that provides exactly zero

current is the VCSA_0 voltage. Applying a voltage below

the VCSA_0 lower limit guarantees zero current.

The PWM pin can be used for PWM dimming. A PWM

signal on the PWM input can be used to switch the LED

current between zero and the level defined by the voltage

level on the DIM pin. The duty−cycle of this signal will

R_S

+

(eq. 13)

7.333 Iled_max

Make sure to select a sense resistor that has a value

between 50 mꢁ and 300 mꢁ. Consider the power rating and

the accuracy. A 1 W or 2 W / 1% sense resistor is sufficient

for most applications.

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24

NCL31010

Buck Inductor

Slope Compensation

The rule of thumb is to choose the inductor so that the

peak−peak current ripple in the inductor is 20..30% of the

max dc−current. Calculate the required inductance

according to:

Since a peak−current−mode buck convertor is sensitive to

sub−harmonic oscillations for duty−cycles above 33% slope

compensation must be added. There is a minimum amount

of slope needed to damp sub−harmonic oscillations within

one switching cycle. The slope value can be programmed in

the SLPCMP register. The default value is a good setting for

most applications and normally no changes have to be made

to this register. If the phase margin is not sufficient

(<60 degrees), program ‘0’ to SLP1 and SLP2 field in the

SLPCMP register.

The required amount of slope increases with output

voltage and the ratio from output to input voltage

(duty−cycle). A separate slope setting can be programmed

for slopes below 50% duty−cycle (SLP1 field) and above

(SLP2 field). The possibilities for SLP1 and SLP2 fields are

presented in table 22 and 23 respectively. The default value

for SLP1 and SLP2 is set to 0.1 V/ꢀ s and 0.3 V/ꢀ s. Increase

SLP1 one level if sub−harmonic oscillation is seen below

50% duty−cycle. Increase SLP2 one level if subharmonic

oscillation is seen above 50% duty−cycle.

Vi

L +

(eq. 14)

4 fs Iled_max 0.3

Make sure that the specified RMS current rating of the

inductor (typically the current that results in a temperature

increase of 40°C due to copper losses) is at or above the max

dc−current used in the application. The saturation current

rating minus 20% derating should still be at or above the

largest peak current. Use the formulas below to find

appropriate minimum RMS current and saturation current

values.

Irms u Iled_max

(eq. 15)

Vi_max

Ir_max*pkpk

+

(eq. 16)

(eq. 17)

4 fs L

Ir_max*pkpk

_{Isat u}ǒ_{Iledmax )}

Ǔ

1.2

2

Table 22. SLP1 VALUES

Output Capacitor

SPL1 Register Value

Slope [V/ms]

The purpose of the output capacitor is to filter the high

frequency inductor ripple current to some extent. This must

be a 100 V rated ceramic capacitor(s) with low ESR. The

required output capacitor depends on the switching

0

1

2

3

0.1

0.2

0.3

0.4

frequency, the expected LED ripple current (Ir

), the

LED−pkpk

dynamic resistance of the LED string (Rd) and the inductor

ripple current (Ir

). The expression is given below:

max−pkpk

Table 23. SLP2 VALUES

Ir_max*pkpk

8

ꢃ ²

C_O

+

SPL2 Register Value

Slope [V/ms]

(eq. 18)

2ꢃ fs Ir_LED Rd

0

1

2

3

0.3

0.4

0.6

0.9

Substituting Ir

gives:

max

Vi_max

C_O

+

31 fs² L Ir_LED*pkpk Rd

(eq. 19)

A reasonable output capacitor value would be anything

between 100 nF and 1 − 3 ꢀ F. Try to avoid 1608 (metric)

packages or smaller to avoid audible noise. The output

capacitance has no significant effect on stability.

Switching Frequency

All the clocks in the chip are derived from a main 8 MHz

clock. The LED driver’s switching frequency can be

programmed with the LEDFC register. The value in the

register relates to the LED driver switching frequency clock

according to table 24. The default switching frequency is

500 kHz. For most applications that regulate LED currents

below 1.5 A, a switching frequency of 500 kHz is a good

choice. For applications that regulate above 1.5 A, 400 kHz

is recommended.

Bandwidth & Stability

The control loop in this configuration exhibits no poles to

be compensated in the bandwidth area so a single

compensation capacitor connected to LDCMP pin will

th

suffice. This strategy is suitable for a bandwidth up to 1/10

of the switching frequency and provides a phase margin of

60 − 75 degrees. The compensation capacitor can be

calculated as:

G_M

C_C+ 2.44

(eq. 20)

2 ꢃ f_C

f is the wanted cross−over frequency and G = 1 mS.

C

M

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25

NCL31010

Table 24. SWITCHING FREQUENCY

Table 25. TRANSISTOR SELECTION

LEDFC [5:0]

DIVISOR

8

LED_CLK [kHz]

1000.00

800.00

666.67

571.43

500.00

444.44

400.00

363.64

333.33

307.69

285.71

250.00

235.29

210.53

190.48

173.91

153.85

142.86

125.00

114.29

105.26

95.24

Product

V

(V)

r

(mW)

DS(on)

DS

Top

NVTFS6H880N

NVTFS6H888N

NVTFS6H860N

FDMA037N08LC

80

32

0

1

10

80

55

2

12

21.1

36.5

3

14

Bottom

4

16

Do not use external gate resistors for the transistors. The

chip uses the voltages at the gate nodes as feedback for

desaturation protection and fast switching.

5

18

6

20

7

22

Thermal Considerations

8

24

Additional copper is needed for good thermal

performance. A typical design with LED currents below 2 A

(<60 W) requires a small (both copper sides) cooling plane

9

26

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

28

2

with size 2 − 3 cm connected to the drain of the top fet. For

32

2

2 A and above (>60 W), a 3 − 4 cm copper plane is

recommended on both sides. The bottom fet drain

connection should also have a small 0.5 − 1 cm copper

34

2

38

plane.

42

Metrology

46

The NCL31010 incorporates a high accuracy metrology

block that measures several voltages, currents and

temperatures in the system. This is made possible by an

internal 10−bit ADC, which is multiplexed to measure

VPORTP, VDD1, VDD2, VLED, ILED, IPORTP, IVDD,

IVDD2 and TLED. The metrology measurements can be

enabled with the DIAG_EN bit in the CTRL register. The

measurements are referenced to RTN and are sampled every

249 ms. The measurements can be read out from the 16−bit

registers. The relationship between the measured

voltage/current/temperature and the values read in the

registers is given in equation 21 to equation 29.

52

56

64

70

76

84

102

112

124

150

180

78.43

71.43

64.52

53.33

5000

201

VREF

2¹⁶

VPORT + VPORTP_reg

(eq. 21)

(eq. 22)

(eq. 23)

(eq. 24)

(eq. 25)

(eq. 26)

(eq. 27)

(eq. 28)

(eq. 29)

44.44

VREF

6 Rs 2¹⁶

IPORT + IPORTP_reg

Switching Transistors

The selection of the switching transistors is a critical

aspect for the correct functioning of the LED driver. It can

significantly impact the power efficiency and thermal

performance. The top fet in particular will dissipate most of

the switching losses. Because this component is essential to

the LED driver performance it is advised to select one of the

validated transistors for top and bottom given in table 25.

The transistors are ranked high−low for efficiency. The

typical LED driver efficiency achievable with the proposed

transistors for 30 − 70 W range is 97%. The best combination

is to use FDMA037N08L as bottom fet and NVTFS6H880N

or NVTFS6H888N as top fet.

3

VREF

2¹⁶

VDD + VDD_reg

2

32

VREF

2¹⁶

VDD2 + VDD2_reg

3

VREF

10 Rs 2¹⁶

IDD + IDD_reg

VREF

IDD2 + IDD2_reg

VLED + VLED_reg

10 Rs 2¹⁶

35

2

VREF

2¹⁶

3

VREF

ILED + ILED_reg

Rs 2¹⁶

22

33

VREF

2¹⁶

TLED + TLED_reg

24

www.onsemi.com

26

NCL31010

TLED

Status Bits

The NCL31010 has ten status−monitoring bits, spread

over two 8−bit registers. The status bits are active when a

particular condition is met. As an example, STAT1.TW is

active when the internally measured temperature exceeds

the temperature limit set by the TWTH (thermal warning

threshold). When the condition disappears, the

corresponding bit becomes inactive immediately. The

actual, immediate, value of the status bits can be accessed

through the read−only status registers (STAT). Status bits

can become active only very briefly. As such, reading the

STAT is not sufficient to detect the activation of a fault in an

NCL31010 device: between subsequent reads, the fault

could have appeared and disappeared. The read−only

‘Status Positive Transition’ register (STATP) addresses this

problem. It reflects all status bits that have become active

since the last read of the STATP. Thus, by reading STAT and

STATP, the host microcontroller can determine whether a

status bit has been active since the last read, and whether it

is still active. The STATP bits are cleared on read. The

addresses of the STAT and STATP are contiguous. Thus the

microcontroller can read out the STAT and STATP

atomically, ensuring coherent information is received.

In addition to STATP, the ‘Status negative transition’

STATN register activates when the fault disappears

(negative edge STAT register). This register is also cleared

on read. The status signals are grouped in two categories:

warnings and errors. This is discussed below.

LEDTW_H

LEDTW_L

MCU READ

STAT + STATP

MCU READ

STAT + STATN

STAT.LEDTW

STATP.LEDTW

STATN.LEDTW

INTb

LEDTW_H = LEDTWTH + LEDTWHYS

LEDTW_L = LEDTWTH − LEDTWHYS

Figure 11. LEDTW [INTCFG=1 INTP/INTN=1]

TLED

LEDTW_H

LEDTW_L

MCU READ

STAT + STATP

MCU READ

STAT + STATN

STAT.LEDTW

STATP.LEDTW

STATN.LEDTW

INTb

LEDTW_H = LEDTWTH + LEDTWHYS

LEDTW_L = LEDTWTH − LEDTWHYS

Warnings

Figure 12. LEDTW [INTCFG=0 INTP/INTN=1]

Some of the status bits can be considered as a warning

signal meaning there is no need for a very fast response from

the NCL31010 itself and the decision can be left up to the

microcontroller. The NCL31010 takes no action other than

signal that a threshold is crossed using the status bits. The

status bits that are considered as warnings are: TW,

LEDTSD, LEDTW, LEDOV, LEDUV, VDD2OC,

VDDOC. These warnings are reflected in the STAT1 and

STATP1/STATN1 registers. These analog values are

measured by the metrology block with the internal ADC and

a sampling rate of 249 ms. For the warnings, all the

thresholds and hysteresis values are programmable except

for TW. An example for LEDTW is given in figures 11 and

12.

A warning occurs when a programmable limit is crossed.

For example, when the voltage on the TLED pin exceeds the

LEDTWTH+LEDTWHYS threshold the status LEDTW bit

is set in the STAT register. The threshold and hysteresis are

programmable in the LEDTWTH and LEDTWHYS

registers. Only when the voltage on the TLED pin drops

below LEDTWTH−LEDTWHYS the LEDTW bit in the

STAT is cleared. If the LEDTW bit in the Interrupt Mask

register is set a pulse interrupt will be given on the INTb pin

when the LEDTW bit is set in the STAT. The warnings

except TW are disabled when LEDTWTH + LEDTWHYS

> 1022. All warnings except TW are disabled by default

because they have 1023 in their threshold registers. All the

warnings are explained below.

www.onsemi.com

27

NCL31010

MCU DISABLES LED

CTRL.LEDEN = 0

TW: Thermal Warning

The TW bit in the STAT is set if the junction temperature

of the NCL31010 goes above TW_H. This warning is active

by default and cannot be de−activated. This threshold is not

programmable.

DESAT LEVEL

MCU READ

MCU RESET LED

STAT + STATP

CTRL.LEDEN = 1

LEDNOK

TH

LEDTW: LED Thermal Warning

This warning will occur if the voltage on TLED pin is

above LEDTWTH+LEDTWHYS. Typically, an NTC is

mounted on the LED load and connected to TLED and RTN.

This warning is not active by default and the threshold and

hysteresis are programmable.

STAT.LEDNOK

STATP.LEDNOK

STATP CLEAR ON READ

LED driver DISABLED

LED driver state

LEDTSD: LED Thermal Shutdown

INTb

This warning will occur if the voltage on TLED pin is

above LEDTSD + LEDTSDHYS. Typically, an NTC is

mounted on the LED load and connected to TLED and RTN.

This warning is not active by default and the threshold and

hysteresis are programmable.

Figure 13. LEDNOK [INTCFG=1 INTP=1 INTN=X]

MCU DISABLES LED

CTRL.LEDEN = 0

DESAT LEVEL

MCU READ

MCU RESET LED

STAT + STATP

CTRL.LEDEN = 1

LEDOV: LED Overvoltage

LEDNOK

TH

This warning will typically occur if the LED string is an

open circuit. The LEDOV bit in the STAT is set if the VLED

pin voltage goes above LEDOVTH + LEDOVHYS. The

threshold and hysteresis are programmable.

STAT.LEDNOK

STATP.LEDNOK

LEDUV: LED Undervoltage

STATP CLEAR ON READ

LED driver DISABLED

This warning will typically occur if the LED string is a

short circuit. The LEDUV bit is set in the STAT. This

warning is not active by default and the threshold and

hysteresis are programmable.

LED driver state

INTb

VDDOC and VDD2OC: VDDx Overcurrent

Figure 14. LEDNOK [INTCFG=0 INTP=1 INTN=X]

A warning is given if the average current is above

VDDxOCTH + VDDxOCHYS. Note that the DC−DC’s also

have a current limiting hick−up mode built−in. This warning

is not active by default and the threshold and hysteresis are

programmable.

An error indicates that there is a hardware issue. Further

explanation for each of the errors is given below.

TSD: Thermal Shutdown

When the junction temperature of the NCL31010 reaches

TSD_H, the NCL31010 will shut down all functions and go

into reset state. This includes disconnecting the pass switch.

Therefore, the PSE will disconnect the device after the MPS

dropout time. The device will remain in reset until the

junction temperature drops below TSD_L and a new

detection and classification cycle is started by the PSE.

Errors

There are severe error conditions that require NCL31010

to disable the block that triggered the error immediately

before any damage can occur. These are LEDNOK, LEDOC

and VDD2NOK. These errors are reflected in the STAT2

and STATP2/STATN2 registers. The STAT signals behavior

is the same for errors and warnings. Note that typically

STATN has no use for errors because the fault is gone when

the micro−controller reads the registers.

In case of a desaturation fault during the switching of the

transistors in the LED driver a LEDNOK error is triggered

and NCL31010 will disable the LED driver block.

NCL31010 will remain disabled until the LEDEN bit is reset

by the user. Similarly if a desaturation fault occurs in the

DC−DC2 block a VDD2NOK error is triggered and the

DC−DC2 block is disabled. A LEDOC error is triggered if

the LED driver sense resistor voltage crosses the OCP_TH

threshold indicating a LED overcurrent. The LED block is

disabled and resumes after a reset of the LEDEN bit. See

figures 13 and 14 for clarification.

VDD2NOK: Desaturation Error Switching Transistors

NCL31010 will shut−down DC−DC2 if this error occurs.

DC−DC2 can be restarted if VDD2EN bit in CTRL is reset.

LEDNOK: Desaturation Error Switching Transistors

NCL31010 will shut−down LED block if this error

occurs. The LED block can be restarted if LEDEN bit in

CTRL is reset.

LEDOC: LED Overcurrent

This error can occur if the LED load wires are not well

connected to the driver board and contact−bounce occurs. A

sudden failure of the sense resistor can also trigger this error.

NCL31010 will shut−down the LED block if this error

occurs and set the LEDOC bit in the STATP.

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28

NCL31010

Interrupts

The FMOD register value affects the modulation period

(Tmod) of the triangular signal. The default value for fmod

is 400 Hz. The value in the FMOD register relates to fmod

according to table 27.

The NCL31010 has a flexible interrupt mechanism that

obviates the need for frequent polling. With an appropriate

configuration of the two interrupt mask registers (INTP and

INTN), most applications will not require polling at all,

while providing for coherent status awareness in the host

microcontroller. When an interrupt is triggered, INTb is

Table 27. MODULATION FREQUENCY

FMOD [1:0]

fmod (1/Tmod)

200 Hz

2

pulled low. INTb is an open−drain pin to ensure multiple I C

0

1

2

3

bus participants can share the same interrupt line. A pull−up

resistor must be provided externally. The NCL31010

provides an open−drain, active−low interrupt pin that

activates, i.e. pulled low, when any interrupt condition is

satisfied. An interrupt condition is satisfied if any of the bits

in the STATP or STATN register is active and if the

corresponding bit in the INTP and INTN are unmasked

(= set).

400 Hz

800 Hz

1600 Hz

The spread spectrum is illustrated with figure 15.

If CTRL.INTCFG is zero (default) level interrupt is used

and INTb goes low as long as the interrupt condition is

satisfied. If CTRL.INTCFG is set, INTb is configured for

pulsed interrupt and INTb will go low for about 10us every

time the interrupt condition is satisfied.

Ts + ꢄ T

Ts (125 ꢀ s)

Spread Spectrum

Ts − ꢄ T

The purpose of spread spectrum is to continuously change

the clock frequency used by the switching convertors in a

periodic pattern to reduce the detected energy levels at a

given frequency. It will improve the results of conducted

EMI tests, not for radiated EMI. The spread spectrum block

modulates the main 8 MHz clock according to a number of

discrete steps in a triangular pattern as shown in figure 15.

The spread clock signal is used by digital, LED driver and

DC−DC convertors. The spread spectrum is disabled by

default and can be enabled with the JIT_EN bit in the

LEDFC register. The amount of spreading can be configured

with the FDEV register. The deviation (%) is the amplitude

variation towards the main clock. When the main clock is

divided the same amount of spread (%) is still present on the

divided clock. Table 26 relates the value for FDEV register

to the amount of spreading. The default spreading when

spread spectrum is enabled is 3%.

Tmod

t

Figure 15. Spread Spectrum

Both fmod and fdev affect the modulation index of the

frequency modulated clock signal.

fdev

MI +

(eq. 30)

fmod

More suppression is achieved when the modulation index

is higher. This is true if the RBW of the spectrum analyzer

would be infinitely small, instead the RBW is 9 kHz for

conducted emission measurements (150 kHz to 30 MHz)

and 120 kHz for radiated emission measurements (30 MHz

to 1 GHz). When the RBW is 9 kHz the spectrum analyzer

will show better suppression if fmod has the maximum

value.

Address Selection (NCL31010I)

Table 26. FREQUENCY DEVIATION

The NCL31010 comes in two variants. One with SPI

FDEV [2:0]

D (%)

3

2

interface and one with I C interface. This is defined by OTP

0

1

2

3

4

5

6

7

(One−time programmable memory) in the chip. In case the

2

5

device is configured as I C slave the ADDR1 and ADDR2

2

pins define the I C slave bus address. The device can have

6

2

6 possible I C slave addresses to differentiate devices on the

8

2

same I C−bus. The mapping between the logic level on these

2

10

11

12.5

14

pins and the I C slave address is given in table 28.

www.onsemi.com

29

NCL31010

Table 28. SLAVE ADDRESS

ADDR1_CSB

RTN

ADDR2_MISO

Slave Address

0x50 (1010000)

0x52 (1010010)

0x54 (1010100)

0x56 (1010110)

0x58 (1011000)

0x5A (1011010)

RTN

VDD

RTN

VDD

RTN

VDD

FLOAT

RTN

Figure 17. I²C Read Operation (1 byte)

VDD

FLOAT

I²C Interface (NCL31010I)

2

The I C interface can be used to interface with the

NCL31010 in order to read or write its registers. The

2

NCL31010 operates as an I C slave device. The SDA and

2

SCL lines comply with the I C electrical specification and

Figure 18. I²C Read Operation (2 bytes or More)

should be terminated with external pull−up resistors. The

device supports the maximum bus speed of 400 kbit/s.

Figure 16 shows how an I C write operation is performed.

SPI Interface (NCL31010S)

2

The serial peripheral interface (SPI) allows an external

microcontroller (Master) to communicate with

NCL31010S. The device acts always as a Slave and cant

initiate any transmission. The operation of the device is

configured and controlled by means of registers which are

observable for read and/or write from the Master. ’

During a SPI transfer, data is simultaneously transmitted

(shifted out serially) and received (shifted in serially). A

serial clock line (SCL/CLK) synchronizes shifting and

sampling of the information on the two serial data lines,

MOSI (SDA_MOSI pin) and MISO (ADDR2_MISO pin).

The MISO signal is the output from the slave and MOSI is

the master output.

The master gives the Start condition followed by the 7−bit

slave address and the read−write bit. The slave

acknowledges the address. The master then places the

register address on the bus. This is again acknowledged by

the slave. Finally the data byte is placed on the bus by the

master. The slave must acknowledge this. The master can

write more than one byte in one transaction if he wishes.

Writing to the registers in this case is contiguous. As more

data bytes follow, the register address is auto−incremented.

NCL31010S is configured for SPI MODE 2. This means

that the signal on the MOSI/MISO data lines is sampled on

the negative clock edge and that the CLK signal is high when

idle. Note that the NCL31010S expects the first data signal

to be present and stable on the first negative clock edge.

Figure 19 shows how to perform a SPI write operation.

The master pulls the chip select signal low and a little later

the master provides a minimum sequence of 16 clock cycles.

During the first eight clock cycles, the master provides the

register address [A6:A0] and the read−write bit on the MOSI

line. If the read−write bit is high, a read operation is selected.

During the following eight clock cycles, the slave clocks in

the data byte [D7:D0]. If the master provides a multiple of

eight clock cycles, more bytes can be written contiguously.

The register counter is automatically incremented.

Figure 20 demonstrates a SPI read operation. The same

principle applies as with a write operation only now the slave

puts the contents of the addressed register on the MISO line

during the last eight clock cycles. If the master provides a

multiple of eight clock cycles more registers can be read

contiguously.

Figure 16. I²C Write Operation (2 bytes)

2

Figure shows how to perform an I C read operation. The

first part of a read operation is the same as for a write

operation. The master provides the slave address, write bit,

and register address were to read from. It then provides a

repeated start condition which behaves the same as a start

condition. It provides the slave address again, but this time

it uses it makes the read−write bit zero to indicate a read

operation. The slave acknowledges and places the requested

data byte on the bus. If the master responds with a NACK

(not acknowledge) and a STOP condition the message

transaction is terminated. If instead the master uses an ACK

it indicates to the slave that it wants to read more bytes. The

slave will auto−increment the register address to read from

and put the bytes on the bus as shown in Figure 18.

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30

NCL31010

Multiple SPI slaves can be used with one SPI master as

shown in figure 21. A separate CSB signal is required for

each slave. Daisy chaining is not supported.

Figure 19. SPI Write Operation (1 byte)

Figure 20. SPI Read Operation (1 byte)

Figure 21. SPI Multi Slave

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31

NCL31010

REGISTER MAP

Table 29. REGISTER MAP

Addr

Name

RID1

Reset Bits

MSB

LSB

00

H

01

H

02

H

03

H

04

H

05

H

06

H

07

H

08

H

09

H

00

H

75

H

7:0

MANUF_H

RID2

MANUF_L

PART_L

Rsv.

PART_H

REV

LCF CLASSEVENT

RID3

8C

7:0

H

CLASS

CTRL

00

7:0

ACS

7:0

INTCFG

Rsv.

DIAG_EN LED_EN VDD2_EN

LEDUV VDD2OC VDD1OC

LEDOC LEDNOK VDD2NOK

LEDUV VDD2OC VDD1OC

LEDOC LEDNOK VDD2NOK

LEDUV VDD2OC VDD1OC

LEDOC LEDNOK VDD2NOK

LEDUV VDD2OC VDD1OC

LEDOC LEDNOK VDD2NOK

LEDUV VDD2OC VDD1OC

LEDOC LEDNOK VDD2NOK

STAT1

STAT2

STATP1

STATP2

STATN1

STATN2

INTP1

INTP2

INTN1

INTN2

VBB

7:0

TW

LEDTSD LEDTW

Rsv.

LEDOV

7:0

Rsv.

LEDTSD LEDTW

Rsv.

7:0

LEDTSD LEDTW

Rsv.

0A

H

0B

H

7:0

LEDTSD LEDTW

Rsv.

0C

0D

7:0

H

7:0

LEDTSD LEDTW

Rsv.

0E

7:0

10

12

14

16

18

0000

15:8

7:0

ADCv

H

ADCv

Rsv.

IBB

VDD1

15:8

7:0

ADCv

val

H

ADCv

val

Rsv.

15:8

7:0

IDD1

15:8

7:0

VDD2

15:8

7:0

1A

H

IDD2

15:8

7:0

1C

VLED

15:8

7:0

H

1E

ILED

15:8

7:0

20

22

24

26

TLED

15:8

7:0

VDD1OCTH

VDD2OCTH

TLEDTWTH

FFFF

15:8

7:0

H

15:8

7:0

val

15:8

7:0

val

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32

NCL31010

Table 29. REGISTER MAP (continued)

Addr

28

Name

Reset Bits

MSB

LSB

TLEDTSDTH

FFFF

15:8

7:0

15:8

7:0

15:8

7:0

val

H

val

Rsv.

2A

H

VLEDOVTH

VLEDUVTH

2C

H

30

H

31

H

32

H

33

H

34

H

35

H

40

H

41

H

42

H

50

H

51

H

52

H

VDD1OCTH_HYS

VDD2OCTH_HYS

TLEDTWTH_HYS

0A

Rsv.

val

H

Rsv.

val

TLEDTSDTH_HYS 0A

Rsv.

val

VLEDOVTH_HYS

VLEDUVTH_HYS

INTDIM

0A

Rsv.

val

Rsv.

val

00

04

EN

DACv

FREQ

LEDFC

JIT_EN

SLCMP

0A

Rsv.

SLP2

SLP1

val

H

MPS

84

06

01

EN

DELTA

FDEV

Rsv.

SSLUT_DIS

Rsv.

FDEV

FMOD

Rsv.

REGISTER RID1

Manufacturer, part and revision identification.

7

6

5

4

3

2

1

0

MANUF_H

r

0

Bits 0–7, MANUF_H: Manufacturer ID.

REGISTER RID2

Manufacturer, part and revision identification.

7

6

5

4

3

2

1

0

MANUF_L

PART_H

r

7

5

Bits 4–7, MANUF_L: Manufacturer ID

Bits 0–3, PART_H:

Part ID

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33

NCL31010

REGISTER RID3

Manufacturer, part and revision identification.

7

6

5

4

3

2

1

REV

r

0

PART_L

r

11

H

4

Bits 3–7, PART_L: Part ID.

Bits 0–2, REV:

Revision ID.

1: N1A

2: O1A

3: P1A

4: Q1A

REGISTER CLASS

PoE classification Register

7

6

5

4

3

ACS

r

2

LCF

r

1

0

Rsv.

CLASSEVENT

r

0

Bits 4–7:

Reserved, do not use.

Bit 3, ACS:

Indicates whether the PD has signaled the PSE that it wants to use auto−classification.

0: The PD will not attempt to use auto−classification.

1: The PD has signaled the PD that it might want to use auto−classification.

Indicates whether a Long Class Finger is detected.

Bit 2, LCF:

0: No LCF given by PSE. A standard MPS pulse is given if MPS enabled.

1: LCF given by PSE. A MPS pulse with longer period is given if MPS enabled.

Bits 0–1, CLASSEVENT: These bits indicate the assigned power class by the PSE. The PD should always keep the power

consumption below this power class budget.

If the requested power budget using the class resistors on the board is lower than the power class budget,

the PD should limit the power budget to whichever is lower.

0: Lowest power class, 13 W.

1: Power class, 25.5 W.

2: Power class, 51 W.

3: Power class, 71 W.

REGISTER CTRL

Control register for the major blocks in the system.

7

INTCFG

r/w

6

5

4

3

2

1

0

Rsv.

DIAG_EN LED_EN VDD2_EN

r

r/w

0

r/w

0

r/w

0

Bit 7, INTCFG:

Bits 3–6:

Define how the interrupt on the INTB line behaves.

0: The INTB pin is pulled low when a interrupt occurs. It stays low until the STATPx registers are read

and provided the alert condition is gone (STATx register bits are cleared).

1: A pulse is given on each interrupt by the INTB pin.

Reserved, do not use.

Bit 2, DIAG_EN: The diagnostics function measures voltages, currents and temperatures in the system using the internal

ADC.

0: Diagnostics block is disabled.

1: Diagnostics block is enabled.

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34

NCL31010

Bit 1, LED_EN:

Enable bit for the LED driver.

0: LED driver is disabled.

1: LED driver is enabled.

Bit 0, VDD2_EN: Enable bit for DC/DC2 converter.

0: DC/DC2 is disabled.

1: DC/DC2 is enabled.

REGISTER STAT1

A signal/alert is currently active.

7

6

5

4

3

2

1

0

Rsv. TW LEDTSD LEDTW

LEDOV

LEDUV VDD2OC VDD1OC

r

0

Bit 7:

Bit 6, TW:

Reserved, do not use.

Thermal warning of the chip.

0: Alert is not active.

1: Alert is active.

Bit 5, LEDTSD:

Bit 4, LEDTW:

Bit 3, LEDOV:

Bit 2, LEDUV:

Bit 1, VDD2OC:

Bit 0, VDD1OC:

LED Thermal shutdown. Is active if the voltage on the TLED pin is above TLEDTSDTH +

TLED_TSDTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDTSDTH −

TLED_TSDTH_HYST.

0: Alert is not active.

1: Alert is active.

LED Thermal warning. Is active if the voltage on the TLED pin is above TLEDTWTH +

TLED_TWTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDWTH −

TLED_TWTH_HYST.

0: Alert is not active.

1: Alert is active.

LED Overvoltage. Is active if the voltage on the VLED pin is above VLEDOVTH +

VLED_OVTH_HYST threshold. Becomes false if the VLED voltage drops below VLEDOVTH −

VLED_OVTH_HYST.

0: Alert is not active.

1: Alert is active.

LED Undervoltage. Is active if the voltage on the VLED pin is below VLEDUVTH −

VLED_UVTH_HYST threshold. Becomes false if the VLED voltage is above VLEDUVTH +

VLED_UVTH_HYST.

0: Alert is not active.

1: Alert is active.

VDD2 Overcurrent. Is active if the IDD2 current is above VDD2OCTH + VDD2_OCTH_HYST

threshold. Becomes false if the VDD2OCTH current is below VDD2_OCTH_UVTH +

VDD2_OCTH_HYST.

0: Alert is not active.

1: Alert is active.

VDD1 Overcurrent. Is active if the IDD1 current is above a fixed limit.

0: Alert is not active.

1: Alert is active.

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35

NCL31010

REGISTER STAT2

A signal/alert is currently active.

7

6

5

Rsv.

r

4

3

2

1

0

LEDOC LEDNOK VDD2NOK

r

0

Bits 3–7:

Bit 2, LEDOC:

Reserved, do not use.

LED Overcurrent. Is active if this condition is true: ILED x Rsns > 0.382.

In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the

LED driver.

The LED current will drop immediately and the LEDOC bit in this register will be cleared before the

MCU can read it and the LEDOC bit in the STATP register will be set indicating a LED overcurrent event

occured.

0: Alert is not active.

1: Alert is active.

Bit 1, LEDNOK:

LED desaturation error. Is active if a severe error occured in one of the switching transistors of the LED

driver.

In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the

LED driver.

The LED current will drop immediately and the LEDNOK bit in this register will be cleared before the

MCU can read it and the LEDNOK bit in the STATP register will be set indicating there is a severe issue

with the transistors.

This error indicates something is wrong with the hardware of the LED driver.

0: Alert is not active.

1: Alert is active.

Bit 0, VDD2NOK: VDD2 desaturation error. True if a severe error occured in of the switching transistors of the DC/DC2

converter.

In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the

DC/DC1.

The VDD2 current will drop immediately and the VDD2NOK bit in this register will be cleared before

the MCU can read it and the VDD2NOK bit in the STATP register will be set indicating there is a severe

issue with the transistors.

This error indicates something is wrong with the hardware of the VDD2 DC/DC1.

0: Alert is not active.

1: Alert is active.

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36

NCL31010

REGISTER STATP1

A signal has become active since the last read to this register.

7

6

5

4

3

2

1

0

Rsv. TW LEDTSD LEDTW LEDOV

LEDUV VDD2OC VDD1OC

r

0

Bit 7:

Bit 6, TW:

Reserved, do not use.

Thermal warning of the chip.

0: Alert is not active.

1: Alert is active.

Bit 5, LEDTSD:

Bit 4, LEDTW:

Bit 3, LEDOV:

Bit 2, LEDUV:

Bit 1, VDD2OC:

Bit 0, VDD1OC:

LED Thermal shutdown. True as long as the voltage on the TLED pin is above TLEDTSDTH +

TLED_TSDTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDTSDTH −

TLED_TSDTH_HYST.

0: Alert is not active.

1: Alert is active.

LED Thermal warning. True as long as the voltage on the TLED pin is above TLEDTWTH +

TLED_TWTH_HYST threshold. Becomes false if the TLED voltage drops below TLEDWTH −

TLED_TWTH_HYST.

0: Alert is not active.

1: Alert is active.

LED Overvoltage. True as long as the voltage on the VLED pin is above VLEDOVTH +

VLED_OVTH_HYST threshold. Becomes false if the VLED voltage drops below VLEDOVTH −

VLED_OVTH_HYST.

0: Alert is not active.

1: Alert is active.

LED Undervoltage. True as long as the voltage on the VLED pin is below VLEDUVTH −

VLED_UVTH_HYST threshold. Becomes false if the VLED voltage is above VLEDUVTH +

VLED_UVTH_HYST.

0: Alert is not active.

1: Alert is active.

VDD2 Overcurrent. True as long as the IDD2 current is above VDD2OCTH + VDD2_OCTH_HYST

threshold. Becomes false if the VDD2OCTH current is below VDD2_OCTH_UVTH +

VDD2_OCTH_HYST.

0: Alert is not active.

1: Alert is active.

VDD1 Overcurrent. True as long as the IDD1 current is above a fixed limit of ....

0: Alert is not active.

1: Alert is active.

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37

NCL31010

REGISTER STATP2

A signal has become active since the last read to this register.

7

6

5

Rsv.

r

4

3

2

1

0

LEDOC LEDNOK VDD2NOK

r

0

Bits 3–7:

Bit 2, LEDOC:

Reserved, do not use.

LED Overcurrent. True as long as this condition is true: ILED x Rsns > 0.382.

In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the

LED driver.

The LED current will drop immediately and the LEDOC bit in this register will be cleared before the

MCU can read it and the LEDOC bit in the STATP register will be set indicating a LED overcurrent

event occured.

0: Alert is not active.

1: Alert is active.

Bit 1, LEDNOK:

LED desaturation error. True if a severe error occured in of the switching transistors of the LED driver.

In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the

LED driver.

The LED current will drop immediately and the LEDNOK bit in this register will be cleared before the

MCU can read it and the LEDNOK bit in the STATP register will be set indicating there is a severe issue

with the transistors.

This error indicates something is wrong with the hardware of the LED driver.

0: Alert is not active.

1: Alert is active.

Bit 0, VDD2NOK: VDD2 desaturation error. True if a severe error occured in of the switching transistors of the DC/DC2

converter.

In reality, when this limit is crossed, a comparator will react in a matter of nanoseconds and turn off the

DC/DC1.

The VDD2 current will drop immediately and the VDD2NOK bit in this register will be cleared before

the MCU can read it and the VDD2NOK bit in the STATP register will be set indicating there is a severe

issue with the transistors.

This error indicates something is wrong with the hardware of the VDD2 DC/DC1.

0: Alert is not active.

1: Alert is active.

REGISTER STATN1

A signal has become inactive since the last read to this register.

7

6

5

4

3

2

1

0

Rsv. TW LEDTSD LEDTW LEDOV

LEDUV VDD2OC VDD1OC

r

0

This register has the same structure as STATP1; refer there for more information.

REGISTER STATN2

A signal has become inactive since the last read to this register.

7

6

5

Rsv.

r

4

3

2

1

0

LEDOC LEDNOK VDD2NOK

r

0

This register has the same structure as STATP2; refer there for more information.

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38

NCL31010

REGISTER INTP1

Interrupt enable register for STATP1. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.

7

6

5

4

3

2

1

0

Rsv. TW LEDTSD LEDTW LEDOV

LEDUV VDD2OC VDD1OC

r

r/w

0

r/w

0

r/w

0

r/w

0

r/w

0

r/w

0

r/w

0

Bit 7:

Reserved, do not use.

Bit 6, TW:

Thermal warning.

0: Interrupt disabled/masked.

1: Interrupt enabled.

Bit 5, LEDTSD:

Bit 4, LEDTW:

Bit 3, LEDOV:

Bit 2, LEDUV:

Bit 1, VDD2OC:

Bit 0, VDD1OC:

LED Thermal shutdown.

0: Interrupt disabled/masked.

1: Interrupt enabled.

LED Thermal warning.

0: Interrupt disabled/masked.

1: Interrupt enabled.

LED Overvoltage.

0: Interrupt disabled/masked.

1: Interrupt enabled.

LED Undervoltage.

0: Interrupt disabled/masked.

1: Interrupt enabled.

VDD2 Overcurrent.

0: Interrupt disabled/masked.

1: Interrupt enabled.

VDD1 Overcurrent.

0: Interrupt disabled/masked.

1: Interrupt enabled.

REGISTER INTP2

Interrupt mask register for STATP2. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.

7

6

5

Rsv.

r

4

3

2

1

0

LEDOC LEDNOK VDD2NOK

r/w

0

r/w

0

r/w

0

Bits 3–7:

Bit 2, LEDOC:

Reserved, do not use.

LED Overcurrent.

0: Interrupt disabled/masked.

1: Interrupt enabled.

Bit 1, LEDNOK:

LED desaturation error.

0: Interrupt disabled/masked.

1: Interrupt enabled.

Bit 0, VDD2NOK: VDD2 desaturation error.

0: Interrupt disabled/masked.

1: Interrupt enabled.

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39

NCL31010

REGISTER INTN1

Interrupt enable register for STATN1. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.

7

6

5

4

3

2

1

0

Rsv. TW LEDTSD LEDTW LEDOV

LEDUV VDD2OC VDD1OC

r

r/w

0

r/w

0

r/w

0

r/w

0

r/w

0

r/w

0

r/w

0

This register has the same structure as INTP1; refer there for more information.

REGISTER INITN2

Interrupt mask register for STATN2. Defines which alert signals, if they become active, result in an interrupt condition on the INTB line.

7

6

5

Rsv.

r

4

3

2

1

0

LEDOC LEDNOK VDD2NOK

r/w

0

r/w

0

r/w

0

This register has the same structure as INTP2; refer there for more information.

REGISTER VBB

VBB−GND voltage measurement.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ADCv

Rsv.

r

0

Bits 6–15, ADCv: ADC value.

Bits 0–5:

Reserved, do not use.

REGISTER IBB

IBB current measurement.

15

14

13

12

11

10

5

4

3

0

ADCv

Rsv.

r

0

Bits 6–15, ADCv: ADC value.

Bits 0–5:

Reserved, do not use.

REGISTER VDD1

VDD1 voltage measurement.

15

14

13

12

11

10

5

4

3

0

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

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40

NCL31010

REGISTER IDD1

IDD1 current measurement.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

REGISTER VDD2

VDD2 voltage measurement.

15

14

13

12

11

10

9

8

7

6

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

REGISTER IDD2

IDD2 current measurement.

15

14

13

12

11

10

9

8

7

6

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

REGISTER VLED

VLED current measurement.

15

14

13

12

11

10

9

8

7

6

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

REGISTER ILED

ILED current measurement.

15

14

13

12

11

10

9

8

7

6

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

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41

NCL31010

REGISTER TLED

TLED voltage measurement.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ADCv

Rsv.

r

0

This register has the same structure as IBB; refer there for more information.

REGISTER VDD10CTH

VDD1 overcurrent threshold register.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

val

r/w

Rsv.

r

3FF

3F

H

Bits 6–15, val: value.

1023: The detection is disabled.

Reserved, do not use.

Bits 0–5:

REGISTER VDD2OCTH

VDD2 overcurrent threshold register.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

val

r/w

Rsv.

r

3FF

3F

H

This register has the same structure as VDD1OCTH; refer there for more information.

REGISTER TLEDTWTH

TLED thermal warning threshold register.

15

14

13

12

11

10

9

8

7

6

5

val

r/w

Rsv.

r

3FF

3F

H

This register has the same structure as VDD1OCTH; refer there for more information.

REGISTER TLEDTSDTH

TLED thermal shutdown threshold register.

15

14

13

12

11

10

9

8

7

6

5

val

r/w

Rsv.

r

3FF

3F

H

This register has the same structure as VDD1OCTH; refer there for more information.

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42

NCL31010

REGISTER VLEDOVTH

VLED overvoltage threshold register.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

val

r/w

Rsv.

r

3FF

3F

H

This register has the same structure as VDD1OCTH; refer there for more information.

REGISTER VLEDUVTH

VLED undervoltage threshold register.

15

14

13

12

11

10

9

8

7

6

5

3

val

r/w

Rsv.

r

3FF

3F

H

This register has the same structure as VDD1OCTH; refer there for more information.

REGISTER VDD1OCTH_HYS

Overcurrent threshold hysteresis register.

7

Rsv.

r

6

5

3

val

r/w

0

0A

H

Bit 7:

Bits 0–6, val:

Reserved, do not use.

value.

REGISTER VDD2OCTH_HYS

Overcurrent threshold hysteresis register.

7

Rsv.

r

4

3

2

1

0

val

r/w

0

0A

H

Bit 7:

Bits 0–6, val:

Reserved, do not use.

value.

REGISTER TLEDTWTH_HYS

LED thermal warning threshold hysteresis register.

7

Rsv.

r

4

3

2

1

0

val

r/w

0

0A

H

This register has the same structure as VDD2OCTH_HYS; refer there for more information.

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43

NCL31010

REGISTER TLEDTSDTH_HYS

TLED thermal shutdown threshold hysteresis register.

7

Rsv.

r

6

5

4

3

2

1

0

val

r/w

0

0A

H

This register has the same structure as VDD2OCTH_HYS; refer there for more information.

REGISTER VLEDOVTH_HYS

VLED overvoltage threshold hysteresis register.

7

Rsv.

r

6

5

4

3

val

r/w

0

0A

H

This register has the same structure as VDD2OCTH_HYS; refer there for more information.

REGISTER VLEDUVTH_HYS

VLED undervoltage threshold hysteresis register.

7

Rsv.

r

6

5

4

3

val

r/w

0

0A

H

This register has the same structure as VDD2OCTH_HYS; refer there for more information.

REGISTER INTDIM

Internal DIM register.

7

EN

r/w

0

6

5

4

3

DACv

r/w

0

Bit 7, EN:

Internal DIM enable.

0: The internal DIM is disabled.

1: The internal DIM is enabled.

Internal DAC value.

Bits 0–6, DACv:

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44

NCL31010

REGISTER LEDFC

LED driver switching frequency register.

7

JIT_EN

r/w

6

5

4

3

FREQ

r/w

2

1

0

4

Bit 7, JIT_EN:

Spread spectrum enable.

0:

1:

Spread spectrum disabled.

Spread spectrum enabled.

Bits 0–6, FREQ:

Switching frequency value.

0:

1:

2:

3:

4:

5:

6:

7:

8:

9:

1 MHz switching frequency.

800 kHz switching frequency.

666 kHz switching frequency.

571 kHz switching frequency.

500 kHz switching frequency.

444 kHz switching frequency.

400 kHz switching frequency.

363 kHz switching frequency.

333 kHz switching frequency.

307 kHz switching frequency.

10: 285 kHz switching frequency.

11: 250 kHz switching frequency.

12: 235 kHz switching frequency.

13: 210 kHz switching frequency.

14: 190 kHz switching frequency.

15: 173 kHz switching frequency.

REGISTER SLCMP

LED driver slope compensation register.

7

6

5

4

3

2

1

0

Rsv.

SLP2

SLP1

r/w

2

r

r/w

2

0

Bits 4–7:

Reserved, do not use.

Bits 2–3, SLP2:

Slope compensation applicable when LED driver is operating in 50% to 100% duty−cycle range.

0: 0.3 V/ꢀ s

1: 0.4 V/ꢀ s

2: 0.6 V/ꢀ s

3: 0.9 V/ꢀ s

Bits 0–1, SLP1:

Slope compensation applicable when LED driver is operating in 0 to 50% duty−cycle range.

0: 0.1 V/ꢀ s

1: 0.2 V/ꢀ s

2: 0.3 V/ꢀ s

3: 0.4 V/ꢀ s

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45

NCL31010

REGISTER MPS

Maintain Power Signature register.

7

EN

r/w

1

6

5

4

3

DELTA

r/w

2

1

0

4

Bit 7, EN:

MPS enable.

0:

1:

MPS disabled.

MPS enabled.

Bits 0–6, DELTA: Define how long the MPS pulse lasts. The minimum MPS pulse is about 7 ms if LCF bit is active and

75 ms if the LCF bit is disabled.

The DELTA value defines how many ms are added to the minimum MPS time.

0:

Add 0 ms to the minimum MPS pulse.

63: Add 63 ms to the minimum MPS pulse.

127: Add 127 ms to the minimum MPS pulse.

REGISTER FDEV

Frequency Deviation register.

7

Rsv.

r

6

5

4

3

2

1

FDEV

r/w

0

SSLUT_DIS

Rsv.

r/w

0

r

0

6

Bit 7:

Reserved, do not use.

Bits 5–6, SSLUT_DIS: Spread Spectrum Look−up Table Disable.

0: The FDEV and FMOD field values are directly used for the spread spectrum block (expert mode).

The user is responsible for calculating the amount of spread.

1: The spread spectrum block calculates the needed deviation and modulation values to achieve a certain

amount of spread (%) based on the FDEV and FMOD field values. The relation between

FMOD/FDEV and the amount of spread (%) is given in a lookup table.

Reserved, do not use.

Bits 3–4:

Bits 0–2, FDEV:

Frequency Deviation value.

0: 1.8 MHz deviation.

1: 914 kHz deviation.

2: 479 kHz deviation.

3: 322 kHz deviation.

4: 246 kHz deviation.

5: 165 kHz deviation.

6: 100 kHz deviation.

7: 56 kHz deviation.

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46

NCL31010

REGISTER FMOD

Frequency Modulation register.

7

6

5

4

3

2

1

0

Rsv.

val

r/w

1

r

0

Bits 2–7:

Reserved, do not use.

Bits 0–1, val:

Frequency Modulation value.

0: 200 Hz modulation.

1: 400 Hz modulation.

2: 800 Hz modulation.

3: 1600 Hz modulation.

All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.

www.onsemi.com

47

NCL31010

PACKAGE DIMENSIONS

QFN48 7x7, 0.5P

CASE 485EP

ISSUE O

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

D

A

B

E

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO THE PLATED

TERMINAL AND IS MEASURED ABETWEEN

0.15 AND 0.25 MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

L

PIN 1

LOCATION

L1

DETAIL A

MILLIMETERS

ALTERNATE TERMINAL

CONSTRUCTIONS

DIM MIN

0.80

A1 0.00

MAX

1.00

0.05

A

A3

b

D

0.20 REF

2X

0.20

0.30

EXPOSED Cu

MOLD CMPD

7.00 BSC

0.10

C

D2 4.00

4.20

E

7.00 BSC

E2 4.00

4.20

0.10

C

2X

TOP VIEW

e

L

0.50 BSC

DETAIL B

0.30

0.50

0.15

ALTERNATE

DETAIL B

CONSTRUCTION

L1 0.00

(A3)

0.10

0.08

C

A

A1

RECOMMENDED

SOLDERING FOOTPRINT*

NOTE 4

SEATING

PLANE

C

SIDE VIEW

D2

2X

48X

0.63

4.40

0.10 C A B

DETAIL A

1

13

12

25

E2

36

0.10 C A B

2X

7.30

PACKAGE

OUTLINE

48X

0.32

1

0.50 PITCH

48

37

DIMENSIONS: MILLIMETERS

48X

b

0.10 C A B

e

48X

L

*For additional information on our Pb−Free strategy and soldering

details, please download the onsemi Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

e/2

NOTE 3

C

0.05

BOTTOM VIEW

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Email Requests to: orderlit@onsemi.com

TECHNICAL SUPPORT

North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada

Phone: 011 421 33 790 2910

Europe, Middle East and Africa Technical Support:

Phone: 00421 33 790 2910

For additional information, please contact your local Sales Representative

onsemi Website: www.onsemi.com

◊

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48


型号：	NCL31010MNITWG
厂家：	ONSEMI
描述：	PoE Interface LED Driver, Visible Light Communication capable
文件：	总48页 (文件大小：911K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCL31010MNITWG [ONSEMI]

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