NCN3612BMTTWG [ONSEMI]
数据开关，6 差分沟道 1:2 开关，用于 PCIe 3.0 和 Display Port 1.2;
| 型号： | NCN3612BMTTWG |
| 厂家： | 
ONSEMI |
| 描述： | 数据开关，6 差分沟道 1:2 开关，用于 PCIe 3.0 和 Display Port 1.2 开关 PC |
| 文件： | 总12页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NCN3612B
6-Channel Differential 1:2
Switch for PCIe 3.0 and
DisplayPort 1.2
The NCN3612B is a 6−Channel differential SPDT switch designed
to route PCI Express Gen3 and/or DisplayPort 1.2 signals. Due to the
ultra−low ON−state capacitance (2.1 pF typ) and resistance (8 W typ),
this switch is ideal for switching high frequency signals up to a signal
bit rate (BR) of 8 Gbps. This switch pinout is designed to be used in
BTX form factor desktop PCs and is available in a space−saving
5x11x0.75 mm WQFN56 package. The NCN3612B uses 80% less
quiescent power than other comparable PCIe switches.
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MARKING
DIAGRAM
NCN3612B
AWLYYWWG
WQFN56
CASE 510AK
1
Features
• BTX Pinout
• V Power Supply from 3 V to 3.6 V
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
DD
WL
YY
WW
G
• Low Supply Current: 250 mA typ
• 6 Differential Channels, 2:1 MUX/DEMUX
• Compatible with Display Port 1.2 & PCIe 3.0
• Data Rate: Supports 8 Gbps
• Low R Resistance: 8 W typ
• Low C Capacitance: 2.1 pF
• Space Saving, Small WQFN−56 Package
• This is a Pb−Free Device
ON
ORDERING INFORMATION
ON
†
Device
NCN3612BMTTWG
Package
Shipping
2000 /
Tape & Reel
WQFN56
(Pb−Free)
Typical Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Notebook Computers
• Desktop Computers
• Server/Storage Networks
D0 +/−
Graphics and
D1 +/−
Memory
Controller Hub
(GMCH)
D2 +/−
D3 +/−
IN_0 +/−
IN_1 +/−
IN_2 +/−
IN_3 +/−
X +/−
PCIe BUFF1
HPD1/HPD2
AUX +/−
PCIe BUFF2
PCI
PCIe BUFF3
Express
NCN3612B
Tx0 +/−
Tx1 +/−
Tx2 +/−
Tx3 +/−
Rx0 +/−
Rx1 +/−
Graphics
PCIe BUFF4
PCIe IN
AUX
(PEG)
OUT +/−
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
September, 2011 − Rev. 0
NCN3612B/D
NCN3612B
IN_0+
IN_0−
IN_1+
D0+
D0−
D1+
D1−
D2+
D2−
D3+
IN_1−
IN_2+
IN_2−
IN_3+
IN_3−
D3−
Tx0+
Tx0−
Tx1+
Tx1−
Tx2+
Tx2−
Tx3+
Tx3−
OUT+
OUT−
X+
AUX+
AUX−
HPD1
HPD2
Rx0+
X−
Rx0−
Rx1+
Rx1−
SEL
LE
Logic Control
Figure 2. NCN3612B Block Diagram
TRUTH TABLE (SEL Control)
Function
TRUTH TABLE (Latch Control)
SEL
L
LE
L
Internal Mux Select
PCI Express Gen3 Path is Active (Tx, Rx)
Digital Video Port is Active (D, HPD, AUX)
Respond to Changes on SEL
Latched
H
H
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2
NCN3612B
GND
SEL
1
2
48 GND
D2+
47
LE
D2−
3
4
5
46
45
44
IN_0+
IN_0−
VDD
IN_1+
IN_1−
IN_2+
IN_2−
GND
IN_3+
IN_3−
OUT+
OUT−
GND
VDD
X+
D3+
D3−
Tx0+
Tx0−
Tx1+
Tx1−
Tx2+
Tx2−
Tx3+
Tx3−
GND
VDD
AUX+
AUX−
HPD1
6
7
8
9
43
42
41
40
Exposed Pad on
Underside
(solder to external
Gnd)
10
11
12
13
14
15
39
38
37
36
35
34
16
17
18
33
32
31
30
29
X−
19
20
HPD2
GND
GND
Figure 3. Pinout
(Top View)
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3
NCN3612B
PIN FUNCTION AND DESCRIPTION
Pin
Name
Description
6, 17, 22, 27,
34,50, 55
VDD
DC Supply, 3.3 V $10%
1, 11, 16, 20, 21,
28, 29, 35, 48,
49, 56
GND
Power Ground.
Exposed Pad
−
The exposed pad on the backside of package is internally connected to Gnd. Externally the exposed
pad should also be user−connected to GND.
2
SEL
SEL controls the mux through a flow−through latch. Do not float this pin.
SEL = 0 for PCIE Mode; SEL = 1 for DP Mode
3
4
LE
LE controls the latch gate. Do not float this pin.
IN_0+
IN_0−
IN_1+
IN_1−
IN_2+
IN_2−
IN_3+
IN_3−
OUT+
Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0−.
Differential input from GMCH PCIE outputs. IN_0− makes a differential pair with IN_0+.
Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1−.
Differential input from GMCH PCIE outputs. IN_1− makes a differential pair with IN_1+.
Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2−.
Differential input from GMCH PCIE outputs. IN_2− makes a differential pair with IN_2+.
Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3−.
Differential input from GMCH PCIE outputs. IN_3− makes a differential pair with IN_3+.
5
7
8
9
10
12
13
14
Pass−through output from AUX+ input when SEL = 1. Pass−through output from Rx0+ input when
SEL = 0.
15
OUT−
Pass−through output from AUX− input when SEL = 1. Pass−through output from Rx0− input when
SEL = 0.
18
19
X+
X+ is an analog pass−through output corresponding to Rx1+.
X−
X− is an analog pass−through output corresponding to the Rx1− input. The path
from Rx1− to X− must be matched with the path from Rx1+ to X+. X+ and X− form a
differential pair when the pass−through mux mode is selected.
23
24
25
26
Rx1−
Rx1+
Rx0−
Rx0+
Differential input from PCIE connector or device. Rx1− makes a differential pair with Rx1+. Rx1− is
passed through to the X− pin on the path that matches the Rx1+ to X+ pin.
Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1−. Rx1+ is
passed through to the X+ pin when SEL = 0.
Differential input from PCIE connector or device. Rx0− makes a differential pair with Rx0+. Rx0− is
passed through to the OUT− pin when SEL = 0.
Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0−. Rx0+ is
passed through to the OUT+ pin when SEL = 0.
30
31
32
HPD2
HPD1
AUX−
Negative low frequency HPD input handshake protocol signal (normally not connected).
Positive low frequency HPD input handshake protocol signal.
Differential input from HDMI/DP connector. AUX− makes a differential
pair with AUX+. AUX− is passed through to the OUT− pin when SEL = 1.
33
AUX+
Differential input from HDMI/DP connector. AUX+ makes a differential
pair with AUX−. AUX+ is passed through to the OUT+ pin when SEL = 1.
37, 36
39, 38
41, 40
43, 42
45, 44
47, 46
52, 51
54, 53
Tx3+, Tx3−
Tx2+, Tx2−
Tx1+, Tx1−
Tx0+, Tx0−
D3+, D3−
D2+, D2−
D1+, D1−
D0+, D0−
Analog pass−through output#2 corresponding to IN_3+ and IN_3− when SEL = 0.
Analog pass−through output#2 corresponding to IN_2+ and IN_2− when SEL = 0.
Analog pass−through output#2 corresponding to IN_1+ and IN_1− when SEL = 0.
Analog pass−through output#2 corresponding to IN_0+ and IN_0− when SEL = 0.
Analog pass−through output#1 corresponding to IN_3+ and IN_3−, when SEL = 1.
Analog pass−through output#1 corresponding to IN_2+ and IN_2−, when SEL = 1.
Analog pass−through output#1 corresponding to IN_1+ and IN_1−, when SEL = 1.
Analog pass−through output#1 corresponding to IN_0+ and IN_0−, when SEL = 1.
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4
NCN3612B
MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Power Supply Voltage
V
−0.5 to 5.3
V
DC
V
DC
DD
Input/Output Voltage Range of the Switch
(Tx, Rx, D, HPD, AUX, IN_, OUT, X)
V
−0.5 to V + 0.3
DD
IS
Selection Pin Voltages (SEL and LE)
Continuous Current Through One Switch Channel
Maximum Junction Temperature (Note 1)
Operating Ambient Temperature
V
−0.5 to V + 0.3
V
IN
DD
DC
I
IS
120
150
mA
°C
°C
°C
°C/W
mA
V
T
J
T
−40 to +85
−65 to +150
37
A
Storage Temperature Range
T
stg
Thermal Resistance, Junction−to−Air (Note 2)
Latch−up Current (Note 3)
R
q
JA
I
LU
100
Human Body Model (HBM) ESD Rating (Note 4)
Machine Model (MM) ESD Rating (Note 4)
Moisture Sensitivity (Note 5)
ESD HBM
ESD MM
MSL
7000
400
V
Level 1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Power dissipation must be considered to ensure maximum junction temperature (T ) is not exceeded.
J
2. This parameter is based on EIA/JEDEC 51−7 with a 4−layer PCB, 80 mm x 80 mm, two 1oz Cu material internal planes and top planes of
2oz Cu material.
3. Latch up Current Maximum Rating: 100 mA per JEDEC standard: JESD78.
4. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 7.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) 400 V per JEDEC standard: JESD22−A115 for all pins.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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5
NCN3612B
ELECTRICAL CHARACTERISTICS (V = +3.3V 10%, T = −40°C to +85°C, unless otherwise noted. All Typical values are at
DD
A
V
DD
= +3.3 V, T = +25°C, unless otherwise noted.)
A
Symbol
Characteristics
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
V
Supply Voltage Range
Power Supply Current
3.0
3.3
3.6
V
DD
I
V
DD
= 3.6 V, V = GND or V
DD
250
350
mA
DD
IN
DATA SWITCH PERFORMANCE (for both PCIe and DisplayPort applications, unless otherwise noted)
V
IS
Data Input/Output Voltage
Range
0
1.2
V
R
R
On Resistance (Tx, Rx)
V
DD
V
DD
V
DD
= 3 V, V = 0 V to 1.2 V, I = 15 mA
8.0
9.0
0.1
13
13
W
W
W
ON
ON
IS
IS
On Resistance (D, HPD, AUX)
On Resistance Flatness
= 3 V, V = 0 V to 1.2 V, I = 15 mA
IS IS
R
= 3 V, V = 0 V to 1.2 V, I = 15 mA
1.24
ON(flat)
IS
IS
(Note 6)
DR
DR
On Resistance Matching
(Tx, Rx)
V
V
= 3 V, V = 0 V, I = 15 mA
0.35
0.35
W
W
ON
ON
DD
IS
IS
On Resistance Matching
(D, HPD, AUX)
= 3 V, V = 0 V, I = 15 mA
IS IS
DD
C
On Capacitance
Off Capacitance
f = 1 MHz, Switch On, Open Output
f = 1 MHz, Switch Off
2.1
1.6
pF
pF
mA
ON
C
OFF
I
ON
On Leakage Current
(IN_/ X/OUT)
V
= 3.6 V, V
= Vx = V = 0 V, 1.2 V;
OUT
−1
−1
+1
+1
DD
IN_
Switch On to D/HPD/AUX or Tx/Rx; outputs
unconnected
I
Off Leakage Current
(D/Tx/HPD/Rx/AUX)
V
DD
= 3.6 V, V
= V = V = 0 V, 1.2 V;
OUT_
mA
OFF
IN_
X_
Switch Off; V = V
= V
or V = V
=
D
HPD
AUX
D
HPD
V
AUX
set to 1.2 V, 0 V
CONTROL LOGIC CHARACTERISTICS (SEL and LE pins)
V
Off voltage input
High voltage input
Off voltage input
High voltage input
0
2
0.8
V
V
IL
IH
IN
V
V
DD
I
V
IN
= 0 V or V
f = 1 MHz
−1
+1
mA
pF
DD
C
1
IN
DYNAMIC CHARACTERISTICS
BR
Signal Data Rate
8
Gbps
dB
D
Differential Insertion Loss
f = 100 MHz
f = 2.7 GHz
f = 4 GHz
−0.7
−1.3
−2
IL
D
Differential Off Isolation
Differential Crosstalk
Differential Return Loss
f = 100 MHz
f = 2.7 GHz
f = 4 GHz
−54
−23
−18
−50
−32
−30
−20
−10
−5
dB
dB
dB
ISO
D
f = 100 MHz
f = 2.7 GHz
f = 4 GHz
CTK
D
f = 100 MHz
f = 3.7 GHz
f = 4 GHz
RL
6. Guaranteed by characterization and/or design.
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6
NCN3612B
SWITCHING CHARACTERISTICS (V = +3.3 V, T = 25°C, unless otherwise specified)
DD
A
Symbol
Characteristics
Bit−to−bit skew
Channel−to−channel skew
Conditions
Min
Typ
7
Max
Max
Unit
ps
t
Within the same differential pair
b−b
t
Maximum skew between all channels
55
ps
ch−ch
SELECTION PINS SWITCHING CHARACTERISTICS (V = +3.3 V, T = 25°C, unless otherwise specified)
DD
A
Symbol
Characteristics
Conditions
= 1 V, R = 50 W, V = V , C = 100 pF
Min
Typ
9.5
5
Unit
ns
T
SEL to Switch turn ON time
SEL to Switch turn OFF time
LE setup time SEL to LE
LE hold time LE to SEL
V
IS
SELON
L
LE
DD
L
T
V
= 1 V, R = 50 W, V = V , C = 100pF
ns
SELOFF
IS
IS
IS
L
LE
DD
L
T
SET
V
V
= 1 V, R = 50 W, V = V , C = 100 pF
1
ns
L
LE
DD
L
T
HOLD
= 1 V, R = 50 W, V = V , C = 100 pF
1
ns
L
LE
DD
L
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7
NCN3612B
TYPICAL OPERATING CHARACTERISTICS
Figure 5. DisplayPort 1.2 Eye Diagram through
NCN3612B at 5.4 Gbps, 340 mVpp Differential
Swing
Figure 4. Reference DisplayPort 1.2 Eye Diagram
without Switch at 5.4 Gbps, 340 mVpp Differential
Swing
Figure 6. Reference PCIe 3.0 Eye Diagram without
Switch at 8 Gbps, 800 mVpp Differential Swing
Figure 7. PCIe 3.0 Eye Diagram through NCN3612B
at 8 Gbps, 800 mVpp Differential Swing
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8
NCN3612B
TYPICAL OPERATING CHARACTERISTICS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
0
−2
−4
−6
−8
−10
−12
−14
100000000
1E+09
1E+10 10000000
100000000
1E+09
1E+10
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. Differential Insertion Loss
Figure 9. Differential Crosstalk
0
−10
−20
−30
−40
−50
−60
−70
−80
0
−5
−10
−15
−20
−25
10000000
100000000
1E+09
1E+10 100000000
1E+09
1E+10
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. Differential Off Isolation
Figure 11. Differential Return Loss
12
V
V
V
=3.0
CC
=3.3
CC
=3.6
CC
11
10
9
8
7
6
5
0
0.5
1
1.5
2
V
IS
(V)
Figure 12. RON vs. VIS
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9
NCN3612B
PARAMETER MEASUREMENT INFORMATION
Figure 14. Differential Off Isolation (SDD21
)
Figure 13. Differential Insertion Loss (SDD21) and
Differential Return Loss (SDD11
)
t
= |t
-t
| or |t
-t
|
skew
PLH1 PLH2
PHL1 PHL2
Figure 15. Differential Crosstalk (SDD21
)
Figure 16. Bit−to−Bit and Channel−to−Channel Skew
Figure 17. tON and tOFF
Figure 19. On State Leakage
Figure 18. Off State Leakage
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10
NCN3612B
PACKAGE DIMENSIONS
WQFN56 5x11, 0.5P
CASE 510AK−01
ISSUE A
D
A B
NOTES:
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN ONE
LOCATION
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
0.80
0.05
E
A
A1
A3
b
0.70
−−−
0.20 REF
0.20
EXPOSED Cu
MOLD CMPD
0.30
D
D2
E
5.00 BSC
2.30
2.50
11.00 BSC
DETAIL B
E2
e
K
L
L1
8.30
0.50 BSC
0.20 MIN
0.30
8.50
0.15
0.15
C
ALTERNATE
CONSTRUCTION
0.50
0.15
TOP VIEW
C
−−−
DETAIL B
(A3)
A
0.10
C
RECOMMENDED
SOLDERING FOOTPRINT*
0.08
C
A1
SEATING
5.30
NOTE 4
SIDE VIEW
D2
C
PLANE
56X
0.63
2.50
0.10
C
A
B
DETAIL A
56X L
1
0.10
C A B
8.50
11.30
E2
PKG
OUTLINE
1
56X
0.50
PITCH
0.35
56
e
K
DIMENSIONS: MILLIMETERS
56X b
e/2
BOTTOM VIEW
0.10
C
C
A B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
0.05
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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For additional information, please contact your local
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NCN3612B/D
相关型号：
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