NCN49597MNRG_技术文档

NCN49597

Power Line Communication

Modem

The NCN49597 is a powerful spread frequency shift keying

(S−FSK) communication system−on−chip (SoC) designed for

communication in hostile environments.

It combines a low power ARM Cortex M0 processor with a high

precision analogue front end. Based on 4800 baud S−FSK

dual−channel technology, it offers an ideal compromise between speed

and robustness.

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Pin−compatible with its predecessor, the AMIS−49587, this new

generation chip extends the communication frequency range to cover

all CENELEC bands for use in applications such as e−metering, home

automation and street lighting. The NCN49597 benefits for more than

10 years of field experience in e−metering and delivers innovative

features such as a smart synchronization and in−band statistics.

Fully reprogrammable, the modem firmware can be updated in the

field. Multiple royalty−free firmware options are available from

ON Semiconductor; refer to the separate datasheets for details. The

configurable GPIOs allow connecting peripherals such as LCDs or

metering ICs.

1

52

QFN52 8x8, 0.5P

CASE 485M

MARKING DIAGRAM

52

1

XXXXYZZ

NCN 49597

C597−901

Features

• Power Line Communication (PLC) Modem for 50 Hz, 60 Hz and DC

Mains

• Embedded ARM Cortex M0 Processor

XXXX = Date Code

• 10 General Purpose IOs Controllable by Software

• Embedded 32 kB RAM

Y

= Plant Identifier

ZZ

= Traceability Code

• Embedded 2 kB ROM Containing Boot Loader

• Hardware Compliant with CENELEC EN 50065−1 and EN 50065−7

Half Duplex S−FSK Channel, Data Rate Selectable:

300 – 600 – 1200 – 2400 – 4800 baud (@ 50 Hz);

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 29 of this data sheet.

360 – 720 – 1440 – 2880 – 5760 baud (@ 60 Hz)

• Programmable Carrier Frequencies in CENELEC A, B, C and D

Band

• UART for Interfacing with an Application Microcontroller

• Power Supply 3.3 V

• Wide Junction Temperature Range: −40°C to +125°C

Available Firmware Options

Typical Applications

• ON−PL110 − Mesh Networking with Collision

Avoidance and Error Correction

• Complete Handling of Protocol Layers (physical,

MAC, LLC)

• AMR: Remote Automated Meter Reading

• Building Automation

• Solar Power Control and Monitoring

• Street Light Control and Monitoring

• Transmission of Alerts (fire, gas leak, water leak)

1

Publication Order Number:

January, 2017 − Rev. 4

NCN49597/D

NCN49597

APPLICATION

Application Example

3V3_A

3V3_D

C₈

R₆

C₆

R₇

R₈

C₁₇

C₁₆

3V3_D

12 V

U₁

C₉

C₇

R

12

12 V

VCC

7

TXD

U₂

−B

12

Vuc OutA

19

D₁

Application

&

Metering

Micro

C₃

RXD

BR 0

BR 1

RESB

6

5

MAINS

R₄

R₅

TX_OUT

4

R₁₀

8

9

−A

+A

OutB

NCS5651

C

4

3

D

2

10 11

VEE

1

13

+B Vcom

2

20 14

15

Rlim

^VwarnR₉

Controller

3V3_D

GNDuC

C₁₀

R₁₄

R₂

C₅

NCN49597

C₁₁

TX_ENB

RX_OUT

Tr

1:2

C₂C₁

R₃

D

RX_IN

REF_OUT

ZC_IN

3

VDD1V8

SEN

D

4

R₁

C₁₅

3V3_A

C_DREF

D₅

EXT_CLK_E

R₁₁

C₁₂

Y₁

C₁₃

C₁₄

Figure 1. Typical Application for the NCN49597 S−FSK Modem

Figure 1 shows an S−FSK PLC modem built around the

NCN49597. The design is a good starting point for a

CENELEC. EN 50065−1−compliant system; for further

information refer to the referenced design manual.

This design is not galvanically isolated; safety must be

considered when interfacing to a microcontroller or a PC.

For synchronization the mains is coupled in via a 1 MW

order low pass filter built around the NCS5651 power

nd

rd

operational amplifier suppresses the 2 and 3 harmonics

to be in line with the CENELEC EN50065−1 specification.

The filter components are tuned for a space and mark

frequency of 63.3 and 74 kHz respectively. The output of the

amplifier is coupled through DC blocking capacitor C to

10

a 2:1 transformer Tr. The high voltage capacitor C couples

11

resistor; the Schottky diode pair D clamps the voltage

the secondary of this transformer to the mains.

High−energetic transients from the mains are clamped by

5

within the input range of the zero crossing detector.

nd

In the receive path a 2 order high pass filter blocks the

the protection diode combination D , D , together with D ,

3 4 1

mains frequency. The corner point − defined by C , C , R

D .

2

1

2

1

th

and R − is designed at 10 kHz. In the transmit path a 3

2

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2

NCN49597

Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component

C , C

Function and Remarks

High pass receive filter

& V ceramic decoupling

Value

1.5

1

Tolerance

10%

Unit

nF

mF

nF

pF

mF

1

2

C , C

V

COM

−20 +80%

20%

5

DREF

REF_OUT

C , C , C , C

17

Supply decoupling

100

470

68

7

9

16

C

TX_OUT signal coupling

Low pass transmit filter

3

10%

4

6

8

Low pass transmit filter

10%

Low pass transmit filter

3

10%

C

Transmission signal coupling cap;

10

20%

10

1 A

ripple @ 70 kHz

RMS

C

High voltage coupling; 630 VDC

Zero crossing noise suppression

Crystal load capacitor

220

20%

−20 +80%

1%

nF

pF

mF

kW

W

11

100

12

C

, C

22

13

14

C

Internal 1.8 V supply decoupling; ceramic

High pass receive filter

Line driver current limitation setting

Low pass transmit filter

Line transients protection; 0.5 W

Zero crossing coupling

Pull up

1

15

R

22

1

2

3

9

4

5

6

7

8

R

11

1%

R

10

1%

10

1%

3.3

1%

10

1%

8.2

1%

500

1%

3

0.47

1%

kW

W

R

10%

10

11

R

1

MW

kW

R

, R

10

12

13

D , D

High−current Schottky clamp diodes

Unidirectional TVS

MBRA340

P6SMB6.8AT3G

BAS70−04

48 MHz

1

2

D , D

3

4

D

Dual low−current Schottky clamp diode

Crystal

5

Y1

Tr

50 ppm

2:1 signal transformer

U1

U2

PLC modem

NCN49597

NCS5651

Power operational amplifier

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3

NCN49597

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating

Symbol

Min

Max

Unit

POWER SUPPLY PINS VDD, VDDA, VSS, VSSA

Absolute max. digital power supply

Absolute max. analog power supply

V

− 0.3

3.9

0.1

V

DD_ABSM

SS

V

SSA

− 0.3

DDA_ABSM

Absolute max. difference between digital and analog power supply

Absolute max. difference between digital and analog ground

CLOCK PINS XIN, XOUT

V

− V

−0.1

DD

DDA_ABSM

SSA_ABSM

V

− V

SS

Absolute maximum input for the clock input pin (Note 1)

Absolute maximum voltage at the clock output pin (Note 1)

V

− 0.2

V

+ 0.2

V

XIN_ABSM18

SS

DD18

V

SS

− 0.2

+ 0.2

XOUT_ABSM18

DD18

NON 5 V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, TDO, SCK, SDO, SCB

Absolute maximum input for normal digital inputs and analog inputs

Absolute maximum voltage at any output pin

V

− 0.3

V

+ 0.3

V

N5VSIN_ABSM

SS

DD

V

DD

V

N5VSOUT_ABSM

SS

Maximum peak input current at the zerocrossing input pin

Maximum average input current at the zerocrossing input pin (1 ms)

Imp

−20

−2

20

mA

ZC_IN

Imavg

2

ZC_IN

5 V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0..IO9, RESB, TDI, TCK, TMS, TRSTB, TEST, SDI

Absolute maximum input for digital 5 V safe pins configured as input (Note 2)

Absolute maximum voltage at 5 V safe pin configured as output (Note 2)

V

− 0.3

5.5

V

5VSIN_ABSM

SS

V

− 0.3

V

+ 0.3

DD

5VSOUT_ABSM

SS

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The upper maximum voltage rating on the clock pins XIN and XOUT is specified with respect to the output voltage of the internal core voltage

regulator. The tolerance of this voltage regulator must be taken into account. In case an external clock is used, care must be taken not to

damage the XIN pin.

2. The direction (input or output) of configurable pins (IO0…IO9) depends on the firmware.

Normal Operating Conditions

Operating ranges define the limits for functional

operation and parametric characteristics of the device as

described in the Electrical Characteristics section and for the

reliability specifications.

Total cumulative dwell time outside the normal power

supply voltage range or the ambient temperature under bias,

must be less than 0.1 percent of the useful life.

Table 3. OPERATING RANGES

Rating

Symbol

Min

3.0

Max

3.6

Unit

V

Power supply voltage range (VDDA and VDD pins)

Junction Temperature Range

Ambient Temperature Range

V

DD

, V

DDA

T

J

−40

125

115

°C

T

A

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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4

NCN49597

PIN DESCRIPTION − QFN Package

1

2

39

38

37

36

35

34

33

32

31

30

29

28

27

NC

ZC_IN

NC

3

TX_EN

TEST

RES

IO3

4

IO4

5

IO5

6

IO0

NC

IO1

7

TDO

TDI

NCN49597

8

BR0

BR1

SEN

IO2

9

TCK

TMS

TRST

IO6

10

11

12

13

CSB

SDO

IO8

Figure 2. QFN Pin−out of NCN49597 (top view)

Table 4. NCN49597 QFN PIN FUNCTION DESCRIPTION

Pin Number

Pin Name

ZC_IN

I/O

In

Type

A

Description

50/60 Hz input for mains zero crossing detection

General purpose I/O’s (Note 3)

1

3..5, 12..14

IO3..IO7

IO0, IO1

IO8, IO9

TDO

In/Out

Out

In

D, 5VS, ST

D, 5VS, ST, PD

D

6, 33

13, 23

7

General purpose I/O’s (Notes 3 and 4)

General purpose IO (Notes 3 and 9)

JTAG test data output

8

TDI

D, 5VS, PD, ST

D, 5VS, PD

D, 5VS, PD, ST

D, 5VS, OD

A, 1.8 V

JTAG test data input (Note 7)

9

TCK

In

JTAG test clock (Note 7)

10

TMS

In

JTAG test mode select (Note 7)

JTAG test reset (active low) (Note 8)

External clock enable input

11

TRSTB

EXT_CLK_E

DATA/PRES

XIN

In

15

In

16

Out

In

Output of transmitted data (DATA) or PRE_SLOT signal (PRES)

Crystal oscillator input

17

18

XOUT

Out

A, 1.8 V

Crystal oscillator output (output must be left floating when XIN is

driven by an external clock)

19

VDD1V8

P

1.8 V regulator output. A decoupling capacitor of at least 1 mF is

required for stability

20

21

VSS

VDD

P

Digital ground

3.3 V digital supply

3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general−pur-

pose IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation

for details.

4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has

been loaded, the pin is available as a GPIO.

5. During normal operation, this pin must be tied to ground (recommended) or left open.

6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.

7. During normal operation, it is recommended that this pin is tied to ground.

8. During normal operation, this pin must be tied to Vdd.

9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.

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NCN49597

Table 4. NCN49597 QFN PIN FUNCTION DESCRIPTION

Pin Number

Pin Name

TXD

I/O

Out

In

Type

Description

22

24

25

26

27

28

29

D, 5VS, OD

D, 5VS, ST

D, 5VS

UART transmit output

UART receive input

RXD

SCK

Out

In

SPI interface to external Flash: clock

SDI

D, 5VS, ST

D, 5VS

SPI interface to external Flash: serial data input (Note 6)

SPI interface to external Flash: serial data output

SPI interface to external Flash: chip select

SDO

CSB

Out

In/Out

D, 5VS

IO2

D, 5VS, ST

Must be kept low while firmware is loaded over the serial inter-

face; available as a normal GPIO afterwards (Note 3)

30

31

32

35

36

37

42

43

46

47

48

49

51

SEN

BR1

In

D, 5VS, PD, ST

Boot mode selection (refer to Boot Loader section)

UART baud rate selection

D, 5VS

BR0

In

D, 5VS

UART baud rate selection

RESB

In

D, 5VS, ST

Reset (active low)

TEST

In

D, 5VS, PD, ST

Production hardware test enable (Note 5)

Transmit enable (active low)

Transmitter output

TX_ENB

TX_OUT

ALC_IN

VDDA

Out

In

D, 5VS, OD

A

P

A

Automatic level control input

3.3 V analog supply

VSSA

Analog ground

RX_OUT

RX_IN

REF_OUT

Out

In

Output of receiver operational amplifier

Non−inverting input of receiver operational amplifier

Out

Internal voltage reference. A decoupling capacitor of at least

1 mF is required for stability

2, 34, 38..41,

44, 45,50, 52

NC

These pins are not connected and must be connected to ground

(recommended) or left open

3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general−pur-

pose IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation

for details.

4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has

been loaded, the pin is available as a GPIO.

5. During normal operation, this pin must be tied to ground (recommended) or left open.

6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.

7. During normal operation, it is recommended that this pin is tied to ground.

8. During normal operation, this pin must be tied to Vdd.

9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.

P:

Power pin

5VS:

5 V safe; pin that supports the presence of 5 V if used as

input or as open−drain output

A:

Analog pin

Out:

In:

Output signal

D:

Digital pin

Input signal

PD:

OD:

Internal Pull Down resistor (Note 9)

Open Drain Output

ST:

Schmitt trigger input.

The maximal voltage on this pin is 1.8 V

1.8V:

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NCN49597

Table 5. ELECTRICAL CHARACTERISTICS

All parameters are valid for T = −40°C to 125°C, V = 3.3 V, f = 48 MHz 50 ppm unless otherwise specified.

CLK

J

DD

Parameter

INTERNAL VOLTAGE REGULATOR: PIN VDD1V8 (power supply and voltage reference)

and V current consumption

Test Conditions

Symbol

Min

Typ

Max

Unit

V

DD

V

DD18

1.62

1.80

40

1.98

60

4

V

DDA

During reception (Note 10)

During transmission (Note 10)

RESB = 0

I

mA

RX

I

40

TX

I

RESET

OSCILLATOR: PIN XIN, XOUT (Note 11)

Duty cycle with quartz connected

Start−up time

35

65

15

18

60

15

%

ms

pF

W

T

startup

Load capacitance external crystal

Series resistance external crystal

Maximum Capacitive load on XOUT

Low input threshold voltage

C

L

R

1

6

S

XIN used as clock input

CL

pF

V

XOUT

VIL

0.3

XOUT

V

DD18

High input threshold voltage

Low output voltage

XIN used as clock input

VIH

0.7

DD18

V

XOUT

V

XIN used as clock input,

XOUT = 2 mA

VOL

0.3

XOUT

High input voltage

XIN used as clock input

VOH

V

−

V

DD18

0.3

Rise and fall time on XIN

XIN used as clock input

t

1.5

ns

rXIN_EXT

ZERO CROSSING DETECTOR AND 50/60 HZ PLL: PIN ZC_IN

Mains voltage input range

With protection resistor at ZC_IN

V

90

550

1.9

V

PK

MAINS

(Note 12)

Rising threshold level

Falling threshold level

Hysteresis

VIR

VIF

V

ZC_IN

0.85

0.4

45

ZC_IN

VHY

V

ZC_IN

Lock range (Note 13)

R_CONF[0] = 0 (50 Hz)

R_CONF[0] = 1 (60 Hz)

R_CONF[0] = 0 (50 Hz)

R_CONF[0] = 1 (60 Hz)

R_CONF[0] = 0 (50 Hz)

Flock

Tlock

55

66

15

20

0.1

Hz

s

50Hz

60Hz

50Hz

60Hz

54

Lock time (Note 13)

s

Frequency variation without going out of

lock (Note 13)

DF

Hz/s

60Hz

Frequency variation without going out of

lock (Note 13)

R_CONF[0] = 1 (60 Hz)

DF

0.1

25

Hz/s

50Hz

Jitter of CHIP_CLK (Note 13)

Jitter

ms

CHIP_CLK

10.With typical firmware. The exact value depends on the firmware variant loaded and the firmware configuration.

11. In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the static parame-

ters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.

12.This parameter is not tested in production.

13.These parameters will not be measured in production as the performance is determined by a digital circuit. Correct operation of this circuit

will be guaranteed by the digital test patterns.

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7

NCN49597

Table 5. ELECTRICAL CHARACTERISTICS

All parameters are valid for T = −40°C to 125°C, V = 3.3 V, f = 48 MHz 50 ppm unless otherwise specified.

CLK

J

DD

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

TRANSMITTER EXTERNAL PARAMETERS: PIN TX_OUT, ALC_IN, TX_ENB

AC output level

f

= 23 – 75 kHz (Note 14)

= 148.5 kHz (Note 14)

V

0.85

0.76

1.15

1.22

V

PK

TX_OUT

f

TX_OUT

DC output level

V

1.65

V

TX_OUT

Second order harmonic distortion

Third order harmonic distortion

Transmitted carrier frequency resolution

Transmitted carrier frequency accuracy

Capacitive output load at pin TX_OUT

Resistive output load at pin TX_OUT

Turn off delay of TX_ENB output

Automatic level control attenuation step

Maximum attenuation

f

= 148.5 kHz (Note 14)

HD2

−55

−57

11.44

30

dB

Hz

pF

kW

ms

dB

TX_OUT

HD3

TX_OUT

Rf

Df

11.44

TX_OUT

(Note 15)

CL

TX_OUT

20

RL

TX_OUT

5

Td

0.25

2.9

0.5

TX_ENB

ALC

3.1

step

ALC

20.3

0.34

0.54

111

21.7

0.46

0.72

189

range

Low threshold level on ALC_IN

High threshold level on ALC_IN

Input impedance of ALC_IN pin

With DC bias equal to V

VTL

VTH

V

REF_OUT

ALC_IN

PK

V

REF_OUT

R

kW

Power supply rejection ratio of the

transmitter section

f = 50 Hz (Note 16)

f = 10 kHz (Note 16)

PSRR

32

10

dB

TX_OUT

Transmit cascade gain (Note 17)

f = 10 kHz

f = 148.5 kHz

f = 195 kHz

f = 245 kHz

f = 500 kHz

f = 1 MHz

V

−0.5

−1.3

−4.5

0.5

−1.5

−3

dB

TX_PF_10kHz

V

TX_LPF_148kHz5

V

TX_LPF_195kHz

TX_LPF_245kHz

TX_LPF_500kHz

−18

V

−36

−50

TX_LPF_1000kHz

TX_LPF_2000kHz

f = 2 MHz

14.With the level control register set for maximal output amplitude. Tested with low pass filter tuned for CENELEC D−band.

15.This parameter will not be tested in production.

16.A sinusoidal signal of 100 mVpp is injected between VDDA and VSSA while the digital AD converter generates an idle pattern. The signal

level at TX_OUT is measured to determine the parameter.

17.The cascade of the digital−to−analog converter (DAC), low−pass filter (LPF), and transmission amplifier is production tested and must

have a frequency characteristic between the limits listed. The level is specified relative to the level at DC; the absolute output level will

depend on the operating condition.

This test is done with the low−pass filter (LPF) tuned to include the CENELEC D−band. In production the measurement will be done for

relative to DC with a signal amplitude of 100 mV.

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8

NCN49597

Table 5. ELECTRICAL CHARACTERISTICS

All parameters are valid for T = −40°C to 125°C, V = 3.3 V, f = 48 MHz 50 ppm unless otherwise specified.

CLK

J

DD

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

RECEIVER EXTERNAL PARAMETERS: PIN RX_IN, RX_OUT, REF_OUT

Input offset voltage

AGC gain = 42 dB

AGC gain = 0 dB

V

5

mV

OFFS_RX_IN

50

OFFS_RX_IN

Max. peak input voltage (corresponding

to 62.5% of the ADC full scale)

AGC gain = 0 dB (Note 18)

V

0.85

1.15

V

PK

MAX_RX_IN

Input referred noise of the analog

receiver path

AGC gain = 42 dB

(Notes 18 and 19)

NF

150

nV/√Hz

RX_IN

Input leakage current of receiver input

Max. current delivered by REF_OUT

I

−1

−300

35

1

mA

dB

V

LE_RX_IN

I

300

Max_REF_OUT

Power supply rejection ratio of the re-

ceiver input section

f = 50 Hz (Note 20)

f = 10 kHz (Note 20)

PSRR

LPF_OUT

10

AGC gain step

AGC

5.3

6.7

step

AGC range

AGC

39.9

1.52

54

44.1

1.78

range

Analog ground reference output voltage

Signal to noise ratio (Notes 18 and 20)

Load current 300 mA

V

1.65

REF_OUT

Signal amplitude of 62.5% of the

full scale of the ADC

SN

dB

AD_OUT

Clipping level at the output of the gain

stage (RX_OUT)

V

1.05

1.65

V

PK

CLIP_AGC_IN

Receive cascade gain (Note 22)

f = 10 kHz, A = 250 mVpk

f = 148.5 kHz, A = 250 mVpk

f = 195 kHz, A = 250 mVpk

f = 245 kHz, A = 250 mVpk

f = 500 kHz, A = 250 mVpk

f = 1 MHz

V

−0.5

−1.3

−4.5

0

0.5

−1

−3

−18

dB

RX_LPF_10kHz

V

RX_LPF_148.5kHz

V

RX_LPF_195kHz

RX_LPF_245kHz

RX_LPF_500kHz

V

−36

−50

RX_LPF_1000kHz

RX_LPF_2000kHz

f = 2 MHz

POWER−ON−RESET (POR)

POR threshold (Note 23)

V

and V

rising

falling

V

PORH

2.7

V

DD

DDA

V

DD

and V

V

2.1

1

DDA

PORL

RPOR

Power supply rise time

0 to 3 V on both V and V

T

ms

DD

DDA

DIGITAL OUTPUTS: TDO, SCK, SDO, CSB, IO0..IO9

Low output voltage (Note 24)

High output voltage (Note 24)

I

= 4 mA

V

0.4

V

XOUT

OL

I

= −4 mA

V

OH

0.85 V

DD

XOUT

DIGITAL OUTPUTS WITH OPEN DRAIN: TX_ENB, TXD, DATA/PRES

Low output voltage

I

= 4 mA

V

OL

V

XOUT

DIGITAL INPUTS: BR0, BR1

Low input level

V

0.2 V

2

V

IL

DD

High input level

0 to 3 V

V

IH

0.8 V

−2

DD

Input leakage current

I

mA

LEAK

18.Input at RX_IN, no other external components.

19.Characterization data only. Not tested in production.

20.A sinusoidal signal of 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and REF_OUT output

is measured to determine the parameter. The AGC gain is fixed at 42 dB.

21.These parameters will be tested in production with an input signal of 95 kHz and 1 V by reading out the digital samples at the output

PK

of the ADC. The AGC gain is switched to 0 dB.

22.The cascade of the receive low−pass filter (LPF), AGC and low noise amplifier is production tested and must have a frequency characteris-

tic between the limits listed. The level is specified relative to the level at DC; the absolute output level will depend on the operating condition.

This test is done with the low−pass filter (LPF) tuned to include the CENELEC D−band.

23.The nominal voltage on the pins VDD and VDDA (the digital and analog power supply) must be equal; both supply rail must be switched

together.

24.For IO0..IO9, this parameter only applies if the pin is configured as output pin by the firmware.

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9

NCN49597

Table 5. ELECTRICAL CHARACTERISTICS

All parameters are valid for T = −40°C to 125°C, V = 3.3 V, f = 48 MHz 50 ppm unless otherwise specified.

CLK

J

DD

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

DIGITAL INPUTS WITH PULL−DOWN: TDI, TMS, TCK, TRSTB, TEST, SEN, IO8, IO9

Low input level (Note 25)

High input level (Note 25)

Pull−down resistor (Note 25)

V

0.2 V

V

IL

DD

V

IH

0.8 V

35

DD

Measured at V = V / 2

R

100

170

0.80 V

2

kW

DD

PU

DIGITAL SCHMITT TRIGGER INPUTS: RXD, RESB, IO0..IO7, SDI

Rising threshold level (Note 26)

V

T+

DD

Falling threshold level (Note 26)

0.2 V

−2

T−

DD

Input leakage current (Note 26)

I

mA

LEAK

BOOT LOADER TIMING (Parameters are valid for a baud rate of 115’200) (Note 27)

IO2 setup time to falling edge of RESB

Boot loader startup time

(Note 28)

(Notes 28 and 29)

(Note 28)

t

5

ms

2s

t

stx

135

3.6

200

20

Inter−byte timeout sent to modem

t

IB

Boot loader acknowledgement after last

byte correctly received

(Note 28)

t

12

ACK

IO2 hold time after start of acknowl-

edgement byte transmission

(Note 28)

t

2h

36

ms

25.For IO8 and IO9, this parameter only applies if the pin is configured as input pin by the firmware.

26.For IO0…IO7, this parameter only applies if the pin is configured as input pin by the firmware.

27.The timing constraints governing the boot loader when uploading firmware over the serial interface are illustrated in Figure 3.

28.These parameters will not be measured in production as the performance is determined by a digital circuit.

29.This parameter is specified with the oscillator stable. Refer to T

for oscillator startup information.

startup

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

t

2s

t

2h

IO2

RESB

TXD

RXD

STX

ACK

AA

H

t

IB

t

stx

t

ds

ACK

Figure 3. Timing Constraints for Uploading the Firmware over the Serial Communication Interface (SCI)

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10

NCN49597

Typical Performance Characteristics

1.68

1.66

1.64

1.62

1.60

0

0.2

0.4

0.6

Time [ms]

0.8

1.0

1.2

Figure 4. Receiver Opamp — Small signal transient response for (top to center) no load, 10 kW load, 3.6 kW load

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0

0.2

0.4

0.6

0.8

1.0

1.2

Time [ms]

Figure 5. Receiver Opamp — Large signal transient response for (top to center) no load, 10 kW load, 3.6 kW load

3.5

No load

3.0

0 kW

0.6 kW

2.5

2.0

1.5

1.0

0.5

0

5

10

Time [ms]

15

20

Figure 6. Receiver Opamp — Output overdrive recovery behavior. The input signal is shown in grey

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11

NCN49597

RX_IN

RX_OUT

49.9 W

R

L

1 mF

Figure 7. Test Circuit for Figures 4–6

25

20

15

10

Output high

Output low

5

0

0.5

1.0

1.5

2.0

2.5

3.0

Voltage at pin [V]

Figure 8. GPIO Current Sourcing and Sinking Capability

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12

NCN49597

General Description

The NCN49597 is a single chip half duplex S−FSK

Because the lower layers are handled on−chip, the

NCN49597 provides an innovative architectural split. The

user benefits from a higher level abstraction. Compared to

a low−level interface, the NCN49597 allows faster

development of applications: the user just needs to send the

raw data to the NCN49597 and no longer has to take care of

the details of the transmission over the specific medium. The

latter part easily represents half of the software development

cost.

modem designed for hostile communication environments

with very low signal−to−noise ratio (SNR) and high

interference. It is particularly suited for power line carrier

(PLC) data transmission on low−or medium−voltage power

lines.

Together with firmware, the device handles of the lower

layers of communication protocols. Firmware solutions are

provided by ON Semiconductor royalty−free for the

ON−PL110 protocol. It handles the physical, Media Access

Control (MAC) and Logical Link Control (LLC) layers

on−chip. For more information, refer to the dedicated

software datasheet.

Figure 9 shows the building blocks of the NCN49597.

Refer to the sections below for a detailed description.

VDD1V8

Transmitter (S−FSK Modulator)

TX_ENB

Communication Controller

TxD

LP

Filter

Transmit Data

& Sine Synthesizer

Serial

Comm.

Interface

TO Power Amplifier

RxD

BR0

BR1

TO Application

Micro Controller

D/A

TX_OUT

ALC_IN

IO[9:0]

Receiver (S−FSK Demodulator)

Local Port

RX_OUT

RX_IN

DATA /PRES

ARM

Risc

Core

FROM Line Coupler

S−FSK

Demodulator

LP

AAF

AGC

A/D

5

Filter

JTAG I /F

TEST

Test

Control

REF

REF_OUT

ZC_IN

RESB

POR

Watchdog

Timer 1 & 2

Clock and Control

4

Zero

crossing

Clock Generator

& Timer

SPI I/F

SEN

PLL

OSC

Flash SPI

TO External Flash

Program/Data Program

Interrupt

Control

RAM

ROM

NCN49597

VDDA

VSSA

VDDD VSSD

XIN XOUT

EXT_CLK_E

Figure 9. Block Diagram of the NCN49597 S−FSK Modem

NCN49597 complies with the CENELEC EN 50065−1

and EN 50065−7 standards. It operates from a single 3.3 V

power supply and is interfaced to the power line by an

external line driver and transformer. An internal PLL is

locked to the mains frequency and is used to synchronize the

data transmission at data rates of 300, 600, 1200, 2400 and

4800 baud for a 50 Hz mains frequency, or 360, 720, 1440,

2880 and 5760 baud for a 60 Hz mains frequency. In both

cases this corresponds to 3, 6, 12 or 24 data bits per half cycle

of the mains period.

S−FSK is a modulation and demodulation technique that

combines some of the advantages of a classical spread

spectrum system (e.g. immunity against narrow band

interferers) with the advantages of the classical FSK system

(low complexity). The transmitter assigns the space

frequency f^Sto “data 0” and the mark frequency fM to

“data 1”. In contrast to classical FSK, the modulation

carriers f^Sand fM used in S−FSK are placed well apart. As

interference and signal attenuation seen at the carrier

frequencies are now less correlated, this results in making

their transmission quality independent from each other.

Thus, more robust communication is possible in

interference−prone environments. The frequency pairs

supported by the NCN49597 are in the range of 9–150 kHz

with a typical separation of 10 kHz.

The conditioning and conversion of the signal is

performed at the analog front−end of the circuit. All further

processing of the signal and the handling of the protocol is

fully digital. The digital processing of the signal is

partitioned between hardwired blocks and a microprocessor

block. Where timing is most critical, the functions are

implemented with dedicated hardware. For the functions

where the timing is less critical − typically the higher level

functions − the circuit makes use of an integrated ARM

microprocessor core. An internal random−access memory

(RAM) stored the firmware and the working data.

After the modem has been reset, the user must upload the

firmware into the modem memory. This may be done over

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13

NCN49597

the asynchronous serial interface (discussed below);

this must be taken into account. IO4–IO10 are usually

configured as inputs and can therefore be grounded safely.

However, it must be considered that some NC pins of

AMIS−49587 are outputs in the NCN49597. These include

pins SDO, SCK and, CSB. IO0 and IO1 are used typically

used by the firmware as status indicators. IO3 is used by the

ON PL110 firmware for controlling the amplifier enable

signal.

Secondly, the NCN49597 incorporates an internal 1.8 V

regulator to power the digital core. For stability, a 1 mF

capacitor to ground must be connected on pin 19

(VDD1V8).

In addition, the lowest baud rate setting of the

AMIS−49587 serial interface (BR0 & BR1 pulled low; 4800

baud) has been replaced by 115200 baud. All other BR0 and

BR1 settings will result in the same baud rate.

Finally, a 48 MHz crystal is required for the NCN49597;

the AMIS−49587 used a 24 MHz crystal.

alternatively, the modem can autonomously retrieve the

firmware from an attached SPI memory. For details, refer to

the Boot Loader section.

The modem communicates to the application

microcontroller over a Serial Communication Interface

(SCI), a standard asynchronous serial link, which allows

interfacing with any microcontroller with a free UART. The

SCI works on two wires: TXD and RXD. The baud rate is

programmed by setting two pins (BR0, BR1).

The NCN49597, together with an NCS5651 line driver, is

functionally equivalent to the NCN49599 modem. Thus, the

same user software works equally well with the NCN49597

as with the NCN49599.

Converting AMIS−49587−based Designs to NCN49597

The NCN49597 is designed to allow easy adaptation of

printed circuit board designs using the AMIS−49587. All

connected pins of the latter (QFN package) are present in the

same location in the NCN49597.

The firmware running on the modem has been updated

substantially compared to the AMIS−49587. As a result, the

interface protocol between the user microcontroller and the

modem is completely different. Refer to the firmware

datasheet for details.

Four important hardware changes must be noted.

Most of the not−connected (NC) pins of the AMIS−49587

are functional in the NCN49597. If these pins were

previously connected to ground (a commendable practice)

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14

NCN49597

Detailed Hardware Description

Clock and Control

The clock and control block (Figure 10) provides the

modem with the clock and synchronization signals required

for correct data transmission and reception. It is composed

of the zero−crossing detector, phase locked loop (PLL),

oscillator and clock generator.

Clock and Control

CHIP_CLK

Zero

crossing

Clock Generator

OSC

PLL

ZC_IN

& Timer

EXT_CLK_E

XIN

XOUT

Figure 10. Clock and Control Block

Oscillator

specified by the crystal manufacturer for correct operation

at the desired frequency. C is determined by the external

The NCN49597 may be clocked from a crystal with the

built−in oscillator or from an external clock. XIN is the input

to the oscillator inverter gain stage; XOUT the output.

XOUT cannot be used directly as a clock output as no

additional loading is allowed on the pin due to the limited

voltage swing. This applies both to operation with a crystal

and an external oscillator.

If an external clock of 48 MHz is to be used, the pin

EXT_CLK_E must be pulled to V and the clock signal

connected to XIN. Note that the high level on XIN must not

exceed the voltage of the internal voltage regulator (V

or about 1.8 V). The output must be floating.

L

capacitors C and stray capacitance (C

):

X

STRAY

C = C / 2 + C

L

X

STRAY

Stray capacitance typically ranges from 2 to 5 pF. This

results in a typical C value of 33 pF.

X

The printed circuit board should be designed to minimize

stray capacitance and capacitive coupling to other parts by

keeping traces as short as possible. The quality of the ground

plane below the oscillator components is critical.

To guarantee startup, the series loss resistance of the

crystal must be smaller than 60 W.

DD

,

DD18

The oscillator output f

(48 MHz) is the base clock for

CLK

If a crystal is to be used, the pin EXT_CLK_E should be

strapped to V and the circuit illustrated in Figure 11

the entire modem. The microcontroller clock, f

, is taken

ARM

directly from f

. The clock for the transmitter, f

SSA

CLK

TX_CLK,

should be employed.

is equal to f

/ 4 or 12 MHz; the master receiver clock,

CLK

f

, equals f

/ 8 or 6 MHz. All the internal clock

RX_CLK

CLK

signals of the transmitter and the receiver will be derived

from f resp. f

.

RX_CLK.

TX_CLK

XIN

XOUT

EXT_CLK_E

Zero Crossing Detector

Depending on the standard and the application,

synchronization with the mains zero crossing may be

required.

In order to recover this timing information, a zero cross

detection of the mains is performed.

48 MHz

C_X

V_SSA

Recommended circuits for the detection of the mains zero

crossing appear in the Application Note “Mains

synchronization for PLC modems”. In case of the modem is

not isolated from the mains a series resistor of 1 MW in

combination with two external Schottky clamp diodes is

recommended (Figure 12). This will limit the current

flowing through the internal protection diodes.

Figure 11. Clocking the NCN49597 with a Crystal

Correct operation is only possible with a parallel

resonance crystal of 48 MHz. A crystal with a load

capacitance C of 18 pF is recommended.

L

The load capacitance is the circuit capacitance appearing

between the crystal terminals; it must be within the range

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15

NCN49597

Clock & Control

3V3_A

BAS70−04

FROM

MAINS

ZC_IN

1 MW

ZeroCross

CHIP_CLK

Debounce

Filter

PLL

100 pF

Figure 12. Zero Crossing Detector with Falling−edge De−bounce Filter

ZC_IN is the mains frequency sense pin. A comparator

with Schmitt trigger ensures a signal with edges, even in the

presence of noise. In addition, the falling edges of the

detector output are de−bounced with a delay of 0.5–1 ms.

Rising edges are not de−bounced.

Because the detector threshold is not 0 V but slightly

positive, the rising edge of the output is delayed compared

to the actual rising mains zero crossing (Figure 13).

Figure 13. Zero Crossing Detector Signals and Timing (example for 50 Hz)

Phase Locked Loop (PLL)

using the register R_CONF. The bit R_CONF[0] specifies

the mains frequency, with a cleared bit (0) corresponding to

50 Hz; a set bit (1) to 60 Hz. The bits R_CONF[2:1] control

the number of data bits per mains period. The values 00b,

01b, 10b and 11b correspond to 6, 12, 24 and 48 bits per

mains period of 20 ms (50 Hz) or 16.7 ms (60 Hz).

Together this results in the baud rates and chip clock

frequencies shown in Table 6.

A phase−locked loop (PLL) structure converts the signal

at the ZC_IN comparator output to the chip clock

(CHIP_CLK). This clock is used for modulation and

demodulation and runs 8 times faster than the bit rate; as a

result, the chip clock frequency depends on the mains

frequency and the baud rate.

The filters of the PLL are dependent on the baud rate and

the mains frequency. They must be correctly configured

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16

NCN49597

Table 6. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY

R_CONF[0]

Mains frequency

R_CONF[2:1]

Baudrate

300 bps

600 bps

1200 bps

2400 bps

360 bps

720 bps

1440 bps

2880 bps

CHIP_CLK

2400 Hz

4800 Hz

9600 Hz

19200 Hz

2880 Hz

5760 Hz

11520 Hz

23040 Hz

00b

01b

10b

11b

00b

01b

10b

11b

0

50 Hz

1

60 Hz

The PLL significantly reduces the clock jitter. This makes

the modem less sensitive to timing variations; as a result, a

cheaper zero crossing detector circuit may be used.

The PLL input is only sensitive to rising edges.

If no zero crossings are detected, the PLL freezes its

internal timers in order to maintain the CHIP_CLK timing.

Figure 14. Using the ZC_ADJUST Register to Compensate for Zero Crossing Delay (example for 50 Hz)

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17

NCN49597

Clock Generator and Timer

The PLL ensures the generated chip clock is in phase with

the rising edge of comparator output. However, these edges

are not precisely in phase with the mains.

The timing generator (Figure 10, center) is responsible for

all synchronization signals and interrupts related to S−FSK

communication.

Inevitably, the external zero crossing detector circuit

The timing is derived from the chip clock (CHIP_CLK,

suffers from a delay t

(e.g. caused by an optocoupler).

DETD

generated by the PLL) and the main oscillator clock f

.

In addition, the comparator threshold is not zero (VIR

CLK

ZC_IN

The timing has a fixed repetition rate, corresponding to the

length of a physical subframe (see reference [1]).

When the NCN49597 switches between receive and

transmit mode, the chip clock counter value is maintained.

As a result, the same timing is maintained for reception and

transmission. Seven timing signals are defined:

= 1.9 V); this results in a further delay, t

between the

COMP0

rising edge of the signal on pin ZC_IN and the rising edge

on the comparator output (as noted before, the PLL takes

only the rising edge into account).

The combination of these delays would cause the modem

to emit and receive data frames too late.

Therefore, the PLL allows tuning the phase difference

between its input and the chip clock. The CHIP_CLK may

be brought forward by setting the register R_ZC_ADJUST.

The adjustment period or granularity is 13 ms, with a

maximum adjustment of 255 x 13 ms = 3.3 ms,

corresponding with a sixth of the 50 Hz mains sine period.

This is illustrated in Figure 9. The “physical frame” (i.e.,

the modulated signal appearing on the mains) starts earlier

with R_ZC_ADJUST[7:0] x 13 ms to compensate for the

zero cross delay.

• CHIP_CLK is the output of the PLL and the input of

the timing generator. It runs 8 times faster than the bit

rate on the physical interface.

• BIT_CLK is only active at chip clock counter values

that are multiples of 8 (0, 8, .., 2872). It indicates the

start of the transmission of a new bit.

• BYTE_CLK is only active at chip clock counter values

that are multiples of 64 (0, 64, .., 2816). It indicates the

start of the transmission of a new byte.

• FRAME_CLK is only active at counter value 0; it

The delay corresponding with the value of

R_ZC_ADJUST is also listed in Table 7.

indicates the transmission or reception of a new frame.

• PRE_BYTE_CLK follows the same pattern as

BYTE_CLK, but precedes it by 8 chip clocks. It can be

used as an interrupt for the internal microcontroller and

indicates that a new byte for transmission must be

generated.

• PRE_FRAME_CLK follows the same pattern at

FRAME_CLK, but precedes it by 8 chip clocks. It can

be used as an interrupt for the internal microcontroller

and indicates that a new frame will start at the next

FRAME_CLK.

Table 7. ZERO CROSSING DELAY COMPENSATION

R_ZC_ADJUST[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

...

Compensation

0 ms (reset value)

13 ms

26 ms

39 ms

...

1111 1111

3315 ms

• PRE_SLOT is active between the rising edge of

PRE_FRAME_CLK and the rising edge of

FRAME_CLK. This signal can be provided at the

digital output pin DATA/PRES when R_CONF[7] = 0.

Thus, the external host controller may synchronize its

software with the internal FRAME_CLK of the

NCN49597. Refer to the SCI section and Table 11 for

details.

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18

NCN49597

Start of the physical subframe

2871 2872 2879

0

1

2

3

4

5

6

7

8

9

63 64 65

R_CHIP_CNT

CHIP_CLK

BIT_CLK

BYTE_CLK

FRAME_CLK

PRE_BYTE_CLK

RE_FRAME_CLK

PRE_SLOT

Figure 15. Timing Signals

Transmitter Path Description (S−FSK Modulator)

The NCN49597 transmitter block (Figure 16) generates

the signal to be sent on the transmission channel. Most

commonly, the output is connected to a power amplifier

which injects the output signal on the mains through a

line−coupler.

The transmitter block is controlled by the microcontroller

core, which provided the bit sequence to be transmitted.

Direct digital synthesis (DDS) is employed to synthesize the

modulated signal; after a conditioning step, this signal is

converted to an analogue voltage. Finally, an amplifier with

variable gain buffers the signal and outputs it on pin

TX_OUT.

As the NCN49597 is a half−duplex modem, this block is

not active when the modem is receiving.

Transmitter(S−FSK Modulato)r

TX_EN

ALC

control

ARM

Interface

&

ALC_IN

Control

LP

Filter

Transmit Data

& Sine Synthesizer

TX_OUT

D/A

f_MIf_MQ

f_SI

f_SQ

TO RECEIVER

Figure 16. Transmitter Block Diagram

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19

NCN49597

Microcontroller Interface & Control

The interface with the internal ARM microcontroller

consists of an 8−bit data register R_TX_DATA, 2 control

register is usually made available by the firmware to the

application microcontroller. The attenuations corresponding

to R_ALC_CTRL[2:0] values are given in Table 8.

registers R_TX_CTRL and R_ALC_CTRL,

a flag

Table 8. FIXED TRANSMITTER OUTPUT ATTENUATION

TX_RXB defining the operating mode (a high level

corresponding to transmit mode; low to receive) and the

frequency control registers. All these registers are memory

mapped; most can be accessed through the firmware: refer

to the specific firmware documentation for details.

ALC_CTRL[2:0]

Attenuation

0 dB

000

001

010

011

100

101

110

111

−3 dB

−6 dB

Sine Wave Generator

−9 dB

The direct digital synthesizer (DDS) generates a

sinusoidal signal alternating between the space frequency

(f , data 0) and the mark frequency (f , data 1) as required

−12 dB

−15 dB

−18 dB

−21 dB

S

M

to modulate the desired bit pattern. Two 16−bit wide

frequency step registers, R_FM and R_FS, control the steps

used by the DDS and thus the frequencies.

The space and mark frequency can be calculated using

Alternatively, automatic level control (ALC) may be used

by clearing the bit R_ALC_CTRL[3].

In this mode, the signal on the analogue input pin ALC_IN

controls the transmitter output level. First, peak detection is

performed. The peak value is then compared to two

18

f = R_FS[15:0]_dec • f

M

Equivalently, values for R_FS[15:0] and R_FM[15:0]

/2

DDS

S

DDS

18

f

= R_FM[15:0]_dec • f

may be calculated from the desired carrier frequencies

18

R_FS[15:0]_dec = [2 • f /f

]

S

DDS

thresholds levels VTL

and VTH

. Depending

ALC_IN

18

R_FM[15:0]_dec = [2 • f /f

]

M

DDS

on the value of the measured peak level on ALC_IN the

attenuation is updated using

With f

= 3 MHz the direct digital synthesizer clock

DDS

frequency and [x] equal to x rounded to the nearest integer.

At the start of the transmission the DDS phase

accumulator starts at 0, resulting in a 0 V output level.

Vp

< VTL increase the level with one 3 dB step

ALC :

ALC_IN

VTL

≤ Vp

≤ VTH do not change the

ALC :

ALC

ALC_IN

attenuation

Switching between f and f is phase−continuous. Upon

M

S

switching to receive mode the DDS completes the active

sine period. These precautions minimize spurious emissions.

Vp > VTH

decrease the level with one 3 dB step

ALC :

ALC_IN

The gain changes in the next chip clock. Therefore, an

evaluation phase and a level adjustment phase take two

CHIP_CLK periods. ALC operation is enabled only during

the first 16 CHIP_CLK cycles after switching to transmit

mode.

Following reset, the level is set at minimum level

(maximum attenuation). When switching to reception mode

the last level is kept in memory. As a result the next transmit

frame starts with the old level.

Note that the DC level on the ALC_IN pin is fixed

internally to 1.65 V. As a result, a coupling capacitor is

usually required.

If the automatic level control feature is not used, the pin

ALC_IN may be left floating (not recommended) or tied to

ground.

DA Converter and Anti−aliasing Filter

A digital to analogue ΣΔ converter converts the sine wave

digital word to a pulse density modulated (PDM) signal. The

PDM stream is converted to an analogue signal with a first

order switched capacitor filter.

rd

A 3 order continuous time low pass filter in the transmit

path filters the quantization noise and noise generated by the

ΣΔ DA converter.

The −3 dB frequency of this filter can be set to 130 kHz for

applications using the CENELEC A band. In this

configuration, the response of the filter is virtually flat up to

95 kHz. Alternatively a −3 dB frequency of 195 kHz can be

selected yielding a flat response for the entire CENELEC A

to D band (i.e., up to 148.5 kHz). Refer to the documentation

of the firmware for more information.

Transmitter Output TX_OUT

The low pass filter is tuned automatically to compensate

for process variation.

The transmitter output is DC coupled to the TX_OUT pin.

Because the entire analogue part of the NCN49597 is

referenced to the analogue reference voltage REF_OUT

Amplifier with Automatic Level Control (ALC)

(about 1.65 V), a decoupling capacitor (C in Figure 17) is

1

The analogue output of the low−pass filter is buffered by

a variable gain amplifier; 8 attenuation steps from 0 to

−21 dB (typical) with steps of 3 dB are provided.

The attenuation can be fixed by setting the bit

R_ALC_CTRL[3]. The embedded microcontroller can then

set the attenuation using register ALC_CTRL[2:0]. This

usually required.

To suppress the second and third order harmonic of the

generated S−FSK signal it is recommended to use a low pass

nd

filter. Figure 17 illustrates an MFB topology of a 2 order

filter.

www.onsemi.com

20

NCN49597

Transmitter (S−FSK Modulator )

ALC_IN

C₄

ALC

control

FROM LINE

DRIVER

R₃

ARM

Interface

&

C₃

C₁

R₂

R₁

C₂

TX_OUT

TX_EN

LP

Filter

Control

TO TX POWER

OUTPUT STAGE

V_SSA

R₄

Figure 17. TX_OUT Filter

The modem indicates whether it is transmitting or

receiving on the digital output pin TX_ENB. This is driven

low when the transmitter is activated. The signal can be used

to turn on an external line driver.

TX_ENB is a 5 V safe with open drain output; an external

pull−up resistor must be added (Figure 17, R ).

4

When the modem switches from transmit to receive mode,

TX_ENB is kept active (i.e., low) for a short period

t

(Figure 13).

dTX_ENB

BIT_CLK

TX_DATA

TX_RXB

TX_ENB

TX_OUT

t_{dTX_ENB}

Figure 18. TX_ENB Timing

Receiver Path Description

The receiver demodulates the signal on the

communication channel.

Typically, an external line coupling circuit is required to

filter out the frequencies of interest on the communication

channel.

The modem receiver block (Figures 19 and 22) filter,

digitalizes and partially demodulates the output signal of the

coupling circuit. Subsequently, the embedded microcontroller

core will demodulate the resulting digital stream. The

demodulation is described in the fact sheets of the various

firmware solutions.

www.onsemi.com

21

NCN49597

RX_OUT

RX_IN

Receiver(Analog Path)

FROM

LOW NOISE

OPAMP

DIGITAL

4th

order

SDAD

TO

DIGITAL

Gain

LPF

REF_OUT

REF

1,65 V

Figure 19. Analog Path of the Receiver Block

FROM TRANSMITTER

Receiver (Digital Path)

Quadrature Demodulator

f_MQf_SIf_SQ

2^nd

f_MI

f_MQ

f_SI

I_M

Q_M

I_S

FROM

ANALOG

Sliding

Filter

Decimator

f_M

Noise

Shaper

1^st

Decimator

Compen−

sator

2^nd

Decimator

Sliding

Filter

2^nd

Decimator

Sliding

Filter

TO

GAIN

Abs

value

accu

f_S

AGC

Control

f_SQ

2^nd

Decimator

Q_S

Sliding

Filter

Figure 20. Digital Path of the Receiver Block

The receiver block is composed of an operation amplifier

provided for filtering, a variable gain amplifier, an

anti−aliasing low pass filter and analogue to digital

convertor (ADC), and a digital quadrature downmixer.

When the modem is transmitting, the receive blocks are

disabled to save power. The only exception is the low−pass

filter, which is shared between receiver and transmitter and

therefore remains active.

For the common case of communication over an AC power

line, a substantial 50 or 60 Hz residue is still present after the

line coupler. This residue − typically much larger than the

received signal − can easily overload the modem.

To improve communication performance, the NCN49597

provides a low−noise operational amplifier in a unity−gain

configuration which can be used to make a 50/60 Hz

suppression filter with only four external passive

components. Pin RX_IN is the non−inverting input and

RX_OUT is the output of the amplifier.

The internal reference voltage (described below) of

1.65 V is provided on REF_OUT and can be used for this

purpose. The current drawn from this pin should be limited

to 300 mA; in addition, adding a ceramic decoupling

capacitor of at least 1 mF is recommended.

50/60 Hz Suppression Filter

The line coupler − external to the modem and not

described in this document − couples the communication

channel to the low−voltage signal input of the modem.

Ideally the signal produced by the line coupler would only

contain the frequency band used by the S−FSK modulation.

R₂

RX_OUT

Receiver (S−FSK Demodulator)

LOW NOISE

OPAMP

C₂

C₁

V_IN

RX_IN

Received

Signal

TO AGC

R₁

REF_OUT

REF

1,65 V

C_DREF

V_SSA

Figure 21. External Component Connection for 50/60 Hz Suppression Filter

www.onsemi.com

22

NCN49597

The recommended topology is shown in Figure 20 and

74.5 kHz; the resulting frequency response is shown in

Figure 22. With a good layout, suppressing the residual

mains voltage (50 or 60 Hz) with 60 dB is feasible. To design

a filter for other frequencies, consult the design manual.

realizes a second order filter. The filter characteristics are

determined by external capacitors and resistors. Typical

values are given in Table 9 for carrier frequencies of 63.3 and

T

20

−20

−60

−100

−140

10

100

1k

10k

100k

Frequency (Hz)

Figure 22. Transfer Function of the 50 Hz Suppression Circuit shown in Figure 17

of the full scale. An AGC cycle takes two chip clocks: a

measurement cycle at the rising edge of the CHIP_CLK and

an update cycle starting at the next chip clock.

Table 9.

VALUE OF THE RESISTORS AND CAPACITORS

Component

Value

1.5

1

Unit

nF

Low Noise Anti Aliasing Filter and ADC

C

1

2

rd

The receiver has a 3 order continuous time low pass filter

nF

in the signal path. This filter is in fact the same block as in

the transmit path which can be shared because NCN49597

works in half duplex mode. The same choice of −3 dB

frequency can be selected between 130 kHz (virtually flat up

to 95 kHz) or 195 kHz (flat up to 148.5 kHz).

C

mF

DREF

R

22

kW

1

R

11

2

th

It is important to note that the analog part of NCN49597

is referenced to the internal analogue reference voltage

REF_OUT, with a nominal value of 1.65 V. As a result, the

DC voltage on pin RX_IN must be 1.65 V for optimal

dynamic range. If the external signal has a substantially

different reference level capacitive coupling must be used.

The output of the low pass filter is input for an analog 4

order sigma−delta converter. The DAC reference levels are

supplied from the reference block. The digital output of the

converter is fed into a noise shaping circuit blocking the

quantization noise from the band of interest, followed by

decimation and a compensation step.

Automatic Gain Control (AGC)

Quadrature Demodulator

In order to extend the range of the analogue−to−digital

convertor, the receiver path contains a variable gain

amplifier. The gain can be changed in 8 steps from 0 to

−42 dB.

This amplifier can be used in an automatic gain control

(AGC) loop. The loop is implemented in digital hardware.

It measures the signal level after analogue−to−digital

conversion. The amplifier gain is changed until the average

digital signal is contained in a window around a percentage

The quadrature demodulation block mixes the digital

output of the ADC with the local oscillators. Mixing is done

with the in−phase and quadrature phase of both the f and f

S

M

carrier frequencies. Thus, four down−mixed (baseband)

signals are obtained.

After low−pass filtering, the in−phase and quadrature

components of each carrier are combined. The resulting two

signals are a measure of the energy at each carrier frequency.

These energy levels are further processed in the firmware.

www.onsemi.com

23

NCN49597

Communication Controller

The Communication Controller block includes the micro−processor and its peripherals (refer to Figure 23 for an overview).

Communication Controller

Data / Program

TxD

RAM

Serial

Comm.

Interface

RxD

BR0

BR1

Program

ROM

ARM

Risc

Core

Timer 1 & 2

IO[9:0]

Local Port

DATA/PRES

TO

TRANSMIT

FROM

RECEIVER

POR

RESB

TEST

Interrupt

Control

Watchdog

Test

Control

Flash SPI

Figure 23. The Communication Controller is Based on a Standard ARM Corex M0 Core

The processor is an ARM Cortex M0 32−bit core with a

reduced instruction set computer (RISC) architecture,

optimized for IO handling. Most instructions complete in a

single clock cycle, including byte multiplication. The

peripherals include a watchdog, test and debug control,

RAM, ROM containing the boot loader, UART, two timers,

an SPI interface to optional external memory, I/O ports and

the power−on reset. The microcontroller implements

interrupts.

The application microcontroller has also low−level access

to internal timing of the modem through the digital output

DATA/PRES pin. The function of this pin depends on the

register bit R_CONF[7].

If the bit is cleared (0), the preslot synchronization signal

(PRE_SLOT) appears on the pin.

If the bit is set (1), the modem outputs the baseband,

unmodulated, data. Thus, DATA/PRES is driven high when

a space symbol is being transmitted (i.e., the space

The 32 kB RAM contains the necessary space to store the

firmware and the working data. A full−duplex serial

communication block allows interfacing to the application

microcontroller.

frequency f appears on pin TX_OUT); it is driven low when

S

a mask symbol is transmitted (f on TX_OUT).

M

Testing

A JTAG debug interface is provided for development,

debugging and production test. An internal pull−down

resistor is provided on the input pins (TDI, TCK, TMS, and

TRSTB).

In practice, the end user of the modem will not need this

interface; this input pins may be tied to ground

(recommended) or left floating; TDO should be left floating.

The pin TEST enables the internal hardware test mode

when driven high. During normal operation, it should be tied

to ground (recommended) or left floating.

Local Port

Ten bidirectional general purpose input/output (GPIO)

pins (IO0..IO9) are provided. All general purpose IO pins

can be configured as an input or an output. In addition, the

firmware can emulate open−drain or open−source pins. All

pins are 5 V tolerant.

When the modem is booting, IO2 is configured as an input

and must be pulled low to enable uploading firmware over

the serial interface. At the same time, IO0 and IO1 are

configured as outputs and show the status of the boot loader.

A LED may be connected to IO0 to help with debugging.

After the firmware has been loaded successfully, IO0..IO2

become available as normal IOs.

Serial Communication Interface (SCI)

The

Serial

Communication

Interface

allows

asynchronous communication with any device

incorporating a standard Universal Asynchronous Receiver

Transmitter (UART).

Typically, the firmware provides status indication on

some IO pins; other IO pins remain available to the

application microcontroller as IO extensions.

www.onsemi.com

24

NCN49597

The serial interface is full−duplex and uses the standard NRZ format with a single start bit, eight data bits and one stop bit

(Figure 24). The baud rate is programmable from 9600 to 115200 baud through the BR0 and BR1 pins.

IDLE (mark)

LSB

D0

MSB

D7

IDLE(mark)

Stop

t_BIT

Start

t_BIT

D1

D2

D3

D4

D5

D6

8 data bits

1 character

PC20080523.3

Figure 24. Data Format of the Serial Interface

+5V

Serial data is sent from the NCN49597 to the application

microcontroller on pin TxD; data is received on pin RxD.

Both pins are 5 V tolerant, allowing communication with

both 3.3 V−and 5 V−powered devices.

R

On the open−drain output pin TxD an external pull−up

resistor must be provided to define the logic high level

(Figure 25). A value of 10 kW is recommended. Depending

on the application, an external pull−up resistor on RxD may

be required to avoid a floating input.

Output

V_SSD

Figure 25. Interfacing to 5 V Logic using a 5 V Safe

Output and a Pull−up Resistor

3V3_D

NCN49597

TxD

RxD

Serial

BR0

Comm.

Application

BR1

Interface

ARM

Risc

Core

Micro

Controller

IO[9:0]

Local Port

DATA/PRES

Communication Controller

Figure 26. Connection to the Application Microcontroller

The baud rate of the serial communication is controlled by

the pins BR0 and BR1. After reset, the logic level on these

pins is read and latched; as a result, modification of the baud

rate during operation is not possible. The baud rate derived

from BR0 and BR1 is shown in Table 10.

Table 10. BR1, BR0 BAUD RATES

BR1

BR0

SCI Baud Rate

115200

9600

0

1

0

1

0

1

19200

38400

BR0 and BR1 are 5 V safe, allowing direct connection to

5 V−powered logic.

www.onsemi.com

25

NCN49597

Watchdog

Configuration Registers

A watchdog supervises the ARM microcontroller. In case

the firmware does not periodically signal the watchdog it is

alive, it is assumed an error has occurred and a hard reset is

generated.

The behavior of the modem is controlled by configuration

registers. Some registers can be accessed by the user through

the firmware. Table 11 gives an overview of some

commonly exposed registers.

Table 11. NCN49597 CONFIGURATION REGISTERS

Register

R_CONF[7]

Reset Value

Function

0

00b

0

Pin DATA/PRES mode selection

R_CONF[2:1]

R_CONF[0]

Baud rate selection

Mains frequency

R_FS[15:0]

0000h

02h

0

Step register for the space frequency fS

Step register for the mark frequency fM

Fine tuning of phase difference between CHIP_CLK and rising edge of mains zero crossing

Automatic level control (ALC) enable

Automatic level control attenuation

R_FM[15:0]

R_ZC_ADJUST[7:0]

R_ALC_CTRL[3]

R_ALC_CTRL[2:0]

000b

Reset and Low Power

NCN49597 has two reset modes: hard reset and soft reset.

The hard reset re−initializes the complete IC (hardware

and ARM) excluding the data RAM for the ARM. This

guarantees correct start−up of the hardware and the

microcontroller.

When switching on the power supply the output of the

crystal oscillator is disabled until a few thousand clock

pulses have been detected; this allows sufficient time for

oscillator start−up.

When the pin RESB is pulled low the power consumption

drops significantly. Power is drawn only to maintain the bias

of some analogue functions and the oscillator cell.

The modem is kept in hard reset as long as pin RESB is

pulled low or the power supply V < V

(See Table 11).

DD

POR

Boot Loader

During operation, the modem firmware is stored in the

internal random access memory (RAM). As this memory is

volatile, the firmware must be uploaded after reset.

The NCN49597 provides two mechanisms to achieve

this: the firmware may be stored in an external SPI memory

or it may be uploaded over the serial communication

interface.

The memory must be connected to the pins of the

dedicated serial peripheral interface (SPI), as shown in

Figure 27. Any non−volatile memory with the standard

command set and three bytes addressing is supported; is

recommended.

The user must program the firmware into the external

memory starting from address 0. Four bytes must be added

at the end of the lowest 256−byte sector that can fit them, i.e.

either the sector containing the last byte of the firmware or

the next sector. These four bytes contain the checksum, the

Booting from External Memory

During reset, the boot loader module in the modem can

retrieve the firmware from an attached memory.

To enable this mode, the boot control pin SEN must be

driven high and IO2 must be driven low; subsequently the

modem must be reset.

number of sectors used, and the magical numbers A5 and

H

5A . The checksum must be computed over the entire

H

binary.

Between the four metadata bytes and the firmware,

zero−padding must be written.

This is illustrated in Table 12.

NCN49597

EEPROM

LE25U20AQGTXG

SDO

SDI

SD0

SCK

CSB

Bootloader

SCK

CSB

Figure 27. Connecting an External SPI Memory to

the Modem

www.onsemi.com

26

NCN49597

bytes), followed by four bytes: checksum, 03 , A5 and

H

Table 12. REQUIRED CONTENTS OF AN EXTERNAL

BOOTABLE SPI MEMORY FOR A BINARY FIRMWARE

FILE OF LENGTH N BYTES

5A .

H

Once the boot loader has finished copying the firmware to

the internal memory, the checksum is calculated and

compared to the stored checksum. If both match, the

processor is released from reset and the firmware starts

executing. IO2 subsequently becomes available as a normal

GPIO.

Address

Content

0

...

Firmware binary

N

N + 1

...

Firmware Upload over the Serial Communication

Interface

Zero padding, if required

During reset, the boot loader module in the modem can

receive the firmware over the serial interface.

100 V S + FB

H

100 V S + FC

Checksum

H

To enable this mode, the IO2 and the boot control pin SEN

must be driven low; subsequently the modem must be reset.

IO2 must remain low during the entire boot process; if

driven high during boot the boot loader terminates

immediately. To restart the boot loader, reset the modem.

As soon as the reset of the modem is released, the boot

loader process starts. When it is ready to receive the

firmware from the external microcontroller, the boot loader

100 V S + FD

S, the number of sectors used

H

100 V S + FE

Magical number: A5

H

100 V S + FF

Magical number: 5A

H

Where S is the numbers of sectors used:

N ) 4

Ȳ₁₀₀ȴ

S +

H

will send a 02 (STX) byte.

H

The tool PlcEepromGenerator.exe, provided by

ON Semiconductor, may be used to convert a binary

firmware file into a file that follows these requirements. The

latter can be written directly in the external memory.

As an example, if the firmware binary size is 618 bytes,

the first two 256−byte sector will be filled completely. The

last 106 bytes of the firmware binary will be written to the

third sector, followed by zero padding (256 − 106 − 4 = 146

Upon receiving this byte the user must send the byte

sequence specified in Table 13. The sequence contains a

checksum to verify correctness of the received binary image.

The CRC must be calculated over the firmware binary only

(excluding the magical number and the size). The program

crc.exe, provided by ON Semiconductor, can be used for this

calculation.

Table 13. BYTE SEQUENCE to be transmitted by the application microcontroller during firmware upload

Value

Description

Should only be sent to restart the boot loader process, in response to a NAK character received from the modem

Magical number

[ CE

AA

]

H

Size (LSB)

Size (MSB)

Binary, first byte

...

The size of the entire firmware binary, including the four bytes for the CRC at the end

Contents of the firmware binary

Binary, last byte

CRC (LSB)

CRC (MSB)

CRC, as calculated on the binary only

Data transmission must start only after receiving the STX

byte. In addition, the first byte must be sent within 350 ms.

If these timing constraints are not satisfied the boot loader

constraints is not met, or if the checksum is incorrect, the

boot loader will send a 15 (NAK) character. This error also

H

occurs when the user attempts to upload a binary exceeding

will send a 15 (NAK) character and will reject any data

the maximal size of 7F00 (32512) bytes. When the

H

received until the application microprocessor stops sending

bytes for at least 100 ms. The pause will restart the boot

loader, and a new STX character will be sent to the

application microcontroller to indicate this.

application microcontroller receives this NAK, it should

transmit a CE (mnemonic for “clear error”) byte. This

H

informs the boot loader that the application microcontroller

understood the problem. Following the CE byte, the

H

Once transmission has started, the maximal delay

between consecutive bytes is 20 ms. If this timing

microcontroller may restart.

The timing constraints are illustrated in Figure 3.

www.onsemi.com

27

NCN49597

Application Information

For

a

system−level overview of power line

The analogue and digital blocks are powered through

independent power supply pins (VDDA resp. VDD); the

nominal supply voltage is 3.3 V. On both pins, decoupling

must be provided with at least a ceramic capacitor of 100 nF

between the pin and the corresponding ground (VSSA resp.

VSS). The connection path of these capacitors on the printed

circuit board (PCB) should be kept as short as possible in

order to minimize the parasitic inductance.

communication, refer to [4]. For more information on how

to design with the NCN49597 modem, refer to the design

manual available from your sales representative [1]. This

section gives a few hints.

Supplies and Decoupling

For optimal stability and noise rejection, all power

supplies must be decoupled as physically close to the device

as possible.

It is recommended to tie both analogue and digital ground

pins to a single, uninterrupted ground plane.

GROUND

C_DA

C_DREF

3,3V SUPPLY

VSSA

REF_OUT

VDDA

1

2

39

38

37

36

35

34

33

32

31

30

29

28

27

3

4

5

6

7

8

9

10

11

12

13

VDD1V8

C _DD1V8

VDD

C _DD

PC20111121.1

3,3V SUPPLY

VSS

Figure 28. Recommended Layout of the Placement of Decoupling

Capacitors (bottom ground plane not shown)

Internal Voltage Reference

Internal Voltage Regulator

REF_OUT is the analog output pin which provides the

voltage reference used by the A/D converter. This pin must

be decoupled to the analog ground by a 1 mF ceramic

An internal linear regulator provides the 1.8 V core

voltage for the microcontroller. This voltage is connected to

pin VDD1V8. A ceramic decoupling capacitor of 1 mF to

ground must be connected as close as possible to this pin

(Figure 28).

capacitance C . The connection path of this capacitor to

DREF

the VSSA on the PCB should be kept as short as possible in

order to minimize the serial inductance.

The internal regulator should not be used to power other

components.

www.onsemi.com

28

NCN49597

References

In this document references are made to:

3. ON Semiconductor. Mains synchronization for

PLC modems (application note). 2015−08−19. The

latest version is available from your sales

representative.

1. ON Semiconductor, Design Manual

NCN495979/9, 2016−08−23. The latest version is

available from your sales representative.

2. CENELEC. EN 50065−1: Signaling on low−

voltage electrical installations in the frequency

range 3 kHz to 148,5 kHz. 2011−04−22. Online at

http://www.cenelec.eu/dyn/www/f?p=104:110:102

2556227334229::::FSP_ORG_ID,FSP_PROJECT,

FSP_LANG_ID:821,22484,25

4. ON Semiconductor. AND9165/D. Getting started

with power line communication (application note).

2016−05−01. Online at

http://www.onsemi.com/pub_link/Collateral/AND

9165−D.PDF

Table 14. ORDERING INFORMATION

†

Part Number

Temperature Range

Package Type

Shipping

NCN49597MNG

−40°C – 125°C

QFN−52

(Pb−Free)

Tube

NCN49597MNRG

−40°C – 125°C

QFN−52

(Pb−Free)

Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

www.onsemi.com

29

NCN49597

PACKAGE DIMENSIONS

QFN52 8x8, 0.5P

CASE 485M

ISSUE C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.25 AND 0.30

MM FROM TERMINAL.

D

A

B

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

MILLIMETERS

DIM MIN

MAX

1.00

0.05

0.80

A

A1

A2

A3

b

0.80

0.00

0.60

E

0.20 REF

0.18

0.30

6.80

2X

D

8.00 BSC

0.15

C

D2

E

6.50

8.00 BSC

2X

E2

e

6.80

0.50 BSC

0.15

C

K

0.20

0.30

---

L

0.50

A2

0.10

0.08

C

A

RECOMMENDED

SOLDERING FOOTPRINT*

A3 REF

26

A1

SEATING PLANE

8.30

6.75

C

52X

0.62

D2

14

27

13

L

52 X

E2

8.30

6.75

39

1

52

40

52X

0.30

PKG

OUTLINE

K

52 X

b

NOTE 3

52 X

0.50

PITCH

e

0.10 C A

0.05

B

DIMENSIONS: MILLIMETERS

C

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

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NCN49597/D

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30


型号：	NCN49597MNRG
厂家：	ONSEMI
描述：	Power Line Communication Modem 电信电信集成电路
文件：	总30页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCN49597MNRG [ONSEMI]

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