NCN5150MNTWG [ONSEMI]

Wired M-BUS Slave Transceiver; 有线M- BUS从收发器


型号：	NCN5150MNTWG
厂家：	ONSEMI
描述：	Wired M-BUS Slave Transceiver 有线M- BUS从收发器
文件：	总12页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCN5150

Wired M-BUS Slave

Transceiver

Description

The NCN5150 is a single-chip integrated slave transceiver for use in

two-wire Meter Bus (M-BUS) slave devices and repeaters. The

transceiver provides all of the functions needed to satisfy the

European Standards EN 13757−2 and EN 1434−3 describing the

physical layer requirements for M-BUS. It includes a programmable

power level of up to 2 (SOIC version) or 6 (NQFP version) unit loads,

which are available for use in external circuits through a 3.3 V LDO

regulator.

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NQFP−20

SOIC−16

D SUFFIX

CASE 751B

MN SUFFIX

CASE 485E

The NCN5150 can provide communication up to the maximum

M-BUS communication speed of 38,400 baud (half-duplex).

Features

MARKING DIAGRAMS

• Single-chip MBUS Transceiver

• UART Communication Speeds Up to 38,400 baud

NCN

5150

ALYW

• Integrated 3.3 V VDD LDO Regulator with Extended Peak Current

Capability of 15 mA

• Supports Powering Slave Device from the Bus or from External

Power Supply

NQFP−20

• Adjustable I/O Levels

• Adjustable Constant Current Sink up to 2 or 6 Unit Loads Depending

on the Package

NCN5150

ALYYWWG

• Low Bus Voltage Operation

• Extended Current Budget for External Circuits: at least 0.88 mA

• Polarity Independent

• Power-Fail Function

SOIC−16

• Fast Startup − No External Transistor Required on STC Pin

• Industrial Ambient Temperature Range of −40°C to +85°C

= Assembly Location

= Wafer Lot (optional)

= Year

Y, YY

• Available in:

W, WW = Work Week

G or G = Pb-free Package

♦ 16-pin SOIC (Pin-to-Pin Compatible with TSS721A)

♦ 20-pin QFN

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

• These are Pb-free Devices

Typical Applications

• Multi-energy Utility Meters

♦ Water

♦ Gas

♦ Electricity

♦ Heating systems

Related Standards − European Standard

EN 13757−2, EN 1434−3

For more information visit www.m-bus.com

Publication Order Number:

September, 2013 − Rev. 2

NCN5150/D

NCN5150

BUSL2

16 BUSL1

15 GND

14 RIS

13 RXI

12 RX

20 19

18 17

GND

BUSL1

BUSL2

STC

RIDD

NCN5150

SOIC16

VIO

QFN20

PFb

TXI

11 VDD

10 VS

TXI

VIO

Figure 1. Pin Out NCN5150 in 20-pin NQFP and 16 Pin SOIC (Top View)

Table 1. NCN5150 PINOUT

Pin Number

NCN5150 SOIC

NCN5150 QFN

Signal Name

BUSL1

BUSL2

Type

Bus

Pin Description

MBUS line. Connect to bus through 220 W series resistors.

Connections are polarity independent

Bus

Power

Output

Rectified bus voltage

STC

Storage capacitor pin. Connect to bulk storage capacitor

(minimum 10 mF, maximum 330 mF−2,700 mF − see Table 9)

RIDD

Input

Mark current adjustment pin.

Connect to programming resistor

PFb

Output

Power Fail, active low

Mark bus voltage level storage capacitor pin.

Connect to ceramic capacitor (typically 220 nF)

TXI

Output

Input

UART Data output (inverted)

UART Data output

VIO

I/O pins (RX, RXI, TX, TXI, PFb) high level voltage

Output

Gate driver for PMOS switch between bus powered operation

and external power supply

VDD

Power

Voltage regulator output.

Connect to minimum 1 mF decoupling capacitor

RXI

RIS

GND

Input

−

UART Data input

UART Data input (inverted)

Modulation current adjustment pin

Ground

Input

Ground

5, 10, 15, 19

Not connected pins. Tie to GND

Exposed Pad. Tie to GND

Ground

−

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NCN5150

PFb

Power

Fail

Detect

VIO_BUF

VB_INT

VIO

Buffer

VIO

BUSL1

CS1

BUSL2

RIDD

STC

VIO_BUF

Receiver

STC

Driver

Voltage

Monitor

TXI

RXI

ECHO

STC

Clamp

3.3 V

LDO

Transmitter

VDD

CS_TX

Thermal

Shutdown

POR

RIS

NCN5150

GND

Figure 2. NCN5150 Block Diagram

Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)

Symbol Parameter

Min

−40

−55

−50

−0.3

4.0

Max

+150

Unit

°C

Junction Temperature

Storage Temperature

Bus Voltage (|BUSL1 − BUSL2|)

Voltage on Pin TX, TXI

BUS

, V

TXI

7.5

5.5

−

, V , V

Voltage on Pin RX, RXI, VIO

ESD Rating − Human Body Model

ESD Rating − Machine Model

ESD Rating − Charged Device Model

RXI

ESD

HBM

ESD

250

750

−

ESD

−

CDM

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. All voltages are referenced to GND.

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NCN5150

Table 3. THERMAL CHARACTERISTICS

Rating

Symbol

Typical Value

Unit

°C/W

Thermal Characteristics, SOIC−16 − Thermal Resistance, Junction-to-Air

Thermal Characteristics, QFN−20 − Thermal Resistance, Junction-to-Air

125

θJA

NOTE: R

obtained with 1S0P (SOIC) or 2S2P (QFN) test boards according to JEDEC JESD51 standard.

,JA

Table 4. RECOMMENDED OPERATING CONDITIONS (Notes 2 and 3)

Symbol Parameter

Min

Max

+85

Unit

°C

Ambient Temperature

Bus Voltage (|V

−40

9.2

9.7

2.5

BUS

− V |)

BUS2

1−2 Unit Loads

3−6 Unit Loads

BUSL1

VIO Pin Voltage (Note 4)

3.8

2. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.

3. All voltages are referenced to GND.

4. V

must be at least 1V higher than V for proper operation.

STC

Table 5. ELECTRICAL CHARACTERISTICS (Note 5)

Symbol Parameter

− V ) (R

Min

−

Typ

−

Max

Unit

Voltage drop over bus rectifier (V

Voltage drop over CS1

(Note 6) = 4.02 kW)

1.25

−

BUS

IDD

(Note 6) ≥ 13 kW

1.30

1.70

−

IDD

(V − V

)

STC

(Note 6) ≤ 4.02 kW

−

IDD

Total Current Drawn from the Bus, Mark

State

1.32

2.71

4.10

5.50

6.80

8.22

0.2

1.50

3.00

4.50

6.00

7.50

9.00

(Note 6) = 30 kW

(Note 6) = 13 kW

BUS

IDD

−

(Note 6) = 8.45 kW

(Note 6) = 6.19 kW

(Note 6) = 4.87 kW

(Note 6) = 4.02 kW

−

IDD

−

BUS

Bus Current Stability (over DV

= 10 V, RX/RXI = mark)

−

BUS

Idle Current Available for the Application

0.88

2.10

3.10

4.20

5.30

6.50

−

1.05

2.35

3.60

4.80

6.10

7.45

200

1.20

2.60

4.00

5.40

6.90

8.40

−

(Note 6) = 30 kW

(Note 6) = 13 kW

STC

IDD

to Draw from STC and V (Including

Current Drawn from IO Pins)

(Note 6) = 8.45 kW

(Note 6) = 6.19 kW

(Note 6) = 4.87 kW

(Note 6) = 4.02 kW

IDD

Additional Current Available for the Application when Transmitting a

Space

STC, space

Internal Supply Current (R

(Note 6) = 13 kW, RX/RXI = mark)

−

359

−

500

0.5

7.0

IDD

Current Drawn by the V Pin

−0.5

6.0

STC, clamp

Clamp Voltage on Pin STC (I < I

)

6.5

−

STC

Threshold Voltage on V to Trigger PFb (Note 7)

+ 0.3

V + 0.8

STC

B, PFb

STC

PFb Voltage High (I

= −100 mA)

− 0.6

−

PFb, OH

PFb

PFb Voltage Low (Note 8) (I = 50 mA)

PFb

−

0.6

PFb, OL

Voltage on RIDD Pin

1.15

− 0.4

1.20

−

1.25

RIDD

Voltage on VS during High State

(V > V , I = −5 mA)

STC

VS, OH

STC

STC, VDD ON VS

VS, PD

Pull-down Resistor on VS during Low State

(V > 2 V, V > V )

100

150

STC

5. All voltages are referenced to GND.

6. Resistor with 1% accuracy.

7. PFb comparator has a 70 mV hysteresis.

8. PFb pin is pulled down with an on-chip resistor of typically 2 MW.

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NCN5150

Table 6. VDD REGULATOR ELECTRICAL CHARACTERISTICS (Note 9)

Symbol

Parameter

Voltage on V (Note 10 ) (I < 15 mA)

Min

3.1

Typ

3.3

−

Max

3.6

−

Unit

Peak Current that can be Supplied by V (Note 11)

BUS

= 0 V, V = 0 V

STC

−0.5

2.65

2.55

5.6

−

0.5

3.15

3.00

6.4

DD, OFF

Power-on Reset Threshold, Release

Power-on Reset Threshold, Reset

2.85

2.75

6.0

POR, ON

POR, OFF

Threshold Voltage on Pin STC to Turn On V Regulator, Pull

the VS Pin High and Enable the PF Function

STC, VDD ON

Threshold Voltage on Pin STC to Turn Off V Regulator and

3.7

4.0

4.3

STC, VDD OFF

Pull the PFb and VS Pins Low

9. All voltages are referenced to GND.

10. Including output resistance of V

11. Average current draw limited by I

STC

Table 7. RECEIVER ELECTRICAL CHARACTERISTICS (Note 12)

Symbol Parameter

Receiver Threshold Voltage

Min

− 8.2

Typ

Max

V − 5.7

Unit

−

Mark Level Storage Capacitor Voltage

−

SC, charge

Mark Level Storage Capacitor Charge Current

Mark Level Storage Capacitor Discharge Current

−40

0.3

−25

0.6

−15

−0.033 ×

SC, discharge

SC, charge

CDR

Charge/Discharge Current Ratio

−

TX/TXI High-level Voltage (I /I

= −100 mA) (Note 13)

− 0.6

−

TX, OH

TXI, OH

TX TXI

TX/TXI Low-level Voltage

−

0.35

1.5

(I /I

= 100 mA)

TX, OL

TXI, OL

TX TXI

(I = 1.1 mA)

, I

= 7.5 V, V = 6 V

STC

TX TXI

12. All voltages are referenced to GND.

13. V must be at least 1 V higher than V for proper operation.

STC

Table 8. TRANSMITTER ELECTRICAL CHARACTERISTICS (Note 14)

Symbol Parameter

Min

12.5

1.2

Typ

Max

Unit

Space Level Modulating Current (R = 100 W (Note 15))

RIS

15.0

1.4

−

18.0

1.6

5.5

0.8

RIS

Voltage on RIS Pin

, V

RXI, IH

, V

RXI, IL

RX/RXI Input High

V − 0.8

RX, IH

RX/RXI Input Low

−

RX, IL

I , I

RX RXI

Current Drawn or Sourced from RX/RXI Pins (Note 16)

(V = 3 V)

−

14.All voltages are referenced to GND.

15.Resistor with 1% accuracy.

16.Including internal pull-up resistor on RX and internal pull-down resistor on RXI.

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NCN5150

APPLICATION SCHEMATICS

VIO

VDD

BUS1

BUSL2

VDD

TXI

TVS

MBUS

NCN5150

BUSL1

BUS2

RXI

PFb

RIS

GND

RIDD

STC

IDD

Figure 3. General Application Schematic

VIO

VDD

BUS1

VDD

BUSL2

TXI

TVS

MBUS

NCN5150

BUSL1

BUS2

RXI

PFb

RIS

GND

RIDD

STC

IDD

Figure 4. Application Schematic with External Power Supply (Battery)

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NCN5150

APPLICATION SCHEMATICS

VIO

VDD

BUS1

VDD

BUSL2

TVS

TXI

MBUS

NCN5150

BUSL1

BUS2

RXI

PFb

RIS

GND

RIDD

STC

IDD

Figure 5. Application Schematic with Backup External Power Supply

STC

VIO

VDD

2.2 kW

15 kW

BUS1

VDD

BUSL2

TXI

TVS

MBUS

NCN5150

BUSL1

BUS2

RXI

PFb

RIS

GND

RIDD

STC

620 W

V_STC

STC

IDD

Figure 6. Optically Isolated Application Schematic

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NCN5150

Table 9. TYPICAL BILL OF MATERIALS

Reference Designator

Value (Typical)

Tolerance

Manufacturer

ON Semiconductor

Part Number

NCN5150

−

TVS

40 V

1SMA40CAT3G

> 1 mF

−20%, +80%

VDD

100 W

220 nF

−20%, +80%

10%

, R

220 W

BUS1

BUS2

1 UL

2 UL

3 UL

4 UL

5 UL

6 UL

1 UL

2 UL

3 UL

4 UL

5 UL

6 UL

30 kW

IDD

13 kW

8.45 kW

6.19 kW

4.87 kW

4.02 kW

≤ 330 mF

≤ 820 mF

≤ 1,200 mF

≤ 1,500 mF

≤ 2,200 mF

≤ 2,700 mF

10%

STC

APPLICATION INFORMATION

The NCN5150 is a slave transceiver for use in the meter

bus (M-BUS) protocol. The bus connection is fully polarity

independent. The transceiver will translate the bus voltage

modulation from master-to-slave communication to TTL

UART communication, and in the other direction translate

UART voltage levels to bus current modulation. The

transceiver also integrates a voltage regulator for utilizing

the current drawn in this way from the bus, and an early

power fail warning. The transceiver also supports an

external power supply and the I/O high level can be set to

match the slave sensor circuit. A complete block diagram is

shown in Figure 2. Each section will be explained in more

detail below.

Communication speeds allowed by the M-BUS standard are

300, 600, 2400, 4800, 9600, 19200 and 38400 baud, all of

which are supported by the NCN5150.

Bus Connection and Rectification

The bus should be connected to the pins BUSL1 and

BUSL2 through series resistors to limit the current drawn

from the bus in case of failure (according to the M-BUS

standard). Typically, two 220 W resistors are used for this

purpose.

Since the M-BUS connection is polarity independent, the

NCN5150 will first rectify the bus voltage through an active

diode bridge.

Slave Power Supply (Bus Powered)

Meter Bus Protocol

A slave device can be powered by the M-BUS or from an

external supply. The M-BUS standard requires the slave to

draw a fixed current from the bus. This is accomplished by

the constant current source CS1. This current is used to

M-BUS is a European standard for communication and

powering of utility meters and other sensors.

Communication from master to slave is achieved by

voltage-level signaling. The master will apply a nominal

+36 V to the bus in idle state, or when transmitting a logical

1 (“mark”). When transmitting a logical 0 (“space”), the

master will drop the bus voltage to a nominal +24 V.

Communication from the slave to the master is achieved

by current modulation. In idle mode or when transmitting a

logical 1 (“mark”), the slave will draw a fixed current from

the bus. When transmitting a logical 0 (“space”), the slave

will draw an extra nominal 15 mA from the bus. M-BUS

uses a half-duplex 11-bit UART frame format, with 1 start

bit, 8 data bits, 1 even parity bit, and a stop bit.

charge the external storage capacitor C . The current

STC

drawn from the bus is defined by the programming resistor

IDD

. The bus current can be chosen in increments of

1.5 mA called unit loads. Table 5 list the different values of

programming resistors needed for different unit loads, as

well as the current drawn from the bus (I ) and the current

BUS

that can be drawn from the STC pin (I ). I

is slightly

STC STC

less than I

to account for the internal power consumption

BUS

of the NCN5150. The R

resistor used must be at least 1%

IDD

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NCN5150

BUS

MARK

= [21 V, 42 V]

accurate. Note that using 5 and 6 Unit Loads is not covered

by the M-BUS standard.

When the voltage on the STC pin reaches V

V = V

− 6 V

MARK

STC, VDD ON

= V

− 12 V

SPACE

MARK

the LDO is turned on, and will regulate the voltage on the

VDD pin to 3.3 V, drawing current from the storage

capacitor. A decoupling capacitor of minimum 1 mF is

required on the VDD pin for stability of the regulator. On the

STC pin, a minimum capacitance of 10 mF is required.

Furthermore, the ratio C /C

The voltage on the STC pin is clamped to V

shunt regulator, which will dissipate any excess current that

is not used by the NCN5150 or external circuits.

must be larger than 9.

STC VDD

TXI

by a

STC, clamp

Slave Power Supply (External)

Figure 7. Communication, Master to Slave

In case the external sensor circuit consumes more than the

allowed bus current or the sensor should be kept operational

when the bus is not present, an external power supply, such

as a battery, is required.

CHARGE

When the external circuitry uses different logical voltage

levels, simply connect the power supply of that voltage level

to V , so that the RX, RXI, TX, TXI and PFb pins will

respond to the correct voltage levels. The NCN5150 will still

be powered from the bus, but all communication will be

DISCHARGE

−

translated to the voltage level of V .

If the external power supply should be used only as a

backup when the bus power supply fails, a PMOS transistor

can be inserted between the external power supply and VDD

as shown in Figure 5. The gate is connected to VS, and will

be driven high when the voltage on STC goes above the

Encoding

Echo

TXI

turn-on threshold of the LDO, nl. V

. For more

STC, VDD ON

information see the paragraph on the power on sequence and

corresponding Figure 12 on page 10.

Figure 8. Communication, Master to Slave

Communication, Slave to Master

Communication, Master to Slave

M-BUS communication from slave to master uses bus

current modulation while the voltage remains constant. This

current modulation can be controlled from either the RX or

RXI pin as shown in Figure 10. When transmitting a space

(“0”), the current modulator will draw an additional current

from the bus. This current can be set with a programming

M-BUS communication from master to slave is based on

voltage level signaling. To differentiate between master

signaling and voltage drop caused by the signaling of

another slave over cabling resistance, etc., the mark level

is stored, and only when the bus voltage drops

BUS, MARK

to less than V will the NCN5150 detect communication. A

resistor R . To achieve the space current required the

RIS

simplified schematic of the receiver is shown in Figure 8.

The received data is transmitted on the pins TX and TXI, as

shown in the waveforms of Figure 7.

M-BUS standard, R

should be 100 W. A simplified

RIS

schematic of the transmitter is shown in Figure 11.

An external capacitor must be connected to the SC pin to

store the mark voltage level. This capacitor is charged to V .

Discharging of this capacitor is typically 40x slower, so that

the voltage on SC drops only a little during the time the

master is transmitting a space. The value of C must be

chosen it the range of 100 nF−330 nF.

Figure 9. Typical Relationship between RIS and

Current Modulation Level

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NCN5150

Because the M-BUS protocol is specified as half-duplex,

shut down gracefully. The times t and t can be

off

an echo function will cause the transmitted signal on RX or

RXI to appear on the receiver outputs TX and TXI. Should

the master attempt to send at the same time, the bitwise

added signal of both sources will appear on these pins,

resulting in invalid data.

approximated by the following formulas:

C_STC

(eq. 1)

(eq. 2)

t_on

V_{STC, VDD ON}

I_STC

C_STC

ǒ_VǓ

_{STC, Clamp}* V_{STC, VDD OFF}

t_off

_CC) I_DD

Where I

is the internal current consumption of the

NCN5150 and I

circuits drawn from either VDD or STC.

is the current consumed by external

RXI

These formulas can be used to dimension the value of the

bulk C

needed, taking into account that the M-BUS

STC

standard requires t to be less than 3 s.

For certain applications where the power drawn from the

bus is not used in external circuits, the storage capacitor

value can be much lower. The NCN5150 requires a

minimum STC capacitance of 10 mF to ensure that the bus

current regulation is stable under all conditions.

BUS

= I

+ 15 mA

SPACE

MARK

= N unit loads

MARK

BUS

Figure 10. Communication, Slave to Master

= V

+ 0.6

STC

B, MIN

IO_BUF

STC, CLAMP

STC

Echo

STC, VDD ON

STC, VDD OFF

Decoding

RXI

STC, CLAMP

Enable

−

3.3 V

RIS

PFb

off

Figure 11. Communication, Slave to Master

Figure 12. Power-on and Power-off

Thermal Shutdown

The NCN5150 includes a thermal shutdown function that

will disable the transmitter when the junction temperature of

the IC becomes too hot. The thermal protection is only active

when the slave is transmitting a space to the master.

Power On/Off Sequence

The power-on and power-off sequence of the NCN5150

is shown in Figure 12. Shown also in Figure 12 is the

operation of the PFb pin. This pin is used to give an early

warning to the microcontroller that the bus power is

collapsing, allowing the microcontroller to save its data and

Table 10. ORDERING INFORMATION

†

Device

Package

Shipping

NCN5150DG

SOIC16

48 Units / Tube

3,000 / Tape & Reel

2,500 / Tape & Reel

(Pb-free)

NCN5150DR2G

NCN5150MNTWG

NQFP20, 4x4

(Pb-free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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NCN5150

PACKAGE DIMENSIONS

QFN20, 4x4, 0.5P

CASE 485E

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30 MM

FROM THE TERMINAL TIP.

EXPOSED Cu

MOLD CMPD

PIN ONE

REFERENCE

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

MILLIMETERS

DETAIL B

DIM MIN

MAX

1.00

0.05

0.15

OPTIONAL CONSTRUCTIONS

0.80

---

0.20 REF

0.15

0.20

0.30

2.90

TOP VIEW

4.00 BSC

2.60

4.00 BSC

(A3)

DETAIL B

2.60

2.90

0.10

0.08

0.50 BSC

0.20 REF

DETAIL A

0.35

0.00

0.45

0.15

OPTIONAL CONSTRUCTIONS

SEATING

PLANE

SIDE VIEW

SOLDERING FOOTPRINT*

0.10 C A B

4.30

20X

0.58

DETAIL A

20X L

2.88

0.10 C A B

2.88

4.30

20X b

0.10 C A B

0.05

NOTE 3

PKG

OUTLINE

BOTTOM VIEW

20X

0.35

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb-free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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NCN5150

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

−B−

P 8 PL

0.25 (0.010)

MILLIMETERS

INCHES

MIN

0.386

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

9.80

3.80

1.35

0.35

0.40

10.00

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

R X 45

1.27 BSC

0.050 BSC

0.19

0.10

0.25 0.008

0.25 0.004

0.009

−T−

SEATING

PLANE

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

16 PL

0.25 (0.010)

T B

SOLDERING FOOTPRINT*

6.40

16X

1.12

16X

0.58

1.27

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb-free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

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