NCN5193_3 [ONSEMI]
HART Modem;型号: | NCN5193_3 |
厂家: | ONSEMI |
描述: | HART Modem |
文件: | 总14页 (文件大小:199K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCN5193
HART Modem
Description
The NCN5193 is a single−chip, CMOS modem for use in highway
addressable remote transducer (HART) field instruments and masters.
The modem and a few external passive components provide all of the
functions needed to satisfy HART physical layer requirements
including modulation, demodulation, receive filtering, carrier detect,
and transmit−signal shaping. In addition, the NCN5193 also has an
integrated DAC for low-BOM current loop slave transmitter
implementation.
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MARKING
DIAGRAM
The NCN5193 uses phase continuous frequency shift keying (FSK)
at 1200 bits per second. To conserve power the receive circuits are
disabled during transmit operations and vice versa. This provides the
half−duplex operation used in HART communications.
1
NCN
5193
32
1
AWLYYWWG
Features
QFN32
CASE 488AM
G
• Single−chip, Half−duplex 1200 Bits per Second FSK Modem
• Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz
• 1.8 V − 3.5 V Power Supply
NCN5193 = Specific Device Code
A
= Assembly Location
= Wafer Lot
• Transmit−signal Wave Shaping
WL
YY
WW
G
= Year
• Receive Band−pass Filter
= Work Week
= Pb−Free Package
• Low Power: Optimal for Intrinsically Safe Applications
• Compatible with 1.8 V or 3.3 V Microcontroller
• Internal Oscillator Requires 460.8 kHz, 920 kHz, 1.84 MHz or
3.68 MHz Crystal or Ceramic Resonator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
• SPI Communication
• Integrated 17 bit Sigma-Delta DAC
• Meets HART Physical Layer Requirements
• Industrial Temperature Range of −40°C to +85°C
• Available in 32−pin NQFP Package
• These are Pb−Free Devices
Applications
• HART Multiplexers
• HART Modem Interfaces
• 4 − 20 mA Loop Powered Transmitters
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2016 − Rev. 3
NCN5193/D
NCN5193
BLOCK DIAGRAM
VDD
VDDA
RxAFI RxAF
RxAP
RxAN
Demodulator
Logic
RxD
CD
FSK_IN
Rx Comp
Filter Amplifier
AREF
Carrier Detect
Counter
CDREF
TxA
Carrier Comp
DEMODULATOR
Numeric
Controlled
Oscillator
Sine
Shaper
TxD
RTS
FSK_OUT
MODULATOR
DAC
NCN5193
JUMP
DAC
DACREF
CS
SCLK
DATA
SPI
Registers
TEST1
TEST2
VPOR
KICK
RESET
CLK1
Crystal
Oscillator
POR
BIAS
CLK2
VSS CBIAS
MODE
XOUT XIN
Figure 1. Block Diagram NCN5193
ELECTRICAL SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Min
−40
−55
−40
−0.3
−0.3
Max
+85
Units
°C
°C
°C
V
T
A
Ambient Temperature
Storage Temperature
Junction Temperature
Supply Voltage
T
S
+150
+150
4.0
T
J
V
DD
V
IN
, V
OUT
DC Input, Output
V + 0.3
DD
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. CMOS devices are damaged by high−energy electrostatic discharge. Devices must be stored in conductive foam or with all pins shunted.
Precautions should be taken to avoid application of voltages higher than the maximum rating. Stresses above absolute maximum ratings
may result in damage to the device.
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2
NCN5193
Table 2. DC CHARACTERISTICS (V = 1.8 V to 3.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Symbol
Parameter
V
Min
Typ
Max
Units
V
DD
V
DD
DC Supply Voltage
Input Voltage, Low
Input Voltage, High
1.8
3.5
V
IL
1.8 – 3.5 V
1.8 – 3.5 V
1.8 – 3.5 V
1.8 – 3.5 V
0.2 * V
V
DD
V
IH
0.8 * V
V
DD
V
Output Voltage, Low (I = 0.67 mA)
0.4
V
OL
OH
OL
V
Output Voltage, High (I = −0.67 mA)
V
− 0.4
V
OH
DD
I /I
Input Leakage Current
Total Power Supply Current
Static Analog Supply Current
Static Digital Current
1
500
270
30
mA
mA
mA
mA
mA
V
IL IH
I
70
190
DD
I
45
0
DDA
DDQ
I
I
Dynamic Digital Current
Analog Reference
25
1.2
200
2.6
DDD
A
REF
1.235
1.15
CD
Carrier Detect Reference (A – 0.08 V)
REF
V
REF
(Note 2)
I
Comparator Bias Current
10
mA
BIAS
(R
= 120 kW, A
= 1.235 V)
BIAS
REF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. The HART specification requires carrier detect (CD) to be active between 80 and 120 mVp−p. Setting CD
at A
− 0.08 VDC will set
REF
REF
the carrier detect to a nominal 100 mVp−p.
Table 3. AC CHARACTERISTICS (V = 1.8 V to 3.5 V, V = 0 V, T = −40°C to +85°C) (Note 3)
DD
SS
A
Pin Name
Description
Min
Typ
Max
Units
RxAP, RxAN
Receive analog input
Leakage current
Frequency – mark (logic 1)
Frequency – space (logic 0)
150
1210
2220
nA
Hz
Hz
1190
2180
1200
2200
RxAF
Output of the high−pass filter
Slew rate
0.04
V/ms
kHz
V
Gain bandwidth (GBW)
Voltage range
300
0.15
V
DD
– 0.15
RxAFI
TxA
Carrier detect and receive filter input
Leakage current
500
nA
Modulator output
Frequency – mark (logic 1)
Frequency – space (logic 0)
Amplitude (IAREF 1.235 V)
Slew Rate − mark (logic 1)
Slew Rate − space (logic 0)
Loading (IAREF = 1.235 V)
1196.9
2194.3
500
1860
3300
Hz
Hz
mV
V/s
V/s
kW
30
RxD
CD
Receive digital output
Rise/fall time
ns
20
20
Carrier detect output
Rise/fall time
ns
3. The modulator output frequencies are proportional to the input clock frequency (460.8 kHz/920 kHz/1.84 MHz / 3.68 MHz).
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3
NCN5193
Table 4. MODEM CHARACTERISTICS (V = 1.8 V to 3.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Parameter
Min
Typ
Max
Units
Demodulator jitter
Conditions
12
% of 1 bit
1. Input frequencies at 1200 Hz 10 Hz, 2200 Hz 20 Hz
2. Clock frequency of 460.8 kHz 0.1%
3. Input (RxAP) asymmetry, 0
Table 5. CERAMIC RESONATOR AND CRYSTAL − External Clock Specifications
(V = 1.8 V to 3.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Parameter
Min
Typ
Max
Units
460.8 kHz / 920 kHz / 1.84 MHz / 3.68 MHz Ceramic resonator
or crystal oscillation frequency tolerance
1.0
%
External Clock
Duty cycle
Amplitude
35
50
− V
OH OL
65
%
V
V
Table 6. DAC CHARACTERISTICS (V = 3.0 V to 5.5 V, V = 0 V, T = −40°C to +85°C)
DD
SS
A
Parameter
Min
Typ
Max
Units
Hz
Bandwidth (Note 4)
Resolution
25
17
Bit
Maximum Output
Return−to−Zero
V
AVDD/2
4. The DAC is a sigma−delta type modulator. Therefore, the bandwidth is determined by the external filter. Decreasing the bandwidth will
increase DAC accuracy.
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NCN5193
TYPICAL APPLICATION
C
4
R
R
6
5
VDDA
1.8 V − 3.5 V
C6
C5
R8
R9
VDD
VDDA
RxAFI
RxAF
RxAN
R10
RESET
R11
R12
R3 C3
C1
R1
C2
VPOR
HART IN
RxAP
KICK
R7
R4 R2
RxD
VDDA
CD
R16
AREF
TxD
R14 R15
U2
RTS
CS
CDREF
NCN5193
μC
DATA
SCLK
TxA
HART &
4 – 20 mA OUT
S
VDDA
DAC
CLK1
CLK2
XOUT
XIN
JUMP
DACREF
TEST2
TEST1
3.6864 MHz
CBIAS
VSS
MODE
C7
C8
U1
R13
XT1
Figure 2. Application Diagram NCN5193
Table 7. TYPICAL BILL OF MATERIALS
Reference Designator
Value (Typical)
−
Tolerance
−
Manufacturer
ON Semiconductor
ON Semiconductor
Part Number
U1
U2
NCN5193
LM285
−
−
R1, R2
R3, R5
R4
1.5M
1%
806k
1%
1.3M
1%
R6
174k
1%
R7
2.2M
1%
R8, R9
R11
422k
1%
240k
1%
R12, R15, R10
R13
200k
1%
120k
1%
R14, R16
C1
14k7
1%
1 nF
5%
C2
470 pF
200 pF
220 pF
20 pF
330 pF
18 pF
3.6864 MHz
5%
C3
5%
C4
5%
C5
5%
C6
5%
C7, C8
XT1
10%
100 ppm
Raltron
AS−3.6864−18
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5
NCN5193
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SCLK
DATA
JUMP
RESET
TxD
RTS
TEST2
TEST1
VSS
KICK
CS
NCN5193
VSS
XIN
TxA
XOUT
AREF
Figure 3. Pin Out NCN5193 in 32-pin NQFP (top view)
Table 8. PIN OUT SUMMARY 32−PIN NQFP
Pin No.
1
Signal Name
SCLK
DATA
JUMP
KICK
Type
Input
Pin Description
SPI Serial Clock
SPI Serial Data
2
Input
3
Input
Sigma−Delta Modulator Alarm condition value
Watchdog kick
4
Input
5
CS
Input
SPI Serial Chip Select
6
VSS
Ground
Output
Input
Ground
7
TxA
Transmit Data Modulator output
Analog reference voltage
8
AREF
CDREF
CBIAS
VPOR
RxAN
VDDA
RxAP
RxAF
RxAFI
XOUT
XIN
9
Input
Carrier detect reference voltage
Comparator bias current
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
−
Output
Input
POR measurement point
Input
Receive filter amplifier negative terminal
Analog supply voltage
Power
Input
Receive filter amplifier positive terminal
Analog receive filter output
Analog receive comparator input
Crystal oscillator output
Output
Input
Output
Input
Crystal oscillator input
VSS
Ground
Input
Ground
TEST1
TEST2
RTSB
TxD
Test pin. Tie to GND
Input
Test pin. Tie to VDD
Input
Request to send
Input
Input transmit data, transmit HART data stream from microcontroller
Reset all digital logic when low
Received demodulated HART data to microcontroller
Carrier detect output
RESETB
RxD
Open Drain
Output
Output
Input
CD
MODE
DACREF
DAC
Mode pin to select external or internal oscillator
Sigma−Delta Modulator Reference Voltage
Sigma−Delta Modulator Output
Digital supply voltage
Input
Output
Power
Output
Output
Ground
VDD
CLK1
CLK2
EP
Programmable Clock Output 1
Programmable Clock Output 2
Exposed pad. Connect to GND
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NCN5193
Table 9. PIN DESCRIPTIONS
Symbol
AREF
Pin Name
Description
Analog reference voltage
Carrier detect reference voltage
Receiver Reference Voltage. See Table 2.
CDREF
Carrier Detect Reference voltage. The value should be 80 mV below AREF to set the
carrier detection to a nominal of 100 mV
.
p−p
RESETB
RTSB
Reset digital logic
Request to send
When at logic low (V ) this input holds all the digital logic in reset. During normal
SS
operation RESETB should be at V
.
DD
Active−low input selects the operation of the modulator. TxA is enabled when this
signal is low. This signal must be held high during power−up.
RxAP
Analog filter amplifier positive
terminal
Positive terminal of the receive filter. For a reference implementation of the receive
filter see Figure 2
RxAN
Analog filter amplifier positive
terminal
Negative terminal of the receive filter. For a reference implementation of the receive
filter see Figure 2
RxAFI
TxD
Analog receive comparator input
Digital transmit input
Positive input of the carrier detect comparator and the receiver filter comparator.
Input to the modulator accepts digital data in NRZ form. When TxD is low, the modu-
lator output frequency is 2200 Hz. When TxD is high, the modulator output frequency
is 1200 Hz.
XIN
Oscillator input
Oscillator output
Input to the internal oscillator must be connected to a parallel mode ceramic resonator
when using the internal oscillator or grounded when using an external clock signal.
XOUT
Output from the internal oscillator must be connected to an external clock signal or to
a parallel mode ceramic resonator when using the internal oscillator.
CLK1
CLK2
CBIAS
Programmable Clock Output
Programmable Clock Output
Comparator bias current
Output signal derived from oscillator output, frequency division set by internal register.
Output signal derived from oscillator output, frequency division set by internal register.
Connection to the external bias resistor. R
should be selected such that AREF /
BIAS
R
= 10 mA 5%
BIAS
CD
Carrier detect output
Output goes high when a valid input is recognized on RxA. If the received signal is
greater than the threshold specified on CDREF for four cycles of the RxA signal, the
valid input is recognized.
RxAF
RxD
Analog receive filter output
Digital receive output
The output of the three pole high pass receive data filter
Signal outputs the digital receive data. When the received signal (RxA) is 1200 Hz,
RxD outputs logic high. When the received signal (RxA) is 2200 Hz, RxD outputs logic
low. The HART receive data stream is only active if Carrier Detect (CD) is high.
MODE
TxA
Digital input
Selects the clock source. Connecting this pin to VDD disables the internal oscillator.
The chip then requires an external clock source. Connecting this pin to VSS enables
the internal oscillator to drive the external crystal or ceramic resonator
Analog transmit output
Transmit Data Modulator Output. A trapezoidal shaped waveform with a frequency of
1200 Hz or 2200 Hz corresponding to a data value of 1 or 0 respectively applied to
TxD. TxA is active when RTSB is low. TxA equals 0.5 V when RTSB is high.
SCLK
DATA
CS
SPI bus clock line
SPI bus data line
SPI bus chip select
Serial communication clock line
Serial communication data line.
Serial communication chip select line. Pulled high by microcontroller while a frame is
transmitted.
JUMP
DAC Alarm value
When a problem is detected, such as a clock failure or the watchdog going off, the DAC
will jump to VSS or DACREF, depending on whether this pin is connected to VSS or
VDD respectively.
DACREF DAC Reference
This is the high value of the output and can be connected to any voltage between AREF
and VDD.
DAC
DAC Output
Output of a 17 bit Sigma−Delta Modulator
KICK
Watchdog Kick
Periodically a pulse should be provided to reset the watchdog. This can be configured in
internal registers for an internal 1.8kHz signal, or to an external signal provided to this pin.
VPOR
POR Input
Input to the POR comparator. The voltage on this pin is compared with AREF. An ex-
ternal resistor divider should divide the supply voltage to this pin.
VDD
Digital power
Analog supply voltage
Ground
Power for the digital modem circuitry
Power for the analog modem circuitry
Digital ground
VDDA
VSS
VSSA
Analog ground
Analog ground
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NCN5193
Functional Description
The Numeric Controlled Oscillator (NCO) works in a
phase continuous mode preventing abrupt phase shifts when
switching between mark and space frequency. The control
signal “Request To Send” (RTSB) enables the NCO. When
RTSB is logic low the modulator is active and NCN5193 is
in transmit mode. When RTSB is logic high the modulator
is disabled and NCN5193 is in receive mode.
The NCN5193 is a single-chip modem for use in Highway
Addressable Remote Transducer (HART) field instruments
and masters. The modem IC contains a transmit data
modulator with signal shaper, carrier detect circuitry, an
analog receiver, demodulator circuitry and an oscillator, as
shown in the block diagram in Figure 1.
The modulator accepts digital data at its digital input TxD
and generates a trapezoidal shaped FSK modulated signal at
the analog output TxA. A digital “1” or mark is represented
with a frequency of 1200 Hz. A digital “0” or space is
represented with a frequency of 2200 Hz. The used bit rate
is 1200 baud.
The digital outputs of the NCO are shaped in the Wave
Shaper block to a trapezoidal signal. This circuit controls the
rising and falling edge to be inside the standard HART
waveshape limits. Figure 6 shows the transmit-signal forms
captured at TxA for mark and space frequency. The slew
rates are SR = 1860 V/s at the mark frequency and SR =
m
s
The demodulator receives the FSK signal at its analog
input, filters it with a band-pass filter and generates 2 digital
signals: RxD: Received Data and CD: Carrier Detect. At the
digital output RxD the original modulated signal is received.
CD outputs the Carrier Detect signal. It goes logic high if the
received signal is above 100 mVpp during 4 consecutive
carrier periods.
3300 V/s at the space frequency. For AREF = 1.235 V, TxA
will have a voltage swing from approximately 0.25 to
0.75 V
.
DC
VTxA
“1” = Mark; fm =1.2 kHz
0.5 V
0.5 V
The oscillator provides the modem with a stable time base
using either a simple external resonator or an external clock
source.
SRm = 1860 V/s
t (ms)
0
1
2
Detailed Description
VTxA
“0” = Space; fs =2.2 kHz
Modulator
The modulator accepts digital data in NRZ form at the
TxD input and generates the FSK modulated signal at the
TxA output.
0.5 V
0.5 V
t (ms)
SRs = 3300 V/s
1
0
2
KVDE20110408
Numeric
Controlled
Oscillator
TxA
Sine
Shaper
TxD
RTS
FSK_OUT
Figure 6. Modulator shaped output signal for Mark
and Space frequency at TxA pin.
MODULATOR
Demodulator
PC20101117.1
The demodulator accepts a FSK signal at the RxA input
and reconstructs the original modulated signal at the RxD
output. Figure 7 illustrates the demodulation process.
Figure 4. Modulator Block Diagram
A logic “1” or mark is represented by a frequency f
1200 Hz. A logic “0”or space is represented by a frequency
f = 2200 Hz.
=
m
s
FSK_IN
“1” = Mark
1.2 kHz
“0” = Space
2.2 kHz
RxD
LSB
MSB
D7
IDLE (mark)
IDLE (mark)
Stop
tBIT
Start
D0
“1”
D1
“0”
D2
“1”
D3
D4
“0”
D5
“1”
D6
“0”
Par
“0”
“0”
“0”
“1”
t
tBIT
8
data bits
PC20101013.4
Figure 7. Modulation Timing
This HART bit stream follows a standard 11-bit UART
frame with Start, Stop, 8 Data – and 1 Parity bit (odd). The
communication speed is 1200 baud.
tBIT
=
ms
tBIT = 833 ms
833
Receive Filter and Comparator
KVDE20110407.5
The received FSK signal first is filtered using a band-pass
filter build around the low noise receiver operational
amplifier. This filter blocks interferences outside the HART
signal band.
Figure 5. Modulation Timing
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NCN5193
C4 R6
C6
R5
C5
R9
R8
RxAFI
RxAF
RxAN
RxAP
R7
AREF
R3 C3 C2 C1
HART IN
R4 R2
R1
Rx Comp
Filter Amplifier
DEMODULATOR
1.235V
Figure 8. Demodulator Receive Filter and Signal Comparator
Carrier Detect Circuitry
The filter output is fed into the Rx comparator. The
threshold value equals the analog ground making the
comparator to toggle on every zero crossing of the filtered
FSK signal. The maximum demodulator jitter is 12% of one
bit given the input frequencies are within the HART
specifications, a clock frequency of 460.8 kHz ( 1.0 %) and
zero input (RxA) asymmetry.
Low HART input signal levels increases the risk for the
generation of bit errors. Therefore the minimum signal
amplitude is set to 80−120 mVpp. If the received signal is
below this level the demodulator is disabled.
This level detection is done in the Carrier Detector. The
output of the demodulator is qualified with the carrier detect
signal (CD), therefore, only RxA signals large enough to be
detected (100 mV typically) by the carrier detect circuit
p-p
produce received serial data at RxD.
FILTERED
HART IN
RxAFI
Demodulator
Logic
RxD
CD
Rx Comp
AREF
1.235 VDC
Carrier Detect
Counter
CDREF
VAREF – 80 mV
Carrier Comp
DEMODULATOR
Figure 9. Demodulator Carrier and Signal Comparator
The carrier detect comparator shown in Figure 9 generates
logic low output if the RxAFI voltage is below CDREF. The
comparator output is fed into a carrier detect block. The
carrier detect block drives the carrier detect output pin CD
high if RTSB is high and four consecutive pulses out of the
comparator have arrived. CD stays high as long as RTSB is
high and the next comparator pulse is received in less than
2.5 ms. Once CD goes inactive, it takes four consecutive
pulses out of the comparator to assert CD again. Four
consecutive pulses amount to 3.33 ms when the received
signal is 1200 Hz and to 1.82 ms when the received signal
is 2200 HZ. The difference between RxD and RxD_ENH is
evident when CD is low: RxD is then also low, while
RxD_ENH is then high. When CD is high, RxD and
RxD_ENH have the same output.
Miscellaneous Analog Circuitry
Voltage References
The NCN5193 requires two voltage references, AREF
and CDREF. AREF sets the DC operating point of the
internal operational amplifiers and is the reference for the
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NCN5193
Rx comparator. The ON Semiconductor LM285D 1.235 V
reference is recommended.
The level at which CD (Carrier Detect) becomes active is
determined by the DC voltage difference (CDREF - AREF).
Selecting a voltage difference of 80 mV will set the carrier
resonator. Typically, capacitors in the range of 10 pF to
470 pF are used. Additionally, a resistor may be required
between XOUT and the crystal terminal, depending on
manufacturer recommendation.
detect to a nominal 100 mV
.
p-p
Bias Current Resistor
The NCN5193 requires a bias current resistor R
connected between CBIAS and V . The bias current
Crystal
Oscillator
to be
BIAS
SS
controls the operating parameters of the internal operational
amplifiers and comparators and should be set to 10 mA.
PC20101118.5
XIN
CX
XOUT
CX
460.8 kHz
BIAS
AREF
OPA
Figure 11. Crystal Oscillator
External Clock Option
It may be desirable to use an external clock as shown in
Figure 12 rather than the internal oscillator. In addition, the
NCN5193 consumes less current when an external clock is
used. Minimum current consumption occurs with the clock
CBIAS
PC20101118 .4
RBIAS
connected to XOUT and XIN connected to V
.
SS
Figure 10. Bias Circuit
The value of the bias current resistor is determined by the
reference voltage AREF and the following formula:
Crystal
Oscillator
AREF
RBIAS
+
10 mA
The recommended bias current resistor is 120 KW when
AREF is equal to 1.235 V.
PC20101118 .6
XIN
XOUT
460.8 kHz
Oscillator
Figure 12. Oscillator with External Clock
The clock signal used by NCN5193 can either be
460.8 kHz, 921.6 kHz, 1.8432 MHz or 3.6864 MHz. This
can be provided by an external clock or a resonator or crystal
connected to the internal oscillator. This is selected by
connecting pin 27 to VDD (for external oscillator) or VSS
(for internal oscillator). The correct divider value must be
chosen so that the internal system clock is always 460.8 kHz.
This divider value can be set in the Clock Configuration
Register (CCR), bits 1−0. In the CCR, divider values can
also be chosen for the CLK1 and CLK2 outputs. These
values can be freely chosen and do not affect operation of the
HART transceiver.
Reset
The NCN5193 modem includes a Power on Reset block.
An external resistor division of the supply voltage is
required, and should be tied to pin VPOR. This pin is
attached to an internal comparator, and is compared to the
AREF voltage. When this comparator trips, the RESETB
pin will be pulled low and the IC will reset. After VPOR
returns to a valid level, the RESETB pin will be held low for
at least an additional 35 ms (may be longer depending on
clock frequency). The RESETB pin will also be pulled low
when a failure is detected by the watchdog timer. When the
microcontroller fails to provide a periodical kick signal,
either by a pulse on the kick pin or by an update to the
sigma−delta register (configurable in the GCR), the
watchdog will pull down the RESETB pin for 140 ms. A kick
signal should be provided to the IC at least every 53 ms. The
watchdog timer can also guard against system clock failures
if bit 2 of the GCR is set. In this case, the RESETB pin will
also be pulled low when the system clock frequency is
outside of 0.5x − 2x the nominal frequency (460.8 kHz).
Internal Oscillator Option
The oscillator cell will function with a 460.8 kHz,
921.6 kHz, 1.8432 MHz or 3.6864 MHz crystal or ceramic
resonator. A parallel resonant ceramic resonator can be
connected between XIN and XOUT. Figure 11 illustrates the
crystal option for clock generation using a 460.8 kHz ( 1%
tolerance) parallel resonant crystal and two tuning
capacitors C . The actual values of the capacitors may
depend on the recommendations of the manufacturer of the
x
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10
NCN5193
CS
POR
AREF
OPA
VDD
SCLK
DATA
b7 b6 b5 b4 b3 b2 b1 b0
VPOR
Figure 14. SPI Frame
KVDE20110408 .1
Figure 13. Power on Reset Block
Byte 0
7 6 5 4 3 2 1 0
Byte 1
7 6 5 4 3 2 1 0
Byte 2
7 6 5 4 3 2 1 0
Byte 3
0
1
0
Address
0
W15−W8 for Reg 1, 2, 3
W7−W0 for Reg 1, 2, 3
7 6 5 4 3 2 1 0
W23−W16 for Reg A
7 6 5 4 3 2 1 0
W15−W8 for Reg A
7 6 5 4 3 2 1 0
W7−W0 for Reg A
Figure 15. Register Write Format
SPI Communication
Once the data is shifted in, CS should go low no sooner than
one clock cycle after the last rising edge of the last byte of
SCLK. To write to a register, first a command byte must be
sent which includes the register address (as shown in Figure
15), followed by 2 bytes (for GCR, CCR, and ACR) or 3
bytes (for SDR) of data. When writing data to the GCR,
CCR, or ACR registers, the first byte must be the bitwise
inverse of the configuration data in the second byte.
The SPI bus on the NCN5193 is made up of three signals;
DATA, SCLK, and CS operating in SPI mode 1 (CPOL = 0,
CPHA = 1, as shown in Figure 14).
CS should first go high at least one clock cycle before the
other signals change. One clock cycle is 2.17 ms at a master
clock frequency of 460.8 kHz.
SCLK can begin to clock in DATA serially to the chip on
the falling edge of SCLK. SCLK should have a maximum
frequency of 460.8 kHz. The format of the data should be
most significant bit first.
DATA is shifted into the chip on the falling edge of SCLK,
and thus for correct operation DATA should change only on
the rising edge of SCLK. The first bit shifted in is the MSB.
Internal Registers
The NCN5193 has four registers to setup its internal
operation. In Tables 10 to 16 an explanation of their usage
is given, together with their reset values.
Table 10. GENERAL CONFIGURATION REGISTER (GCR)
Address
0x01
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
1
Bit 1
Bit 0
Reset
Data
1
-
0
-
0
-
0
-
0
1
RXD_IDLE
WDT_CLK
WDT_KICK
The general configuration register is used to set the RxD idle state, enable or disable the monitoring of the system clock and
setting the watchdog timer kick source. A write to this register should always be preceded with an inverted value to the shadow
register.
Table 11. GENERAL CONFIGURATION REGISTER PARAMETERS
Parameter
Value
Low
Description
Info
RXD_IDLE
0
1
Sets the idle state for the RxD pin (when CD is low)
High
Enable
WDT_CLK
WDT_KICK
0
Disable/Enable monitoring of the clock frequency by the watchdog timer.
1
Disable
00
01
10
11
Disable
Kick signal to watchdog timer is disabled
External
Sigma-Delta
Watchdog kick source is a pulse on the KICK pin
Watchdog kick source is an write to the Sigma-Delta Data register (SDR)
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11
NCN5193
Table 12. CLOCK CONFIGURATION REGISTER (CCR)
Address
0x02
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
Reset
Data
1
1
1
1
1
1
CLK2_DIV
CLK1_DIV
SYSCLK_DIV
The clock configuration register is used to set the correct division ratios for both clock outputs and the system clock. A write
to this register should always be preceded with an inverted value to the shadow register.
Table 13. CLOCK CONFIGURATION REGISTER PARAMETERS
Parameter
Value
Divide by 1
Description
Info
CLK2_DIV
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
00
Set the clock division value for clock output 2 (CLK2) with regard to the
oscillator frequency.
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 8
Divide by 16
Divide by 32
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 8
Divide by 16
Divide by 32
Divide by 1
Divide by 2
Divide by 4
Divide by 8
CLK1_DIV
Set the clock division value for clock output 1 (CLK1) with regard to the
oscillator frequency.
SYSCLK_DIV
Set the clock division value for the system clock with regard to the oscil-
lator frequency. These bits must be set so the system clock is 460.8 kHz
01
10
11
Table 14. ANALOG CONFIGURATION REGISTER – ACR
General Configuration Register (GCR)
Address
0x03
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
1
1
1
1
1
1
0
1
Data MOD_EN RXAMP_EN RXCMP_EN CDCMP_EN TXAMP_EN MODDAC_EN WDOSC_EN SDDAC_EN
The analog configuration register is used to enable or disable various analog blocks. A write to this register should always
be preceded with an inverted value to the shadow register.
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12
NCN5193
Table 15. ANALOG CONFIGURATION REGISTER PARAMETERS
Parameter
MOD_EN
Value
Enable
Description
Disable/Enable the modulator/demodulator
Info
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
RXAMP_EN
RXCMP_EN
CDCMP_EN
TXAMP_EN
MODDAC_EN
WDOSC_EN
SDDAC_EN
Disable/Enable the receive filter opamp
Disable/Enable the receive comparator
Disable/Enable the carrier detect comparator
Disable/Enable the transmit output amplifier
Disable/Enable the DAC used to provide the waveshaping to the modulator
Disable/Enable the watchdog timer oscillator
Disable/Enable the sigma-delta DAC
Table 16. SIGMA-DELTA DAC REGISTER – SDR
General Configuration Register (GCR)
Address
0x0A
Bit 23:16
0x00
Bit 15:8
0x00
Bit 7
0
Bit 6:0
0x00
-
Reset
Data
Data 16:9
Data 8:1
Data 0
The sigma-delta register is used to update the output value
of the 17-bit sigma delta modulator. The sigma-delta
modulator is disabled at reset and must be enabled in the
ACR first before the value in the SDR will appear at the
sigma-delta output.
how to create a current loop slave transmitter, see
application notes on the ON Semiconductor website. The
DAC output will switch between 0 V and the voltage
provided to DACREF. To achieve maximum accuracy, the
DACREF voltage should be kept stable, so that power
supply variations are not visible in the DAC output. The
Sigma−Delta modulator output can be set through the Sigma
Delta Register (SDR). When a clock failure is detected,
using an internal oscillator, the DAC output will jump to the
level set by the JUMP pin, until the IC is reset or a rising
flank is detected on KICK.
Sigma Delta DAC
The NCN5193 Modem has an integrated Sigma−Delta
Modulator for use in a current loop slave transmitter.
Through this DAC, an analog value can be set and
transmitted across the current loop. For more information on
Ordering Information
The NCN5193 is available in a 32−pin no lead quad flat pack (NQFP). Use the following part numbers when ordering.
Contact your local sales representative for more information: www.onsemi.com.
Table 17. ORDERING INFORMATION
†
Part Number
NCN5193MNTWG
Temperature Range
Package
32−pin NQFP
Shipping
−40°C to +85°C (Industrial)
1000 / Tape & Reel
Green/RoHS compliant
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
NCN5193
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
A
B
D
NOTES:
L
L
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
L1
LOCATION
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
A
MILLIMETERS
DIM
A
A1
A3
b
D
D2
E
MIN
0.80
−−−
MAX
1.00
0.05
0.15
C
0.20 REF
0.15
C
EXPOSED Cu
MOLD CMPD
0.18
2.95
0.30
TOP VIEW
5.00 BSC
3.25
5.00 BSC
DETAIL B
E2
2.95
3.25
(A3)
A1
0.10
C
C
e
0.50 BSC
DETAIL B
ALTERNATE
CONSTRUCTION
K
L
L1
0.20
0.30
−−−
−−−
0.50
0.15
0.08
SEATING
PLANE
C
NOTE 4
SIDE VIEW
RECOMMENDED
DETAIL A
32X L
SOLDERING FOOTPRINT*
K
D2
9
5.30
32X
0.63
17
8
3.35
E2
1
3.35 5.30
32
25
32X
b
e
M
M
0.10
C A B
e/2
NOTE 3
0.05
C
BOTTOM VIEW
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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NCN5193/D
◊
相关型号:
NCN6001MUR2G
SPECIALTY INTERFACE CIRCUIT, PBCC20, 6 X 5 MM, 0.80 MM PITCH, LEAD FREE, LLGA-20
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