NCP10672BD060R2G_技术文档

NCP10670B, NCP10671B,

NCP10672B

High-Voltage Switcher for

Low Power Offline SMPS

The NCP1067X products integrate a fixed frequency current mode

controller with a 700 V MOSFET. Available in a SOIC−7 package, the

NCP1067X offer a high level of integration, including soft−start,

frequency−jittering, short−circuit protection, skip−cycle, ramp

compensation, and a Dynamic Self−Supply (eliminating the need for

an auxiliary winding).

During nominal load operation, the NCP1067X switches at one of

the available frequencies (60 or 100 kHz). When the output power

demand diminishes, the IC automatically enters into a skip mode to

reduce the standby consumption down.

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SOIC8

CASE 751EV

MARKING DIAGRAM

Protection features include: a timer to detect an overload or a

short−circuit event, Overvoltage Protection with auto−recovery.

For improved standby performance, the connection of an auxiliary

winding or supplying the IC from the output, stops the DSS operation

and helps to reduce input power consumption below 25 mW at high

line.

8

P1067xy

ALYW

G

1

NCP1067x can be seamlessly used both in non−isolated and in

isolated topologies.

P1067 = Specific Device Code

x

y

A

L

Y

G

= Current Limit (0, 1, 2)

= Frequency (060, 100)

= Assembly Location

= Wafer Lot

= Year

= Pb−Free Package

Features

• Built−in 700 V MOSFET with R

12 ꢀ (NCP10672)

of 34 ꢀ (NCP10670/1) and

DS(on)

• Large Creepage Distance Between High−Voltage Pins

• Current−Mode Fixed Frequency Operation – 60 or 100 kHz

• Fixed Ramp Compensation

PIN CONNECTION

• Direct Feedback Connection for Non−isolated Converter

• Skip−Cycle Operation at Low Peak Currents Only

• Dynamic Self−Supply: No Need for an Auxiliary Winding

VCC

FB

COMP

GND

• Internal 4 ms Soft−Start

DRAIN

• Auto−Recovery Output Short Circuit Protection with Timer−Based

Detection

SOIC−7

• Auto−Recovery Overvoltage Protection with Auxiliary Winding

Operation

ORDERING INFORMATION

See detailed ordering and shipping information on page 23 of

this data sheet.

• Frequency Jittering for Better EMI Signature

• No Load Input Consumption < 25 mW

• These Devices are Pb−Free and are RoHS Compliant

Applications

• Auxiliary / Standby Isolated and Non−Isolated Power Supplies

• Power Meter SMPS

• Wide Vin Low Power Industrial SMPS

1

Publication Order Number:

February, 2019 − Rev. 0

NCP10670/D

NCP10670B, NCP10671B, NCP10672B

Table 1. PRODUCTS INFOS & INDICATIVE MAXIMUM OUTPUT POWER

230 Vac +15%

85 − 265 Vac

Adapter

OpenFrame

Adapter

OpenFrame

1.5 W

Product

R

I

IPK(0)

DS(on)

NCP10670 60 kHz

NCP10671 60 kHz

NCP10672 100 kHz

34

ꢀ

100 mA

250 mA

780 mA

1.1 W

2.7 W

6.2 W

2.7 W

0.6 W

1.5 W

3.3 W

34

12

6.7 W

3.7 W

15.5 W

7.8 W

1. Informative values only, with T

= 25°C, T

= 100°C, Self supply via Auxiliary winding and circuit mounted on minimum copper area

amb

case

as recommended.

Table 2. SELECTION TABLE

Device

Frequency

60 kHz

R

I

Package Type

DS(on)

IPK(0)

NCP10670

34

100 mA

250 mA

780 mA

SOIC−7

(Pb−Free)

NCP10670

100 kHz

60 kHz

34

12

NCP10671

100 kHz

60 kHz

NCP10672

100 kHz

Figure 1. Typical Non−Isolated Application (Buck Converter)

Figure 2. Typical Isolated Application (Flyback Converter)

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2

NCP10670B, NCP10671B, NCP10672B

PIN DESCRIPTION

Pin No.

SOIC−7

Name

Function

Description

1

V

CC

Powers the internal

circuitry

This pin is connected to an external capacitor.

The V includes an auto−recovery over voltage protection.

CC

2

Comp

Compensation

The error amplifier output is available on this pin. The network connected

between this pin and ground adjusts the regulation loop bandwidth. Also, by

connecting an opto−coupler to this pin, the peak current set point is adjusted

accordingly to the output power demand.

3

4

This missing pin ensures adequate creepage distance

The internal drain MOSFET connection

Drain

GND

FB

Drain connection

The IC Ground

5−7

8

Feedback signal input

This is the inverting input of the trans conductance error amplifier. It is normally

connected to the switching power supply output through a resistor divider.

Table 3. TYPICAL APPLICATION

Non Isolated Buck

• If the output voltage is above 9.0 V

typ. (between V

OVP

output via D2

level and

CC(on)

V

level) VCC is supplied from

• If the output voltage is below 9.0 V,

D2 is redundant, the IC is supplied

from DSS

• Direct feedback, resistive divider

formed by R3, R4 sets output

voltage

• If the output voltage is above 9.0 V

typ. (between V

OVP

output via D3

level and

CC(on)

V

level) VCC is supplied from

• If the output voltage is below 9.0 V,

D3 is redundant, the IC is supplied

from DSS

• Optocoupler feedback, output

voltage is set by D4

Non Isolated Buck−Boost (Invert)

• If the output voltage is above 9.0 V

typ. between V

OVP

output via D2

level and

CC(on)

V

level, VCC is supplied from

• If the output voltage is below 9.0 V,

D2 is redundant, the IC is supplied

from DSS

• Direct feedback, resistive divider

formed by R3, R4 sets output

voltage

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3

NCP10670B, NCP10671B, NCP10672B

Table 3. TYPICAL APPLICATION

Non Isolated Flyback

• If the output voltage is above 9.0 V

typ. between V level and

CC(on)

V

level –VCC supplied from

OVP

output via D4

• If the output voltage is below 9.0 V,

D4 is redundant, the IC is supplied

from DSS

• Resistive divider formed by R2, R3

sets output voltage

Isolated Flyback

• VCC supplied from auxiliary

winding

• Optocoupler feedback, resistive

divider formed by R6, R7 sets

output voltage

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4

NCP10670B, NCP10671B, NCP10672B

V

cc

DRAIN

UVLO

Reset

V_dd

80−ꢁ s Filter

V_CCOVP

VCC

Management

SCP

t_SCP

V_OVP

S

R

I_pflag

Q

t_recovery

UVLO

Jittering

OSC

OFF

TSD

VCC

V_COMP(REF)

R_COMP(up)

Sawtooth

S

Sawtooth

Q

R

I_COMPskip

SKIP

Ramp

compensation

→

SKIP = ”1”

Shut down some

GND

blocks to reduce consumption

LEB

I

pflag

FB/COMP

Processing

COMP

I_COMPfault

I_COMPto CS setpoint

Reset

Soft−Start

I_Freeze

I

IPK(0)

I_FB

Reset SS as recoving from

SCP, TSD, VCC OVP or UVLO

FB

Figure 3. Simplified Internal Circuit Architecture

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5

NCP10670B, NCP10671B, NCP10672B

MAXIMUM RATINGS (All voltages related to GND terminal)

Symbol Parameter

Power supply voltage, V pin, continuous voltage

Rating

−0.3 to 20

−0.3 to 10

−0.3 to 700

10

Units

V

CC

Vinmax

BVdss

Voltage on all pins, except Drain and V pin

V

CC

Drain voltage

V

I

Maximum Current into V pin

mA

CC

I

Drain Current Peak during Transformer Saturation (T = 150°C):

DS(PK)

J

NCP10670

NCP10671

NCP10672

300

850

mA

Drain Current Peak during Transformer Saturation (T = 125°C):

J

NCP10670

NCP10671

NCP10672

335

950

mA

Drain Current Peak during Transformer Saturation (T = 25°C):

J

NCP10670

NCP10671

NCP10672

520

1500

mA

2

R

Thermal Resistance Junction−to−Air – NCP10670(1) SOIC7 with 200 mm of 35−ꢁ copper area

116

°C/W

°C

θ

J−A

2

Thermal Resistance Junction−to−Air – NCP10672 SOIC7 with 200 mm of 35−ꢁ copper area

102

T

JMAX

Maximum Junction Temperature

150

Storage Temperature Range

−60 to +150

°C

HBM

CDM

Human Body Model ESD Capability per JEDEC JESD22−A114F

Charged−Device Model ESD Capability per JEDEC JESD22−C101E

2

1

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

i _D(t)

< 1.5 x I _{DS(PK )}

< t_LEB

I _{DS(PK )}

Transformer

Saturation

t

Figure 4. Spike Limits

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6

NCP10670B, NCP10671B, NCP10672B

ELECTRICAL CHARACTERISTICS

(Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 14 V unless otherwise noted)

Symbol

Rating

Min

Typ

Max

Unit

SUPPLY SECTION AND V MANAGEMENT

CC

V

increasing level at which the switcher starts operation

decreasing level at which the HV current source restarts

decreasing level at which the switcher stops operation (UVLO)

1

8.4

7.0

6.7

9.0

7.5

7.0

9.5

7.8

7.2

V

CC(on)

CC

V

CC(min)

V

CC(off)

I

Internal IC consumption, NCP10670 switching at 60 kHz

Internal IC consumption, NCP10670 switching at 100 kHz

Internal IC consumption, NCP10671 switching at 60 kHz

Internal IC consumption, NCP10671 switching at 100 kHz

Internal IC consumption, NCP10672 switching at 60 kHz

Internal IC consumption, NCP10672 switching at 100 kHz

−

0.84

0.88

0.84

0.88

0.91

1.00

1.05

1.10

1.05

1.10

1.15

1.25

mA

CC1

I

Internal IC consumption, COMP is 0 V (No switching on MOSFET)

1

4

−

340

−

ꢁ

A

CCskip

POWER SWITCH CIRCUIT

R

Power Switch Circuit on−state resistance

NCP10670, NCP10671 (Id = 50 mA)

Tj = 25°C

DS(on)

−

34

65

41

72

ꢀ

Tj = 125°C

NCP10672 (Id = 50 mA)

Tj = 25°C

−

12

22

14

24

ꢀ

Tj = 125°C

BV

Power Switch Circuit & Startup breakdown voltage

4

700

−

V

DSS

(ID

= 120 ꢁ A, Tj = 25°C)

(off)

I

Power Switch & Startup breakdown voltage off−state leakage current

Tj = 125°C (Vds = 700 V)

Tj = 25°C (Vds = 700 V)

DSS(off)

−

7

1

−

ꢁ A

Switching characteristics (R = 50 ꢀ, V set for I

Turn−on time (90% − 10%)

Turn−off time (10% − 90%)

= 0.7 x Ilim)

4

L

DS

drain

t

−

20

10

−

ns

r

f

t

Minimum on time

NCP10670

NCP10671

NCP10672

on(min)

−

200

230

−

ns

INTERNAL START−UP CURRENT SOURCE

I

High−voltage current source, V = V

– 200 mV

4

1

4

−

8

12

−

mA

V

start1

start2

CC

CC(on)

High−voltage current source, V = 0 V

0.4

1.2

−

CC

V

VCC Transient level for Istart1 to Istart2 toggling point

Minimum startup voltage, V = 0 V

−

CCTH

V

22

V

start(min)

CC

CURRENT COMPARATOR

I

Maximum internal current setpoint at 50% duty cycle

FB = 2 V, Tj = 25°C

NCP10670

NCP10671

NCP10672

IPK

−

83

208

650

−

mA

I

Maximum internal current setpoint at beginning of switching cycle

FB = 2 V, Tj = 25°C

NCP10670

NCP10671

NCP10672

IPK(0)

−

85

223

702

100

250

780

115

277

858

mA

I

Final switch current with a primary slope of 200 mA/ꢁ s,

SW

IPKSW

F

= 60 kHz (Note 3)

NCP10670

NCP10671

NCP10672

−

120

258

740

−

mA

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7

NCP10670B, NCP10671B, NCP10672B

ELECTRICAL CHARACTERISTICS

(Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 14 V unless otherwise noted) (continued)

Symbol

Rating

Min

Typ

Max

Unit

CURRENT COMPARATOR

I

Final switch current with a primary slope of 200 mA/ꢁ s,

= 100 kHz (Note 3)

IPKSW

F

SW

NCP10670

NCP10671

NCP10672

−

120

250

710

−

mA

t

Soft−start duration (guaranteed by design)

−

4

−

ms

ns

SS

t

Propagation delay from current detection to drain OFF state

70

prop

t

Leading Edge Blanking Duration

NCP10670

LEB

−

130

160

−

ns

NCP10671

NCP10672

INTERNAL OSCILLATOR

f

Oscillation frequency, 60 kHz version, Tj = 25°C (Note 4)

Oscillation frequency, 100 kHz version, Tj = 25°C (Note 4)

−

54

90

−

60

100

6

66

110

−

kHz

%

OSC

f

Frequency jittering in percentage of f

Jittering swing frequency

jitter

OSC

f

−

300

66

−

Hz

%

swing

D

Maximum duty−cycle

62

72

max

ERROR AMPLIFIER SECTION

Voltage Feedback Input (V

V

REF

= 2.5 V)

COMP

8

2

8

3.2

−

3.3

3.4

−

V

ꢁ A

mS

ꢁ A

V

I

FB

Input Bias Current (V = 3.3 V)

1

FB

G

Transconductance

−

2

−

M

I

OTA maximum current capability (V > V )

OTAen

−

+150/−150

1.3

−

OTAlim

FB

V

OTAen

FB voltage to disable OTA

0.7

1.7

COMPENSATION SECTION

COMP current for which Fault is detected

I

2

−

−40

−44

−80

−

ꢁ A

COMPfault

I

COMP current for which internal current set−point is 100% (I

)

IPK(0)

COMP100%

I

COMP current for which internal current set−point is:

Freeze1, 2 or 3

COMPfreeze

I

(NCP10670/1/2)

V

Equivalent pull−up voltage in linear regulation range

2

−

2.7

−

V

COMP(REF)

(Guaranteed by design)

R

Equivalent feedback resistor in linear regulation range

(Guaranteed by design)

17.7

kꢀ

COMP(up)

SKIP CYCLE

I

The COMP pin current level to enter skip mode

2

−

−120

35

−

ꢁ A

mA

COMPskip

I

Internal minimum current setpoint (I

= I

) in NCP10670

) in NCP10671

) in NCP10672

Freeze1

Freeze2

Freeze3

COMP

COMPFreeze

92

270

RAMP COMPENSATION

S

a(60)

The internal ramp compensation @ 60 kHz:

NCP10670

NCP10671

NCP10672

−

2.8

8.4

15.6

−

mA/ꢁ s

S

a(100)

The internal ramp compensation @ 100 kHz:

NCP10670

NCP10671

NCP10672

−

4.7

14

26

−

mA/ꢁ s

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8

NCP10670B, NCP10671B, NCP10672B

ELECTRICAL CHARACTERISTICS

(Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 14 V unless otherwise noted) (continued)

Symbol

Rating

Min

Typ

Max

Unit

PROTECTIONS

t

Fault validation further to error flag assertion

OFF phase in fault mode

−

1

−

35

−

48

400

18.0

80

−

ms

V

SCP

t

recovery

V

CC

voltage at which the switcher stops pulsing

17.0

−

18.8

−

OVP

t

The filter of V OVP comparator

ꢁ

s

CC

TEMPERATURE MANAGEMENT

TSD Temperature shutdown (Guaranteed by design)

TSD Hysteresis in shutdown (Guaranteed by design)

−

150

163

20

−

°C

−

HYST

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The final switch current is: I

/ (V /L + S ) x V /L + V /L x t

, with S the built−in slope compensation, Vin the input voltage,

IPK(0)

in

P

a

in

P

in

P

prop

a

L

the primary inductor in a flyback, and t

the propagation delay..

P

prop

4. Oscillator frequency is measured with disabled jittering.

TYPICAL CHARACTERISTICS

V

CC(on)

CC(min)

9.10

9.05

9.00

8.95

8.90

8.85

8.80

7.48

7.46

7.44

7.42

7.40

7.38

7.36

7.34

7.32

7.30

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 5. V_CC(on)vs. Temperature

Figure 6. V_CC(min)vs. Temperature

I

V

DSS(off)

CC(off)

6.98

6.96

6.94

6.92

6.90

6.88

6.86

10

9

8

7

6

5

4

3

2

1

0

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 8. I_DSS(off)vs. Temperature

Temperature [5C]

Figure 7. V_CC(off)vs. Temperature

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9

NCP10670B, NCP10671B, NCP10672B

TYPICAL CHARACTERISTICS (continued)

I

CC1(10670_100k)

CC1(10670_60k)

0.89

0.88

0.87

0.86

0.85

0.84

0.83

0.82

0.89

0.87

0.85

0.83

0.81

0.79

0.77

0.75

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 9. I_{CC1 (10670_60k)}vs. Temperature

Temperature [5C]

Figure 10. I_{CC1 (NCP10670_100k)}vs. Temperature

I

CC1(10672_60k)

CC1(10672_100k)

0.92

0.91

0.90

0.89

0.88

0.87

0.86

0.85

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 12. I_{CC1 (10672_100k)}vs. Temperature

Temperature [5C]

Figure 11. I_{CC1 (10672_60k)}vs. Temperature

I

IPK(0)10670

IPK(0)10671

110

105

100

95

250

245

240

235

230

225

220

90

85

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 13. I_IPK(0)10670vs. Temperature

Temperature [5C]

Figure 14. I_IPK(0)10671vs. Temperature

I

IPK(0)10672

freeze10670

770

760

750

740

730

720

710

34.5

34.0

33.5

33.0

32.5

32.0

31.5

31.0

−40

−20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature [5C]

Figure 15. I_IPK(0)10672vs. Temperature

Figure 16. I_freeze10670vs. Temperature

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NCP10670B, NCP10671B, NCP10672B

TYPICAL CHARACTERISTICS (continued)

I

freeze10672

freeze10671

86

85

84

83

82

81

80

79

270

268

266

264

262

260

258

256

254

252

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 17. I_freeze10671vs. Temperature

Figure 18. I_freeze10672vs. Temperature

R

DS(on)10672

DS(on)10670/1

70

25

20

15

10

5

60

50

40

30

20

10

0

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 19. R_{DS(on)10670/1}vs. Temperature

Figure 20. R_DS(on)10672vs. Temperature

f

OSC100

OSC60

62

110

105

100

95

60

58

56

54

52

50

90

85

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 21. f_OSC60vs. Temperature

Figure 22. f_OSC100vs. Temperature

I

start2

start1

0.7

0.6

0.5

0.4

0.3

0.2

0.1

12

10

8

6

4

2

0

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 23. I_start1vs. Temperature

Figure 24. I_start2vs. Temperature

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NCP10670B, NCP10671B, NCP10672B

TYPICAL CHARACTERISTICS (continued)

t

D

max

recovery

440

435

430

425

420

415

410

66.4

66.3

66.2

66.1

66.0

65.9

65.8

65.7

65.6

−40

−20

0

20

40

60

80

100

120

−40

−20

0

20

40

60

80

100

120

Temperature [5C]

Figure 25. t_recoveryvs. Temperature

Figure 26. D_(max)vs. Temperature

V

OVP

t

SCP

18.2

18.1

18.0

17.9

17.8

17.7

17.6

17.5

17.4

54

53

52

51

50

−40

−20

0

20

40

60

80

100

−40

−20

0

20

40

60

80

100

Temperature [5C]

Figure 27. V_OVPvs. Temperature

Figure 28. t_SCPvs. Temperature

V

REF

OTAen

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.26

3.25

3.24

−40

−20

0

20

40

60

80

100

−40

−20

0

20

40

60

80

100

Temperature [5C]

Figure 29. V_OTAenvs. Temperature

Figure 30. V_REFvs. Temperature

V

f

start(min)

min

20

19

18

17

25.6

25.4

25.2

25.0

24.8

24.6

24.4

24.2

24.0

−40

−20

0

20

40

60

80

100

−40

−20

0

20

40

60

80

100

Temperature [5C]

Figure 31. f_minvs. Temperature

Temperature [5C]

Figure 32. V_start(min)vs. Temperature

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12

NCP10670B, NCP10671B, NCP10672B

APPLICATION INFORMATION

Introduction

output power demand diminishes. By skipping

un−needed switching cycles, the NCP1067X drastically

reduces the power wasted during light load conditions.

The NCP1067X offers a complete current−mode control

solution. The component integrates everything needed to

build a rugged and cost effective Switch−Mode Power

Supply (SMPS) featuring low standby power. The Quick

Selection Table is on details the differences between

references, mainly peak current setpoints, R

operating frequency.

• Current−mode operation: the controller uses

current−mode control architecture.

Startup sequence

When the power supply is first powered from the mains

outlet, the internal current source (typically 8.0 mA) is

value and

DS(on)

biased and charges up the V capacitor from the drain pin.

CC

Once the voltage on this V capacitor reaches the V

CC

CC(on)

level (typically 9.0 V), the current source turns off and

pulses are delivered by the output stage: the circuit is awake

and activates the power MOSFET if the bulk voltage is

• 700 V – _ Power MOSFET: Due to ON Semiconductor

Very High Voltage Integrated Circuit technology, the

circuit hosts a high−voltage power MOSFET featuring a

above V

(22 V dc). Figure 33 details the simplified

start(min)

internal circuitry.

34 or 12 ꢀ R

– Tj = 25°C. This value lets the

DS(on)

designer build a power supply up to 7.8 W operated on

universal mains. An internal current source delivers the

startup current, necessary to crank the power supply.

V_bulk

I1

• Dynamic Self−Supply: Due to the internal high voltage

current source, this device could be used in the application

without the auxiliary winding to provide supply voltage.

R

limit

• Short circuit protection: by permanently monitoring the

COMP line activity, the IC is able to detect the presence

of a short−circuit, immediately reducing the output power

Drain

5

I_start1

I_CC1

←

1

for a total system protection. A t

timer is started as

SCP

soon as the COMP current is below threshold, I

,

COMPfault

I2

which indicates the maximum peak current. If at the end

of this timer the fault is still present, then the device enters

a safe, auto−recovery burst mode, affected by a fixed

−

+

timer recurrence,

disappeared, the controller resumes and goes back to

normal operation.

t

. Once the short has

C_VCC

recovery

+

V_CC(on)

V_CC(min)

• Built−in VCC Over Voltage Protection: when the

auxiliary winding is used to bias the V pin (no DSS),

CC

VCC >18V?

OVP fault

→

an internal comparator is connected to V pin. In case

8

CC

V_OVP

the voltage on the pin exceeds a level of V

(18 V

OVP

typically), the controller immediately stops switching and

waits a full timer period (t ) before attempting to

recovery

Figure 33. The Internal Arrangement of the Start−up

restart. If the fault is gone, the controller resumes

operation. If the fault is still there, e.g. a broken

opto−coupler, the controller protects the load through a

safe burst mode.

Circuitry

Being loaded by the circuit consumption, the voltage on

the V capacitor goes down. When V is below V

CC

CC(min)

• Frequency jittering: an internal low−frequency

modulation signal varies the pace at which the oscillator

frequency is modulated. This helps spreading out energy

in conducted noise analysis.

• Soft−Start: a 4 ms soft−start ensures a smooth startup

sequence, reducing output overshoots.

level (7.5 V typically), it activates the internal current source

to bring V toward V level and stops again: a cycle

CC

CC(on)

takes place whose low frequency depends on the V

CC

capacitor and the IC consumption. A 1.5 V ripple takes place

on the V pin whose average value equals (V

+

CC(on)

CC

V ) / 2. Figure 34 portrays a typical operation of the

CC(min)

DSS.

• Skip: if SMPS naturally exhibits a good efficiency at

nominal load, they begin to be less efficient when the

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13

NCP10670B, NCP10671B, NCP10672B

10

9

9.0 V

8

7

6

5

4

3

2

1

0

7.5 V

V_CC

Device

Internal

Pulses

V_CCTH

0

1

2

3

4

5

6

7

8

9

10

time [ms]

Startup Duration

Figure 34. The Charge/Discharge Cycle Over a 1 mF V_CCCapacitor

As one can see, even if there is auxiliary winding to

The V capacitor has only a supply role and its value

CC

provide energy for V , it happens that the device is still

biased by DSS during start−up time or some fault mode

when the voltage on auxiliary winding is not ready yet. The

does not impact other parameters such as fault duration or

the frequency sweep period for instance. As one can see on

Figure 33, an internal OVP comparator, protects the

CC

V

capacitor shall be dimensioned to avoid V crosses

switcher against lethal V runaways. This situation can

CC

level, which stops operation. The ꢂV between

occur if the feedback loop optocoupler fails, for instance,

and you would like to protect the converter against an over

voltage event. In that case, the over voltage protection

(OVP) circuit and immediately stops the output pulses for

CC(off)

CC(min)

and V

is 0.5 V. There is no current source to

CC(off)

charge V capacitor when driver is on, i.e. drain voltage is

close to zero. Hence the V capacitor can be calculated

CC

using

t

duration (400 ms typically). Then a new start−up

recovery

attempt takes place to check whether the fault has

disappeared or not. The OVP paragraph gives more design

details on this particular section.

I_CC1D_max

C_VCC

≥

(eq. 1)

f_OSC

@ ꢂ V

Take the 60 kHz device as an example. C

above

should be

VCC

0.84 m @ 72%

+ 22 nF

(eq. 2)

54 kHz @ 0.5

A margin that covers the temperature drift and the voltage

drop due to switching inside FET should be considered, and

thus a capacitor above 0.1 ꢁ F is appropriate.

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14

NCP10670B, NCP10671B, NCP10672B

Fault Condition – Short−circuit on V_CC

Fault Condition – Output Short−circuit

In some fault situations, a short−circuit can purposely

occur between V and GND. In high line conditions

As soon as V

internally enabled. If everything is correct, the auxiliary

reaches V

, drive pulses are

CC

CC(on)

CC

(V = 370 V ) the current delivered by the startup

winding increases the voltage on the V pin as the output

HV

DC

CC

device will seriously increase the junction temperature. For

instance, since I equals 4 mA (the min corresponds to

voltage rises. During the start−sequence, the controller

smoothly ramps up the peak drain current to maximum

start1

the highest T ), the device would dissipate

setting, i.e. I , which is reached after a typical period of

j

IPK

370 · 4 m 1.48 W. To avoid this situation, the controller

4 ms. When the output voltage is not regulated, the current

includes a novel circuitry made of two startup levels, I

coming through COMP pin is below I

level (40 ꢁ A

start1

COMPfault

and I

. At power−up, as long as V is below a 1.2 V

typically), which is not only during the startup period but

also anytime an overload occurs, an internal error flag is

asserted, Ipflag, indicating that the system has reached its

maximum current limit set point. The assertion of this flag

start2

CC

level, the source delivers I

then, when V

transitions to I

(around 400 ꢁ A typical),

start2

reaches 1.2 V, the source smoothly

CC

and delivers its nominal value. As a

start1

result, in case of short−circuit between V and GND, the

triggers a fault counter t

(48 ms typically). If at counter

CC

SCP

power dissipation will drop to 370 · 400 ꢁ = 148 mW.

Figure 34 portrays this particular behavior.

completion, I

stopped and the part stays off in t

remains asserted, all driving pulses are

pflag

duration (about

recovery

The first startup period is calculated by the formula

C · V = I · t, which implies a 1 ꢁ · 1.2 / 400 ꢁ = 3 ms startup

time for the first sequence. The second sequence is obtained

by toggling the source to 8 mA with a delta V of

400 ms). A new attempt to re−start occurs and will last 48 ms

providing the fault is still present. If the fault still affects the

output, a safe burst mode is entered, affected by a low

duty−cycle operation (11%). When the fault disappears, the

power supply quickly resumes operation. Figure 35 depicts

this particular mode:

V

CC(on)

– V

= 9.0 – 1.2 = 7.8 V, which finally leads to

CCTH

a second startup time of 1 ꢁ · 7.8 / 8 m = 975 ꢁ s. The total

startup time becomes 3 m + 0.975 m = 3.975 ms. Please note

that this calculation is approximated by the presence of the

knee in the vicinity of the transition.

V_CC(on)

V_CC(min)

V_CC

IpFlag

Open Loop

FB

V

COMP

48 ms typ

.

Fault level

TIMER

400 ms typ

.

DRV

internal

Figure 35. In Case of Short−circuit or Overload, the NCP1067X Protects Itself and the Power Supply via a Low

Frequency Burst Mode. The V_CCis Maintained by the Current Source and Self−supplies the Controller.

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15

NCP10670B, NCP10671B, NCP10672B

Auto−recovery Over Voltage Protection

The particular NCP1067X arrangement offers a simple

way to prevent output voltage runaway when the

optocoupler fails. As Figure 36 shows, a comparator

and to filter out the Vcc line to avoid undesired OVP

activation. R should be carefully selected to avoid

triggering the OVP as we discussed, but also to avoid

limit

monitors the V pin. If the auxiliary pushes too much

disturbing the V in low / light load conditions.

CC

voltage into the C

considers an OVP situation and stops the internal drivers.

When an OVP occurs, all switching pulses are permanently

capacitor, then the controller

Self−supplying controllers in extremely low standby

applications often puzzles the designer. Actually, if a SMPS

operated at nominal load can deliver an auxiliary voltage of

VCC

disabled. After t

delay, it resumes the internal drivers.

an arbitrary 16 V (V ), this voltage can drop below 10 V

recovery

nom

If the failure symptom still exists, e.g. feedback

(V ) when entering standby. This is because the

stby

opto−coupler fails, the device keeps the auto−recovery OVP

recurrence of the switching pulses expands so much that the

mode. It is recommended insertion of a resistor (R

)

low frequency re−fueling rate of the V capacitor is not

limit

CC

between the auxiliary dc level and the V pin to protect the

enough to keep a proper auxiliary voltage.

CC

IC against high voltage spikes, which can damage the IC,

Drain

V_CC(on)= 9.0 V

V_CC(min)= 7.5 V

I_start1

D1

V_CC

R

limit

Shut down

Internal DRV

C_VCC

C_AUX

N_AUX

80 ꢁ s

filter

V_OVP

GND

Figure 36. A More Detailed View of the NCP1067X Offers Better Insight on How to Properly Wire an Auxiliary

Winding

V_OVP

V_CC(on)

V_CC(min)

V_CC

V

COMP

48 ms typ

Fault level

TIMER

400 ms typ

DRV

internal

Figure 37 Describes the Main Signal Variations when the Part Operates in Auto−recovery OVP:

Figure 37. If the VCC Current Exceeds a Certain Threshold, an Auto−recovery Protection is Activated

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16

NCP10670B, NCP10671B, NCP10672B

Soft−start

The NCP1067X features a 4 ms soft−start which reduces

the power−on stress but also contributes to lower the output

overshoot. Figure 38 shows a typical operating waveform.

The NCP1067X features a novel patented structure which

offers a better soft−start ramp, almost ignoring the start−up

pedestal inherent to traditional current−mode supplies:

V

CC

V

CCON

0 V (fresh PON)

Drain current

Max I

IPK

4 ms

Figure 38. The 4 ms Soft−start Sequence

Jittering

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. The NCP1067X offers a 6%

deviation of the nominal switching frequency. The sweep

sawtooth is internally generated and modulates the clock up

and down with a fixed frequency of 300 Hz. Figure 39 shows

the relationship between the jitter ramp and the frequency

deviation. It is not possible to externally disable the jitter.

Jitter ramp

63.6 kHz

60 kHz

Internal

sawtooth

56.4 kHz

adjustable

Figure 39. Modulation Effects on the Clock Signal by the Jittering Sawtooth

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17

NCP10670B, NCP10671B, NCP10672B

Ipk Reduction

The internal peak current set−point is following the

COMP current information until its level reaches I

of I

(120 ꢁ A typically). Below this point, if the

COMPskip

.

output power continues to decrease, the part enters skip

cycle for the best performance in no−load conditions.

Figure 40 depict the adopted scheme for the part.

Freeze

Below this value, the peak current setpoint is frozen to 30%

of the I . This value is reached at a COMP current level

IPK(0)

800

700

NCP10672

NCP10671

NCP10670

600

500

400

300

200

100

0

40

50

60

70

80

90

100

I

[mA]

COMP

Figure 40. I_IPKSet−point is Frozen at Lower Power Demand

Feedback and Skip

Figure 41 depicts the relationship between COMP pin

voltage and current. The COMP pin operates linearly as the

this linear operating range, the dynamic resistance is

17.7 kꢀ typically (R ) and the effective pull up

COMP(up)

voltage is 2.7 V typically (V

). When I

is

COMP(REF)

COMP

absolute value of COMP current (I ) is above 40 ꢁ A. In

COMP

decreases, the COMP voltage will increase to 3.2 V.

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

−180

−160 −140 −120 −100

−80

−60

−40

−20

0

I

[mA]

COMP

Figure 41. COMP Pin Voltage vs. Current

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18

NCP10670B, NCP10671B, NCP10672B

Figure 42 depicts the skip mode block diagram. When the

COMP current information reaches I , the internal

internal skip comparator is minimized to lower the ripple of

the auxiliary voltage for V pin and V of power supply

COMPskip

CC

OUT

clock to set the flip−flop is blanked and the internal

during skip mode. It easies the design of V over load

CC

consumption of the controller is decreased. The hysteresis of

range.

Jittering

OSC

S

DRV stage

Q

R

V

COMP(REF)

I

COMPskip

R

−

COMP(UP)

SKIP

CS comparator

+

COMP

Figure 42. Skip Cycle Schematic

Ramp Compensation and Ipk Set−point

In order to allow the NCP106X to operate in CCM with a

duty cycle above 50%, a fixed slope compensation is

internally applied to the current−mode control.

Here we got a table of the ramp compensation, the initial

current set point, and the final current set−point of different

versions of switcher.

NCP10670

NCP10671

NCP10672

F

60 kHz

100 kHz

60 kHz

8.4 mA/ꢁ s

100 kHz

60 kHz

100 kHz

sw

S

2.8 mA/ꢁ s

4.7 mA/ꢁ s

14 mA/ꢁ s

15.6 mA/ꢁ s

26 mA/ꢁ s

a

I

83 mA

208 mA

250 mA

650 mA

780 mA

IPK(Duty = 50%)

I

100 mA

IPK(0)

Figure 43 depicts the variation of I

set−point vs. the

IPK

power switcher duty ratio, which is caused by the internal

ramp compensation.

800

700

600

500

NCP10672

NCP10671

NCP10670

400

300

200

100

0

0%

10%

20%

30%

40%

50%

60%

70%

Dutty Ratio [%]

Figure 43. I_IPKSet−point Varies with Power Switch on Time, Which is Caused by the Ramp Compensation

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19

NCP10670B, NCP10671B, NCP10672B

FB pin function

The FB pin is used in non isolated SMPS application only.

Portion of the output voltage is connected into the pin. The

1. The lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of a

large leakage inductance) or in normal operation as

shown in Figure 45. This condition sets the

voltage is compared with internal V

(3.3 V) using

REF

Operation Transconductance Amplifier (Figure 44). The

OTAs output is connected to COMP pin. From the outside

an user defined compensation network is connected to the

COMP pin. The current capability of OTA is limited to

−150 ꢁ A typically. The positive current is defined by

maximum voltage that can be reflected during t .

off

As a result, the Flyback voltage which is reflected on

the drain at the switch opening cannot be larger than

the input voltage. When selecting components, you

thus must adopt a turn ratio which adheres to the

following equation:

internal R

resistor and V

voltage. If FB

COMP(up)

COMP(ref)

path loop is broken (i.e. the FB pin is disconnected), an

N (V_out) V_f) t V_{in, min}

(eq. 3)

internal current I (1 ꢁ A typ.) will pull up the FB pin and

FB

2. In our case, since we operate from a 127 V DC rail

while delivering 12 V, we can select a reflected

voltage of 120 V dc maximum. Therefore, the turn

ratio Np:Ns must be smaller than

the IC stops switching to avoid uncontrolled output voltage

increasing.

In isolated topology, the FB pin should be connected to

GND pin. In this configuration no current flows from OTA

to COMP pin (OTA is disabled) so the OTA has no influence

on regulation at all.

V_reflect

120

+

+ 9.6

(eq. 4)

V

_out) V_f

12 ) 0.5

or Np:Ns < 9.6. Here we choose N = 8 in this case.

We will see later on how it affects the calculation.

V

COMP(REF)

R

COMP(up)

350

I

COMP

250

150

50.0

I

FB

I

OTA ouT = 0 A

if FB = 0 V

−

OTAlim

FB

OTA

+

> 0 !!

−50.0

V

REF

1.004M

1.011M

1.018M

1.025M

1.032M

Figure 45. The Drain−Source Wave Shall

Figure 44. FB Pin Connection

Always be Positive

Design Procedure

The design of an SMPS around a monolithic device does

not differ from that of a standard circuit using a controller

and a MOSFET. However, one needs to be aware of certain

characteristics specific of monolithic devices. Let us follow

the steps:

I

L

I

peak

ꢂ I

L

I

1

V min = 90 Vac or 127 Vdc once rectified, assuming a low

in

bulk ripple

I

valley

V

in

max = 265 Vac or 375 Vdc

V

= 12 V

= 5 W

out

I

avg

P

out

Operating mode is CCM

h = 0.8

t

dT

sw

T

sw

Figure 46. Primary Inductance Current

Evolution in CCM

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20

NCP10670B, NCP10671B, NCP10672B

3. Lateral MOSFETs have a poorly doped body−diode

peak to peak

which naturally limits their ability to sustain the

avalanche. A traditional RCD clamping network

shall thus be installed to protect the MOSFET. In

some low power applications, a simple capacitor can

also be used since

The peak current can be evaluated to be:

I_avg

d

ꢂ I_L

49.2 m 92.8 m

I_peak

+

)

+

)

+ 158 mA

(eq. 11)

2

0.44

2

On , I can also be calculated:

1

L_f

ꢂ I_L

92.8 m

2

Ǹ

V_drain,max+ V_in) N (V_out) V_f) ) I_peak

(eq. 5)

C_tot

I_Lavg+ I_peak

*

+ 158 m *

+ 111.6 mA

(eq. 12)

2

where L is the leakage inductance, C the total

f

tot

6. Based on the above numbers, we can now evaluate

the conduction losses:

capacitance at the drain node (which is increased by

the capacitor you will wire between drain and

source), N the N :N turn ratio, V the output

ꢂ I²_L

P

S

out

I_d,rms

+

d

ǒ

I²_peak* I_peakꢂ I_L)

Ǔ

+

Ǹ

voltage, V the secondary diode forward drop and

f

3

finally, I

the maximum peak current. Worse case

peak

occurs when the SMPS is very close to regulation,

e.g. the V target is almost reached and I is still

ꢂ I²_L

out

peak

+

d

ǒ

I²_peak* I_peakꢂ I_L)

Ǔ

+ 57 mA

Ǹ

3

pushed to the maximum. For this design, we have

selected our maximum voltage around 650 V

(eq. 13)

(at V = 375 Vdc). This voltage is given by the RCD

clamp installed from the drain to the bulk voltage.

We will see how to calculate it later on.

in

If we take the maximum R

temperature, i.e. 34 ꢀ, then conduction losses worse

case are:

for a 125°C junction

ds(on)

4. Calculate the maximum operating duty−cycle for

this flyback converter operated in CCM:

2

P_cond+ I_d,dmsR_{ds (on)}+ 110mW

(eq. 14)

N (V_out) V_f)

1

d_max

+

+ 0.44

7. Off−time and on−time switching losses can be

V_in,min

N (V_out) V_f) ) V_in,min

estimated based on the following calculations:

1 )

N (V_out)V_f)

I_peak(V_bulk) V_clamp) t_off

(eq. 6)

P_off

+

2T_SW

0.158 @ (127 ) 100 @ 2) @ 10 n

5. To obtain the primary inductance, we have the

choice between two equations:

+ 15.5 mW

(eq. 15)

(V_ind)²

2 @ 16.7

ꢁ

L +

(eq. 7)

f_swK P_in

Where, assume the V

reflected voltage.

is equal to 2 times of

clamp

where

ꢂ I_L

I_valley(V_bulk) N (V_out) V_f)) t_on

K +

(eq. 8)

I_Lavg

P_on

+

6T_SW

and defines the amount of ripple we want in CCM

(see Figure 46 ).

• Small K: deep CCM, implying a large primary

inductance, a low bandwidth and a large leakage

inductance.

• Large K: approaching DCM where the RMS

losses are worse, but smaller inductance, leading

to a better leakage inductance.

0.0464 @ (127 ) 100 @ 2) @ 20 n

+ 2.1 mW

(eq. 16)

6 @ 16.7

ꢁ

It is noted that the overlap of voltage and current seen

on MOSFET during turning on and off duration is

dependent on the snubber and parasitic capacitance

seen from drain pin. Therefore the t and t in

eq. 15 and eq. 16 have to be modified after

measuring on the bench.

off

on

From eq.17, a K factor of 1 (50% ripple), gives an

inductance of:

8. The theoretical total power is then

117 + 15.5 + 2.1 = 127.6 mW

(127 @ 0.44)²

9. If the NCP106X operates at DSS mode, then the

losses caused by DSS mode should be counted as

losses of this device on the following calculation:

L +

+ 10.04 mH

(eq. 9)

60k @ 1 @ 5)

V_ind

127 @ 0.44

ꢂ

I

+

92.8 mA

L

(eq. 10)

LF_SW

10.04 m @ 60 k

P_DSS+ I_cc1@ V_in,max+ 0.8 m @ 375 + 300 mW

(eq. 17)

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21

NCP10670B, NCP10671B, NCP10672B

MOSFET Protection

which is 700 V. Figure 47 a−b−c present possible

As in any Flyback design, it is important to limit the drain

excursion to a safe value, e.g. below the MOSFET BVdss

implementations:

HV

Dz

Rclamp

Cclamp

D

NCP1067x

GND

CVcc

C

GND

a)

GND

b)

GND

c)

Figure 47. Different Options to Clamp the Leakage Spike

Figure 47a: the simple capacitor limits the voltage

according to the lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of a large

leakage inductance) or in normal operation as shown by

Figure 45. This condition sets the maximum voltage that can

area is far bigger for a transient suppressor than that of zener.

A 5 W zener diode like the 1N5388B will accept 180 W peak

power if it lasts less than 8.3 ms. If the peak current in the

worse case (e.g. when the PWM circuit maximum current

limit works) multiplied by the nominal zener voltage

exceeds these 180 W, then the diode will be destroyed when

the supply experiences overloads. A transient suppressor

like the P6KE200 still dissipates 5 W of continuous power

but is able to accept surges up to 600 W @ 1 ms. Select the

zener or TVS clamping level between 40 to 80 volts above

the reflected output voltage when the supply is heavily

loaded.

As a good design practice, it is recommended to

implement one of this protection to make sure Drain pin

voltage doesn’t go above 650 V (to have some margin

between Drain pin voltage and BVdss) during most stringent

operating conditions (high Vin and peak power).

be reflected during t . As a result, the flyback voltage which

off

is reflected on the drain at the switch opening cannot be

larger than the input voltage. When selecting components,

you must adopt a turn ratio which adheres to the following

equation eq. 5. This option is only valid for low power

applications, e.g. below 5 W, otherwise chances exist to

destroy the MOSFET. After evaluating the leakage

inductance, you can compute C with (eq. 6). Typical values

are between 100 pF and up to 470 pF. Large capacitors

increase capacitive losses…

Figure 47b: the most standard circuitry is called the RCD

network. You can calculate R

and C

using the

clamp

following formula:

Power Dissipation and Heatsinking

The NCP1067X welcomes two dissipating terms, the DSS

current−source (when active) and the MOSFET. Thus,

2 V_clamp(V_clamp) (V_out) V_f) N)

R_clamp

+

2

(eq. 18)

(eq. 19)

L

_leakI_leakF_sw

P

tot

= P

+ P . It is mandatory to properly manage

MOSFET

DSS

V_clamp

the heat generated by losses. If no precaution is taken, risks

exist to trigger the internal thermal shutdown (TSD). To help

dissipating the heat, the PCB designer must foresee large

copper areas around the package. When the package is

surrounded by a surface approximately 200 mm of 35 ꢁ m

copper, the maximum power the device can thus evacuate is:

C_clamp

V_rippleF_swR_clamp

V

clamp

is usually selected 50 − 80 V above the reflected

value N x (V + V ). The diode needs to be a fast one and

out

f

2

a MUR160 represents a good choice. One major drawback

of the RCD network lies in its dependency upon the peak

current. Worse case occurs when I

t

_jmax* t_ambmax

and V are maximum

peak

in

P_max

+

(eq. 20)

and V is close to reach the steady−state value.

R_{ꢃ JA}

out

Figure 47c: this option is probably the most expensive of

all three but it offers the best protection degree. If you need

a very precise clamping level, you must implement a zener

diode or a TVS. There are little technology differences

behind a standard zener diode and a TVS. However, the die

which gives around 862 mW for an ambient of 50°C and

a maximum junction of 150°C. If the surface is not large

enough, the R

is growing and the maximum power the

θJA

device can evacuate decreases. Figure 48 gives a possible

layout to help drop the thermal resistance.

www.onsemi.com

22

NCP10670B, NCP10671B, NCP10672B

Figure 48. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

Bill of Material:

C1

Bulk capacitor, input DC voltage is connected

to the capacitor

C2, R1, D1 Clamping elements

C3

OK1

Vcc capacitor

Optocoupler

ORDERING INFORMATION

†

Device

Marking

Frequency

60 kHz

R

I

Package Type

Shipping

DS(on)

IPK(0)

NCP10670BD060R2G

NCP10670BD100R2G

NCP10671BD060R2G

NCP10671BD100R2G

NCP10672BD060R2G

NCP10672BD100R2G

P10670060

P10670100

P10671060

P10671100

P10672060

P10672100

34

100 mA

250 mA

780 mA

SOIC−8

MISSING PIN 3

(Pb−Free)

2500 / Tape & Reel

100 kHz

60 kHz

34

12

100 kHz

60 kHz

100 kHz

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

23

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC8 MISSING PIN 3

CASE 751EV

ISSUE O

SCALE 1:1

D

DATE 19 SEP 2017

NOTES:

NOTE 5

A

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

F

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL

BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL

CONDITION.

4. DIMENSIONS D & E1 DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR GATE BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM F.

5. DATUMS A AND B ARE TO BE DETERMINED AT

DATUM F.

8

0.10 C

5

NOTE 6

M

A1

E

E1

L2

L

SEATING

PLANE

C

0.20

C

1

4

DETAIL A

7X b

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

B

NOTE 5

M

0.12

C

A-B D

TOP VIEW

D

MILLIMETERS

0.10

C

A-B

DIM MIN

MAX

1.75

0.25

0.51

0.25

5.00

6.20

4.00

A

A1

b

c

D

E

E1

e

1.35

0.10

0.33

0.19

4.80

5.80

3.80

DETAIL A

7X

0.10

C

A

c

e

END VIEW

1.27 BSC

SEATING

PLANE

C

L

L2

M

0.40

0.25 BSC

0 °

1.27

SIDE VIEW

8 °

RECOMMENDED

SOLDERING FOOTPRINT*

GENERIC

MARKING DIAGRAM*

8

XXXXXXXXX

7X

1.17

ALYWX G

6.30

G

1

7X

0.60

XXXXX = Specific Device Code

1.27

PITCH

A

L

= Assembly Location

= Wafer Lot

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Y

W

G

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON76133G

SOIC8 MISSING PIN 3

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

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www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

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◊


型号：	NCP10672BD060R2G
厂家：	ONSEMI
描述：	High-Voltage Switcher for Low Power Offline SMPS
文件：	总25页 (文件大小：423K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP10672BD060R2G [ONSEMI]

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