NCP1201P100G [ONSEMI]
PWM Current-Mode Controller for Universal Off-Line Supplies Featuring Low Standby Power with Fault Protection Modes; PWM电流模式控制器的通用离线用品，具有低待机功耗，具有故障保护模式
| 型号： | NCP1201P100G |
| 厂家： | 
ONSEMI |
| 描述： | PWM Current-Mode Controller for Universal Off-Line Supplies Featuring Low Standby Power with Fault Protection Modes |
| 文件： | 总20页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1201
PWM Current−Mode
Controller for Universal
Off−Line Supplies Featuring
Low Standby Power with
Fault Protection Modes
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Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhances the
previous NCP1200 series by offering a reduced optocoupler current
with additional Brownout Detection Protection (BOK). Similarly, the
circuit allows the implementation of complete off−line AC−DC
adapters, battery chargers or Switchmode Power Supplies (SMPS)
where standby power is a key parameter.
The NCP1201 features efficient protection circuitry. When in the
presence of a fault (e.g. failed optocoupler, overcurrent condition, etc.)
the control permanently disables the output pulses to avoid subsequent
damage to the system. The IC only restarts when the user cycles the
mains power supply.
With the low power internal structure, operating at a fixed 60 or
100 kHz, the controller supplies itself from the high−voltage rail,
avoiding the need of an auxiliary winding. This feature naturally eases
the designer’s task in battery charger applications. Finally,
current−mode control provides an excellent audio−susceptibility and
inherent pulse−by−pulse control.
MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
201Dy
ALYW
8
8
1
1
8
1
PDIP−8
P SUFFIX
CASE 626
1201Pxx
AWL
YYWW
1
y
y
xx
xx
A
L
= Device Code: 6 for 60 kHz
= Device Code: 1 for 100 kHz
= Device Code: 60 for 60 kHz
= Device Code: 10 for 100 kHz
= Assembly Location
When the load current falls down to a pre−defined setpoint (V
)
= Wafer Lot
Y, YY = Year
W, WW = Work Week
SKIP
value, e.g. the output power demand diminishes, the IC automatically
enters the skip cycle mode and can provide excellent efficiency under
light load conditions. The skip mode is designed to operate at
relatively lower peak current so that acoustic noise that commonly
takes place will not happen with NCP1201.
PIN CONNECTIONS
BOK
FB
1
2
3
4
8
7
6
5
HV
Features
NC
• Pb−Free Packages are Available
• AC Line Brownout Detect Protection, BOK Function
• Latchoff Mode Fault Protection
VCC
DRV
CS
GND
• No Auxiliary Winding Operation
(Top View)
• Internal Output Short−Circuit Protection
• Extremely Low No−Load Standby Power
• Current−Mode with Skip−Cycle Capability
• Internal Overtemperature Shutdown
• Internal Leading Edge Blanking
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
• 250 mA Gate Peak Current Driving Capability
• Internally Fixed Switching Frequency at 60 or 100 kHz
• Built−in Frequency Jittering for EMI Reduction
• Direct Optocoupler Connection
Typical Applications
• AC−DC Adapters
• Offline Battery Chargers
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 3
NCP1201/D
NCP1201
C3
R3
470 p 100 k
250 V 1.0 W
T1
L1
470 mH
0.2 A
6.5 V, 600 mA
L3
*
R1
195.7 k
D2
47 mH
1.0 A
1N5819
BR1
DF06S
4
U1
D1
1
8
+
−
3
1N4937
2
3
+
+
90X264
Vac
C5
10 m
C6
10 m
6
5
+
+
C1
4.7 m
C2
4.7 m
4
NCP1201
400 V
400 V
Q1
MTD1N60E
C7
1.0 n
250 VAC Y1
+
C4
10 mF
SFH6156−2
4
1
2
R2
4.3 k
R4
2.7
U2
0.5 W
L2
D3
5V1
470 mH
0.2 A
* Please refer to the application information section.
Figure 1. Typical Application Example
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2
NCP1201
I
ref
8
1
2
3
HV
NC
BOK
FB
+
−
+
−
HV Current
Source
50 mA
Output
+
−
+
−
7
10.5 V/12.5 V
Oscillator
60 or 100 kHz Clock
Maximum 83%
Duty Cycle
Output
+
−
+
−
Skip Cycle
Comparator
1.92 V
CS
80 K 1.07 V
6
Set
V
CC
+
−
Output
Q
Reset
24 K
250 ns
L.E.B.
TSD
+
−
4
GND
5
DRV
250 mA
Startup
Blanking
Output
20 k
57 k
25 k
Internal
Regulator
V
ref
0.9 V
+
−
V
ref
Overload
Figure 2. Simplified Functional Block Diagram
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NCP1201
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
BOK
Bulk OK
This pin detects the input line voltage by sensing the bulk capacitor, and
disables the PWM when line voltage is lower than normal.
2
3
FB
CS
Sets the Peak Current Setpoint
Current Sense Input
By connecting an optocoupler to this pin, the peak current setpoint is ad-
justed according to the output power demand. Internal monitoring of this
pin level triggers the fault management circuitry.
This pin senses the primary inductor current and routes it to the internal
comparator via an LEB circuit.
4
5
6
7
GND
DRV
VCC
NC
The IC Ground
Driving Pulses
Supplies the IC
No Connection
−
The driver’s output to an external MOSFET.
This pin is connected to an external bulk capacitor of typically 10 mF.
This unconnected pin ensures adequate creepage distance between High
Voltage pin to other pins.
8
HV
Generates the V from the Line
Connected to the high−voltage rail, this pin injects a constant current into
CC
the V capacitor.
CC
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
Unit
V
Power Supply Voltage, Pin 6
V
CC
−0.3, 16
−0.3, 6.5
Input/Output Pins
Pins 1, 2, 3, 5
V
IO
V
Maximum Voltage on Pin 8 (HV)
V
R
500
V
HV
Thermal Resistance, Junction−to−Air, PDIP−8 Version
Thermal Resistance, Junction−to−Air, SOIC Version
100
178
°C/W
°C/W
q
q
JA
JA
R
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
T
−40 to +150
−25 to +125
−55 to +150
2.0
°C
°C
°C
kV
V
J
T
A
T
stg
ESD Capability, HBM (All pins except V and HV pins) (Note 1)
−
CC
ESD Capability, Machine Model (All pins except V and HV pins) (Note 1)
−
200
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) > 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) > 200 V per JEDEC standard: JESD22−A115.
2. Latchup Current Maximum Rating: ±150 mA per JEDEC standard: JESD78.
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NCP1201
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −25°C to +125°C,
J
J
V
CC
= 11 V unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
DYNAMIC SELF−SUPPLY
V
V
Increasing Level at which the Current Source Turns−Off
VCC
11.5
9.6
12.5
10.5
905
13.5
11.3
V
V
CC
CC
OFF
Decreasing Level at which the Current Source Turns−On
VCC
ON
CC1
Internal IC Current Consumption, No Output Load on Pin 5
I
I
440
1300
mA
mA
Internal IC Current Consumption, 1.0 nF Output Load on Pin 5
CC2
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
0.75
1.6
1.6
2.1
2.2
2.8
Internal IC Current Consumption, Latchoff Phase
INTERNAL STARTUP CURRENT SOURCE
High−Voltage Current Source at V – 0.2 V
I
405
575
772
mA
CC3
I
I
3.6
7.5
−
5.3
11.1
30
7.1
15
70
mA
mA
mA
CCON
C1
High−Voltage Current Source at V = 0 V
CC
C2
HV Pin Leakage Current @ 450 V, V Pin Connected to Ground
I
LEAK
CC
OUTPUT SECTION
Output Voltage Rise−Time (CL = 1.0 nF, 10 V Output)
Output Voltage Fall−Time (CL = 1.0 nF, 10 V Output)
Tr
Tf
−
−
116
41
−
−
ns
ns
W
Source Resistance (V
= )
R
26
4.0
38
60
22
DRV
OH
Sink Resistance (V
= )
R
10
W
DRV
OL
CURRENT SENSE SECTION (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Current Sense Input Threshold
I
−
10
0.9
325
65
100
1.0
nA
V
IB−CS
V
0.8
250
35
ILIMIT
ILSKIP
Default Current Sense Threshold for Skip Cycle Operation
Propagation Delay from Current Detection to Gate OFF State
Leading Edge Blanking Duration
V
390
160
400
mV
ns
ns
T
DEL
T
150
260
LEB
OSCILLATOR SECTION (V = 11 V, Pin 5 Loaded by 1.0 KW)
CC
Oscillation Frequency
F
kHz
Hz/V
%
OSC
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
52
92
60
100
72
117
Built−in Frequency Jittering (as a function of Vcc voltage)
F
jitter
NCP1201P60, NCP1201D60
NCP1201P100, NCP1201D100
−
−
493
822
−
−
Maximum Duty Cycle
D
74
83
87
max
FEEDBACK SECTION (V = 11 V, Pin 5 Unloaded)
CC
Internal Pullup Resistor
R
10
17
24
kW
UP
Feedback Pin to Pin 3 Current Setpoint Division Ratio
BROWNOUT DETECT SECTION
BOK Input Threshold Voltage
I
2.9
3.3
4.0
−
ratio
V
1.75
−
1.92
11
2.05
100
58
V
th
BOK Input Bias Current (V
< V )
I
nA
mA
BOK
th
IB−BOK
Source Bias Current (Turn on After V
> V )
I
SC
40
50
BOK
th
FREQUENCY SKIP CYCLE SECTION
Built−in Frequency Skip Cycle Comparator Voltage Threshold
THERMAL SHUTDOWN
V
SKIP
0.96
1.07
1.18
V
Thermal Shutdown Trip Point, Temperature Rising (Note 3)
Thermal Shutdown Hysteresis
T
−
−
145
25
−
−
°C
°C
SD
T
HYST
3. Verified by design.
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NCP1201
TYPICAL CHARACTERISTICS
10.8
12.9
12.7
12.5
12.3
12.1
10.6
10.4
10.2
10
11.9
11.7
9.8
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. VCC OFF Threshold Voltage
vs. Junction Temperature
Figure 4. VCC ON Threshold Voltage
vs. Junction Temperature
1100
2.6
2.4
2.2
2.0
1.8
1 nF Load
1000
900
100 KHz
800
700
600
60 KHz
50
1.6
1.4
−25
0
25
50
75
100
125
−25
0
25
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. IC Current Consumption, ICC1
vs. Junction Temperature
Figure 6. IC Current Consumption, ICC2
vs. Junction Temperature
700
600
500
8.0
6.5
5.0
3.5
V
CC
= 11 V
400
300
2.0
0.5
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. IC Current Consumption at Latchoff Phase
vs. Junction Temperature
Figure 8. HV Pin Startup Current Source
vs. Junction Temperature
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NCP1201
TYPICAL CHARACTERISTICS
14
12
10
8
80
60
40
20
0
6
4
V
CC
= 0 V
0
−25
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. HV Pin Startup Current Source
vs. Junction Temperature
Figure 10. Leakage Current vs.
Junction Temperature
70
20
16
12
8
60
50
40
30
20
4
0
10
0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Output Source Resistance
vs. Junction Temperature
Figure 12. Output Sink Resistance
vs. Junction Temperature
1.00
0.96
0.92
0.88
12
11
10
9
8
0.84
0.80
7
6
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. CS Pin Input Bias Current @ 1.0 V
vs. Junction Temperature
Figure 14. Maximum Current Sense Threshold
vs. Junction Temperature
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NCP1201
TYPICAL CHARACTERISTICS
340
330
320
310
100
85
70
55
40
300
290
25
10
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Default Current Setpoint for Skip Cycle
vs. Junction Temperature
Figure 16. Propagation Delay from Current Detection to
Gate Driver vs. Junction Temperature
400
350
300
250
200
150
100
120
100 KHz
100
80
60 KHz
60
40
20
0
50
0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. Leading Edge Blanking Duration
vs. Junction Temperature
Figure 18. Oscillator Frequency
vs. Junction Temperature
1400
1200
1000
800
85
84
83
82
81
100 KHz
60 KHz
600
400
80
79
200
0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 20. Maximum Duty Cycle
vs. Junction Temperature
Figure 19. Frequency Jittering
vs. Junction Temperature
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NCP1201
TYPICAL CHARACTERISTICS
3.40
19
18
17
16
15
3.35
3.30
3.25
3.20
3.15
3.10
14
13
3.05
3.00
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. FB Pin Pullup Resistor
vs. Junction Temperature
Figure 22. Feedback Pin to Pin 3 Current Setpoint Ratio
vs. Junction Temperature
12
11
10
9
2.00
1.95
1.90
1.85
1.80
8
1.75
1.70
7
V
< V
th
BOK
6
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. BOK Threshold Voltage
vs. Junction Temperature
Figure 24. BOK Input Bias Current
vs. Junction Temperature
1.15
1.10
1.05
51
50
49
48
47
1.00
0.95
46
45
V
< V
th
BOK
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. BOK Source Bias Current
vs. Junction Temperature
Figure 26. Skip Mode Threshold Voltage
vs. Junction Temperature
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NCP1201
DETAILED OPERATING DESCRIPTION
Dynamic Self−Supply
Introduction
The NCP1201 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count is the key criteria,
particularly in low−cost AC−DC adapters, auxiliary
supplies etc. Due to its high−performance High−Voltage
technology, the NCP1201 incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, low−pass filter and
self−supply. This later point emphasizes the fact that
ON Semiconductor’s NCP1201 does NOT need an
auxiliary winding to operate: the device is self supplied from
The DSS principle is based on the charge/discharge of the
bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation following
simple logic equations:
V
CC
POWER−ON: IF V < V
THEN
CC
CCOFF
Current Source is ON, no output pulses
IF VCC decreasing > V THEN
CCON
Current Source is OFF, output is pulsing
IF VCC increasing < V THEN
CCOFF
Current Source is ON, output is pulsing
Typical values are: V = 12.5 V, V
= 10.5 V
CCON
CCOFF
the high−voltage rail and delivers a V to the IC. This
system is named the Dynamic Self−Supply (DSS).
CC
To better understand the operation principle, Figure 27
sketch offers the necessary explanation,
Vripple = 2 V
VCC
= 12.5 V
OFF
V
CC
VCC = 10.5 V
ON
ON
OFF
Current
Source
Output Pulses
10 mS
30 mS
50 mS
70 mS
90 mS
Figure 27. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor
The DSS behavior actually depends on the internal IC
The total standby power consumption at no−load will
therefore heavily rely on the internal IC current
consumption plus the driving current (altered by the driver’s
efficiency). Suppose that the IC is supplied from a 350 VDC
line. The current flowing through pin 8 is a direct image of
the NCP1201 current consumption (neglecting the
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg max equals
22 nC. With a maximum switching frequency of 70 kHz for
the oscillator 60 kHz, the average power necessary to drive
the MOSFET (excluding the driver efficiency and
neglecting various voltage drops) is:
switching losses of the HV current source). If I
equals
CC2
2.1 mA @ T = 25°C, then the power dissipated (lost) by the
A
P
+ F
Q V
sw(max) g CC
(eq. 1)
driver
IC is simply: 350 V x 2.1 mA = 735 mW. For design and
reliability reasons, it would be interesting to reduce this
source of wasted power. In order to achieve that, different
methods can be used.
Where,
P
F
= Average Power to drive the MOSFET
driver
= Maximum switching frequency
sw(max)
1. Use a MOSFET with lower gate charge Qg;
2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes:
Qg = MOSFET’s gate charge
= VGS level applied to the gate of the MOSFET
To obtain an estimation of the driving current, simply
divide Pdriver by V
V
CC
,
CC
V
2
mainsPEAK
(eq. 3)
(eq. 2)
Q + 1.54 mA
sw(max) g
I
+ F
driver
p
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NCP1201
Our power contribution example drops to 223 V x 2.1 mA
Skipping Cycle Mode
= 468.3 mW. If a resistor is installed between the mains and
the diode, you further force the dissipation to migrate from
the package to the resistor. The resistor value should be
carefully selected to account for low−line startup.
The NCP1201 automatically skips switching cycles when
the output power demand drops below a preset level. This is
accomplished by monitoring the FB pin. In normal
operation, FB pin imposes a peak current according to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this set−point reaches the
skip mode threshold level, 1.07 V, the IC prevents the
current from decreasing further down and starts to blank the
output pulses, i.e. the controller enters the so−called Skip
Cycle Mode, also named Controlled Burst Operation. The
power transfer now depends upon the width of the pulse
bunches, Figure 29.
HV
1
2
3
4
8
7
6
5
Mains
Cbulk
Suppose we have the following component values:
Lp, primary inductance = 1.0 mH
F
, switching frequency = 60 kHz
sw
I (skip) = 200 mA (or 333 mV/R
)
sense
p
Figure 28. A Simple Diode Naturally Reduces the
Average Voltage on Pin 8
The theoretical power transfer is therefore:
1
2
2
(eq. 4)
L I F + 1.2 W
sw
p
p
3. Permanently force the V level above VCC
CC
OFF
If the controller enters Skip Cycle Mode with a pulse
packet length of 20 ms over a recurrent period of 100 ms,
then the total power transfer reduced to 1.2 W x 0.2 =
240 mW.
To better understand how this Skip Cycle Mode takes
place, a look at the operation mode versus the FB pin voltage
level shown below, immediately gives the necessary insight.
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self−supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. By using this approach,
user need to make sure the auxiliary voltage never
exceeds the 16 V limit for all line conditions.
FB
4.2 V, FB Pin Open
2.97 V, Upper Dynamic Range
Normal Current Mode Operation
1.07 V
Skip Cycle Operation
= 333 mV / R
I
p(min)
sense
Figure 29. Feedback Pin Voltage and Modes of Operation
When FB pin voltage level is above the skip cycle threshold
(1.07 V by default), the peak current cannot exceed
0.9 V/R . When the IC enters the skip cycle mode, the
peak current cannot go below V
current limit reduction scheme, the skip cycle takes place at
a lower peak current, which guarantees noise free operation.
/3.3. By using the peak
SKIP
sense
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11
NCP1201
P = 0.4 W
1
P = 1.8 W
2
P = 3.6 W
3
Figure 30. MOSFET VDS at Various Power Levels, P1<P2<P3
Max peak
current
300.0M
200.0M
100.0M
0
Skip Cycle
current limit
315.4uS
2.585mS
882uS
1.450mS
2.017mS
Figure 31. The Skip Cycle Takes Place at Low Peak Current
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NCP1201
V
BULK
Brownout Detect Protection
In order to avoid output voltage bouncing during
electricity brownout, a Bulk Capacitor Voltage Comparator
with programmable hysteresis is included in this device. The
non−inverting input, pin 1, is connected to the voltage
V
REF
R
R
Upper
divider comprised of R
and R
as shown in
Upper
Lower
Figure 32, monitoring the bulk capacitor voltage level. The
inverting input is connected to a threshold voltage of 1.92 V
internally. As bulk capacitor voltage drops below the
pre−programmed level, i.e. Pin 1 voltage drops below
1.92 V, a reset signal will be generated via internal
protection logic to the PWM Latch to turn off the Power
Switch immediately. At the same time, an internal current
source controlled by the state of the comparator provides a
mean to setup the voltage hysteresis through injecting
50 mA
1.92 V
BOK
+
−
UVLO
Lower
Figure 32. Brown−Out Protection Operation
current into R . The equations below (Equations 5 and
Lower
6) show the relationship between V
voltage divider network resistors.
levels and the
BULK
Equations for resistors selection are:
(V * V
BULK_H
50 mA
)
BULK_L
R
) R
+
(eq. 5)
Upper
Lower
[1.92 V(V
* V
)]
BULK_H
BULK_L
R
+
(eq. 6)
Lower
(50 mA V
)
BULK_H
Assume V
= 90 Vdc and V
= 80 Vdc, by
BULK_H
BULK_L
using 4.3 kW for R
then R
is about 195.7 kW.
Lower
Upper
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13
NCP1201
APPLICATION INFORMATION
Power Dissipation
MOSFET’s Q which I
≈ I + F x Q . Final
CC1 sw g
g
CC2
The NCP1201 can be directly supplied from the DC rail
through the internal DSS circuitry. The average current
flowing through the DSS is therefore the direct image of the
NCP1201 current consumption. The total power dissipation
calculation should thus account for the total gate−charge Q
your MOSFET will exhibit.
g
If the power estimation is beyond the limit, supply to the
with a series diode as suggested in Figure 28 can be
V
CC
can be evaluated using: (V
* 11 V) I
. If the
device operates on a 250 VAC rail, the maximum rectified
voltage can go up to 350 VDC. At T = 25°C, I = 2.1 mA
used. As a result, it will drop the average input voltage and
HVDC
CC2
350 V 2
lower the dissipation to
1.6 mA + 356.5 mW.
p
A
CC2
Alternatively, an auxiliary winding can be used to disable
the DSS and hence reduce the power consumption down to
for the 60 kHz version over a 1.0 nF capacitive load. As a
result, the NCP1201 will dissipate 350 V x 2.1 mA =
V
x I
. By using the auxiliary winding supply method,
CC CC2
735 mW (T = 25_C). The SOIC−8 package offers a
A
the rectified auxiliary voltage should permanently stays
above the V threshold voltage, keeping DSS off and
junction−to−ambientthermal resistance R
of 178°C/W.
qJ−A
CCOFF
Adding some copper area around the device pins will help
to improve this number, 12mm x 12mm copper can drop
is safely kept well below the 16 V maximum rating for
whole operating conditions.
R
qJ−A
down to 100°C/W with 35 m copper thickness (1 oz.)
or 6.5mm x 6.5mm with 70 m copper thickness (2 oz.). With
this later number, we can compute the maximum power
dissipation the package accepts at an ambient of 50°C:
Non−Latching Shutdown
In some cases, it might be desirable to shut off the device
temporarily and authorize its restart once the control signal
has disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
T
−T
jmax Amax
P
+
+ 750 mW (T
= 125_C),
max
Jmax
R
qJ−A
which is acceptable with our previous thermal budget. For
the DIP8 package, adding a min−pad area of 80mm of 35 m
and ground. By pulling FB pin voltage below the V
SKIP
2
level, the output pulses are disabled as long as FB pin
voltage is pulled below the skip mode threshold voltage. As
soon as FB pin is released, the the device resumes its normal
operation again. Figure 33 depicts an application example.
copper (1 oz.), R
drops from 100°C/W to about 75°C/W.
qJ−A
In the above calculations, I
capacitor. As seen before, I
is based on a 1.0 nF output
will depend on your
CC2
CC2
1
2
3
4
8
7
6
5
Q1
ON/OFF
Figure 33. A Method to Shut Down the Device Without a Definitive Latchoff State
Fault Protection
situations, NCP1201 included a dedicated overload
protection circuitry. Once the protection activated, the
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
often required to permanently latchoff the power supply in
presence of a fault. This fault can be either a short−circuit on
the output or a broken optocoupler. In this later case, it is
important to quickly react in order to avoid a lethal output
voltage runaway. The NCP1201 includes a circuitry tailored
to tackle both events. A short−circuit forces the output
voltage to be at a low level, preventing a bias current to
circulate in the optocoupler LED. As a result, the FB pin
level is pulled up to 4.2 V, as internally imposed by the IC.
The peak current set−point goes to the maximum and the
supply delivers a rather high power with all the associated
effects. However, this can also happen in case of feedback
loss, e.g. a broken optocoupler. To account for those
circuitry permanently stops the pulses while the V moves
CC
between 10−12 V to maintain this latchoff state. The system
resets when the user purposely cycles the V down below
CC
3.0 V, e.g. when the power plug is removed from the mains.
In NCP1201, the controller stops all output pulses as soon
as the error flag is asserted, irrespective to the V level.
CC
However, to avoid false triggers during the startup sequence,
NCP1201 purposely omits the very first V descent from
CC
12 to 10 V. The error circuitry is actually armed just after this
sequence, e.g. V
crossing 10 V. Figure 34 details the
CC
timing sequence. The V capacitor should be calculated
CC
carefully to offer a sufficient time out during the first startup
V
CC
descent.
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14
NCP1201
As shown below, the fault logic is armed once V crosses
V ), but in presence of a broken optocoupler, i.e. feedback
out
CC
10 V after startup phase. When powering the device from an
auxiliary winding, meeting this condition can sometimes be
is open, V increases and the fault will never triggered! To
CC
avoid this problem, the application note “Tips and Tricks
with NCP1200, AN8069/D” offers some possible solutions
where the DSS is kept for protection logic operation only but
all the driving power is derived from the auxiliary winding.
Some solutions even offer the ability to disable the DSS in
standby and benefit to low standby power.
problematic since upon startup, V naturally goes up and
CC
not down as with a DSS. As a result, V never crosses 10 V
CC
and the fault logic is not activated. If a short−circuit takes
place, the fault circuitry activates as soon as V collapses
CC
below 10 V (because of the coupling between V
and
aux
V
CC
Regulation
occurs here
12 V
10 V
No synchronization
between DSS and
fault event
Time
Overload is
not activated
Overload is
activated
Drv
Driver
Pulses
Latched−off
Time
Time
Open−loop
FB level
FB
Regulation
Fault occurs here
Figure 34. Fault Protection Timing Diagram
Calculating the V Capacitor
that this time corresponds to 6.0 ms. Therefore a V fall
CC
CC
As the above section describes, the fall down sequence
time of 10 ms could be well appropriated in order to not
trigger the overload detection circuitry. If the corresponding
IC consumption, including the MOSFET drive, establishes
at 1.8 mA for instance, we can calculate the required
DV C
depends upon the V level, i.e. how long does it take for the
CC
V
line to decrease from 12.5 V to 10.5 V. The required
CC
time depends on the powerup sequence of your system, i.e.
when you first apply the power to the device. The
corresponding transient fault duration due to the output
capacitor charging must be less than the time needed to
discharge from 12.5 V to 10.5 V, otherwise the supply will
not properly startup. The test consists in either simulating or
measuring in the laboratory to determine time required for
the system to reach the regulation at full load. Let’s assume
capacitor using the following formula: Dt +
, with
i
DV = 2.0 V. Then for a wanted Dt of 10 ms, C equals 9.0 mF
or 10 mF for a standard value. When an overload condition
occurs, the IC blocks its internal circuitry and its
consumption drops to 575 mA typical. This explains the V
CC
falling slope changes after latchoff in Figure 34.
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15
NCP1201
Protecting the Controller Against Negative
Spikes
fed by its V capacitor and keeps activating the MOSFET
CC
ON and OFF with a peak current limited by Rsense.
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
Unfortunately, if the quality coefficient Q of the resonating
network formed by Lp and Cbulk is low (e.g. the MOSFET
Rdson + Rsense are small), conditions are met to make the
circuit resonate and thus negatively bias the controller. Since
we are talking about ms pulses, the amount of injected
charge (Q = I x t) immediately latches the controller which
brutally discharges its V capacitor. If this V capacitor
CC
CC
path is offered between V and GND. If the current sense
is of sufficient value, its stored energy damages the
controller. Figure 35 depicts a typical negative shot
CC
pin is often the seat of such spurious signals, the
high−voltage pin can also be the source of problems in
certain circumstances. During the turn−off sequence, e.g.
when the user unplugs the power supply, the controller is still
occurring on the HV pin where the brutal V discharge
CC
testifies for latchup.
Figure 35. A negative spike takes place on the Bulk capacitor at the switch−off sequence
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 36). Please note that the negative
spike is clamped to –2 x Vf due to the diode bridge. Please
refer to AND8069 for power dissipation calculations.
Another option (Figure 37) consists in wiring a diode from
to the bulk capacitor to force V to reach UVLOlow
sooner and thus stops the switching activity before the bulk
capacitor gets deeply discharged. For security reasons, two
diodes can be connected in series.
V
CC
CC
3
Rbulk
> 4.7 k
2
3
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
D3
1N4007
+
+
Cbulk
Cbulk
1
1
+
CV
+
CV
CC
CC
Figure 36. A simple resistor in series avoids any
latchup in the controller
Figure 37. or a diode forces VCC to reach
UVLOlow sooner
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16
NCP1201
ORDERING INFORMATION
Device
†
Package
Shipping
NCP1201P60
PDIP−8
50 Units / Rail
2500 Units / Reel
2500 Units / Reel
NCP1201D60R2
SOIC−8
NCP1201D60R2G
SOIC−8
(Pb−Free)
NCP1201P100
PDIP−8
50 Units / Rail
50 Units / Rail
NCP1201P100G
PDIP−8
(Pb−Free)
NCP1201D100R2
SOIC−8
2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NCP1201
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AC
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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18
NCP1201
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
1
4
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
_
1.01
−−−
0.030
10
_
0.040
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
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19
NCP1201
The product described herein (NCP1201), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may
be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NCP1201/D
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