NCP1217P65G [ONSEMI]
Enhanced PWM Current−Mode Controller for High−Power Universal Off−Line Supplies; 增强型PWM电流模式控制器的高功率通用离线用品
| 型号： | NCP1217P65G |
| 厂家： | 
ONSEMI |
| 描述： | Enhanced PWM Current−Mode Controller for High−Power Universal Off−Line Supplies |
| 文件： | 总18页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1217, NCP1217A
Enhanced PWM Current−Mode
Controller for High−Power
Universal Off−Line Supplies
Housed in an SO−8 or PDIP−7 package, the NCP1217 represents
the enhanced version of the NCP1203−based controllers. Thanks to its
high drive capability, NCP1217 drives large gate−charge MOSFETs,
which together with internal ramp compensation and built−in
overvoltage protection, ease the design of modern AC/DC adapters.
NCP1217 offers a true alternative to UC384X−based designs.
With an internal structure operating at different fixed frequencies
(65–100–133 kHz), the controller features a high−voltage startup FET,
which ensures a clean and loss less startup sequence. Its current−mode
control topology provides an excellent input audio−susceptibility and
inherent pulse−by−pulse control. Internal ramp compensation easily
prevents subharmonic oscillations from taking place in continuous
conduction mode designs.
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MARKING
DIAGRAMS
8
SOIC−8
D1, D2 SUFFIX
CASE 751
17xxx
ALYW
G
8
1
1
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1217 features two efficient protective circuitries: 1) In
presence of an overcurrent condition, the output pulses are disabled
and the device enters a safe burst mode, trying to restart. Once the
default has gone, the device auto−recovers. 2) If an external signal
(e.g. a temperature sensor) pulls Pin 1 above 3.2 V, output pulses are
immediately stopped and the NCP1217 stays latched in this position.
P1217xxxx
AWL
YYWWG
PDIP−8
N SUFFIX
CASE 626
8
1
1
xxxx
A
L, WL
Y, YY
= Specific Device Code
= Assembly Location
= Wafer Lot
Reset occurs when the V collapses to ground, e.g. the user unplugs
CC
the power supply.
= Year
W, WW = Work Week
Features
G or G
= Pb−Free Package
• Current−Mode with Adjustable Skip−Cycle Capability
• Built−in Internal Ramp Compensation
• Auto−Recovery Internal Output Short−Circuit Protection
• Internal 1.0 ms Soft−Start (NCP1217A Only)
• Limited Duty−Cycle to 50% (NCP1217A Only)
• Full Latchoff if Adjustment Pin is Brought High
• Extremely Low No−Load Standby Power
• Internal Temperature Shutdown
PIN CONNECTIONS
Adj
1
2
3
4
8
7
6
5
HV
NC
V
FB
CS
CC
GND
Drv
• 500 mA Peak Current Capability
(Top View)
• Fixed Frequency Versions at 65 kHz, 100 kHz and 133 kHz
• Direct Optocoupler Connection
DEVICE MARKING INFORMATION
See detailed device marking information in the ordering
information section on page 16 of this data sheet.
• Internal Leading Edge Blanking
• SPICE Models Available for TRANsient and AC Analysis
• Pb−Free Packages are Available
Typical Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 16 of this data sheet.
• High Power AC/DC Converters for TVs, Set−Top Boxes, etc.
• Offline Adapters for Notebooks
• Telecom DC−DC Converters
• All Power Supplies
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
September, 2005 − Rev. 4
NCP1217/D
NCP1217, NCP1217A
See Application
Section
V
OUT
+
Aux.
+
NCP1217
Adj HV
1
2
3
4
8
7
6
5
FB
CS V
CC
EMI
FILTER
Gnd Drv
UNIVERSAL
INPUT
Ramp Adjustment
+
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
Adj
Adjust the skipping peak current This pin lets you adjust the level at which the cycle skipping process takes
place. Shorting this pin to ground permanently disables the skip cycle
feature.
By bringing this pin above 3.1 V, you permanently shut off the device.
2
3
FB
CS
Sets the peak current setpoint
Current sense input
By connecting an optocoupler to this pin, the peak current setpoint is ad-
justed accordingly to the output power demand.
This pin senses the primary current and routes it to the internal compara-
tor via an L.E.B. By inserting a resistor in series with the pin, you control
the amount of ramp compensation you need.
4
5
6
7
8
Gnd
Drv
The IC ground
Driving pulses
Supplies the IC
−
−
The driver’s output to an external MOSFET.
V
This pin is connected to an external bulk capacitor of typically 22 ꢀ F.
This unconnected pin ensures adequate creepage distance.
Connected to the high−voltage rail, this pin injects a constant current into
CC
NC
HV
Ensures a clean and lossless
startup sequence
the V capacitor during the startup sequence.
CC
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2
NCP1217, NCP1217A
Latchoff
Comparator
Adj
1
HV
8
+
−
HV Current
Source
+
−
Set
Reset
Latch
UVLO
3.1 V
Skip Cycle
Comparator
80 k
1.1 V
24 k
NC
7
FB
2
+
−
UVLO High and Low
Internal V
CC
Reset
Current
Sense
V
Q Flip−Flop
CC
Set
DCmax = 74%
Q
250 ns
L.E.B.
65−100−133 kHz
Clock
Overload
Management
3
6
Reset
19 k
Ramp
Compensation
+
−
20 k
57 k
Drv
5
Ground
4
V
REF
1ms SS*
+
−
25 k
500 mA
1 V
* Available for “A” version only
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Symbol
Value
16
Unit
V
Power Supply Voltage
V
CC
Power Supply Voltage on All Other Pins Except Pin 8 (HV), Pin 6 (V ) and Pin 5 (Drv)
−
−0.3 to 10
500
V
CC
Maximum Voltage on Pin 8 (HV), Pin 6 (V ) Decoupled to Ground with 10 ꢀ F
V
V
V
CC
HV
HV
Maximum Voltage on Pin 8 (HV), Pin 6 (V ) Grounded
450
V
CC
Maximum Current into All Pins Except V (6) and HV (8) when 10 V ESD Diodes are Activated
−
5.0
mA
°C/W
°C/W
CC
Thermal Resistance, Junction−to−Case
R
57
ꢁ
JC
Thermal Resistance, Junction−to−Air, PDIP−7 Version
Thermal Resistance, Junction−to−Air, SO−8 Version
R
R
100
178
ꢁ
JA
JA
ꢁ
Maximum Junction Temperature
Temperature Shutdown
T
150
155
°C
°C
°C
°C
kV
V
JMAX
−
Hysteresis in Shutdown
−
−
−
−
30
Storage Temperature Range
−60 to +150
2.0
ESD Capability, HBM Model (All Pins Except V and HV)
CC
ESD Capability, Machine Model
200
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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3
NCP1217, NCP1217A
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = 0°C to +125°C, Max T = 150°C,
J
J
J
V
= 11 V unless otherwise noted.)
CC
Characteristic
SUPPLY SECTION (All frequency versions, unless otherwise noted)
Pin
Symbol
Min
Typ
Max
Unit
Turn−On Threshold Level, V Going Up
6
6
6
6
VCC
VCC
11.8
6.9
−
12.8
7.6
13.8
8.3
−
V
V
CC
ON
Minimum Operating Voltage After Turn−On
min
V
Decreasing Level at which the Latchoff Phase Ends
VCC
5.6
V
CC
latch
Internal IC Consumption, No Output Load on Pin 5,
= 65 kHz
ICC1
−
960
1110
(Note 1)
ꢀ
A
F
SW
Internal IC Consumption, No Output Load on Pin 5,
= 100 kHz
6
6
6
6
6
6
ICC1
ICC1
ICC2
ICC2
ICC2
ICC3
−
−
−
−
−
−
1020
1060
1.7
1180
(Note 1)
ꢀ A
ꢀ A
F
SW
Internal IC Consumption, No Output Load on Pin 5,
= 133 kHz
1200
(Note 1)
F
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
= 65 kHz
2.0
(Note 1)
mA
mA
mA
ꢀ A
F
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
= 100 kHz
2.1
2.4
(Note 1)
F
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
= 133 kHz
2.4
2.9
(Note 1)
F
SW
Internal IC Consumption, Latchoff Phase, V = 6.0 V
230
−
CC
INTERNAL STARTUP CURRENT SOURCE (T u 0°C)
J
High−Voltage Current Source, V = 10 V
8
8
IC1
IC2
3.5
(Note 2)
6.0
7.0
7.8
−
mA
mA
CC
High−Voltage Current Source, V = 0
−
CC
DRIVE OUTPUT
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of a 12 V
Output Signal
5
5
T
−
−
60
20
−
−
ns
ns
r
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of a 12 V
Output Signal
T
f
Source Resistance
5
5
R
15
20
10
35
18
ꢂ
ꢂ
OH
Sink Resistance
R
5.0
OL
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
3
3
3
3
3
I
−
0.9
−
0.02
1.0
−
1.1
−
ꢀ A
V
IB
I
Limit
Default Internal Current Setpoint for Skip Cycle Operation
Propagation Delay from Current Detection to Gate OFF State
Leading Edge Blanking Duration
I
330
90
mV
ns
ns
Lskip
T
DEL
T
LEB
−
150
−
−
250
INTERNAL OSCILLATOR (V = 11 V, Pin 5 Loaded by 1.0 kꢂ)
CC
Oscillation Frequency, 65 kHz Version
Oscillation Frequency, 100 kHz Version
Oscillation Frequency, 133 kHz Version
Maximum Duty−Cycle, NCP1217
−
−
−
−
−
f
f
f
58.5
90
65
100
133
74
71.5
110
146
80
kHz
kHz
kHz
%
OSC
OSC
OSC
120
69
Dmax
Dmax
Maximum Duty−Cycle, NCP1217A
42
46.5
50
%
1. Maximum Value @ T = 0°C.
J
2. Minimum Value @ T = 125°C.
J
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NCP1217, NCP1217A
ELECTRICAL CHARACTERISTICS (continued) (For typical values T = 25°C, for min/max values T = 0°C to +125°C,
J
J
Max T = 150°C, V = 11 V unless otherwise noted.)
J
CC
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
FEEDBACK SECTION (V = 11 V, Pin 5 Loaded by 1.0 kꢂ)
CC
Internal Pull−Up Resistor
2
−
Rup
−
−
19
−
−
kꢂ
Pin 2 (FB) to Internal Current Setpoint Division Ratio
SKIP CYCLE GENERATION
Iratio
3.3
−
Default Skip Mode Level
1
1
Vskip
Zout
0.93
−
1.1
27
1.26
−
V
Pin 1 Internal Output Impedance
kꢂ
INTERNAL RAMP COMPENSATION
Internal Ramp Level @ 25°C (Note 3)
Internal Ramp Resistance to CS Pin
ADJUSTMENT LATCHOFF LEVEL
Latching Level
3
3
Vramp
Rramp
2.6
−
2.9
19
3.2
−
V
kꢂ
1
Vlatch
2.69
3.10
3.42
V
3. A 1.0 Mꢂ resistor is connected to the ground for the measurement.
TYPICAL CHARACTERISTICS
80
70
60
14.0
13.5
13.0
12.5
12.0
11.5
11.0
50
40
30
20
10
0
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. High Voltage Pin Leakage Current vs.
Temperature
Figure 4. VCCOFF vs. Temperature
9.0
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
8.5
8.0
133 kHz
100 kHz
65 kHz
7.5
7.0
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VCCMIN vs. Temperature
Figure 6. ICC 1.0 nF Load vs. Temperature
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NCP1217, NCP1217A
TYPICAL CHARACTERISTICS (continued)
150
130
110
5.90
133 kHz
100 kHz
5.80
5.70
5.60
5.50
5.40
5.30
90
70
50
65 kHz
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Switching Frequency vs.
Temperature
Figure 8. VCClatch vs. Temperature
500
450
400
350
300
250
200
30
25
20
15
10
5
0
−50
−50
0
50
100
150
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. ICC3 vs. Temperature
Figure 10. Drive Source Resistance vs.
Temperature
30
25
20
15
10
5
1.10
1.05
1.00
0.95
0.90
0
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Drive Sink Resistance vs.
Temperature
Figure 12. Current Sense Limit vs.
Temperature
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NCP1217, NCP1217A
TYPICAL CHARACTERISTICS (continued)
1.20
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
1.15
1.10
1.05
1.00
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Skip Mode Level vs. Temperature
Figure 14. Int Comp Ramp Max Level vs.
Temperature
8.0
7.0
6.0
5.0
4.0
3.0
−50
0
50
TEMPERATURE (°C)
100
150
Figure 15. High Voltage Current Source
(@ VCC = 10V) vs. Temperature
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NCP1217, NCP1217A
APPLICATION INFORMATION
Introduction
help reducing magnetics or improve the EMI signature
before reaching the 150 kHz starting point.
The NCP1217 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count is the key parameter,
particularly in low−cost AC/DC adapters, TV power
supplies, etc. Due to its high−performance High−Voltage
technology, the NCP1217 incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, low−pass filter and
startup device but also enhances the original component
by offering: 1) an externally triggerable latchoff
2) ramp compensation and finally, 3) short−circuit
protection. Due to its high−voltage current source,
ON Semiconductor’s NCP1217 does not need an external
startup resistance but supplies the startup current directly
from the high−voltage rail. On the other hand, more and
more applications are requiring low no−load standby power,
e.g. for AC/DC adapters, VCRs, etc. UC384X series have a
lot of difficulty to reduce the switching losses at low power
levels. NCP1217 elegantly solves this problem by skipping
unwanted switching cycles at a user−adjustable power level.
By ensuring that skip cycles take place at low peak current,
the device ensures quiet, noise−free operation:
Overcurrent Protection (OCP): By continuously
monitoring the V auxiliary winding voltage, NCP1217
CC
enters burst mode as soon as the power supply undergoes an
overload: when the V voltage goes down until it crosses
CC
the undervoltage lockout level (VCC ). When the
min
NCP1217 reaches this level (typically 7.6 V), it stops the
switching pulses until the V pin voltage reaches VCC
CC
latch
(5.6 V). At VCC
, the NCP1217 attempts to restart. As
latch
soon as the default disappears, the power supply resumes
operation.
Overvoltage Protection (OVP): If pin1 is brought to a level
higher than the internal 3.2 V reference voltage, the
controller is permanently shut down until the user cycles the
VCC OFF and ON again. This allows the building of
efficient and low−cost over voltage protection circuits.
Wide Duty−Cycle Operation: Wide mains operation
requires a large duty−cycle excursion. The NCP1217 can go
up to 74% typically.
Low Standby−Power: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less efficient
when the output power demand diminishes. By skipping
unneeded switching cycles, the NCP1217 drastically
reduces the power wasted during light load conditions. In
no−load conditions, the NPC1217 allows the total standby
power to easily reach next International Energy Agency
(IEA) recommendations.
Current−Mode Operation: As the UC384X series, the
NCP1217 features a well−known current mode control
architecture which provides superior input audio−
susceptibility compared to traditional voltage−mode
controllers. Primary current pulse−by−pulse checking
together with a fast over current comparator offers greater
security in the event of a difficult fault condition, e.g. a
saturating transformer.
No Acoustic Noise While Operating: Instead of skipping
cycles at high peak currents, the NCP1217 waits until the
peak current demand falls below a user−adjustable 1/3 of the
maximum limit. As a result, cycle skipping can take place
without having a singing transformer … You can thus select
cheap magnetic components free of noise problems.
Ramp Compensation: By inserting a resistor between the
current−sense (CS) pin and the actual sense resistor, it
becomes possible to inject a given amount of ramp
compensation since the internal saw tooth clock is routed to
the CS pin. Subharmonic oscillations in Continuous
Conduction Mode (CCM) can thus be compensated via a
single resistor.
External MOSFET Connection: By leaving the external
MOSFET external to the IC, you can select avalanche proof
devices, which in certain cases (e.g. low output powers), let
you work without an active clamping network. Also, by
controlling the MOSFET gate signal flow, you have an
option to slow down the device commutation, therefore
reducing the amount of ElectroMagnetic Interference
(EMI).
Adjustable Skip Cycle Level: By offering the ability to
tailor the level at which the skip cycle takes place, the
designer can make sure that the skip operation only occurs
at low peak current. This point guarantees a noise−free
operation with cheap transformers. Skip cycle offers a
proven mean to reduce the standby power in no or light loads
situations.
SPICE Model: A dedicated model to run transient
cycle−by−cycle simulations is available but also an
averaged version to help you closing the loop. Ready−to−use
templates can be downloaded in OrCAD’s Pspice and
INTUSOFT’s IsSpice from ON Semiconductor web site,
NCP1217 related section.
Wide Switching−Frequency Offer: Three different options
are available: 65 kHz – 100 kHz–133 kHz. Depending on
the application, the designer can pick up the right device to
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NCP1217, NCP1217A
Startup Sequence
12.8 V), the current source turns off and no longer wastes
When the power supply is first powered from the mains
outlet, the internal current source (typically 7.0 mA) is
any power. At this time, the V capacitor only supplies the
CC
controller and the auxiliary supply is supposed to take over
before V collapses below VCC . Figure 16 shows the
biased and charges up the V capacitor. When the voltage
CC
CC
min
on this V capacitor reaches the VCC level (typically
internal arrangement of this structure.
CC
ON
8
HV
+
−
12.8 V/5.6 V
6 mA or 0
6
4
Aux
CV
CC
Figure 16. The Current Source Brings VCC Above 12.8 V and then Turns Off
Once the power supply has started, the V
constrained below 16 V, which is the maximum rating on
Pin 6. Figure 17 portrays a typical startup sequence with a
shall be
level, preventing a bias current to circulate in the
optocoupler LED. As a result, the auxiliary voltage also
decreases because it also operates in Flyback and thus
duplicates the output voltage, providing the leakage
inductance between windings is kept low. To account for this
situation and properly protect the power supply, NCP1217
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty−cycle. The system auto−recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. The auxiliary voltage takes place
after a few switching cycles and self−supplies the IC. In
presence of a short circuit on the output, the auxiliary
voltage will go down until it crosses the undervoltage
lockout level of typically 7.6 V. When this happens,
NCP1217 immediately stops the switching pulses and
unbiases all unnecessary logical blocks. The overall
consumption drops, while keeping the gate grounded, and
CC
V
regulated at 12.5 V.
CC
13.5
12.5
11.5
10.5
9.5
REGULATION
12.8 V
3.00 M
8.00 M
13.0 M
18.0 M
23.0 M
t, TIME (sec)
Figure 17. A Typical Startup Sequence for
the NCP1217
the V slowly falls down. As soon as V reaches typically
CC
CC
5.6 V, the startup source turns−on again and a new startup
sequence occurs, bringing V toward 12.8 V as an attempt
CC
Overload Operation
to restart. If the default has gone, then the power supply
normally restarts. If not, a new protective burst is initiated,
shielding the SMPS from any runaway. Figure 18 portrays
the typical operating signals in short circuit.
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
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NCP1217, NCP1217A
VCC
= 12.8 V
ON
VCC
= 7.6 V
min
V
CC
VCC
= 5.6 V
latch
DRIVING PULSES
Figure 18. Typical Waveforms in Short Circuit Conditions
Calculating the VCC Capacitor
The theoretical power transfer is therefore:
The V
capacitor can be calculated knowing the IC
1
2
CC
2
· Lp · Ip · Fsw + 4.1 W. If this IC enters skip cycle
consumption as soon as V reaches 12.8 V. Suppose that a
CC
mode with a bunch length of 10 ms over a recurrent
period of 100 ms, then the total power transfer is:
4.1 * 0.1 + 410 mW.
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight.
NCP1217P065 is used and drives a MOSFET with a 30 nC
total gate charge (Qg). The total average current is thus
made of ICC1 (750 ꢀ A) plus the driver current,
Fsw * Qg + 1.95 mA. The total current is therefore 2.7 mA.
TheꢃV available to fully startup the circuit (e.g. never reach
the 8.2 V VCC
during power on) is 13.7−8.2 + 5.5 V
min
best case or 4.9 V worse case (11.9−7.0). We have a
capacitor that then needs to supply the NCP1217 with
2.7 mA during a given time until the auxiliary supply takes
over. Suppose that this time was measured at around 15 ms.
ꢃt · i
FB
4.2 V, FB Pin Open
3.2 V, Upper
Dynamic Range
NORMAL CURRENT
MODE OPERATION
CV
is calculated using the equation C +
or
CC
ꢃ
V
C w 8.3 ꢀF. Select a 22 ꢀ F/25 V and this will fit.
1 V
Skipping Cycle Mode
SKIP CYCLE OPERATION
The NCP1217 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level (Vpin 1), the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 20).
Suppose we have the following component values:
I
= 333 mV/R
P(min) SENSE
Time
Figure 19.
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/Rsense.
When the IC enters the skip cycle mode, the peak current
cannot go below Vpin1/3.3. The user still has the flexibility
to alter this 1.0 V by either shunting pin 1 to ground through
a resistor or raising it through a resistor up to the desired
level. In this later case, care must be taken to keep sufficient
margin between this pin 1 adjustment level and the latchoff
level. Grounding pin 1 permanently invalidates the skip
cycle operation.
Lp, primary inductance = 350 ꢀ H
Fsw, switching frequency = 65 kHz
Ip skip = 600 mA (or 333 mV/Rsense)
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NCP1217, NCP1217A
Power P1
Power P2
Power P3
Figure 20. Output Pulses at Various Power Levels (X = 5.0 ms/div) P1 t P2 t P3
MAX PEAK
CURRENT
300 M
200 M
100 M
0
SKIP CYCLE
CURRENT LIMIT
315.40 U
882.70 U
1.450 M
2.017 M
2.585 M
Figure 21. The Skip Cycle Takes Place at Low Peak Currents which Guarantees Noise−Free Operation
Sufficient margin shall be kept between normal Pin1 level and the latchoff point in order to avoid false triggering.
Ramp Compensation
Continuous Conduction Mode (CCM) with a duty−cycle
greater than 50%. To lower the current loop gain, one usually
injects between 50 and 100% of the inductor down−slope.
Figure 22 depicts how internally the ramp is generated.
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
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11
NCP1217, NCP1217A
Duty Cycle Typ = 74%
2.9 V
Latching Off the NCP1217
Total latched shutdown can easily be implemented
through a simple PNP bipolar transistor as depicted by
Figure 23. When OFF, Q1 is transparent to the operation.
When forward biased, the transistor pulls the Adj pin toward
0 V
V
and permanently latches−off the IC as soon Vadj goes
19 k
CC
Rcomp
above the latching level (typical 3.1 V). Figure 23 shows
how to wire the bipolar transistor to activate the latchoff. A
typical candidate for Q1 could be an MMBT3906 from
ON Semiconductor.
+
−
L.E.B.
CS
Rsense
V
From
Setpoint
CC
Figure 22. Inserting a Resistor in Series with the Current
Sense Information Brings Ramp Compensation
Off
Q1
In the NCP1217, the ramp features a swing of 2.9 V with
a duty cycle max at 74%. Over a 65 kHz frequency, for
instance, it corresponds to a 254 mV/ꢀ s ramp. In our
FLYBACK design, let’s suppose that our primary
inductance Lp is 350 ꢀ H, delivering 12 V with a Np:Ns ratio
of 1:0.1. The OFF time primary current slope is thus given
Rlimit
1
2
3
4
8
7
6
5
Np
(Vout ) Vf) ·
by:
Ns + 371 mAńꢀs or 37 mVńꢀ s when
Lp
CV
CC
projected over an Rsense of 0.1 ꢂ, for instance. If we select
75% of the downslope as the required amount of ramp
compensation, then we shall inject 27 mV/ꢀ s. Our
internal compensation being of 254 mV/ꢀ s, the divider
ratio (divratio) between Rcomp and the 19 kꢂ is 0.106.
Figure 23. A Simple Bipolar Transistor Totally
Disables the IC
A
few lines of algebra to determine Rcomp:
19 k · divratio
(1−divratio)
+ 2.26 kꢂ.
V
CC
The startup current source keeps the
device latched until reset occurs.
VCC
= 12.8 V
ON
VCC
= 7.6 V
= 5.6 V
min
VCC
latch
Reset level
Time
Drv
Driver
Pulses
Latched−off
Time
Adj
Default
adj level
Fault brings adj above latching level
Time
Figure 24. When Vadj is Pulled Above 3.1 V, NCP1217 Permanently Latches−Off the Output Pulses
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12
NCP1217, NCP1217A
In normal operation, the Adj pin level is kept at a fixed
output pulses are disabled as long as FB is pulled below
Pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 26 depicts the application example.
level, the default one or lower. As soon as some external
signal pulls this Adj pin level above 3.1 V typical, the output
pulses are permanently disabled. Care must be taken to limit
the injected current into pin 1 to less than 2.0 mA, e.g.
1
2
3
4
8
7
6
5
through a series resistor of 5.6 k with a 10 V V . The
CC
startup switch is activated every time V reaches 5.6 V and
CC
maintains a V voltage ramping up and down between
CC
Q1
ON/OFF
5.6 V and 12.8 V. Reset occurs when V falls below 5.6 V,
CC
e.g. when the user cycle the SMPS down. Figure 25
illustrates the operation. Adding a zener diode from Q1 base
to ground makes a cheap OVP, protecting the supply from
any lethal open−loop operation. If a thermistor (NTC) is
added in parallel with the Zener−diode, overtemperature
protection is also ensured.
Figure 26. Another Way of Shutting Down the IC
Without a Definitive Latchoff State
Vaux
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
1
2
3
4
8
7
6
5
OVP
t16 V
T
offered between V and GND. If the current sense pin is
CC
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
Laux
CV
CC
power supply, the controller is still fed by its V capacitor
CC
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
coefficient Q of the resonating network formed by Lp and
Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge (Q = I * t) immediately
Figure 25. A Thermistor and a Zener Diode Offer
Both OVP and Overtemperature Latched−Off
Protection
Nonlatching Shutdown
latches the controller that brutally discharges its V
CC
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj Pin 1 level, the
capacitor. If this V capacitor is of sufficient value, its
CC
stored energy damages the controller. Figure 27 depicts a
typical negative shot occurring on the HV pin where the
brutal V discharge testifies for latchup.
CC
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13
NCP1217, NCP1217A
Vcc 5 V/DIV
Vlatch 1 V/DIV
Time 10 ms/DIV
Figure 27. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−Off Sequence
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 28). Please note that the negative
spike is clamped to (−2*Vf) thanks to the diode bridge. Also,
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
Another option (Figure 29) consists in wiring a diode
from V to the bulk capacitor to force V to reach
CC
CC
VCC sooner and thus stops the switching activity before
ON
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
3
Rbulk
u4.7 k
+
+
2
3
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
D3
1N4007
Cbulk
Cbulk
1
+
1
+
CV
CV
CC
CC
Figure 28. A simple resistor in series avoids any
latch−up in the controller . . .
Figure 29. . . . or one diode forces VCC to reach
VCCON sooner.
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NCP1217, NCP1217A
Soft−Start (NCP1217A only)
The NCP1217A features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
also activated during the Over Current Burst (OCP)
sequence. Every restart attempt is followed by a soft−start
activation. Generally speaking, the soft−start will be
V
CC
reaches VCC , the peak current is gradually
activated when V
ramps up either from zero (fresh
OFF
CC
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). This situation lasts during 1.0 ms and
further to that time period, the peak current limit is blocked
to 1.0 V until the supply enters regulation. The soft−start is
power−on sequence) or 5.6 V, the latchoff voltage occurring
during OCP. Figure 30 portrays the soft−start behavior. The
time scales are purposely shifted to offer a better zoom
portion.
Figure 30. Soft−start is activated during a startup sequence or an OCP condition
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15
NCP1217, NCP1217A
ORDERING INFORMATION
Device
†
Version
Marking
17D06
Package
Shipping
NCP1217D65R2
65 kHz
65 kHz
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
NCP1217D65R2G
17D06
SO−8
(Pb−Free)
NCP1217D100R2
NCP1217D100R2G
100 kHz
100 kHz
17D10
17D10
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
SO−8
(Pb−Free)
NCP1217D133R2
NCP1217D133R2G
133 kHz
133 kHz
17D13
17D13
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
SO−8
(Pb−Free)
NCP1217P65
65 kHz
65 kHz
P1217P065
P1217P065
PDIP−7
50 Units / Rail
50 Units / Rail
NCP1217P65G
PDIP−7
(Pb−Free)
NCP1217P100
100 kHz
100 kHz
P1217P100
P1217P100
PDIP−7
50 Units / Rail
50 Units / Rail
NCP1217P100G
PDIP−7
(Pb−Free)
NCP1217P133
133 kHz
133 kHz
P1217P133
P1217P133
PDIP−7
50 Units / Rail
50 Units / Rail
NCP1217P133G
PDIP−7
(Pb−Free)
NCP1217AD65R2
NCP1217AD65R2G
65 kHz
65 kHz
17A06
17A06
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
SO−8
(Pb−Free)
NCP1217AD100R2
NCP1217AD100R2G
100 kHz
100 kHz
17A10
17A10
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
SO−8
(Pb−Free)
NCP1217AD133R2
NCP1217AD133R2G
133 kHz
133 kHz
17A13
17A13
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
SO−8
(Pb−Free)
NCP1217AP65
65 kHz
65 kHz
P1217AP06
P1217AP06
PDIP−7
50 Units / Rail
50 Units / Rail
NCP1217AP65G
PDIP−7
(Pb−Free)
NCP1217AP100
100 kHz
100 kHz
P1217AP10
P1217AP10
PDIP−7
50 Units / Rail
50 Units / Rail
NCP1217AP100G
PDIP−7
(Pb−Free)
NCP1217AP133
133 kHz
133 kHz
P1217AP13
P1217AP13
PDIP−7
50 Units / Rail
50 Units / Rail
NCP1217AP133G
PDIP−7
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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16
NCP1217, NCP1217A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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17
NCP1217, NCP1217A
PACKAGE DIMENSIONS
PDIP−7
P SUFFIX
CASE 626B−01
ISSUE A
NOTES:
J
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION L TO CENTER OF LEAD
WHEN FORMED PARALLEL.
8
5
M
4. PACKAGE CONTOUR OPTIONAL
(ROUND OR SQUARE CORNERS).
5. DIMENSIONS A AND B ARE DATUMS.
B
L
1
4
MILLIMETERS
DIM MIN
MAX
A
B
C
D
F
9.40 10.16
F
6.10
3.94
0.38
1.02
6.60
4.45
0.51
1.78
A
NOTE 2
G
H
J
K
L
2.54 BSC
0.76
0.20
2.92
1.27
0.30
3.43
C
7.62 BSC
M
N
−−−
0.76
10 °
1.01
−T−
SEATING
PLANE
N
H
D
K
G
M
M
M
B
0.13 (0.005)
T A
The product described herein (NCP1217), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357.
There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NCP1217/D
相关型号：
NCP1217_10
Enhanced PWM Current--Mode Controller for High--Power Universal Off--Line Supplies
ONSEMI
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