NCP1271 [ONSEMI]
Soft−Skip Mode Standby PWM Controller with Adjustable Skip Level and External Latch; 软跳过待机模式PWM控制器，可调节跳过级和外部锁存器
| 型号： | NCP1271 |
| 厂家： | 
ONSEMI |
| 描述： | Soft−Skip Mode Standby PWM Controller with Adjustable Skip Level and External Latch |
| 文件： | 总19页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1271
Soft−Skipt Mode Standby
PWM Controller with
Adjustable Skip Level and
External Latch
http://onsemi.com
The NCP1271 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent stand by power consumption by use of
its adjustable Soft−Skip mode and integrated high voltage startup
FET. This proprietary Soft−Skip also dramatically reduces the risk of
acoustic noise. This allows the use of inexpensive transformers and
capacitors in the clamping network. Internal frequency jittering,
ramp compensation, timer−based fault detection and a latch input
make this controller an excellent candidate for converters where
ruggedness and component cost are the key constraints.
MARKING
DIAGRAMS
8
SOIC−7
D SUFFIX
CASE 751U
1271x
ALYWG
G
1
x
= A or B
A= 65 kHz
B= 100 kHz
Features
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Fixed−Frequency Current−Mode Operation with Ramp
Compensation and Skip Cycle in Standby Condition
• Timer−Based Fault Protection for Improved Overload Detection
• “Soft−Skip Mode” Technique for Optimal Noise Control in Standby
• Internal High−Voltage Startup Current Source for Lossless Startup
• "5% Current Limit Accuracy over the Full Temperature Range
• Adjustable Skip Level
• Internal Latch for Easy Implementation of Overvoltage and
Overtemperature Protection
• Frequency Jittering for Softened EMI Signature
• +500 mA/−800 mA Peak Current Drive Capability
• Sub−100 mW Standby Power can be Achieved
• Pin−to−Pin Compatible with the Existing NCP120X Series
• This is a Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTIONS
SOIC−7
1
2
3
4
8
Skip/latch
FB
HV
6
5
CS
V
CC
Drv
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Typical Applications
• AC−DC Adapters for Notebooks, LCD Monitors
• Offline Battery Chargers
• Consumer Electronic Appliances STB, DVD, DVDR
dimensions section on page 18 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
downloadthe ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 2
NCP1271/D
NCP1271
+
EMI
AC
Output
Input
Filter
Voltage
−
latch input*
skip/latch
FB
HV
CS
Gnd
Vcc
Drv
*Optional
*
NCP1271
R
ramp
R
skip
Figure 1. Typical Application Circuit
MAXIMUM RATINGS (Notes 1 and 2)
Rating
Symbol
Value
Unit
V
CC
Pin (Pin 6)
Maximum Voltage Range
Maximum Current
V
I
−0.3 to +20
100
V
mA
max
max
Skip/Latch, FB, CS Pin (Pins 1−3)
Maximum Voltage Range
Maximum Current
V
I
−0.3 to +10
100
V
mA
max
max
Drv Pin (Pin 5)
Maximum Voltage Range
Maximum Current
V
I
−0.3 to +20
−800 to +500
V
mA
max
max
HV Pin (Pin 8)
Maximum Voltage Range
Maximum Current
V
I
−0.3 to +500
100
V
mA
max
max
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction−to−Air, SO−7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction−to−Lead, SO−7, Low Conductivity PCB
Thermal Resistance, Junction−to−Air, SO−7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction−to−Lead, SO−7, High Conductivity PCB
R
177
75
136
69
°C/W
°C/W
°C/W
°C/W
q
JA
R
R
q
JL
q
JA
R
q
JL
Operating Junction Temperature Range
Maximum Storage Temperature Range
T
−40 to +125
−60 to +125
°C
°C
J
T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains ESD protection and exceeds the following tests:
Pins 1−6: Human Body Model 2000 V per Mil−Std−883, Method 3015
Machine Model Method 150 V (on Pins 5 and 6) and 200 V (all other pins)
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
2. Guaranteed by design, not tested.
2
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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2
NCP1271
8 V
I
skip
latch−off, reset
when Vcc < 4V
Skip/ latch
−
+
13 us filter
S
R
1
8
HV
Q
4.1 mA when Vcc > 0.6 V
0.2 mA when Vcc < 0.6 V
R
10V
skip
V
V
skip
V
V
= R
* I
or
skip
skip
skip skip
= 1.2 V when pin 1 is opened
skip
+
−
turn off
FB
4.8 V
16.7k
2.85 V
12.6/
5.8 V
disable
soft
TLD
V
soft−skip
FB
FB
−
+
skip
2
−
+
S
V
ss
Soft start/ soft−skip
management
4 ms/ 300 us
75.3k
(1V max)
Q
R
UVLO
soft
start
1 / 3
/ 3
−
+
double
hiccup
130ms
10V
V
V
FB
delay
&
0
1
9.1 V
short
circuit
fault
B2
Counter
V
CC
PWM
−
+
−
+
V
PWM
CS
6
CS
180 ns
LEB
3
&
20V
10V
100uA
0
R
ramp
turn on internal bias
V
OR
jittered ramp
current source
CC
R
CS
Drv
4
Gnd
5
R
S
Q
7.5% Jittering
65, 100 kHz
Oscillator
1
0
driver:
+500 mA
/ −800 mA
Max duty
= 80%
Figure 2. Functional Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1
Skip/latch
Skip Adjust or
Latchoff
A resistor to ground provides the adjustable standby skip level. Additionally, if this pin is
pulled higher than 8.0 V (typical), the controller latches off the drive.
2
3
FB
CS
Feedback
An optocoupler collector pulls this pin low during regulation. If this voltage is less than
the Skip pin voltage, then the driver is pulled low and Soft−Skip mode is activated. If this
pin is open (>3 V) for more than 130 ms, then the controller is placed in a fault mode.
Current Sense
This pin senses the primary current for PWM regulation. The maximum primary current
is limited to 1.0 V / R where R is the current sense resistor. Additionally, a ramp
CS
CS
resistor R
between the current sense node and this pin sets the compensation ramp
ramp
for improved stability.
4
5
6
Gnd
Drv
IC Ground
Driver Output
Supply Voltage
−
The NCP1271’s powerful output is capable of driving the gates of large Qg MOSFETs.
V
CC
This is the positive supply of the device. The operating range is between 10 V (min) and
20 V (max) with a UVLO start threshold 12.6 V (typ).
8
HV
High Voltage
This pin provides (1) Lossless startup sequence (2) Double hiccup fault mode (3)
Memory for latch−off shutdown and (4) Device protection if V is shorted to GND.
CC
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3
NCP1271
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values, T = −40°C to +125°C, V = 14 V,
J
J
CC
HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Oscillation Frequency (65 kHz Version, T = 25_C)
5
f
61.75
58
55
95
89
65
65
65
100
100
100
68.25
69
69
105
107
107
kHz
J
osc
Oscillation Frequency (65 kHz Version, T = −40 to + 85_C)
J
Oscillation Frequency (65 kHz Version, T = −40 to + 125_C)
J
Oscillation Frequency (100 kHz Version, T = 25_C)
J
Oscillation Frequency (100 kHz Version, T = −40 to +85_C)
J
Oscillation Frequency (100 kHz Version, T = −40 to +125_C)
85
J
Oscillator Modulation Swing, in Percentage of f
5
5
5
−
−
−
−
"7.5
6.0
−
−
%
ms
%
osc
Oscillator Modulation Swing Period
Maximum Duty Cycle (V = 0 V, V = 2.0 V)
D
max
75
80
85
CS
FB
GATE DRIVE
Gate Drive Resistance
5
W
Output High (V = 14 V, Drv = 300 W to Gnd)
R
R
6.0
2.0
11
6.0
20
12
CC
OH
Output Low (V = 14 V, Drv = 1.0 V)
CC
OL
Rise Time from 10% to 90% (Drv = 1.0 nF to Gnd)
Fall Time from 90% to 10% (Drv = 1.0 nF to Gnd)
5
5
t
−
−
30
20
−
−
ns
ns
r
t
f
CURRENT SENSE
Maximum Current Threshold
3
−
−
3
−
3
3
I
0.95
−
1.0
4.0
300
180
50
1.05
−
V
Limit
Soft−Start Duration
t
t
ms
ms
ns
ns
mA
mA
SS
Soft−Skip Duration
−
−
SK
Leading Edge Blanking Duration
Propagation Delay (Drv =1.0 nF to Gnd)
Ramp Current Source Peak
Ramp Current Source Valley
t
100
−
330
150
−
LEB
−
I
−
100
0
ramp(H)
I
−
−
ramp(L)
SKIP
Default Standby Skip Threshold (Pin 1 = Open)
2
1
1
2
V
I
−
1.2
43
−
V
mA
V
skip
Skip Current (Pin 1 = 0 V, T = 25_C)
26
56
J
skip
Skip Level Reset (Note 5)
V
5.0
2.6
5.7
2.85
6.5
3.15
skip−reset
Transient Load Detection Level to Disable Soft−Skip Mode
V
TLD
V
EXTERNAL LATCH
Latch Protection Threshold
1
1
1
1
V
7.1
0.6
−
8.0
1.2
13
8.7
−
V
V
latch
Latch Threshold Margin (V
= V
− V
)
V
latch−m
latch−m
CC(off)
latch
Noise Filtering Duration
−
−
ms
ns
Propagation Delay (Drv = 1.0 nF to Gnd)
T
latch
−
100
−
SHORT−CIRCUIT FAULT PROTECTION
Time for Validating Short−Circuit Fault Condition
2
t
−
130
−
ms
protect
5. Please refer to Figure 39 for detailed description.
6. Guaranteed by design.
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NCP1271
ELECTRICAL CHARACTERISTICS (continued) (For typical values T = 25°C, for min/max values, T = −40°C to +125°C,
J
J
V
CC
= 14 V, HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
STARTUP CURRENT SOURCE
High−Voltage Current Source
Inhibit Voltage (I = 200 mA, HV = 50 V)
6
6
6
8
V
190
80
3.0
10
600
200
4.1
25
800
350
6.0
50
mV
mA
mA
mA
CC
inhibit
I
inhibit
I
Inhibit Current (V = 0 V, HV = 50 V)
CC
Startup (V = V
− 0.2 V, HV = 50 V)
CC
CC(on)
HV
I
HV−leak
Leakage (V = 14 V, HV = 500 V)
CC
Minimum Startup Voltage (V = V
– 0.2 V, I = 0.5 mA)
8
V
−
20
28
V
CC
CC(on)
CC
HV(min)
SUPPLY SECTION
V
CC
Regulation
6
Startup Threshold, V Increasing
V
V
11.2
8.2
3.0
5.0
−
12.6
9.1
3.6
5.8
4.0
13.8
10
4.2
6.5
−
V
V
V
V
V
CC
CC(on)
CC(off)
− V
CC(off)
Minimum Operating Voltage After Turn−On
Operating Hysteresis
V
CC
V
CC(on)
Undervoltage Lockout Threshold Voltage, V Decreasing
V
CC
CC(latch)
V
CC(reset)
Logic Reset Level (V
–V
CC(reset)
> 1.0 V) (Note 7)
CC(latch)
V
CC
Supply Current
6
Operating (V = 14 V, 1.0 nF Load, V = 2.0 V, 65 kHz Version)
I
I
I
I
−
−
−
−
2.3
3.1
1.3
500
3.0
3.5
2.0
720
mA
mA
mA
mA
CC
FB
CC1
CC1
CC2
CC3
Operating (V = 14 V, 1.0 nF Load, V = 2.0 V, 100 kHz Version)
CC
FB
Output Stays Low (V = 14 V, V = 0 V)
CC
FB
Latchoff Phase (V = 7.0 V, V = 2.0 V)
CC
FB
7. Guaranteed by design.
TYPICAL CHARACTERISTICS
110
100
90
85
84
100 kHz
83
82
81
80
79
80
70
78
65 kHz
77
76
75
60
50
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. Oscillation Frequency vs.
Temperature
Figure 4. Maximum Duty Cycle vs.
Temperature
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NCP1271
TYPICAL CHARACTERISTICS
16
14
12
10
8
1.04
1.02
1.0
R
OH
0.98
6
R
OL
4
0.96
0.94
2
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Output Gate Drive Resistance vs.
Temperature
Figure 6. Current Limit vs. Temperature
8
7
6
5
4
350
300
250
200
150
100
3
2
1
50
0
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Soft−Start Duration vs. Temperature
Figure 8. Leading Edge Blanking Time vs.
Temperature
1.40
45
44
43
42
41
40
39
38
37
1.30
1.20
1.10
1.00
36
35
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Default Skip Level vs. Temperature
Figure 10. Skip Pin Current vs. Temperature
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NCP1271
TYPICAL CHARACTERISTICS
6.0
5.9
5.8
5.7
3.0
2.9
2.8
2.7
2.6
2.5
5.6
5.5
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Skip Level Reset Threshold vs.
Temperature
Figure 12. Transient Load Detection Level vs.
Temperature
8.5
150
8.4
145
8.3
8.2
8.1
8.0
7.9
7.8
7.7
140
135
130
125
120
115
110
7.6
7.5
105
100
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Latch Protection Level vs.
Temperature
Figure 14. Fault Validation Time vs.
Temperature
1.0
0.9
300
250
200
V
CC
= 0 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
150
100
50
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Startup Inhibit Voltage vs.
Temperature
Figure 16. Startup Inhibit Current vs.
Temperature
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NCP1271
TYPICAL CHARACTERISTICS
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
6
5
4
3
2
V
CC
= V
− 0.2 V
CC(on)
125°C
−40°C
25°C
1
0
3.6
3.5
−50
−25
0
25
50
75
100
125
0
2
4
6
8
10
12
TEMPERATURE (°C)
V , SUPPLY VOLTAGE (V)
CC
Figure 17. High Voltage Startup Current vs.
Temperature
Figure 18. Startup Current vs. VCC Voltage
25
24
23
22
21
40
35
30
25
20
15
10
20
19
18
17
5
0
16
15
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Startup Leakage Current vs.
Temperature
Figure 20. Minimum Startup Voltage vs.
Temperature
14
12
10
8
3.5
V
CC(on)
I
(100 kHz)
(65 kHz)
CC1
3.0
2.5
2.0
1.5
1.0
V
CC(off)
I
CC1
V
CC(latch)
6
I
I
CC2
V
CC(reset)
4
CC3
2
0
0.5
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Supply Voltage Thresholds vs.
Temperature
Figure 22. Supply Currents vs. Temperature
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NCP1271
OPERATING DESCRIPTION
Introduction
• Current−Mode Operation: The NCP1271 uses
current−mode control which provides better transient
response than voltage−mode control. Current−mode
control also inherently limits the cycle−by−cycle
primary current.
• Compensation Ramp: A drawback of current−mode
regulation is that the circuit may become unstable
when the operating duty cycle is too high. The
NCP1271 offers an adjustable compensation ramp to
solve this instability.
The NCP1271 represents a new generation of the
fixed−frequency PWM current−mode flyback controllers
from ON Semiconductor. The device features integrated
high−voltage startup and excellent standby performance.
The proprietary Soft−Skip Mode achieves extremely
low−standby power consumption while keeping power
supply acoustic noise to a minimum. The key features of
the NCP1271 are as follows:
• Timer−Based Fault Detection: In the event that an
abnormally large load is applied to the output for more
than 130 ms, the controller will safely shut the
application down. This allows accurate overload (OL)
or short−circuit (SC) detection which is not dependent
on the auxiliary winding.
• 80% Maximum Duty Cycle Protection: This feature
limits the maximum on time of the drive to protect the
power MOSFET from being continuously on.
• Frequency Jittering: Frequency jittering softens the
EMI signature by spreading out peak energy within a
band +/− 7.5% from the center frequency.
• Switching Frequency Options: The NCP1271 is
available in either 65 kHz or 100 kHz fixed frequency
options. Depending on the application, the designer
can pick the right device to help reduce magnetic
switching loss or improve the EMI signature before
reaching the 150 kHz starting point for more
restrictive EMI test limits.
• Soft−Skip Mode: This proprietary feature of the
NCP1271 minimizes the standby low−frequency
acoustic noise by ramping the peak current envelope
whenever skip is activated.
• Adjustable Skip Threshold: This feature allows the
power level at which the application enters skip to be
fully adjusted. Thus, the standby power for various
applications can be optimized. The default skip level
is 1.2 V (40% of the maximum peak current)
.
• 500 V High−Voltage Startup Capability: This
AC−DC application friendly feature eliminates the
need for an external startup biasing circuit, minimizes
the standby power loss, and saves printed circuit board
(PCB) space.
NCP1271 Operating Conditions
There are 5 possible operating conditions for the NCP1271:
1. Normal Operation – When V is above V
CC
CC(off)
)
FB
(9.1 V typical) and the feedback pin voltage (V
is within the normal operation range (i.e.,V < 3.0
FB
V), the NCP1271 operates as a fixed−frequency
current−mode PWM controller.
• Dual High−Voltage Startup−Current Levels: The
NCP1271 uniquely provides the ability to reduce the
startup current supply when Vcc is low. This prevents
damage if Vcc is ever shorted to ground. After Vcc
rises above approximately 600 mV, the startup current
increases to its full value and rapidly charges the Vcc
capacitor.
• Latched Protection: The NCP1271 provides a pin,
which if pulled high, places the part in a latched off
mode. Therefore, overvoltage (OVP) and
2. Standby Operation (or Skip−Cycle Operation)
When the load current drops, the compensation
network responds by reducing the primary peak
current. When the peak current reaches the skip
peak current level, the NCP1271 enters Soft−Skip
operation to reduce the power consumption. This
Soft−Skip feature offers a modified peak current
envelope and hence also reduces the risk of audible
noise. In the event of a sudden load increase, the
transient load detector (TLD) disables Soft−Skip
and applies maximum power to bring the output
into regulation as fast as possible.
overtemperature (OTP) protection can be easily
implemented. A noise filter is provided on this function
to reduce the chances of falsely triggering the latch. The
latch is released when Vcc is cycled below 4 V.
3. Fault Operation – When no feedback signal is
• Non−Latched Protection/ Shutdown Option: By
pulling the feedback pin below the skip threshold
level, a non−latching shutdown mode can be easily
implemented.
• 4.0 ms Soft−Start: The soft start feature slowly ramps
up the drive duty cycle at startup. This forces the
primary current to also ramp up slowly and
dramatically reduces the stress on power components
during startup.
received for 130 ms or when V drops below
CC
V
CC(off)
(9.1 V typical), the NCP1271 recognizes it
as a fault condition. In this fault mode, the Vcc
voltage is forced to go through two cycles of slowly
discharging and charging. This is known as a
“double hiccup.” The double hiccup insures that
ample time is allowed between restarts to prevent
overheating of the power devices. If the fault is
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9
NCP1271
cleared after the double hiccup, then the application
restarts. If not, then the process is repeated.
Startup current
4. Latched Shutdown – When the Skip/latch pin (Pin
1) voltage is pulled above 8.0 V for more than
13 ms, the NCP1271 goes into latchoff shutdown.
4.1 mA
The output is held low and V stays in hiccup
CC
mode until the latch is reset. The reset can only
occur if Vcc is allowed to fall below V
CC(reset)
(4.0 V typical). This is generally accomplished by
unplugging the main input AC source.
200 uA
V
V
V
0.6 V
CC(on)
CC
CC(latch)
5. Non−Latched Shutdown – If the FB pin is pulled
below the skip level, then the device will enter a
non−latched shutdown mode. This mode disables
the driver, but the controller automatically recovers
when the pulldown on FB is released. Alternatively,
Vcc can also be pulled low (below 190 mV) to
shutdown the controller. This has the added benefit
of placing the part into a low current consumption
mode for improved power savings.
Figure 23. Startup Current at Various VCC Levels
V
Double Hiccup Mode
CC
Figure 24 illustrates the block diagram of the startup
circuit. An undervoltage lockout (UVLO) comparator
monitors the V supply voltage. If V falls below
CC
CC
V
CC(off)
, then the controller enters “double hiccup mode.”
V
bulk
Biasing the Controller
HV
During startup, the Vcc bias voltage is supplied by the
HV Pin (Pin 8). This pin is capable of supporting up to
500 V, so it can be connected directly to the bulk capacitor.
Internally, the pin connects to a current source which
8
4.1 mA when Vcc > 0.6 V
200 uA when Vcc < 0.6 V
turn off
rapidly charges V to its V
threshold. After this
CC
CC(on)
level is reached, the controller turns on and the transformer
auxiliary winding delivers the bias supply voltage to V
UVLO
+
CC.
Q
S
R
−
The startup FET is then turned off, allowing the standby
power loss to be minimized. This in−chip startup circuit
minimizes the number of external components and Printed
Circuit Board (PCB) area. It also provides much lower
power dissipation and faster startup times when compared
12.6/
5.8 V
double
hiccup
B2
Counter
9.1 V
to using startup resistors to V . The auxiliary winding
CC
Vcc
needs to be designed to supply a voltage above the V
CC(off)
−
+
6
level but below the maximum V level of 20 V.
CC
For added protection, the NCP1271 also include a dual
startup mode. Initially, when V is below the inhibit
&
20V
CC
voltage V
(600 mV typical), the startup current source
inhibit
turn on internal bias
is small (200 uA typical). The current goes higher (4.1 mA
typical) when V goes above V . This behavior is
Figure 24. VCC Management
CC
inhibit
illustrated in Figure 23. The dual startup feature protects
the device by limiting the maximum power dissipation
During double hiccup operation, the Vcc level falls to
(5.8 V typical). At this point, the startup FET is
V
CC(latch)
when the V pin (Pin 6) is accidentally grounded. This
turned back on and charges V to V
(12.6 V typical).
level. This
CC
CC
CC(on)
slightly increases the total time to charge V , but it is
V
CC
then slowly collapses back to the V
CC(latch)
CC
generally not noticeable.
cycle is repeated twice to minimize power dissipation in
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10
NCP1271
external components during a fault event. After the second
cycle, the controller tries to restart the application. If the
restart is not successful, then the process is repeated.
V
out
During this mode, V never drops below the 4 V latch
reset level. Therefore, latched faults will not be cleared
unless the application is unplugged from the AC line (i.e.,
CC
V
CC
12.6 V
9.1 V
V
bulk
discharges).
t
startup
0.6 V
Figure 25 shows a timing diagram of the V double
CC
time
hiccup operation. Note that at each restart attempt, a soft
start is issued to minimize stress.
Output waveforms with a large enough V capacitor
CC
Desired level of V
out
Supply voltage, V
CC
12.6 V
9.1 V
12.6 V
9.1 V
V
CC
5.8 V
0.6 V
V
out
5.8 V
time
Output waveforms with too small of a V capacitor
time
time
CC
Figure 26. Different Startup Scenarios of the
Circuits with Different VCC Capacitors
t
startup
Drain current, I
D
It is highly recommended that the V capacitor be as
CC
close as possible to the V and ground pins of the product
to reduce switching noise. A small bypass capacitor on this
pin is also recommended. If the switching noise is large
CC
Switching is missing in
every two V hiccup cycles
CC
featuring a “double−hiccup”
Figure 25. VCC Double Hiccup Operation in a Fault
Condition
enough, it could potentially cause V to go below V
and force a restart of the controller.
CC
CC(off)
It is also recommended to have a margin between the
winding bias voltage and V so that all possible
V
Capacitor
CC
CC(off)
As stated earlier, the NCP1271 enters a fault condition
when the feedback pin is open (i.e. FB is greater than 3 V)
for 130 ms or V drops below V (9.1 V typical).
transient swings of the auxiliary winding are allowed. In
standby mode, the V voltage swing can be higher due to
CC
CC
CC(off)
the low−frequency skip−cycle operation. The V
CC
Therefore, to take advantage of these features, the V
CC
capacitor also affects this swing. Figure 27 illustrates the
possible swings.
capacitor needs to be sized so that operation can be
maintained in the absence of the auxiliary winding for at
least 130 ms.
Supply voltage, V
CC
The controller typically consumes 2.3 mA at a 65 kHz
frequency with a 1 nF switch gate capacitance. Therefore,
to ensure at least 130 ms of operation, equation 1 can be
used to calculate that at least an 85 mF capacitor would be
necessary.
9.1 V
time
C
DV
85 mF · (12.6 V−9.1 V)
VCC
I
t
+
+
+ 130 ms
Feedback pin voltage, V
FB
startup
2.3 mA
CC1
(eq. 1)
V
skip
If the 130 ms timer feature will not be used, then the
capacitance value needs to at least be large enough for the
output to charge up to a point where the auxiliary winding
time
time
can supply V . Figure 26 describes different startup
CC
Drain current, I
scenarios with different V capacitor values. If the V
CC
CC
D
cap is too small, the application fails to start because the
bias supply voltage cannot be established before V is
CC
reduced to the V
level.
CC(off)
Figure 27. Timing Diagram of Standby Condition
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NCP1271
Soft−Start Operation
Current−Mode Pulse−Width Modulation
Figures 28 and 29 show how the soft−start feature is
included in the pulse−width modulation (PWM)
comparator. When the NCP1271 starts up, a soft−start
The NCP1271 uses a current−mode fixed−frequency
PWM with internal ramp compensation. A pair of current
sense resistors R and R
sense the flyback drain
ramp
CS
voltage V begins at 0 V. V increasesgradually from 0 V
current I . As the drain current ramps up through the
SS
SS
D
to 1.0 V in 4.0 ms and stays at 1.0 V afterward. This voltage
is compared with the divided−by−3 feedback pin
inductor and current sense resistor, a corresponding voltage
ramp is placed on the CS pin (pin 3). This voltage ranges
V
SS
voltage (V /3). The lesser of V and (V /3) becomes the
from very low to as high as the modulation voltage V
FB
SS
FB
PWM
modulation voltage V
in the PWM duty cycle
(maximum of 1.0 V) before turning the drive off. If the
PWM
generation. Initially, (V /3) is above 1.0 V because the
internal current ramp is ignored (i.e., R
≈ 0) then the
is shown in
FB
ramp
output voltage is low. As a result, V
is limited by the
maximum possible drain current I
PWM
D(max)
soft start function and slowly ramps up the duty cycle (and
therefore the primary current) for the initial 4.0 ms. This
provides a greatly reduced stress on the power devices
during startup.
Equation 2. This sets the primary current limit on a cycle
by cycle basis.
1 V
(eq. 2)
I
+
D(max)
R
CS
V
SS
/ 3
−
+
V
bulk
V
FB
0
1
I
ramp
V
V
PWM
CS
180ns
LEB
+
PWM
Output
−
Q
R
S
Figure 28. VPWM is the lesser of VSS and (VFB/3)
I
CS
R
D
ramp
80%
max duty
V
PWM
3
Soft−start voltage, V
(1V max. signal)
SS
Clock
1
0
R
CS
1 V
Figure 30. Current−Mode Implementation
time
4 ms
Feedback pin voltage divided−by−3, V /3
PWM
Output
FB
V
1 V
PWM
V
CS
time must be less than130 ms
to prevent fault condition
time
clock
Pulse Width Modulation voltage, V
PWM
Figure 31. Current−Mode Timing Diagram
1 V
The timing diagram of the PWM is in Figure 31. An
internal clock turns the Drive Output (Pin 5) high in each
switching cycle. The Drive Output goes low when the CS
time
time
4 ms
Drain Current, I
(Pin 3) voltage V intersects with the modulation voltage
CS
V . This generates the pulse width (or duty cycle). The
PWM
D
maximum duty cycle is limited to 80% (typically) in the
output RS latch.
4 ms
Figure 29. Soft−Start (Time = 0 at VCC = VCC(on)
)
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NCP1271
43 mVńms
8.1 mAńms
Ramp Compensation
R
+
+ 5.3 kW
(eq. 4)
ramp
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty−cycle
greater than 50%. To lower the current loop gain, one
usually injects between 50 and 75% of the inductor down
slope. The NCP1271 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
It is recommended that the value of R
be limited to
ramp
less then 10 kW. Values larger than this will begin to limit
the effective duty cycle of the controller and may result in
reduced transient response.
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The NCP1271 switching frequency
ranges from +7.5% to −7.5% of the switching frequency in
a linear ramp with a typical period of 6 ms. Figure 34
demonstrates how the oscillation frequency changes.
simply formed by placing a resistor, R
pin and the sense resistor.
, between the CS
ramp
Ramp current, I
ramp
Oscillator Frequency
100uA
107.5 kHz
100 kHz
time
0
92.5 kHz
80% of period
100% of period
6 ms
Figure 32. Internal Ramp Current Source
time
Figure 34. Frequency Jittering
(The values are for the 100 kHz frequency option)
DRIVE
Fault Detection
Figure 35 details the timer−based fault detection
circuitry. When an overload (or short circuit) event occurs,
the output voltage collapses and the optocoupler does not
Clock
100 mA Peak
conduct current. This opens the FB pin (pin 2) and V is
FB
Current
Ramp
R
ramp
CS
internally pulled higher than 3.0 V. Since (V /3) is greater
FB
than 1 V, the controller activates an error flag and starts a
130 ms timer. If the output recovers during this time, the
timer is reset and the device continues to operate normally.
However, if the fault lasts for more than 130 ms, then the
Oscillator
R
sense
driver turns off and the device enters the V
Hiccup mode discussed earlier. At the end of the double
hiccup, the controller tries to restart the application.
Double
CC
Figure 33. Inserting a Resistor in Series with the
Current Sense Information brings Ramp Compensation
For the NCP1271, the current ramp features a swing of
100 mA. Over a 65 kHz frequency with an 80% max duty
cycle, that corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance
(Lp) is 350 mH, the SMPS output is 19 V, the Vf of the
output diode is 1 V and the Np:Ns ratio is 10:1. The OFF
time primary current slope is given by:
4.8V
V
FB
FB 2
V
FB
3
Np
(Vout ) Vf) @
Fault
disable Drv
Ns
+
−
130ms
delay
+ 571 VńmH + 571 mAńms
(eq. 3)
Lp
V
SS
&
When projected over an Rsense of 0.1 W (for example),
this becomes or 57 mV/ms. If we select 75% of the
downslope as the required amount of ramp compensation,
Softstart
1V max
Figure 35. Block Diagram of Timer−Based Fault
Detection
then we shall inject 43 mV/ms. Therefore, R
is simply
ramp
equal to:
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NCP1271
Besides the timer−based fault detection, the NCP1271
also enters fault condition when V drops below V
Skip Duty Cycle
Skip peak current, %Ics , is the percentage of the
)
(off
CC
CC
skip
(9.1 V typical). The device will again enter a double hiccup
mode and try to restart the application.
maximum peak current at which the controller enters skip
mode. Ics
can be any value from 0 to 100% as defined
skip
by equation 5. However, the higher that %Ics
greater the drain current when skip is entered. This
increases the risk of acoustic noise. Conversely, the lower
is, the
skip
Operation in Standby Condition
During standby operation, or when the output has a light
load, the duty cycle on the controller can become very
small. At this point, a significant portion of the power
dissipation is related to the power MOSFET switching on
and off. To reduce this power dissipation, the NCP1271
“skips” pulses when the FB level (i.e. duty cycle) drops too
low. The level that this occurs at is completely adjustable
by setting a resistor on pin 1.
that %Ics
is the larger the percentage of energy is
skip
expended turning the switch on and off. Therefore it is
important to adjust %Ics
application.
to the optimal level for a given
skip
V
skip
(eq. 5)
% Ics
+
· 100%
skip
3 V
By discontinuing pulses, the output voltage slowly drops
and the FB voltage rises. When the FB voltage rises above
Skip Adjustment
By default, when the Skip/latch Pin (Pin 1) is opened, the
skip level is 1.2 V (V = 1.2 V). This corresponds to a
the V
level, the drive is turned back on. However, to
skip
skip
minimize the risk of acoustic noise, when the drive turns
back on the duty cycle of its pulses are also ramped up. This
is similar to the soft start function, except the period of the
Soft−Skip operation is only 300 ms instead of 4.0 ms for the
soft start function. This feature produces a timing diagram
shown in Figure 36.
40% Ics
(%Ics
= 1.2 V / 3.0 V 100% = 40%).
skip
skip
Therefore, the controller will enter skip mode when the
peak current is less than 40% of the maximum peak current.
However, this level can be externally adjusted by placing
a resistor R
between skip/latch pin (Pin 1) and Ground
skip
(Pin 4). The level will change according to equation 6.
V
+ R
I
skip
(eq. 6)
V
skip skip
skip
FB
To operate in skip cycle mode, V
0 V and 3.0 V. Therefore, R
given in Table 1.
must be between
skip
must be within the levels
Soft Skip
skip
I
D
Figure 36. Soft−Skip Operation
Table 1. Skip Resistor Rskip Range for Dmax = 80% and Iskip = 43 mA
%Ics
V
skip
or V
R
skip
Comment
skip
pin1
0%
0 V
0 W
Never skips.
12%
25%
40%
50%
100%
0.375 V
0.75 V
1.2 V
8.7 kW
17.4 kW
28 kW
−
−
−
1.5 V
34.8 kW
70 kW
−
3.0 V
Always skips.
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14
NCP1271
Recover from Standby
to be opened. The skip level V is restored to
skip
In the event that a large load is encountered during skip
cycle operation, the circuit automatically disables the
normal Soft−Skip procedure and delivers maximum power
to the load (Figure 37). This feature, the Transient Load
Detector (TLD), is initiated anytime a skip event is exited
and the FB pin is greater than 2.85 V, as would be the case
for a sudden increase in output load.
the default 1.2 V.
3. When the voltage is between about 3.0 V and
, the V level is above the normal
V
skip−reset
skip
operating range of the feedback pin. Therefore,
the output does not switch.
4. When the voltage is between 0 V and 3.0 V, the
V
skip
is within the operating range of the
feedback pin. Then the voltage on this pin sets
the skip level as explained earlier.
output voltage
300 ms max
V
pin1
10 V (max limit)
Output is latched off here.
8V (V
load current
V
)
TLD
latch
Maximum current available
when TLD level is hit
Pin 1 considered to be opened.
is reset to default level 1.2 V.
V
skip
V
skip
V
FB
5.7 V (V
)
skip−reset
Output always low (skipped) here.
3.0 V (always skip)
I
D
Figure 37. Transient Response from Standby
Adjustable V
range.
skip
External Latchoff Shutdown
0 V (no skip)
When the Skip/Latch input (Pin 1) is pulled higher than
V
V
(8.0 V typical), the drive output is latched off until
latch
drops below V
(4.0 V ). If Vbulk stays
typical
CC
CC(reset)
Figure 39. NCP1271 Pin 1 Operating Regions
The external latch feature allows the circuit designers to
implement different kinds of latching protection. The
NCP1271 applications note (AND8242/D) details several
simple circuits to implement overtemperature protection
(OTP) and overvoltage protection (OVP).
above approximately 30 Vdc, then the HV FET ensure that
remains above V (5.8 V ). Therefore, the
V
CC
CC(latch)
typical
controller is reset by unplugging the power supply from the
wall and allowing V to discharge. Figure 38 illustrates
the timing diagram of V in the latchoff condition.
bulk
CC
In order to prevent unexpected latchoff due to noise,
it is very important to put a noise decoupling capacitor
near Pin 1 to increase the noise immunity. It is also
recommended to always have a resistor from pin 1 to GND.
This further reduces the risk of premature latchoff. Also
note that if the additional latch−off circuitry has leakage,
it will modify the skip adjust setup.
Startup current source is
Startup current source is
off when V is 12.6 V
charging the V capacitor
CC
CC
12.6 V
External Non−Latched Shutdown
Figure 40 illustrates the Feedback (pin 2) operation. An
external non−latched shutdown can be easily implemented
by simply pulling FB below the skip level. This is an
inherent feature from the standby skip operation. Hence, it
allows the designer to implement additional non−latched
shutdown protection.
5.8 V
Startup current source turns
on when V reaches 5.8 V
CC
CC
Figure 38. Latchoff VCC Timing Diagram
Figure 39 defines the different voltage regions of the
Skip/latch Pin (Pin 1) operation.
The device can also be shutdown by pulling the V pin
CC
to GND (<190 mV). In addition to shutting off the output,
this method also places the part into a low current
consumption state.
1. When the voltage is above V
(7.1 V min,
latch
8.7 V max), the circuit is in latchoff and all drive
pulses are disabled until V cycles below 4.0 V
CC
(typical).
2. When the voltage is between V
(5.0 V
skip−reset
min, 6.5 V max) and V
, the pin is considered
latch
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15
NCP1271
V
time of 30 ns and 20 ns with a 1.0 nF load. This allows the
FB
NCP1271 to drive a high−current power MOSFET directly
for medium−high power application.
Fault operation when staying
in this region longer than 130 ms
3 V
Noise Decoupling Capacitors
There are three pins in the NCP1271 that may need
external decoupling capacitors.
PWM operation
V
skip
0 V
1. Skip/Latch Pin (Pin 1) – If the voltage on
this pin is above 8.0 V, then the circuit enters
latchoff. Hence, a decoupling capacitor on this
pin is essential for improved noise immunity.
Additionally, a resistor should always be placed
from this pin to GND to prevent noise from
causing the pin 1 level to exceed the latchoff
level.
Non−latched shutdown
Figure 40. NCP1271 Operation Threshold
1
2
8
3
6
5
2. Feedback Pin (Pin 2) – The FB pin is a high
impedance point and is very easily polluted in a
noisy environment. This could effect the circuit
operation.
OFF
4
NCP1271
opto
coupler
3. V Pin (Pin 6) – The circuit maintains normal
CC
operation when V is above V
(9.1 V
CC
CC(off)
typical). But, if V drops below V
of switching noise, then the circuit can incorrectly
recognize it as a fault condition. Hence, it is
because
CC
CC(off)
Figure 41. Non−Latchoff Shutdown
Output Drive
important to locate the V capacitor or an
CC
The output stage of the device is designed to directly
drive a power MOSFET. It is capable of up to +500 mA and
−800 mA peak drive currents and has a typical rise and fall
additional decoupling capacitor as close as possible
to the device.
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16
NCP1271
D1 − D4
Fuse 2A
1N5406 x 4
C5 10 nF
+
19 V / 3 A
−
85 to
265 Vac
T1
E3506−A
D8 MBR3100
D7 MURS160
IC1 NCP1271A
R2 10
R6 10
R7 511
C12
0.15 uF
R8
0.2 / 1W
D10 MZP4746A (18V)
IC4 TL431
R3 200
IC2 SFH615AA−X007
Flyback transformer :
Cooper CTX22−17179
Lp = 180uH, leakage 2.5uH max
np : ns : naux = 30 : 6 : 5
C11 1nF/ 1000V
Hi−pot 3600Vac for 1 sec, primary to secondary
Hi−pot 8500Vac for 1 sec, winding to core
D9 1N5358B (22V@50mA)
Figure 42. 57 W Example Circuit Using NCP1271
Figure 42 shows a typical application circuit using the
NCP1271. The standby power consumption of the circuit
is 83 mW with 230 Vac input. The details of the application
circuit are described in application note AND8242/D. The
efficiency of the circuit at light load up to full load is shown
in Figure 43.
95
90
120 Vac
85
230 Vac
80
75
70
65
60
0
10
20
30
(W)
40
50
60
P
out
Figure 43. Efficiency of the NCP1271 Demo
Board at Nominal Line Voltages
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17
NCP1271
ORDERING INFORMATION
Device
†
Frequency
Package
Shipping
NCP1271D65R2G
65kHz
SOIC−7
2500 Tape & Reel
(Pb−Free)
NCP1271D100R2G
100 kHz
SOIC−7
2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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NCP1271
PACKAGE DIMENSIONS
SOIC−7
D SUFFIX
CASE 751U−01
ISSUE C
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
D 7 PL
M
S
S
0.25 (0.010)
T
B
A
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
The product described herein (NCP1271), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221, 6,633,193. There may
be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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