NCP1343BADBDEAD1R2G_技术文档

High Frequency Quasi-

Resonant Flyback Controller

NCP1343

The NCP1343 is a highly integrated quasi−resonant flyback

controller suitable for designing high−performance off−line power

converters.

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The NCP1343 features a proprietary valley−lockout circuitry,

th

ensuring stable valley switching. This system works down to the 6

valley and transitions to frequency foldback mode to reduce switching

losses. As the load decreases further, the NCP1343 enters quiet−skip

mode to manage the power delivery while minimizing acoustic noise.

Additionally, the NCP1343 integrates power excursion mode

(PEM) to minimize transformer size in designs requiring high

transient load capability. If transient load capability is not desired, the

NCP1342 offers the same performance and features without PEM.

To ensure light load performance with high frequency designs, the

NCP1343 incorporates Rapid Frequency Foldback with Minimum

Peak Current Modulation to reduce the switching frequency quickly.

To help ensure converter ruggedness, the NCP1343 implements

several key protective features such as internal brownout detection, a

non−dissipative Over Power Protection (OPP) for constant maximum

output power regardless of input voltage, and a latched overvoltage

and NTC−ready overtemperature protection through a dedicated pin.

8

9

1

SOIC−9 NB

D SUFFIX

CASE 751BP

SOIC−8 NB

D SUFFIX

CASE 751

MARKING DIAGRAMS

8

9

1

343abcdef

ALYWg

G

343abcdef

ALYWg

G

1

Features

343abcdef = Specific Device Code

• Integrated High−Voltage Startup Circuit with Brownout Detection

A

L

= Assembly Location

= Wafer Lot

• Wide V Range from 9 V to 28 V

CC

Y

W

g

G

= Year

= Work Week

= Additional Options Code

= Pb−Free Package

• 28 V V Overvoltage Protection

CC

• Abnormal Overcurrent Fault Protection for Winding Short Circuit or

Saturation Detection

• Internal Temperature Shutdown

• Valley Switching Operation with Valley−Lockout for Noise−Free

Operation

• Frequency Foldback with 25 kHz Minimum Frequency Clamp for

Increased Efficiency at Light Loads

• Rapid Frequency Foldback for Fast Reduction of Switching

Frequency at Light Loads

PIN CONNECTIONS

1

Fault

HV

FMAX

FB

ZCD/OPP

CS

VCC

DRV

GND

• Skip Mode with Quiet−Skip Technology for Highest Performance

During Light Loads

1

HV

FMAX

FB

• Minimized Current Consumption for No Load Power Below 30 mW

• Frequency Jittering for Reduced EMI Signature

VCC

DRV

GND

ZCD/OPP

CS

• Latching or Auto−Recovery Timer−Based Overload Protection

• Adjustable Overpower Protection (OPP)

(Top Views)

• Adjustable Maximum Frequency Clamp

ORDERING INFORMATION

See detailed ordering and shipping information on page 3 of

this data sheet.

• CCM Operation During Power Excursion Mode (PEM)

• Fault Pin for Severe Fault Conditions, NTC Compatible for OTP

1

Publication Order Number:

March, 2021 − Rev. 2

NCP1343/D

NCP1343

TYPICAL APPLICATION SCHEMATIC

Vout

+

NCP1343

HV

FMAX

+

FB

ZCD/OPP DRV

CS

VCC

L

EMI

Filter

GND

N

+

Figure 1. NCP1343 8−Pin Typical Application Circuit

Vout

+

NCP1343

Fault

HV

FMAX

+

FB

VCC

L

EMI

Filter

ZCD/OPP DRV

CS

GND

N

+

−tº

Figure 2. NCP1343 9−Pin Typical Application Circuit

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2

NCP1343

Table 1. PART NUMBER DECODE − NCP1343ABCDEFG

NCP1343

A

B

C

D

E

F*

G**

OTP/Overload Jitter Frequency/Amplitude Quiet−Skip

CS Min

CS Min Shift

A − 400 mV

B − 350 mV

PEM

Additional

A − AR/AR

B − Latch/AR

C − AR/Latch

D − Latch/Latch

E − AR/None

F − Latch/None

A − 1.55 kHz/75 mV

B − 1.55 kHz/92 mV

C − 1.55 kHz/55 mV

D − 1.55 kHz/61 mV

E − 1.3 kHz/75 mV

F − 1.3 kHz/92 mV

G − 1.3 kHz/55 mV

H − 1.3 kHz/61 mV

J − 3.9 kHz/75 mV

K − 3.9 kHz/92 mV

L − 3.9 kHz/55 mV

M − 3.9 kHz/61 mV

N − Disabled

A − 800 Hz

B − 1.2 kHz

A − 200 mV

B − 150 mV

A − 2x, 4.5s

B − 2x, R

−

A

B

C

C − 1.56 kHz C − 100 mV

D − Disabled D − 250 mV

C − 300 mV C − 2xa, 4.5s

D − 250 mV

E − Disabled

D − 2xa, R

E − 1.5x

Device

*See Table 2 for PEM option details.

** Not present in all parts. See Table 3 for details.

Table 2. PEM OPTION DETAIL

F

Description

A

B

C

D

E

V

ILIM1

V

ILIM1

V

ILIM1

V

ILIM1

V

ILIM1

= 1 V, V

= 800 mV, t

= 667 mV, t

= 4.5 sec, Frequency = Scaled (2x Power)

= R, Frequency = Scaled (2x Power)

= 4.5 sec, Frequency = Fixed (2x Power)

= R, Frequency = Fixed (2x Power)

PEM

OVLD(PEM)

= 800 mV, V

= 800 mV, Frequency = Scaled (1.5x Power)

PEM

Table 3. ADDITIONAL PART OPTIONS

G

Description

−

A

B

C

Default Configuration

Resettable Overload Timer, V

= 81 V, V

= 95 V

BO(stop)

BO(start)

V

CC(off)

Triggers Autorecovery Timer (t

)

restart

Brownout Disabled

Table 4. ORDERING INFORMATION

Part Number

Device Marking

343BADBDEA

343ENAAEBB

343FNAAABC

Package

Shipping

NCP1343BADBDEAD1R2G

NCP1343ENAAEBBD1R2G

SOIC−9 NB (Pb−Free)

2500 / Tape & Reel

NCP1343FNAAABCD1R2G

(In Development)

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3

NCP1343

FUNCTIONAL BLOCK DIAGRAM

TSD

BO

BO Detect

+

V

DD

HV

Abnormal OCP

OVLD

V

Fault

Management

CC

CC(OVP)

FMAX

Control

Management

OVP

OTP

FMAX

QR_FMAX

VCC

Valley/FF

Control

FB

Fault

Off−Time

Control

Dead−Time

Control

ZCD/OPP

OPP

Control

V

CC

t

QR_FMAX

tout

Clamp

V

OPP

FB(open)

R

Quiet−Skip

Control

FB

S

R

Q

FB

DRV

GND

Jitter Ramp

K

FB

CS

÷

MPCM

Control

On−Time

FB

Control

Fault

V

DD

OVP

OVP/OTP

Detect

ILIM1

Detect

Fault

t

OVLD

LEB1

OTP

R

Fault(clamp)

OPP

ILIM2

Detect

V

Fault(clamp)

t

Abnormal OCP

Count 4

LEB2

8−Pin

9−Pin

Figure 3. NCP1343 Block Diagram

Table 5. PIN FUNCTIONAL DESCRIPTION

8−Pin

9−Pin

Pin Name

Function

−

1

Fault

The controller enters fault mode if the voltage on this pin is pulled above or below the fault

thresholds. A precise pull up current source allows direct interface with an NTC thermistor.

1

2

FMAX

A resistor to ground sets the value for the maximum switching frequency clamp. If this pin is

pulled above 4 V, the maximum frequency clamp is disabled. For versions xxxxxA and xxxxxB,

pulling this pin above 4 V switches the PEM control method to fixed frequency mode.

2

3

4

FB

Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.

ZCD/OPP

A resistor divider from the auxiliary winding to this pin provides input to the demagnetization de-

tection comparator and sets the OPP compensation level.

4

5

6

5

6

7

CS

Input to the cycle−by−cycle current limit comparator.

GND

DRV

Ground reference.

This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suit-

able to effectively drive high gate charge power MOSFETs.

7

8

VCC

This pin is the positive supply of the IC. The circuit starts to operate when V exceeds 17 V and

CC

turns off when V goes below 9 V (typical values). After start−up, the operating range is 9 V up

CC

to 28 V.

−

9

N/C

HV

Removed for creepage distance.

8

10

This pin is the input for the high voltage startup and brownout detection circuits.

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4

NCP1343

Table 6. MAXIMUM RATINGS

Rating

Symbol

Value

Unit

V

High Voltage Startup Circuit Input Voltage

High Voltage Startup Circuit Input Current

Supply Input Voltage

V

−0.3 to 700

HV(MAX)

I

20

mA

V

−0.3 to 30

CC(MAX)

Supply Input Current

I

30

1

mA

V/ms

V

Supply Input Voltage Slew Rate

Fault Input Voltage

dV /dt

CC

V

−0.3 to V + 0.7 V

Fault(MAX)

CC

Fault Input Current

I

10

mA

V

Zero Current Detection and OPP Input Voltage

Zero Current Detection and OPP Input Current

Maximum Input Voltage (Other Pins)

Maximum Input Current (Other Pins)

Driver Maximum Voltage (Note 1)

Driver Maximum Current

V

−0.3 to V + 0.7 V

ZCD(MAX)

CC

I

−2/+5

−0.3 to 5.5

10

mA

V

ZCD(MAX)

V

MAX

I

mA

V

MAX

V

DRV

−0.3 to V

DRV(high)

I

500

800

mA

DRV(SRC)

DRV(SNK)

Operating Junction Temperature

Storage Temperature Range

T

−40 to 125

–60 to 150

°C

J

T

STG

2

Power Dissipation (T = 25°C, 1 oz. Cu, 42 mm Copper Clad Printed Circuit)

P

mW

A

D(MAX)

DR2G Suffix, SOIC−8

D1R2G Suffix, SOIC−9

450

330

2

Thermal Resistance (T = 25°C, 1 oz. Cu, 42 mm Copper Clad Printed Circuit)

R

°C/W

A

qJA

DR2G Suffix, SOIC−8

D1R2G Suffix, SOIC−9

225

300

ESD Capability

Human Body Model per JEDEC Standard JESD22−A114F (All pins except HV)

Human Body Model per JEDEC Standard JESD22−A114F (HV Pin)

Charge Device Model per JEDEC Standard JESD22−C101F

Latch−Up Protection per JEDEC Standard JESD78E

2000

800

1000

100

V

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Maximum driver voltage is limited by the driver clamp voltage, V

, when V

DRV(high)

exceeds the driver clamp voltage. Otherwise, the

CC

maximum driver voltage is V

.

CC

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NCP1343

Table 7. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V

= open, V = 2 V, V = 0 V, V

= 0 V, V

=

CC

HV

Fault

FB

CS

ZCD

FMAX

0 V, C

= 100 nF , C

= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

VCC

DRV J J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

START−UP AND SUPPLY CIRCUITS

Supply Voltage

dV/dt = 0.1 V/ms

V

Startup Threshold

V

increasing

decreasing

V

16.0

8.5

7.5

4.5

0.30

17.0

9.0

–

6.5

0.70

18.0

9.5

–

7.5

1.05

CC

CC(on)

Minimum Operating Voltage

Operating Hysteresis

Internal Latch / Logic Reset Level

CC(off)

V

CC(on)

− V

V

CC(off)

CC(HYS)

CC(reset)

CC(inhibit)

V

CC

decreasing

V

Transition from I

to I

V

CC

increasing, I = 650 mA

start1

start2

HV

V

Delay

V

decreasing

t

delay(VCC_off)

25

–

32

–

40

500

40

ms

V

CC(off)

CC

Startup Delay

Delay from V

to DRV Enable

t

delay(start)

CC(on)

Minimum Voltage for Start−Up Current

Source

V

–

HV(MIN)

Inhibit Current Sourced from V Pin

V

= 0 V

I

0.2

0.5

0.65

mA

CC

cc

start1

Start−Up Current Sourced from V Pin

V

cc

= V

– 0.5 V

CC

cc(on)

start2

–40°C to 105°C

–40°C to 125°C

2.4

2.0

3.75

5.0

Start−Up Circuit Off−State Leakage Current

V

= 162.5 V

I

–

15

20

50

mA

HV

HV(off1)

HV(off2)

HV(off3)

= 325 V

= 700 V

HV

Supply Current

mA

Fault or Latch

Skip Mode (excluding FB current)

Operating Current

V

= V

– 0.5 V

I

−

0.115

0.230

1.0

0.250

0.400

1.5

CC

CC(on)

CC1

CC2

CC3

V = 0 V

FB

f

= 50 kHz, C

= open

sw

DRV

V

CC

V

CC

Overvoltage Protection Threshold

Overvoltage Protection Delay

V

27

25

28

32

29

40

V

CC(OVP)

t

ms

delay(VCC_OVP)

BROWNOUT DETECTION

System Start−Up Threshold

Other Versions

Versions xxxxxA

V

increasing

decreasing

increasing

decreasing

V

HV

BO(start)

BO(stop)

BO(HYS)

BO(stop)

107

89

112

94

116

99

Brownout Threshold

Other Versions

Versions xxxxxA

V

HV

V

93

79

98

84

102

89

Hysteresis

Other Versions

Versions xxxxxA

V

HV

V

9.0

6.0

14

10

–

Brownout Detection Blanking Time

GATE DRIVE

V

HV

t

40

70

100

ms

Rise Time

V

from 10% to 90%

from 90% to 10%

t

–

20

5

40

30

ns

DRV

DRV(rise)

Fall Time

V

DRV

t

DRV(fall)

Current Capability

Source

Sink

mA

I

–

500

800

–

DRV(SRC)

I

DRV(SNK)

High State Voltage

V

CC

= V

V

+ 0.2 V, R

= 10 kW

V

8.0

10

–

12

–

14

V

CC(off)

DRV

DRV(high1)

= 30 V, R

= 10 kW

DRV(high2)

CC

DRV

Low Stage Voltage

FEEDBACK

V

= 0 V

V

–

0.25

5.1

Fault

DRV(low)

Open Pin Voltage

2. NTC with R110 = 8.8 kW

V

4.8

5.0

V

FB(open)

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NCP1343

Table 7. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V

= open, V = 2 V, V = 0 V, V

= 0 V, V

=

CC

HV

Fault

FB

CS

ZCD

FMAX

0 V, C

= 100 nF , C

= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

VCC

DRV J J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

FEEDBACK

V

to Internal Current Setpoint Division

K

R

−

3

−

–

FB

Ratio

Internal Pull−Up Resistor

V

FB

= 0.4 V

17

20

23

kW

FB

Valley Thresholds

Transition from 1 to 2 valley

Transition from 2 to 3 valley

Transition from 3 to 4 valley

Transition from 4 to 5 valley

Transition from 5 to 6 valley

Transition from 6 to 5 valley

Transition from 5 to 4 valley

V

st

nd

V

decreasing

increasing

V

1to2

V

2to3

V

3to4

V

4to5

V

5to6

V

6to5

V

5to4

V

4to3

V

3to2

V

2to1

0.987

0.846

0.776

0.705

0.635

1.199

1.269

1.340

1.410

1.551

1.050

0.900

0.825

0.750

0.675

1.275

1.350

1.425

1.500

1.650

1.113

0.954

0.874

0.795

0.715

1.352

1.431

1.511

1.590

1.749

FB

nd

rd

th

FB

th

rd

Transition from 4 to 3 valley

Transition from 3 to 2 valley

Transition from 2 to 1 valley

rd

nd

st

Maximum Frequency Clamp

kHz

V

FMAX

V

FMAX

= 0.5 V

= 3.5 V

f

440

61

500

70

560

79

MAX1

MAX2

f

FMAX Disable Threshold

FMAX Pin Source Current

Maximum On Time

V

3.85

9.0

28

4.00

10

4.15

11

V

FMAX(disable)

I

mA

ms

FMAX

t

32

40

on(MAX)

DEMAGNETIZATION INPUT

ZCD threshold voltage

V

decreasing

increasing

V

35

15

–

60

25

80

90

55

mV

ns

ZCD

ZCD(trig)

ZCD hysteresis

V

ZCD(HYS)

ZCD

Demagnetization Propagation Delay

V

ZCD

step from 4.0 V to −0.3 V

t

250

demag

ZCD Clamp Voltage

Positive Clamp

Negative Clamp

V

I

= 5.0 mA

= −2.0 mA

V

12.4

−0.9

12.7

−0.7

13

0

QZCD

ZCD(MAX)

ZCD(MIN)

I

V

QZCD

Blanking Delay After Turn−Off

t

2.7

3.0

3.5

ms

ZCD(blank)

Timeout After Last Demagnetization

Detection

While in soft−start

After soft−start complete

t

80

5.1

100

6.0

120

6.9

(tout1)

(tout2)

CURRENT SENSE

Current Limit Threshold Voltage

Versions xxxxxE

Versions xxxxxA, xxxxxB, xxxxxC, xxxxxD

V

CS

increasing

V

ILIM1

V

0.76

0.95

0.80

1.00

0.84

1.05

Leading Edge Blanking Duration

DRV minimum width minus

t

220

265

330

175

ns

LEB1

t

delay(ILIM1)

Current Limit Threshold Propagation Delay

PWM Comparator Propagation Delay

Step V

0 V to V

FB

+ 0.5 V,

t

delay(ILIM1)

–

95

CS

ILIM1

V

= 4 V

Step V

0 V to 0.7 V, V = 2

t

delay(PWM)

–

125

ns

CS

FB

Minimum Peak Current

Versions xxxAxx

Versions xxxBxx

Versions xxxCxx

Versions xxxDxx

V

mV

CS(MIN)

170

115

70

200

150

100

250

230

185

130

285

215

Abnormal Overcurrent Fault Threshold

Versions xxxxxE

Versions xxxxxA, xxxxxB, xxxxxC, xxxxxD

V

CS

increasing, V = 4 V

V

ILIM2

V

FB

1.125

1.400

1.200

1.500

1.275

1.600

Abnormal Overcurrent Fault Blanking

Duration

DRV minimum width minus

t

80

110

140

ns

LEB2

t

delay(ILIM2)

2. NTC with R110 = 8.8 kW

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NCP1343

Table 7. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V

= open, V = 2 V, V = 0 V, V

J

= 0 V, V

=

CC

HV

Fault

FB

CS

ZCD

FMAX

0 V, C

= 100 nF , C

= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

VCC

DRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

CURRENT SENSE

Abnormal Overcurrent Fault Propagation

Delay

Step V

0 V to V

FB

+ 0.5 V,

t

–

80

4

175

–

ns

CS

ILIM2

delay(ILIM2)

V

= 4 V

Number of Consecutive Abnormal Overcur-

rent Faults to Enter Latch Mode

n

ILIM2

Overpower Protection Delay

V

dv/dt = 1 V/ms, measured from

t

95

175

CS

V

OPP(delay)

to DRV falling edge

OPP(MAX)

Overpower Signal Blanking Delay

Pull−Up Current Source

JITTERING

t

220

0.7

280

1.0

330

1.5

ns

OPP(blank)

V

CS

= V

− 10 mV

I

CS

mA

ILIM2

Jitter Frequency

f

kHz

mV

jitter

Versions xJxxxx, xKxxxx, xLxxxx, xMxxxx

Versions xAxxxx, xBxxxx, xCxxxx, xDxxxx

Versions xExxxx, xFxxxx, xGxxxx, xHxxxx

Versions xNxxxx

3.5

1.43

1.2

−

3.9

1.55

1.3

−

4.2

1.68

1.4

−

Peak Jitter Voltage

V

jitter

Versions xBxxxx, xFxxxx, xKxxxx

Versions xAxxxx, xExxxx, xJxxxx

Versions xDxxxx, xHxxxx, xMxxxx

Versions xCxxxx, xGxxxx, xLxxxx

Versions xNxxxx

82

65

52

45

−

92

75

61

55

−

102

85

70

65

−

POWER EXCURSION MODE (PEM)

PEM Activation Threshold

Versions xxxxxA, xxxxxB, xxxxxE

Versions xxxxxC, xxxxxD

V

D

mV

PEM

760

630

800

667

840

705

Maximum Duty Ratio During PEM

−

75

−

%

V

MAX

Maximum FB Voltage for Off−Time Scaling

V

FB

increasing

V

3.5

−

FB(MAX)

Maximum Frequency Scaling During PEM

Versions xxxxxA, xxxxxB

Versions xxxxxC, xxxxxD

Version xxxxxE

V

FB

= 3.6 V

K

scale(MAX)

2.2

−

1.5

−

1.0

−

PEM Arming Threshold

V

1.0

1.5

2.0

V

s

PEM(arm)

PEM Overload Timer

Versions xxxxxA, xxxxxC

Versions xxxxxB, xxxxxD, xxxxxE

t

OVLD(PEM)

4.3

−

4.5

−

4.7

−

FAULT PROTECTION

Soft−Start Period

Measured from

DRV pulse to V = V

t

2.8

4.0

5.0

ms

SSTART

st

1

CS

ILIM1

Flyback Overload Fault Timer

Overvoltage Protection (OVP) Threshold

OVP Detection Delay

V

= V

t

OVLD

120

2.79

22.5

380

160

3.00

30

200

3.21

37.5

420

ms

V

CS

ILIM1

V

increasing

decreasing

V

Fault

Fault(OVP)

delay(OVP)

t

ms

Overtemperature Protection (OTP) Thresh-

old (Note 2)

V

400

mV

Fault(OTP_in)

Overtemperature Protection (OTP) Exiting

Threshold (Note 2)

V

increasing

V

880

910

940

mV

Fault

Fault(OTP_out)

Versions B Only

OTP Detection Delay

V

Fault

decreasing

t

22.5

30

37.5

ms

delay(OTP)

OTP Pull−Up Current Source

V

Fault

= V

J

+ 0.2 V

I

OTP

43.75

45.00

46.25

mA

Fault(OTP_in)

T = 25°C to 125°C

Fault Input Clamp Voltage

V

1.15

1.7

2.25

V

Fault(clamp)

2. NTC with R110 = 8.8 kW

www.onsemi.com

8

NCP1343

Table 7. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V

= open, V = 2 V, V = 0 V, V

J

= 0 V, V

=

CC

HV

Fault

FB

CS

ZCD

FMAX

0 V, C

= 100 nF , C

= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

VCC

DRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

FAULT PROTECTION

Fault Input Clamp Series Resistor

Autorecovery Timer

R

1.32

1.8

1.55

2.0

1.78

2.2

kW

Fault(clamp)

t

s

restart

LIGHT/NO LOAD MANAGEMENT

Minimum Frequency Clamp

f

21.5

32

25

27.0

kHz

MIN

Dead−Time Added During Frequency

Foldback

V

FB

= 300 mV

t

−

ms

DT(MAX)

Quiet−Skip Timer

Versions xxAxxx

Versions xxBxxx

Versions xxCxxx

Versions xxDxxx

t

ms

quiet

1.18

0.770

0.590

−

1.25

0.833

0.640

−

1.40

0.900

0.690

−

Skip Threshold

V

decreasing

increasing

V

263

10

300

337

60

mV

FB

skip

Skip Hysteresis

V

37.5

FB

skip(HYS)

RAPID FREQUENCY FOLDBACK

Minimum Peak Current Shift

Versions xxxxAx

V

mV

MPCM(delta)

340

300

250

200

−

400

350

300

250

−

460

400

350

300

−

Versions xxxxBx

Versions xxxxCx

Versions xxxxDx

Versions xxxxEx

Entry Threshold

Versions xxxxAx, xxxxBx, xxxxCx, xxxxDx

Versions xxxxEx

V

mV

ms

MPCM(entry)

585

600

615

−

Exit Threshold

Versions xxxxAx, xxxxBx, xxxxCx, xxxxDx

Versions xxxxEx

V

MPCM(exit)

535

−

550

−

565

−

Transition Timer

Versions xxxxAx, xxxxBx, xxxxCx, xxxxDx

Versions xxxxEx

t

MPCM

0.85

−

1.00

−

1.05

−

THERMAL PROTECTION

Thermal Shutdown

Temperature increasing

Temperature decreasing

T

–

140

40

–

°C

SHDN

T

SHDN(HYS)

Thermal Shutdown Hysteresis

2. NTC with R110 = 8.8 kW

www.onsemi.com

9

NCP1343

INTRODUCTION

The NCP1343 implements a quasi−resonant flyback

frequency. When the load is light enough, the NCP1343

enters rapid frequency foldback mode. During this

mode, the minimum peak current is limited and

dead−time is added to the switching cycle, thus

reducing the frequency and switching operation to

discontinuous conduction mode (DCM). Dead−time

continues to be added until skip mode is reached, or the

switching frequency reaches its minimum level of 25

kHz.

converter utilizing current−mode architecture where the

switch−off event is dictated by the peak current. This IC is

an ideal candidate where low parts count and cost

effectiveness are the key parameters, particularly in ac−dc

adapters, open−frame power supplies, etc. The NCP1343

incorporates all the necessary components normally needed

in modern power supply designs, bringing several

enhancements such as non−dissipative overpower

protection (OPP), brownout protection, and frequency

reduction management for optimized efficiency over the

entire power range. Accounting for the needs of extremely

low standby power requirements, the controller features

minimized current consumption.

• High−Voltage Start−Up Circuit: Low standby power

consumption cannot be obtained with the classic

resistive start−up circuit. The NCP1343 incorporates a

high−voltage current source to provide the necessary

current during start−up and then turns off during normal

operation.

• Internal Brownout Protection: The ac input voltage is

sensed via the high−voltage pin. When this voltage is

too low, the NCP1343 stops switching. No restart

attempt is made until the ac input voltage is back within

its normal range.

• Quasi−Resonant, Current−Mode Operation:

Quasi−Resonant (QR) mode is a highly efficient mode

of operation where the MOSFET turn−on is

synchronized with the point where its drain−source

voltage is at the minimum (valley). A drawback of this

mode of operation is that the operating frequency is

inversely proportional to the system load. The

NCP1343 incorporates a valley lockout (VLO) and

frequency foldback technique to eliminate this

drawback, thus maximizing the efficiency over the

entire power range.

• Minimum Peak Current Modulation (MPCM): In

order to reduce the switching frequency even faster (for

high frequency designs), the NCP1343 uses MPCM to

increase the minimum peak current during frequency

foldback. It also reduces the minimum peak current

gradually as the load decreases to ensure optimum skip

mode entry.

• Skip Mode: To further improve light or no−load power

consumption while avoiding audible noise, the

NCP1343 enters skip mode when the operating

frequency reaches its minimum value. To avoid

acoustic noise, the circuit prevents the switching

frequency from decaying below 25 kHz. This allows

regulation via bursts of pulses at 25 kHz or greater

instead of operating in the audible range.

• Quiet−Skip: To further reduce acoustic noise, the

NCP1343 incorporates a novel circuit to prevent the

skip mode burst period from entering the audible range

as well.

• Internal OPP: In order to limit power delivery at high

line, a scaled version of the negative voltage present on

the auxiliary winding during the on−time is routed to

the ZCD/OPP pin. This provides the designer with a

simple and non−dissipative means to reduce the

maximum power capability as the bulk voltage

increases.

• Frequency Jittering: In order to reduce the EMI

signature, a low frequency triangular voltage waveform

is added to the input of the PWM comparator. This

helps by spreading out the energy peaks during noise

analysis.

• Internal Soft−Start: The NCP1343 includes a 4 ms

soft−start to prevent the main power switch from being

overly stressed during start−up. Soft−start is activated

each time a new startup sequence occurs or during

auto−recovery mode.

• Valley Lockout: In order to limit the maximum

frequency while remaining in QR mode, one would

traditionally use a frequency clamp. Unfortunately, this

can cause the controller to jump back and forth between

two different valleys, which is often undesirable. The

NCP1343 patented VLO circuitry solves this issue by

determining the operating valley based on the system

load, and locking out other valleys unless a significant

change in load occurs.

• Rapid Frequency Foldback: As the load continues to

decrease, it becomes beneficial to reduce the switching

www.onsemi.com

10

NCP1343

forces the system into CCM to allow momentary power

• Dedicated Fault Input: The NCP1343 includes a

dedicated fault input. It can be used to sense an

overvoltage condition and latch off the controller by

pulling the pin above the overvoltage protection (OVP)

threshold. The controller is also disabled if the Fault pin

is pulled below the overtemperature protection (OTP)

threshold. The OTP threshold is configured for use with

a NTC thermistor.

• Overload/Short−Circuit Protection: The NCP1343

implements overload protection by limiting the

maximum time duration for operation during overload

conditions. The overload timer operates whenever the

maximum peak current is reached. In addition to this,

special circuitry is included to prevent operation in

CCM during extreme overloads, such as an output

short−circuit.

• Maximum Frequency Clamp: The NCP1343 includes

a maximum frequency clamp. In all versions, the clamp

is available disabled or fixed at 110 kHz. In the 9−pin

versions, the clamp can be adjusted via an external

resistor from the FMAX Pin to ground. It can also be

disabled by pulling the FMAX pin above 4 V.

• Power Excursion Mode (PEM): When the power

demand exceeds the power excursion threshold, the

NCP1343 enters Power Excursion Mode (PEM) and

excursions of up to 2x for versions xxxxxA and

xxxxxB, or 1.5x for version xxxxxE, thus reducing or

eliminating the need for a larger transformer. For

versions xxxxxC and xxxxxD, the PEM control mode is

set to fixed frequency, where the switching frequency is

frozen and the peak current is increased to achieve 2x

power. This allows for lower switching losses at the

expense of a slightly larger transformer. This is also

accomplished in versions xxxxxA and xxxxxB to

achieve 1.5x power by pulling the FMAX pin above

4 V.

HIGH VOLTAGE START−UP

The NCP1343 contains a multi−functional high voltage

(HV) pin. While the primary purpose of this pin is to reduce

standby power while maintaining a fast start−up time, it also

incorporates brownout detection.

The HV pin must be connected directly to the ac line. Line

and neutral should be diode “ORed” before connecting to the

HV pin as shown in Figure 4. The diodes prevent the pin

voltage from going below ground. A resistor in series with

the pin should be used to protect the pin during EMC or surge

testing. A low value resistor should be used (<5 kW) to

reduce the voltage offset during start−up.

AC

CON

EMI

HV

Controller

Figure 4. High−Voltage Input Connection

Start−up and V_CCManagement

During start−up, the current source turns on and charges

the V capacitor with I (typically 6 mA). When V

power dissipation on the device in the event that the V pin

CC

CC(inhibit)

is shorted to ground. Once V rises back above V

,

CC

start2

cc

CC

reaches V

(typically 16.0 V), the current source turns

the start−up current returns to I

.

CC(on)

start2

off. If the input voltage is not high enough to ensure a proper

start−up (i.e. V has not reached V ), the controller

Once V reaches V

the controller bias current increases to I (typically

, the controller is enabled and

CC

CC(on)

HV

BO(start)

CC3

will not start. V then begins to fall because the controller

2.0 mA). However, the total bias current is greater than this

due to the gate charge of the external switching MOSFET.

CC

bias current is at I

(typically 1 mA) and the auxiliary

CC2

supply voltage is not present. When V falls to V

The increase in I due to the MOSFET is calculated using

CC

CC(off)

CC

(typically 10.5 V), the current source turns back on and

charges V . This cycle repeats indefinitely until V

Equation 1.

DI_CC+ f_sw@ Q_G@ 10⁻³

(eq. 1)

CC

HV

reaches V

. Once this occurs, the current source

BO(start)

where DI is the increase in milliamps, f is the switching

immediately turns on and charges V to V

, at which

CC(on)

CC

sw

CC

frequency in kilohertz and Q is the gate charge of the

point the controller starts (see Figure 6).

G

external MOSFET in nanocoulombs.

When V is brought below V

, the start−up

CC

CC(inhibit)

current is reduced to I

(typically 0.5 mA). This limits

start1

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11

NCP1343

C

VCC

must be sized such that a V voltage greater than

auxiliary winding supplies the IC. The total I current after

CC

V

CC(off)

is maintained while the auxiliary supply voltage

the controller is enabled (I plus DI ) must be

CC3 CC

increases during start−up. If C

is too small, V will fall

considered to correctly size C

.

VCC

CC

VCC

below V

and the controller will turn off before the

CC(off)

Figure 5. Start−up Circuitry Block Diagram

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12

NCP1343

V_HV

V_BO(start)

V_HV(MIN)

V_CC

V_CC(on)

V_CC(off)

Start−up

Current = I_start2

t_delay(start)

Start−up

Current = I_start1

V_CC(inhibit)

DRV

Figure 6. Start−up Timing

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13

NCP1343

DRIVER

The NCP1343 maximum supply voltage, V , is

CC(MAX)

The peak current level is clamped during the soft−start

28 V. Typical high−voltage MOSFETs have a maximum

gate voltage rating of 20 V. The DRV pin incorporates an

active voltage clamp to limit the gate voltage on the external

phase. The setpoint is actually limited by a clamp level

ramping from 0 to 1.0 V within 4 ms.

In addition to the PWM comparator, a dedicated

comparator monitors the current sense voltage, and if it

MOSFETs. The DRV voltage clamp, V

12 V with a maximum limit of 14 V.

is typically

DRV(high)

reaches the maximum value, V

(typically 1.00 mV), the

ILIM

gate driver is turned off and the overload timer is enabled.

This occurs even if the limit imposed by the feedback

REGULATION CONTROL

Peak Current Control

The NCP1343 is a peak current−mode controller, thus the

FB voltage sets the peak current flowing in the transformer

and the MOSFET. This is achieved by sensing the MOSFET

current across a resistor and applying the resulting voltage

ramp to the non−inverting input of the PWM comparator

through the CS pin. The current limit threshold is set by

voltage is higher than V

. Due to the parasitic

ILIM1

capacitances of the MOSFET, a large voltage spike often

appears on the CS Pin at turn−on. To prevent this spike from

falsely triggering the current sense circuit, the current sense

signal is blanked for a short period of time, t

(typically

LEB1

275 ns), by a leading edge blanking (LEB) circuit. Figure 7

shows the schematic of the current sense circuit.

The peak current is also limitied to a minimum level,

applying the FB voltage divided by K (typically 3) to the

FB

V

(0.2 V, typically). This results in higher efficiency

CS(MIN)

inverting input of the PWM comparator. When the current

sense voltage ramp exceeds this threshold, the output driver

is turned off, however, the peak current is affected by several

functions (see Figure 7):

at light loads by increasing the minimum energy delivered

per switching cycle, while reducing the overall number of

switching cycles during light load.

R

OPP

ZCD/OPP

OPP

V

FB(open)

Minimum Peak

Current

R

+

FB

*

DRV Off

V

ILIM1

V

CS(MIN)

Soft−Start

Ramp

K

FB

*

+

PWM

*

+

OCP

*

+

CS

t

LEB1

LEB2

Overload Timer

R

sense

AOCP

t

+

*

Abnormal OCP Counter

V

ILIM2

Figure 7. Current Sense Logic

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14

NCP1343

Zero Current Detection

As shown by Figure 13, a valley is detected once the ZCD

pin voltage falls below the demagnetization threshold,

The NCP1343 is a quasi−resonant (QR) flyback

controller. While the power switch turn−off is determined by

the peak current set by the feedback loop, the switch turn−on

is determined by the transformer demagnetization. The

demagnetization is detected by monitoring the transformer

auxiliary winding voltage.

V

, typically 55 mV. The controller will either switch

ZCD(trig)

once the valley is detected or increment the valley counter,

depending on the FB voltage.

Overpower Protection

The average bulk capacitor voltage of the QR flyback

varies with the RMS line voltage. Thus, the maximum

power capability at high line can be much higher than

desired. An integrated overpower protection (OPP) circuit

provides a relatively constant output power limit across the

Turning on the power switch once the transformer is

demagnetized has the benefit of reduced switching losses.

Once the transformer is demagnetized, the drain voltage

starts ringing at a frequency determined by the transformer

magnetizing inductance and the drain lump capacitance,

eventually settling at the input voltage. A QR flyback

controller takes advantage of the drain voltage ringing and

turns on the power switch at the drain voltage minimum or

“valley” to reduce switching losses and electromagnetic

interference (EMI).

input voltage on the bulk capacitor, V . Since it is a

bulk

high−voltage rail, directly measuring V

will contribute

bulk

losses in the sensing network that will greatly impact the

standby power consumption. The NCP1343 OPP circuit

achieves this without the need for a high−voltage sensing

network, and is essentially lossless.

V

FB(open)

R

FB

PWM

K

FB

t

LEB1

CS

OCP

DRV Off

V

OPP

ZCD/OPP

V

ILIM1

Figure 8. OPP Circuit Schematic

www.onsemi.com

15

NCP1343

⎝

⎛

⎢

⎝

N_AUX

N_P

⎢

.

−

V_BULK

⎛

Figure 9. Auxiliary Winding Voltage

Since the auxiliary winding voltage during the power

switch on time is a reflection of the input voltage scaled by

the primary to auxiliary winding turns ratio, N (see

Figure 9), OPP is achieved by scaling down reflected

voltage during the on−time and applying it to the ZCD pin

The ratio between R

Equation 5. It is obtained by combining Equations 3 and 4.

and R

is given by

ZCD

OPPL

P:AUX

R_ZCD

R_OPPL

V

_AUX* V_F* V_ZCD

(eq. 5)

+

V_ZCD

A design example is shown below:

System Parameters:

as a negative voltage, V . The voltage is scaled down by

OPP

a resistor divider comprised of R

and R

. The

OPPU

OPPL

V

N

_AUX+ 18 V

maximum internal current setpoint (V

) is simply the

CS(OPP)

sum of V

and the peak current sense threshold, V

.

OPP

ILIM1

_F+ 0.6 V

Figure 8 shows the schematic for the OPP circuit.

The adjusted peak current limit is calculated using

Equation 2. For example, a V of −150 mV results in a

_P:AUX+ 0.18

The ratio between R

and R

is calculated using

OPP

ZCD

OPPL

peak current limit of 650 mV in NCP1343.

Equation 5 for a minimum V

of 8 V.

ZCD

R_ZCD

R_OPPL

V

_CS(OPP)+ V_OPP) V_ILIM1

18 V * 0.6 V * 8 V

(eq. 2)

+

+ 1.2 kW

8 V

To ensure optimal zero−crossing detection, a diode is

needed to bypass R

used to calculate R

during the off−time. Equation 3 is

R

is arbitrarily set to 1 kW. R

is also set to 1 kW

OPPU

ZCD

OPPL

and R

.

because the ratio between the resistors is close to 1.

The NCP1343 maximum overpower compensation or

peak current setpoint reduction is 31.25% for a V

−250 mV. We will use this value for the following example:

Substituting values in Equation 3 and solving for R

we obtain:

OPPL

R

_ZCD) R

N

_P:AUX@ V_bulk* V_OPP

^OPPU+ *

(eq. 3)

of

OPP

R_OPPL

V_OPP

R

OPPU

is selected once a value is chosen for R

.

OPPL

OPPU

R

OPPL

is selected large enough such that enough voltage is

available for the zero−crossing detection during the

off−time. It is recommended to have at least 8 V applied on

the ZCD pin for good detection. The maximum voltage is

R

_ZCD) R_OPPU

0.18 @ 370 V * (−0.25 V)

−0.25 V

+

+ 271

R_OPPL

internally clamped to V . The off−time voltage on the ZCD

Pin is given by Equation 4.

R

_OPPU+ 271 @ R_OPPL* R_ZCD

CC

_OPPU+ 271 @ 1 kW * 1 kW + 270 kW

R_OPPL

_ZCD) R_OPPL

ǒ Ǔ

@ V_AUX* V_F

(eq. 4)

V_ZCD

+

For optimum performance over temperature, it is

recommended to keep R below 3 kW.

R

OPPL

Where V

is the voltage across the auxiliary winding

AUX

and V is the D

forward voltage drop.

F

OPP

www.onsemi.com

16

NCP1343

Soft−Start

in CCM for several cycles until the voltage on the ZCD pin

is high enough to prevent the timer from running. Therefore,

Soft−start is achieved by ramping up an internal reference,

V

, and comparing it to the current sense signal.

a longer timeout period, t

(typically 100 ms), is used

SSTART

tout1

ramps up from 0 V once the controller initially

during soft−start to prevent CCM operation.

SSTART

powers up. The peak current setpoint is then limited by the

ramp resulting in a gradual increase of the switch

Frequency Jittering

V

SSTART

In order to help meet stringent EMI requirements, the

NCP1343 features frequency jittering to average the energy

peaks over the EMI frequency range. As shown in Figure 10,

the function consists of summing a triangular wave of

current during start−up. The soft−start duration, t

, is

SSTART

typically 4 ms.

During startup, demagnetization phases are long and

difficult to detect since the auxiliary winding voltage is very

small. In this condition, the 6 ms steady−state timeout is

generally shorter than the inductor demagnetization period.

If it is used to restart a switching cycle, it can cause operation

amplitude V

and frequency f

with the CS signal

jitter

immediately before the PWM comparator. This current acts

to modulate the on−time and hence the operation frequency.

V

DD

R

FB

K

FB

V

jitter

LEB

CS

V

OPP

DRV Off

V

ILIM1

V

CS(MIN)

Figure 10. Jitter Implementation

1000

Since the jittering function modulates the peak current

level, the FB signal will attempt to compensate for this effect

in order to limit the output voltage ripple. Therefore, the

bandwidth of the feedback loop must be well below the jitter

frequency, or the jitter function will be filtered by the loop.

Due to the minimum peak current, the effect of the

jittering circuit will not be seen during frequency foldback

mode.

900

800

700

600

500

400

300

200

100

0

Maximum Frequency Clamp

All 9−pin versions of the NCP1343 include an adjustable

maximum frequency clamp via an external resistor from the

FMAX Pin to ground. It can also be disabled by pulling the

FMAX pin above 4 V. The maximum frequency can be

programmed using Equation 6, and is shown in Figure 11.

0

50

100

150 200

250

300 350 250

R

(kW)

FMAX

Figure 11. F_SW(MAX)vs. R_FMAX

261 kHz * 1 V

(eq. 6)

F_SW(MAX)

+

R_FMAX* 10 mA

www.onsemi.com

17

NCP1343

LIGHT LOAD MANAGEMENT

a valley is selected, the controller stays locked in this valley

until the output power changes significantly. This technique

extends the QR mode operation over a wider output power

range while maintaining good efficiency and limiting the

maximum operating frequency.

Valley Lockout Operation

The operating frequency of a traditional QR flyback

controller is inversely proportional to the system load. In

other words, a load reduction increases the operating

frequency. A maximum frequency clamp can be useful to

limit the operating frequency range. However, when used by

itself, such an approach often causes instabilities since when

this clamp is active, the controller tends to jump (or hesitate)

between two valleys, thus generating audible noise.

Instead, the NCP1343 also incorporates a patented valley

lockout (VLO) circuitry to eliminate valley jumping. Once

st

nd

rd, th

th

The operating valley (1 , 2 , 3 4 , 5 or 6 ) is

determined by the FB voltage. An internal counter

increments each time a valley is detected by the ZCD/OPP

Pin. Figure 12 shows a typical frequency characteristic

obtainable at low line in a 65 W application.

6^th5^th4^th

3^rd

2^nd

1^st

5

4

1x10

8x10

6x10

4x10

2x10

VCO

mode

6^th

5^th4^th

3^rd

2^nd

1^st

VCO

mode

0

20

40

60

Pout (W)

Figure 12. Valley Lockout Frequency vs. Output Power

When an “n” valley is asserted by the valley selection

circuitry, the controller is locked in this valley until the FB

voltage decreases to the lower threshold (“n+1” valley

activates) or increases to the “n valley threshold” + 600 mV

(“n−1” valley activates). The regulation loop adjusts the

peak current to deliver the necessary output power. Each

valley selection comparator features a 600 mV hysteresis

that helps stabilize operation despite the FB voltage swing

produced by the regulation loop.

Table 8. VALLEY FB THRESHOLDS (typical values)

FB Falling

FB Rising

st

nd

st

1

to 2 valley

1.050 V

0.900 V

0.825 V

0.750 V

0.675 V

2

to 1 valley

1.650 V

1.500 V

1.425 V

1.350 V

1.275 V

nd

rd

th

nd

2

to 3 valley

3

to 2 valley

th

rd

3

4

5

to 4 valley

4

5

to 3 valley

th

to 5 valley

to 4 valley

th

to 6 valley

6

to 5 valley

Valley Timeout

signal acts as a substitute for the ZCD signal to the valley

counter. Figure 13 shows the valley timeout circuit

In case of extremely damped oscillations, the ZCD

comparator may not be able to detect the valleys. In this

condition, drive pulses will stop while the controller waits

for the next valley or ZCD event. The NCP1343 ensures

continued operation by incorporating a maximum timeout

period after the last demagnetization detection. The timeout

schematic. The steady state timeout period, t

, is set at 6

tout2

ms (typical) to limit the frequency step.

During startup, the voltage offset added by the OPP diode,

, prevents the ZCD Comparator from accurately

D

OPP

detecting the valleys. In this condition, the steady state

www.onsemi.com

18

NCP1343

timeout period will be shorter than the inductor

the FB voltage sets VLO mode to turn on at the fifth valley,

and the ZCD ringing is damped such that the ZCD circuit is

only able to detect:

demagnetization period causing CCM operation. CCM

operation lasts for a few cycles until the voltage on the ZCD

pin is high enough to detect the valleys. A longer timeout

• Valleys 1 to 4: the circuit generates a DRV pulse 6 ms

th

period, t

, (typically 100 ms) is set during soft−start to

tout1

(steady−state timeout delay) after the 4 valley

limit CCM operation.

detection.

In VLO operation, the number of timeout periods are

counted instead of valleys when the drain−source voltage

oscillations are too damped to be detected. For example, if

• Valleys 1 to 3: the timeout delay must run twice, and

rd

the circuit generates a DRV pulse 12 ms after the 3

valley detection.

Figure 13. Valley Timeout Circuitry

Rapid Frequency Foldback with Minimum Peak

Current Modulation (MPCM)

As the output load decreases (FB voltage decreases), the

valleys are incremented from 1 to 6. When the sixth valley

is reached and the FB voltage further decreases to

minimum frequency clamp prevents the switching

frequency from dropping below 25 kHz to eliminate the risk

of audible noise. Note that the dead−time is not added (it is

blanked) until MPCM is engaged to ensure valley switching

prior to entering MPCM mode.

V

(600 mV typical), the controller enters MPCM

MPCM(entry)

In addition to dead−time, the peak current setpoint is

and begins frequency foldback (FF). At this point, the

minimum peak current is increased by V

linearly reduced as V falls down to 0.3 V. This ensures that

FB

MPCM(delta)

the peak current is not too high during the lightest loads, and

has the effect of reducing the skip entry power level.

Figure 14 shows the MPCM with respect to the feedback

voltage, while Figure 15 shows the VLO to FF operation.

To reduce the output power hysteresis between entering

(400 mV typical). The increase in peak current serves to

force the switching frequency to a much lower value, thus

improving the efficiency at light loads. During this mode,

the controller regulates the power delivery by modulating

the switching frequency.

Once in frequency foldback mode, the controller reduces

the switching frequency by adding dead−time after the 6

valley is detected. This dead−time increases as the FB

voltage decreases.

The dead−time circuit is designed to add 0 ms dead−time

and exiting MPCM, the exit threshold (V ) is set

MPCM(exit)

slightly below the entry threshold (550 mV typical). A 1 ms

timer, t , is engaged every time MPCM is entered or

th

MPCM

exited to prevent oscillations during the operating point

th

transition. If at any time FB falls to skip mode, or rises to 5

valley, MPCM will be immediately exited regardless of

when V = 0.6 V and linearly increases the total dead−time

FB

DT(MAX)

t

.

MPCM

to t

(36 ms typical) as V falls down to 0.3 V. The

FB

www.onsemi.com

19

NCP1343

Minimum Peak Current

V

+ V

MPCM(delta)

CS(MIN)

V

MPCM(delta)

V

CS(MIN)

V_FB

V

MPCM(entry)

V_skip

Figure 14. Minimum Peak Current Modulation

Operating Mode

V

decreases

increases

FB

FF

V

FB

Valley 6

Valley 5

Valley 4

Valley 3

Valley 2

Fault !

Valley 1

V

3.5

(V)

0.60 0.67 0.75 0.82 0.90 1.05 1.28 1.35 1.43 1.50 1.65

FB

Figure 15. Valley Lockout Thresholds

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20

NCP1343

Minimum Frequency Clamp and Skip Mode

as the current drive pulses ends – it does not stop

immediately.

Once switching stops, FB will rise. As soon as FB crosses

the skip−exit threshold, drive pulses will resume, but the

controller remains in burst mode. At this point, a 1.25 ms

As mentioned previously, the circuit prevents the

switching frequency from dropping below f (25 kHz

MIN

typical). When the switching cycle would be longer than

40 ms, the circuit forces a new switching cycle. However, the

f

clamp cannot generate a DRV pulse until the

timer, t , is started together with a count−to−3 counter.

quiet

MIN

demagnetization is completed. In other words, it will not

cause operation in CCM.

The next time the FB voltage drops below the skip−in

threshold, drive pulses stop at the end of the current pulse as

long as 3 drive pulses have been counted (if not, they do not

Since the NCP1343 forces a minimum peak current and a

minimum frequency, the power delivery cannot be

continuously controlled down to zero. Instead, the circuit

starts skipping pulses when the FB voltage drops below the

skip level, V , and recovers operation when V exceeds

rd

stop until the end of the 3 pulse). They are not allowed to

start again until the timer expires, even if the skip−exit

threshold is reached first. It is important to note that the

timer will not force the next cycle to begin – i.e. if the natural

skip frequency is such that skip−exit is reached after the

timer expires, the drive pulses will wait for the skip−exit

threshold.

This means that during no−load, there will be a minimum

of 3 drive pulses, and the burst−cycle period will likely be

much longer than 1.25 ms. This operation helps to improve

efficiency at no−load conditions.

skip

FB

V

skip

+ V

. This skip−mode method provides an

skip(HYS)

efficient method of control during light loads.

Quiet−Skip

To further avoid acoustic noise, the circuit prevents the

burst frequency during skip mode from entering the audible

range by limiting it to a maximum of 800 Hz. This is

achieved via a timer (t ) that is activated during

quiet

In order to exit burst mode, the FB voltage must rise higher

Quiet−Skip. The start of the next burst cycle is prevented

until this timer has expired.

As the output power decreases, the switching frequency

decreases. Once it hits 25 kHz, the skip−in threshold is

reached and burst mode is entered − switching stops as soon

than 1 V. If this occurs before t

expires, the drive pulses

quiet

will resume immediately – i.e. the controller won’t wait for

the timer to expire. Figure 16 provides an example of how

Quiet−Skip works.

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21

NCP1343

MAX

Load

Fsw >= 25 kHz

DRV

FB

1.25 ms

Fsw >= 25 kHz

DRV

FB

DRV

FB

DRV

FB

>1.25 ms

DRV

FB

MIN

Load

Figure 16. Quiet−Skip Timing Diagram

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22

NCP1343

POWER EXCURSION MODE (PEM)

In order to achieve 2x power, the off−time clamp is

decreased linearly as the FB voltages increases. This has the

effect of increasing the switching frequency to boost the

output power. The frequency continues to be scaled until the

maximum switching frequency (set by FMAX) or the

When the power demand exceeds the maximum power

limit, the NCP1343 linearly increases the switching

frequency forcing the power stage into CCM. Version

xxxxxE accomplishes a 1.5x power increase by linearly

increasing the switching frequency up to 2.5x, thus

eliminating the need for a larger transformer. Versions

xxxxxA and xxxxxB achieve 2x power by also increasing

the peak current by 25%, requiring a significantly smaller

transformer than a converter that remained in QR mode.

Versions xxxxxC and xxxxxD achieve 2x power by freezing

the switching frequency and increasing the peak current by

50%. This allows for lower switching losses at the expense

of a slightly larger transformer. This is also accomplished in

versions xxxxxA and xxxxxB by pulling the FMAX pin

above 4 V, however the power increase is limited to 1.5x. In

all versions, the maximum switching frequency (and power)

is set by the FMAX pin.

maximum feedback voltage, V

reached.

(3.5 V typical), is

FB(MAX)

This operation continues as long as the controller remains

in PEM, and the PEM comparator is tripped before each

drive turn−off. Once a drive turn−off occurs without first

tripping the PEM comparator, PEM is exited immediately

(in the same cycle) and the controller immediately defaults

back to QR mode with the next switching cycle starting at the

ZCD transition.

Since CCM operation is maintained via off−time

modulation instead of fixed−frequency duty cycle

modulation, the system is naturally immune to subharmonic

oscillations and slope compensation is not required.

In addition to operation in CCM, the NCP1343 contains

The NCP1343 contains a register to store the off−time

during QR mode. During each switching period, the

off−time is measured and the register is updated. As long as

the PEM comparator is not tripped, this operation will

continue indefinitely.

a maximum CS setpoint, V

(typically 1.0 V), to allow

ILIM1

a 25% increase in peak current. When this comparator

triggers, the drive pulse is terminated. This corresponds to

a FB voltage of 3 V (typical). The V

comparator shares

ILIM1

When the PEM comparator is tripped (due to an increase

in power demand), the NCP1343 will enter PEM on the

following cycle. During PEM, the stored value in the

off−time register becomes a maximum off−time clamp, and

when that clamp is reached, the next drive cycle will

commence. Since the demagnetization time of a QR flyback

is directly proportional to the load, as the load increases, the

system will naturally enter CCM with a fixed off−time. The

switching frequency is then determined by the on−time

(which increases with load) and the fixed off−time. This

operation alone provides a 1.5x power increase.

the same LEB as the V

higher than 3 V will not cause any additional increase in

peak current, the switching frequency continues to increase

comparator. While FB voltages

PEM

until the FB pin reaches V

. At this point, the

FB(MAX)

switching frequency will be scaled by a maximum value of

, 2.5 typical, provided FMAX has not been

K

fscale(MAX)

reached. Figure 17 shows the block schematic for PEM,

while Figure 18 shows the timing for a fixed frequency.

Figure 19 shows the timing with a frequency excursion.

www.onsemi.com

23

NCP1343

Figure 17. PEM Block Diagram

Figure 18. PEM Timing for Fixed Frequency

Figure 19. PEM Timing for Scaled Frequency

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24

NCP1343

FAULT MANAGEMENT

The NCP1343 contains three separate fault modes.

external latch input. When the NCP1343 detects a latching

fault, the driver is immediately disabled. The operation

during a latching fault is identical to that of a non−latching

fault except the controller will not attempt to restart at the

Depending on the type of fault, the device will either latch

off, restart when the fault is removed, or resume operation

after the auto−recovery timer expires.

next V

, even if the fault is removed. In order to clear

CC(on)

Latching Faults

Some faults will cause the NCP1343 to latch off. These

include the abnormal OCP (AOCP), V OVP, and the

the latch and resume normal operation, V must first be

allowed to drop below V

Figure 20.

CC

. This operation is shown in

CC(reset)

CC

Fault

Applied

Fault

Removed

time

V_CC

V_CC(on)

V_CC(off)

time

FDRV

I_HV

I_{start 2}

I_start(off)

time

Figure 20. Operation During Latching Fault

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25

NCP1343

Non−Latching Faults

re−enabled when V reaches V

according to the

CC

CC(on)

When the NCP1343 detects a non−latching fault

(brownout or thermal shutdown), the drivers are disabled,

initial power−on sequence, provided V

is above

HV

V

This operation is shown in Figure 21. When V

BO(start).

HV

and V falls towards V

due to the IC internal current

is reaches V

, V immediately charges to V

.

CC

CC(off)

BO(start)

CC

CC(on)

consumption. Once V reaches V

, the HV current

CC(off)

If V is already above V

when the fault is removed,

CC

CC(on)

source turns on and C

begins to charge towards V

.

the controller will start immediately as long as V is above

VCC

CC(on)

HV

When V , reaches V

, the cycle repeats until the fault

V

CC

CC(on)

BO(start).

is removed. Once the fault is removed, the NCP1343 is

Fault

Applied

Fault

Removed

time

Waits for next

V_CC(on)before

starting

V_CC

V_CC(on)

V_{CC(off )}

time

FDRV

I_HV

I_{start 2}

I_{start (off)}

time

Figure 21. Operation During Non−Latching Fault

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26

NCP1343

Auto−recovery Timer Faults

Some faults faults cause the NCP1343 auto−recovery

timer to run. If an auto−recovery fault is detected, the gate

drive is disabled and the auto−recovery timer, t

(typically 1.2 s), starts. While the auto−recovery timer is

running, the HV current source turns on and off to maintain

between V and V . Once the auto−recovery

V

cc

cc(off)

cc(on)

timer expires, the controller will attempt to start normally at

the next V provided V is above V . This

autorec

CC(on)

HV

BO(start)

operation is shown in Figure 22.

Fault

Applied

Fault

Removed

Fault

time

V_CC

V_CC(on)

V_CC(off)

Restarts

At V_CC(on)

(new burst

cycle if Fault

still present)

time

DRV

Controller

stops

Autorecovery

Timer

1.2 s

t_restart

time

Figure 22. Operation During Auto−Recovery Fault

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27

NCP1343

PROTECTION FEATURES

Brownout Protection

A timer is enabled once V

Figure 23 shows the brownout detector waveforms during

a brownout.

When a brownout is detected, the controller stops

switching and enters non−latching fault mode (see

Figure 21). The HV current source alternatively turns on and

drops below its disable

HV

threshold, V

(typically 99 V). The controller is

BO(stop)

disabled if V

doesn’t exceed V

before the

HV

BO(stop)

brownout timer, t (typically 54 ms), expires. The timer is

BO

set long enough to ignore a two cycle dropout. The timer

starts counting once V drops below V

off to maintain V between V

and V

until the

CC

CC(on)

CC(off)

.

input voltage is back above V

.

HV

BO(stop)

BO(start)

V_HV

V_{BO(start )}

V_BO(stop)

time

Fault

Cleared

Brownout

Timer

Brownout

detected

Starts

Charging

Immediately

V_CC

Restarts at

next V _CC(on)

V_CC(on)

V_CC(off)

t_{delay (start )}

time

DRV

Figure 23. Operation During Brownout

Dedicated Fault Input

and lower fault thresholds. Figure 24 shows the architecture

of the Fault input.

The Fault input signal is filtered to prevent noise from

triggering the fault detectors. Upper and lower fault detector

The NCP1343 includes a dedicated fault input accessible

via the Fault pin (8−pin and 9−pin versions only). The

controller can be latched by pulling up the pin above the

upper fault threshold, V

(typically 3.0 V). The

blanking delays, t

and t ,are both

delay(OTP)

Fault(OVP)

delay(OVP)

controller is disabled if the Fault pin voltage is pulled below

the lower fault threshold, V (typically 0.4 V).

typically 30 ms. A fault is detected if the fault condition is

asserted for a period longer than the blanking delay.

Fault(OTP_in)

The lower threshold is normally used for detecting an

overtemperature fault. The controller operates normally

while the Fault pin voltage is maintained within the upper

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28

NCP1343

OVP

voltage drop across the thermistor. The resistance of the

An active clamp prevents the Fault pin voltage from

NTC thermistor decreases at higher temperatures resulting

in a lower voltage across the thermistor. The controller

detects a fault once the thermistor voltage drops below

reaching the upper latch threshold if the pin is open. To reach

the upper threshold, the external pull−up current has to be

higher than the pull−down capability of the clamp (set by

V

.

Fault(OTP_in)

R

at V

), i.e., approximately 1 mA.

The controller bias current is reduced during power up by

Fault(clamp)

The upper fault threshold is intended to be used for an

disabling most of the circuit blocks including I

.

Fault(OTP)

overvoltage fault using a zener diode and a resistor in series

from the auxiliary winding voltage. The controller is latched

This current source is enabled once V reaches V

. A

CC

CC(on)

filter capacitor is typically connected between the Fault and

GND pins. This will result in a delay before V reaches

once V

exceeds V

.

Fault

Fault(OVP)

Fault

Once the controller is latched, it follows the behavior of

a latching fault according to Figure 20 and is only reset if

its steady state value once I

the lower fault comparator (i.e. overtemperature detection)

is ignored during soft−start.

is enabled. Therefore,

Fault(OTP)

V

CC

is reduced to V

. In the typical application these

CC(reset)

conditions occur only if the ac voltage is removed from the

system.

Versions Bxxxxx, Dxxxxx and Fxxxxx latch off the

controller after an overtemperature fault is detected

according to Figure 20. In Versions Axxxxx, Cxxxxx and

Exxxxx, the controller is re−enabled once the fault is

OTP

The lower fault threshold is intended to be used to detect

an overtemperature fault using an NTC thermistor. A pull up

removed such that V

increases above V

,

Fault

Fault(OTP_out)

the auto−recovery timer expires, and V reaches V

CC

CC(on)

current source, I

(typically 45.0 mA), generates a

Fault(OTP)

as shown in Figure 22.

Figure 24. Fault Pin Internal Schematic

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29

NCP1343

Overload Protection

• Enters a safe, low duty−ratio auto−recovery mode

(versions Axxxxx and Bxxxxx).

• The overload protection is disabled in versions Exxxxx

and Fxxxxx.

The overload timer integrates the duration of the overload

fault. That is, the timer count increases while the fault is

present and reduces its count once it is removed. The

overload timer duration, t

the overload timer expires, the controller detects an overload

condition does one of the following:

, is typically 160 ms. When

OVLD

Figure 25 shows the overload circuit schematic, while

Figure 26 and Figure 27 show operating waveforms for

latched and auto−recovery overload conditions.

• The controller latches off (versions Cxxxxx and

Dxxxxx) or

V

FB(open)

R

FB

PWM

K

FB

t

OVLD

LEB1

CS

OCP + OPP

Count Down

Count Up

V

OPP

ZCD/OPP

V

ILIM1

DRV Off

AOCP

t

LEB2

Abnormal OCP

Count 4

V

ILIM2

Figure 25. Overload Circuitry

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30

NCP1343

Latch

Event

Fault

Latch

time

V_CC

V_CC(on)

V_CC(off)

time

DRV

I_HV

I_start2

I_HV(off)

time

Figure 26. Latched Overload Operation

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31

NCP1343

Fault

disappears

Overcurrent

applied

Output Load

Max Load

time

Fault Flag

Fault

timer

starts

V_CC

V_CC(on)

V_CC(off)

Restarts

At V_CC(on)

(new burst

cycle if Fault

still present)

time

DRV

Controller

stops

Fault timer

160 ms

time

t_OVLD

t_restart

t_delay(start)

Figure 27. Auto−Recovery Overload Operation

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32

NCP1343

Abnormal Overcurrent Protection (AOCP)

core. Due to the valley timeout feature of the controller, the

flux level will quickly walk up until the core saturates. This

can cause excessive stress on the primary MOSFET and

secondary diode. This is not a problem for the NCP1343,

however, because the valley timeout timer is disabled while

the ZCD Pin voltage is above the arming threshold. Since the

leakage energy is high enough to arm the ZCD trigger, the

timeout timer is disabled and the next drive pulse is delayed

until demagnetization occurs.

Under some severe fault conditions, like a winding

short−circuit, the switch current can increase very rapidly

during the on−time. The current sense signal significantly

exceeds V

, but because the current sense signal is

ILIM1

blanked by the LEB circuit during the switch turn−on, the

power switch current can become huge and cause severe

system damage.

The NCP1343 protects against this fault by adding an

additional comparator for Abnormal Overcurrent Fault

detection. The current sense signal is blanked with a shorter

V_CCOvervoltage Protection

An additional comparator on the V pin monitors the

CC

LEB duration, t

, typically 125 ns, before applying it to

LEB2

V

CC

voltage. If VCC exceeds VCC(OVP), the gate drive is

the Abnormal Overcurrent Fault Comparator. The voltage

threshold of the comparator, V , typically 1.2 V, is set

disabled and the NCP1343 follows the operation of a

latching fault (see Figure 20).

ILIM2

50% higher than V

, to avoid interference with normal

ILIM1

operation. Four consecutive Abnormal Overcurrent faults

cause the controller to enter latch mode. The count to 4

provides noise immunity during surge testing. The counter

is reset each time a DRV pulse occurs without activating the

Fault Overcurrent Comparator.

Thermal Shutdown

An internal thermal shutdown circuit monitors the

junction temperature of the controller. The controller is

disabled if the junction temperature exceeds the thermal

shutdown threshold, T

thermal shutdown fault is detected, the controller enters a

non−latching fault mode as depicted in Figure 21. The

controller restarts at the next V

temperature drops below below T

shutdown hysteresis, T

(typically 140°C). When a

SHDN

Current Sense Pin Failure Protection

A 1mA (typically) pull−up current source, I , pulls up the

CS

once the junction

CC(on)

CS pin to disable the controller if the pin is left open.

by the thermal

SHDN

Additionally, the maximum on−time, t

(32 ms

on(MAX)

, typically 40°C.

SHDN(HYS)

typically), prevents the MOSFET from staying on

permanently if the CS Pin is shorted to GND.

The thermal shutdown is also cleared if V drops below

CC

V

. A new power up sequence commences at the next

once all the faults are removed.

CC(reset)

Output Short Circuit Protection

CC(on)

During an output short−circuit, there is not enough

voltage across the secondary winding to demagnetize the

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33

NCP1343

TYPICAL CHARACTERISTICS

17.14

17.12

17.1

9

8.99

8.98

8.97

8.96

8.95

8.94

8.93

17.08

17.06

17.04

17.02

17

16.98

16.96

16.94

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 28. V_CC(on)vs. Temperature

Figure 29. V_CC(off)vs. Temperature

0.6

0.5

0.4

0.3

0.2

0.1

0

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

−40

−20

0

20

40

60

80

100 120

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 30. I_start1vs. Temperature

Figure 31. I_start2vs. Temperature

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 32. I_HV(off1)vs. Temperature

Figure 33. I_HV(off2)vs. Temperature

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34

NCP1343

TYPICAL CHARACTERISTICS

0.126

0.124

0.122

0.120

0.118

0.116

0.114

0.112

0.110

0.108

0.106

0.255

0.250

0.245

0.240

0.235

0.230

0.225

0.220

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 34. I_CC1vs. Temperature

Figure 35. I_CC2vs. Temperature

1.075

1.070

1.065

1.060

1.055

1.050

1.045

1.040

1.035

1.030

28.35

28.3

28.25

28.2

28.15

28.1

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 36. I_CC3vs. Temperature

Figure 37. V_CC(OVP)vs. Temperature

112.6

112.4

112.2

112

111.8

111.6

111.4

111.2

110

110.8

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

Figure 38. V_BO(start)vs. Temperature

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35

NCP1343

TYPICAL CHARACTERISTICS

98.2

98

90

80

70

60

50

40

30

20

10

0

CDRV = 1 nF

97.8

97.6

97.4

97.2

97

CDRV = 100 pF

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 39. V_BO(stop)vs. Temperature

Figure 40. t_DRV(rise)vs. Temperature

45

40

35

30

25

20

15

10

5

111.8

111.6

111.4

111.2

111

CDRV = 1 nF

110.8

110.6

110.4

110.2

CDRV = 100 pF

0

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 41. t_DRV(fall)vs. Temperature

Figure 42. f_MAX1vs. Temperature

367

366.5

366

73.45

73.4

73.35

73.3

73.25

73.2

73.15

73.1

73.05

73

365.5

365

364.5

364

363.5

363

362.5

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 43. f_MAX2vs. Temperature

Figure 44. f_MAX3vs. Temperature

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36

NCP1343

TYPICAL CHARACTERISTICS

32.5

32.4

32.3

32.2

32.1

32

63.6

63.5

63.4

63.3

63.2

63.1

63

31.9

31.8

31.7

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 45. t_on(MAX)vs. Temperature

Figure 46. V_ZCD(trig)vs. Temperature

25.65

25.6

12.95

12.9

12.85

12.8

25.55

25.5

25.45

25.4

12.75

25.35

12.7

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 47. V_ZCD(HYS)vs. Temperature

Figure 48. V_ZCD(MAX)vs. Temperature

0

−0.1

−0.2

−0.3

−0.4

−0.5

−0.6

−0.7

−0.8

−0.9

198.8

198.6

198.4

198.2

198

197.8

197.6

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 49. V_ZCD(MIN)vs. Temperature

Figure 50. V_CS(MIN)vs. Temperature

www.onsemi.com

37

NCP1343

TYPICAL CHARACTERISTICS

1.31

1.308

1.306

1.304

1.302

1.3

104.2

104

103.8

103.6

103.4

103.2

103

1.298

1.296

1.294

102.8

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 51. f_jittervs. Temperature

Figure 52. V_jittervs. Temperature

3.1

3.09

3.08

3.07

3.06

3.05

3.04

3.03

402.5

402

401.5

401

400.5

400

399.5

399

−40

−20

0

20

40

60

80

100 120

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 53. V_Fault(OVP)vs. Temperature

Figure 54. V_{Fault(OTP_in)}vs. Temperature

920

918

916

914

912

910

908

906

45.1

45

44.9

44.8

44.7

44.6

44.5

44.4

44.3

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 55. V_{Fault(OTP_out)}vs. Temperature

Figure 56. I_OTPvs. Temperature

www.onsemi.com

38

NCP1343

TYPICAL CHARACTERISTICS

1.731

1.73

1.55

1.545

1.54

1.535

1.53

1.729

1.728

1.727

1.726

1.525

1.52

1.515

1.51

1.505

1.5

1.495

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 57. V_Fault(clamp)vs. Temperature

Figure 58. R_Fault(clamp)vs. Temperature

24.5

24.45

24.4

1.39

1.385

1.38

24.35

24.3

24.25

24.2

1.375

1.37

24.15

24.1

24.05

1.365

24

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 59. f_MINvs. Temperature

Figure 60. t_quietvs. Temperature

840

830

820

810

800

790

780

0.8

0.799

0.798

0.797

0.796

0.795

0.794

0.793

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 61. t_ZCD(blank)vs. Temperature

Figure 62. V_ILIM1vs. Temperature

www.onsemi.com

39

NCP1343

TYPICAL CHARACTERISTICS

1.202

1.201

1.2

40

39.9

39.8

39.7

39.6

39.5

39.4

39.3

39.2

39.1

1.199

1.198

1.197

1.196

1.195

1.194

1.193

−40

−20

0

20

40

60

80

100 120

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 64. t_DT(MAX)vs. Temperature

Figure 63. V_ILIM2vs. Temperature

399

398.5

398

397.5

397

396.5

396

−40

−20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

Figure 65. V_skipvs. Temperature

www.onsemi.com

40

NCP1343

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

−X−

A

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

1.27 BSC

0.050 BSC

−Z−

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

0.10 (0.004)

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

41

NCP1343

PACKAGE DIMENSIONS

SOIC−9 NB

CASE 751BP

ISSUE A

2X

NOTES:

0.10

C

A-B

0.10

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

D

H

A

2X

0.20

C

4 TIPS

C A-B

F

10

6

E

1

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

5

L2

A3

SEATING

PLANE

L

C

0.20

C

9X b

DETAIL A

B

5 TIPS

M

MILLIMETERS

0.25

C A-B D

DIM MIN

MAX

1.75

0.25

0.51

5.00

4.00

TOP VIEW

A

A1

A3

b

1.25

0.10

0.17

0.31

4.80

3.80

9X

h

X 45

_

0.10

C

0.10

C

D

E

M

e

1.00 BSC

H

h

5.80

0.37 REF

6.20

A

L

L2

M

0.40

0

1.27

0.25 BSC

DETAIL A

e

SIDE VIEW

A1

SEATING

PLANE

C

8

_

END VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

1.00

9X

0.58

PITCH

6.50

1

9X

1.18

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

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42


型号：	NCP1343BADBDEAD1R2G
厂家：	ONSEMI
描述：	High Frequency Quasi- Resonant Flyback Controller
文件：	总42页 (文件大小：705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1343BADBDEAD1R2G [ONSEMI]

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