NCP1351DPG [ONSEMI]
Variable Off Time PWM Controller;
| 型号： | NCP1351DPG |
| 厂家： | 
ONSEMI |
| 描述： | Variable Off Time PWM Controller 开关 光电二极管 |
| 文件： | 总27页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1351
Variable Off Time PWM
Controller
The NCP1351 is a current-mode controller targeting low power
off-line flyback Switched Mode Power Supplies (SMPS) where cost
is of utmost importance. Based on a fixed peak current technique
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MARKING DIAGRAMS
(quasi-fixed T ), the controller decreases its switching frequency as
ON
the load becomes lighter. As a result, a power supply using the
NCP1351 naturally offers excellent no-load power consumption,
while optimizing the efficiency in other loading conditions. When the
frequency decreases, the peak current is gradually reduced down to
approximately 30% of the maximum peak current to prevent
transformer mechanical resonance. The risk of acoustic noise is thus
greatly diminished while keeping good standby power performance.
An externally adjustable timer permanently monitors the feedback
activity and protects the supply in presence of a short-circuit or an
overload. Once the timer elapses, NCP1351 stops switching and stays
latched for version A, and tries to restart for version B.
Versions C and D include a dual overcurrent protection trip point,
allowing the implementation of the controller in peak-power
requirements applications such as printers and so on. When the fault is
acknowledged, C version latches-off whereas D version
auto-recovers.
8
SOIC-8
D SUFFIX
CASE 751
1351x
ALYW
G
8
1
1
NCP1351x
AWL
YYWWG
PDIP-8
P SUFFIX
CASE 626
8
1
1
x
= A, B, C, or D Options
= Assembly Location
A
L, WL = Wafer Lot
Y, YY = Year
The internal structure features an optimized arrangement which
allows one of the lowest available startup current, a fundamental
parameter when designing low standby power supplies.
W, WW = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
The negative current sensing technique minimizes the impact of the
switching noise on the controller operation and offers the user to select
the maximum peak voltage across his current sense resistor. Its power
dissipation can thus be application optimized.
Finally, the bulk input ripple ensures a natural frequency smearing
which smooths the EMI signature.
PIN CONNECTIONS
FB
Ct
TIMER
LATCH
1
2
3
4
8
7
6
5
CS
V
CC
Features
•ꢀQuasi-fixed T , Variable T
Current Mode Control
ON
OFF
GND
DRV
•ꢀExtremely Low Current Consumption at Startup
•ꢀPeak Current Compression Reduces Transformer Noise
•ꢀPrimary or Secondary Side Regulation
•ꢀDedicated Latch Input for OTP, OVP
•ꢀProgrammable Current Sense Resistor Peak Voltage
•ꢀNatural Frequency Dithering for Improved EMI Signature
•ꢀEasy External Over Power Protection (OPP)
•ꢀUndervoltage Lockout
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
•ꢀVery Low Standby Power via Off-time Expansion
•ꢀSOIC-8 Package
Typical Applications
• Standard Overcurrent Protection, Latched or
Auto-Recovery, A & B Versions
• Auxiliary Power Supply
• Printer, Game Stations, Low-Cost Adapters
• Off-line Battery Charger
• Dual Trip Point Overcurrent Protection, Latched or
Auto-Recovery, C & D Versions
• These are Pb-Free Devices
©ꢀ Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 3
1
Publication Order Number:
NCP1351/D
NCP1351
V
OUT
+
NCP1351
LATCH
+
1
2
3
4
8
85-265VAC
*OPP
7
6
5
+
GND
*Optional
Figure 1. Typical Application Circuit
PIN FUNCTION DESCRIPTION
Pin N°
Pin Name
FB
Function
Feedback Input
Oscillator Frequency
Current Sense Input
–
Pin Description
Injecting Current in this Pin Reduces Frequency
1
2
3
4
5
6
7
8
Ct
A capacitor sets the maximum switching frequency at no feedback current
CS
Senses the Primary Current
–
GND
DRV
Driver Output
Driving Pulses to the Power MOSFET
Supplies the controller up to 28 V
V
CC
Supply Input
Latch
Timer
Latchoff Input
Fault Timer Capacitor
A positive voltage above V
fully latches off the controller
LATCH
Sets the time duration before fault validation
OVERCURRENT PROTECTION ON NCP1351 VERSIONS:
NCP1351
Auto-recovery
Latched
Dual level
A
B
C
D
x
x
x
x
x
x
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2
NCP1351
INTERNAL CIRCUIT ARCHITECTURE
V
DD
20 ꢀ s Filter
+
-
V
DD
+
V
I
TIMER
TIMER
FB
TIMER
UVLO Reset
Fault = Low
+
-
I
P Flag
40 ꢀꢁ
+
V
Fault
V
20 ꢀ s Filter
DD
+
-
IC
LATCH
t
+
S
Ct
V
LATCH
Q
Q
UVLO Reset
45k
R
V
DD
V
CC
Mngt
4V Reset
V
ZENER
V
CC
V
CCSTOP
Clamp
V
1 = OK
DD
V
OFFset
0 = not OK
1 ꢀ s
+
Pulse
ICS-dif*
ICS-dif*
S
Q
DRV
Q
CS
ICS-min*
R
-
+
GND
+
Vth
*(ICS-diff = ICS-max -ICS-min)
Figure 2. A Version (Latched Short-Circuit Protection)
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3
NCP1351
V
DD
+
-
V
DD
+
S
Q
Q
VI
TIMER
I
TIMER
FB
TIMER
UVLO Reset
Fault = Low
R
+
-
I
P Flag
40 ꢀꢁ
+
V
Fault
V
20 ꢀ s Filter
DD
+
-
IC
LATCH
t
+
S
Ct
V
LATCH
Q
Q
UVLO Reset
45k
R
V
DD
V
CC
Mngt
4V Reset
V
ZENER
V
CC
VCC
STOP
Clamp
V
1 = OK
0 = not OK
DD
V
OFFset
1 ꢀ s
+
Pulse
ICS-dif*
ICS-dif*
S
Q
DRV
Q
CS
ICS-min*
R
-
+
GND
+
Vth
*(ICS-diff = ICS-max -ICS-min)
Figure 3. B Version (Auto-recovery Short-Circuit Protection)
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4
NCP1351
V
DD
20 ꢀ s Filter
+
-
V
DD
+
V
I
TIMER
TIMER
FB
TIMER
UVLO Reset
Fault = Low
+
-
D
Q
I
P Flag
40 ꢀꢁ
+
V
Fault
CLK
V
20 ꢀ s Filter
DD
+
-
IC
LATCH
t
+
S
Ct
V
LATCH
Q
Q
UVLO Reset
45k
R
V
DD
V
CC
Mngt
4V Reset
V
ZENER
V
CC
VCC
STOP
Clamp
V
1 = OK
0 = not OK
DD
V
OFFset
1 ꢀ s
+
Pulse
ICS-dif*
ICS-dif*
S
Q
DRV
Q
CS
ICS-min*
R
-
+
GND
+
Vth
*(ICS-diff = ICS-max -ICS-min)
Figure 4. C Version (Latched Short-Circuit Protection)
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5
NCP1351
V
DD
+
-
V
DD
+
S
Q
Q
VI
TIMER
I
TIMER
FB
TIMER
UVLO Reset
Fault = Low
R
+
-
D
Q
I
P Flag
40 ꢀꢁ
+
V
Fault
V
20 ꢀ s Filter
DD
CLK
+
-
IC
LATCH
t
+
S
Ct
V
LATCH
Q
Q
UVLO Reset
45k
R
V
DD
V
CC
Mngt
4V Reset
V
ZENER
V
CC
VCC
STOP
Clamp
V
1 = OK
0 = not OK
DD
V
OFFset
1 ꢀ s
+
Pulse
ICS-dif*
ICS-dif*
S
Q
DRV
Q
CS
ICS-min*
R
-
+
GND
+
Vth
*(ICS-diff = ICS-max -ICS-min)
Figure 5. D Version (Auto-recovery Short-Circuit Protection)
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6
NCP1351
MAXIMUM RATINGS
Symbol
Rating
Value
-0.3 to 28
20
Unit
V
V
Maximum Supply on V Pin 6
CC
SUPPLY
SUPPLY
I
Maximum Current in V Pin 6
CC
mA
V
V
I
Maximum Voltage on DRV Pin 5
Maximum Current in DRV Pin 5
-0.3 to 20
$400
-0.3 to 10
$10
DRV
mA
V
DRV
V
Supply Voltage on all pins, except Pin 6 (V ), Pin 5 (DRV)
CC
MAX
MAX
I
Maximum Current in all Pins Except Pin 6 (V ) and Pin 5 (DRV)
CC
mA
mA
kꢂ
°C/W
I
Maximum Injected Current in Pin 1 (FB)
Minimum Resistive Load on DRV Pin
Thermal Resistance Junction-to-Air
0.5
FBmax
R
33
Gmin
R
PDIP-8
SOIC-8
142
176
ꢃ
JA
T
JMAX
Maximum Junction Temperature
Storage Temperature Range
150
°C
°C
kV
V
-60 to +150
ESD Capability, Human Body Model V per Mil-STD-883, Method 3015
ESD Capability, Machine Model
2
200
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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7
NCP1351
Electrical Characteristics (For typical values T = 25°C, for Min/Max Values T = -25°C to +125°C, Max T = 150°C, V = 12 V
J
J
J
CC
unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION AND V MANAGEMENT
CC
VCC
V
V
Increasing Level at Which Driving Pulses are Authorized
Decreasing Level at Which Driving Pulses are Stopped
6
6
6
6
6
6
6
6
6
15
8.3
6
18
8.9
-
22
9.5
-
V
V
ON
STOP
CC
CC
VCC
VCC
Hysteresis VCC - VCC
ON STOP
V
HYST
V
Clamped V When Latched Off
CC
-
6
-
V
ZENER
ICC1
ICC2
ICC3
ICC4
Startup Current
-
-
10
1.8
2.5
-
ꢀ A
mA
mA
ꢀ A
ꢀ A
Internal IC Consumption with I = 50 ꢀ A, F
FB
= 65 kHz and C = 0
L
-
1.0
1.6
600
-
SW
Internal IC Consumption with I = 50 ꢀ A, F
FB
= 65 kHz and C = 1 nF
L
-
SW
Internal IC Consumption in Auto-Recovery Latch-off Phase
Current Flowing into V pin that Keeps the Controller Latched
-
ICC
20
-
LATCH
CC
CURRENT SENSE
I
I
Minimum Source Current (I = 90 ꢀ A)
FB
T = 0°C to +125°C
3
3
3
3
3
3
61
58
70
70
75
75
ꢀ A
ꢀ A
ꢀ A
ꢀ A
mV
ns
CSmin
CSmin
J
Minimum Source Current (I = 90 ꢀ A)
FB
T = -25°C to +125°C
J
I
Maximum Source Current (I = 50 ꢀ A)
FB
T = 0°C to +125°C
J
251
242
10
270
270
20
289
289
35
CSmax
CSmax
I
Maximum Source Current (I = 50 ꢀ A)
FB
T = -25°C to +125°C
J
V
TH
Current Sense Comparator Threshold Voltage
t
Propagation Time Delay (CS Falling Edge to Gate Output)
TIMING CAPACITOR
Minimum Voltage on C Capacitor, I = 30 ꢀ A
-
160
300
delay
V
2
2
2
475
5
510
-
565
-
mV
V
OFFSET
T
FB
VCT
Voltage on C Capacitor at I = 150 ꢀ A
T FB
MAX
I
CT
Source Current (Ct Pin Grounded)
T = 25°C
9.8
9.3
10.8
10.8
11.8
11.9
ꢀ A
J
T = -25°C to +125°C
J
VCT
Minimum Voltage on C , Discharge Switch Activated
T
2
2
2
-
-
1
20
mV
ꢀ s
V
MIN
T
C Capacitor Discharge Time (Activated at DRV Turn-on)
T
DISCH
V
FAULT
C Capacitor Level at Which Fault Timer Starts
T
A and B Versions
C and D Version
0.4
-
0.5
0.96
0.6
-
K
FAULT
Factor Linking V
and V
(Note 1)
C and D Version
-
1.67
1.86
2.05
OFFSET
FAULT
FEEDBACK SECTION
V
FB Pin Voltage for an Injected Current of 200 ꢀ A
1
1
-
0.7
-
V
FB
FAULT
I
FB Current Under Which a Fault is Detected
A and B Versions
C and D Versions
-
-
40
51
-
-
ꢀ
A
I
FB Current at Which CS Compression Starts
1
1
-
-
60
80
-
-
ꢀ A
ꢀ A
FBcomp
I
FB Current at Which CS Compression is Finished
FBred
DRIVE OUTPUT
Output Voltage Rise-time @ CL = 1 nF, 10 - 90% of Output Signal
T
r
5
5
5
5
5
5
-
-
90
100
80
30
-
-
-
ns
ns
ꢂ
ꢂ
V
T
f
Output Voltage Fall-time @ CL = 1 nF, 10 - 90% of Output Signal
R
Source Resistance
Sink Resistance
-
-
OH
R
-
-
OL
V
DRV Pin Level at V Close to VCC with a 33 kꢂ Resistor to GND
CC STOP
8.0
15
-
DRVlow
V
DRV Pin Level at V = 28 V with 33 kꢂ Resistor to GND
CC
17
20
V
DRVhigh
Protection
I
Timing Capacitor Charging Current
Fault Voltage on Pin 8
8
8
-
7
10
4.5
-
11.5
5
13
5.5
-
ꢀ A
V
TIMER
V
T
TIMER
TIMER
LATCH
Fault Timer Duration, C
Latching Voltage
= 100 nF
42
5
ms
V
TIMER
V
4.5
5.5
1. Guaranteed by design.
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8
NCP1351
The NCP1351 implements a fixed peak current mode
• Extended V Range: By accepting V levels up to
CC
CC
technique whose regulation scheme implements a variable
switching frequency. As shown on the typical application
diagram, the controller is designed to operate with a
minimum number of external components. It incorporates
the following features:
28 V, the device offers added flexibility in presence of
loosely coupled transformers. The gate drive is safely
clamped below 20 V to avoid stressing the driven
MOSFET.
• Easy OPP: Connecting a resistor from the CS pin to
the auxiliary winding allows easy bulk voltage
compensation.
• Frequency Foldback: Since the switching period
increases when power demand decreases, the switching
frequency naturally diminishes in light load conditions.
This helps to minimize switching losses and offers
good standby power performance.
• Secondary or Primary Regulation: The feedback
loop arrangement allows simple secondary or primary
side regulation without significant additional external
components.
• Very Low Startup Current: The patented internal
supply block is specially designed to offer a very low
current consumption during startup. It allows the use of
a very high value external startup resistor, greatly
reducing dissipation, improving efficiency and
minimizing standby power consumption.
• Latch Input: If voltage on Pin 7 is externally brought
above 5 V, the controller permanently latches off and
stays latched until the user cycles V down, below 4
CC
V typically.
• Fault Timer: In presence of badly coupled transformer,
it can be quite difficult to detect an overload or a
short-circuit on the primary side. When the feedback
current disappears, a current source charges a capacitor
connected to Pin 8. When the voltage on this pin
reaches a certain level, all pulses are shut off and the
• Natural Frequency Dithering: The quasi-fixed t
ON
mode of operation improves the EMI signature since
the switching frequency varies with the natural bulk
ripple voltage.
• Peak Current Compression: As the load becomes
lighter, the frequency decreases and can enter the
audible range. To avoid exciting transformer
mechanical resonances, hence generating acoustic
noise, the NCP1351 includes a patented technique,
which reduces the peak current as power goes down. As
such, inexpensive transformer can be used without
having noise problems.
V
voltage is pulled down below the VCC
(min)
This protection is latched on the A version (the
level.
CC
controller must be shut down and restart to resume
normal operation), and auto-recovery on Version B (if
the fault goes away, the controller automatically
resumes operation).
• Dual Trip Point: in some applications, such as printer
power supplies, it is necessary to let the power supply
deliver more power on a transient event. If the event
lasts longer than what the fault timer authorizes, then
the NCP1351 either latches-off (C Version) or enters an
auto-recovery mode (D Version). The level at which
the timer starts is internally set to 55% of the maximum
power capability.
• Negative Primary Current Sensing: By sensing the
total current, this technique does not modify the
MOSFET driving voltage (V ) while switching.
GS
Furthermore, the programming resistor, together with
the pin capacitance, forms a residual noise filter which
blanks spurious spikes.
• Programmable Primary Current Sense: It offers a
second peak current adjustment variable, which
improves the design flexibility.
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9
NCP1351
APPLICATION INFORMATION
The Negative Sensing Technique
current increases. When the result reaches the threshold
voltage (around 20 mV), the comparator toggles and resets
the main latch. Figure 3 details how the voltage moves on the
CS pin on a 1351 demoboard, whereas Figure 9 zooms on
the sense resistor voltage captured by respect to the
controller ground.
The choice of these two elements is simple. Suppose you
want to develop 1 V across the sense resistor. You would
select the offset resistor via the following formula:
Standard current-mode controllers use the positive
sensing technique as portrayed by Figure 6. In this
technique, the controller detects a positive voltage drop
across the sense resistor, representative of the flowing
current. Unfortunately, this solution suffers from the
following drawbacks:
1. Difficulties to precisely adjust the peak current. If
1 V is the maximum sense level, you must
combine low valued resistors to reach the exact
limit you need.
2. The voltage developed across the sense resistor
1
1
R
+
+
+ 3.7ꢀkꢂ
(eq. 1)
offset
270ꢀꢀ
I
CS
If you need a peak current of 2 A, then, simply apply the
ohm law to obtain the sense resistor value:
subtracts from the gate voltage. If your VCC
(min)
is 7 V, then the actual gate voltage at the end of the
on time, assuming a full load condition, is 7 V –
1 V = 6 V.
1
1
2
R
+
+
+ 0.5ꢀꢂ
(eq. 2)
sense
I
peak_max
3. The current in the sense resistor also includes the
current at turn-on. This narrow spike often
Due to the circuit flexibility, suppose you only have access
to a 0.33 ꢂ resistor. In that case, the peak current will exceed
the 2 A limit. Why not changing the offset resistor value
then? To obtain 2 A from the 0.33 ꢂ resistor, you should
develop:
C
iss
disturbs the controller and requires adequate
treatment through a LEB circuitry for instance.
Figure 7 represents the negative current sense technique.
In this simplified example, the source directly connects to
the controller ground. Hence, if V is 8 V, the effective
The offset resistor is thus derived by:
CC
V
+ R
I
sense peak_max
+ 0.33 2 + 660ꢀmV
gate-source voltage is very close to 8 V: no sense resistor
drop. How does the controller detect a negative excursion?
In lack of primary current, the voltage on the CS pin reaches
sense
(eq. 3)
0.66
0.66
R
offset
x I . Let us assume that these elements lead to have
CS
R
+
+
+ 2.44ꢀkꢂ
(eq. 4)
offset
270ꢀꢀ
I
CS
1 V on this pin. Now, when the power MOSFET activates,
the current flows via the sense resistor and develop a
negative voltage by respect to the controller ground. The
voltage seen on the CS is nothing else than a positive voltage
If reducing the sense resistor is of good practice to
improve the efficiency, we recommend to adopt sense values
between 0.5 V and 1 V. Reducing the voltage below these
levels will degrade the noise immunity.
(R
x I ) plus the voltage across the sense resistor which
offset CS
is negative. Thus, the CS pin voltage goes low as the primary
I
Lp
L
L
P
P
DRV
DRV
CS
V
DD
+
+
ICS
C
C
V
gs
Bulk
Bulk
CS
R
I
Lp
I
Lp
GND
-
+
Reset
+
-
Reset
I
I
Lp
Lp
Peak
Setpoint
offset
R
+
V
sense
offset
V
V
th
sense
I
Lp
I
Lp
GND
V
sense
Figure 6. Positive Current-Sense Technique
Figure 7. A Simplified Circuit of the Negative Sense
Implementation
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10
NCP1351
Current Sense Resistor
Current Sense Pin
Figure 8. The Voltage on the Current Sense Pin
Figure 9. The Voltage Across the Sense
Resistor
Below are a few recommendations concerning the wiring
and the PCB layout:
in this NCP1351 for simplicity and ease of implementation.
Thus, once the peak current has been selected, the feedback
loop automatically reacts to satisfy Equations 5 and 6. The
external capacitor that you connect between pin 2 and
ground (again, place it close to the controller pins) sets the
maximum frequency you authorize the converter to operate
up to. Normalized values for this timing capacitor are
270 pF (65 kHz) and 180 pF (100 kHz). Of course, different
combinations can be tried to design at higher or lower
frequencies. Please note that changing the capacitor value
does not affect the operating frequency at nominal line and
load conditions. Again, the operating frequency is selected
by the feedback loop to cope with Equations 5 and 6
definitions.
• A small 22 pF capacitor can be placed between the CS
pin and the controller ground. Place it as close as
possible to the controller.
• Do not place the offset resistor in the vicinity of the
sense element, but put it close to the controller as well.
• Regulation by frequency
• The power a flyback converter can deliver relates to the
energy stored in the primary inductance Lp and obeys
the following formulae:
1
2
(eq. 5)
(eq. 6)
P
+ ꢁ L ꢁI
ꢁF
P peak SW
ꢁꢄ
out_DCM
2
The feedback current controls the frequency by changing
the timing capacitor end of charge voltage, as illustrated by
Figure 10.
The timing capacitor ending voltage can be precisely
computed using the following formula:
1
2
2
)
F
(
2 P peak
P
+
ꢁL
I
* I
ꢁꢄ
out_CCM
valley SW
Where:
ꢄ (eta) is the converter efficiency
is the peak inductor current reached at the on time
I
peak
VCt + 45ꢀkꢀ(IFB * 40u) ) 500m
termination
represents the current at the end of the off time. It
(eq. 7)
I
valley
Where I represents the injected current inside the FB
FB
equals zero in DCM.
is the operating frequency.
Thus, to control the delivered power, we can either play on
pin (pin 1). The 40u term corresponds to a 40 ꢀ ꢁ offset
current purposely placed to force a minimum current
injection when the loop is closed. This allows the controller
to detect a short-circuit condition as the feedback current
drops to zero in that condition.
F
SW
the peak current setpoint (classical peak current mode
control) or adjust the switching frequency by keeping the
peak current constant. We have chosen the second scheme
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11
NCP1351
V
Ct
Controlled by the
FB Current
Minimum Frequency
I
Ct
= 10 ꢀ A
P
out
Decreases
P
out
Increases
Maximum Frequency
Figure 10. The Current Injected into the Feedback Loop Adjusts the Switching Frequency
C Voltage
t
C Voltage
t
Figure 11. In Light Load Conditions, the
Oscillator Further Delays the Restart Time
Figure 12. Ct Voltage Swing at a Moderate
Loading
In light load conditions, the frequency can go down to a
few hundred Hz without any problem. The internal circuitry
naturally blocks the oscillator and softly shifts the restart
time as shown on Figure 11 scope shot.
power supply can deliver at low line. This discrepancy
relates to the propagation delay from the point where the
peak is detected to the MOSFET gate effective pulldown. It
naturally includes the controller reaction time, but also the
driver capability to pull the gate down. If the MOSFET Q
g
Delays The Restart Time
is too large, then this parameter will greatly affect your
overpower parameter. Sometimes, the small PNP can help
and we recommend it if you use a large Q MOSFET:
In lack of feedback current, for instance during a startup
sequence or a short circuit, the oscillator frequency is pushed
to the limit set by the timing capacitor. In this case, the lower
threshold imposed to the timing capacitor is blocked to
g
D1
1N4148
500 mV (parameter V ). This is the maximum power the
fault
converter can deliver. To the opposite, as you inject current
via the optocoupler in the feedback pin, the off time expands
and the power delivery reduces. The maximum threshold
level in standby conditions is set to 6 V.
DRV
Q1
2N2907
GND
Over Power Protection
As any universal-mains operated converters, the output
power slightly increases at high line compared to what the
Figure 13. A Low-Cost PNP Improves the Drive
Capability at Turn-off
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12
NCP1351
Over power protection can be done without power
the standby power can be affected. Again, the resistor R
OPP
dissipation penalty by arranging components around the
auxiliary as suggested by Figure 14. On this schematic, the
diode anode swings negative during the on time. This
negative level directly depends on the input voltage and
should be placed as close as possible to the CS pin. The
22 pF can help to circumvent any picked-up noise and D
2
prevents the positive loading of the 270 pF capacitor during
the flyback swing. We have put a typical 100 kꢂ O
PP
offsets the current sense pin via the R resistor. A small
OPP
integration is necessary to reduce the O action in light load
resistor but a tweak is required depending on your
application.
PP
conditions. However, depending on the compensation level,
L
P
DRV
DRV
+
D
aux
CS
V
CC
C
Bulk
C4
22p
I
Lp
+
R1
150k
CV
L
aux
CC
R
offset
D2
1N4148
C3
270p
R
sense
R
OPP
100k
Figure 14. The OPP is Relatively Easy to Implement and It Does not Waste Power
Suppose you would need to reduce the peak current by
15% in high-line conditions. The turn-ratio between the
auxiliary winding and the primary winding is N . Assume
Typically, we measured around –4 V on our 50 W prototype.
By calculation, we want to decrease the peak current by
15%. Compared to the internal 270 ꢀ A source, we need to
derive:
aux
its value is 0.15. Thus, the voltage on D cathode swings
aux
negative during the on time to a level of:
(eq. 11)
I
+ -0.15 270ꢀꢀ + -40.5ꢀꢀ A
offset
V
+ -V ꢁN
in_max aux
+ -375 0.15 + -56ꢀV
(eq. 8)
aux_peak
Thus, from the –4 V excursion, the R
derived by:
resistor is
OPP
If we selected a 3.7 kꢂ resistor for R
offset
maximum sense voltage being developed is:
, then the
4
R
+
+ 98ꢀkꢂ
(eq. 12)
OPP
40.5ꢀꢀ
(eq. 9)
V
sense
+ 3.7ꢀk 270ꢀꢀ + 1ꢀV
After experimental measurements, the resistor was
normalized down to 100 kꢂ.
The small RC network made of R and C , purposely limits
1
3
the voltage excursion on D anode. Assume the primary
2
inductance value gives an on time of 3 ꢀ s at high-line. The
voltage across C thus swings down to:
Feedback
3
Unlike other controllers, the feedback in the NCP1351
works in current rather than voltage. Figure 15 details the
internal circuitry of this particular section. The optocoupler
injects a current into the FB pin in relationship with the
input/output conditions.
t
V
on aux_peak
3ꢀꢀ 56
V
C
+
+ -
+ -4.2ꢀV
3
(eq.
10)
R C
1 3
150ꢀk 270ꢀp
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13
NCP1351
V
CC
IC
t
10ꢀ
C
t
C
270p
Reset
t
V
CC
V
offset
500mV
-
+
FB
I
FB
I
FB
Clock
+
I
FB
R
FB
45k
D
FB
C1
100n
R1
2.5k
V
CC
ICS
I
diff
I
diff
C3
22pF
min
CS
I
diff
= ICS - ICS
max min
f
(IFB)
R
3.9k
offset
to R
sense
Figure 15. The Feedback Section Inside the NCP1351
The FB pin can actually be seen as a diode, forward biased
by the optocoupler current. The feedback current, I on
load conditions, the feedback current is weak and all the
current flowing through the external offset resistor is:
FB
Figure 15, enter an internal 45 kꢂ resistor which develops
a voltage. This voltage becomes the variable threshold point
for the capacitor charge, as indicated by Figure 10. Thus, in
lack of feedback current (start-up or short-circuit), there is
no voltage across the 45 kꢂ and the series offset of 500 mV
clamps the capacitor swing. If a 270 pF capacitor is used, the
maximum switching frequency is 65 kHz.
I
+ I
+ I
) I + I
dif CS_max
* I ) I
CS_min
CS
CS_min
CS_max
CS_min
(eq. 13)
As the load goes lighter, the feedback current increases and
starts to steal current away from the generators. Equation 12
can thus be updated by:
I
+ I
CS_max
* kI
FB
(eq. 14)
CS
Folding the frequency back at a rather high peak current
can obviously generate audible noise. For this reason, the
NCP1351 uses a patented current compression technique
which reduces the peak current in lighter load conditions. By
design, the peak current changes from 100% of its full load
value, to 30% of this value in light load conditions. This is
the block placed on the lower left corner of Figure 15. In full
Equation 13 testifies for the current reduction on the offset
generator, k represents an internal coefficient. When the
feedback current equals I , the offset becomes:
dif
I
+ I
CS_min
(eq. 15)
CS
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14
NCP1351
Fault detection
At this point, the current is fully compressed and remains
frozen. To further decrease the transmitted power, the
frequency does not have other choice than going down.
The fault detection circuitry permanently observes the FB
current, as shown on Figure 19. When the feedback current
decreases below 40 ꢀ A, an external capacitor is charged by
a 11.7 ꢀ A source. As the voltage rises, a comparator detects
when it reaches 5 V typical. Upon detection, there can be
two different scenarios:
CS Current
270 ꢀ A
1. A version: the circuit immediately latches-off and
remains latched until the voltage on the current
into the V pin drops below a few ꢀ A. The latch
FAULT
CC
(A, B versions)
is made via an internal SCR circuit who holds
VCC to around 6 V when fired. As long as the
current flowing through this latch is above a few
ꢀ A, the circuit remains locked-out. When the user
70 ꢀ A
unplugs the converter, the V current falls down
CC
and resets the latch.
2. B version: the circuit stops its output pulses and
60 ꢀ A 80 ꢀ A
40 ꢀ A
FB Current
Figure 16. The NCP1351 Peak Current Compression
Scheme
the auxiliary V decreases via the controller own
CC
consumption (≈600 ꢀ A). When it touches the
V
CC(min)
point, the circuit re-starts and attempts to
Looking to the data-sheet specifications, the maximum
peak current is set to 270 ꢀ A whereas the compressed
current goes down to 70 ꢀ A. The NCP1351 can thus be
considered as a multi operating mode circuit:
crank the power supply. If it fails again, an hiccup
mode takes place (Figure 18).
3. C version: this version includes the dual Over
Current Protection (OCP) level. When the
switching frequency imposed by the feedback loop
reaches around 50% of the maximum value set by
the Ct capacitor, the timer starts to count down. If
the fault disappears, the timer is reset. When the
fault is finally confirmed, the controller latches off
as the A version.
• Real fixed peak current / variable frequency mode for
FB current below 60 ꢀ A.
• Then maximum peak current decreases to I
over a
CS,min
narrow linear range of I (to avoid instability created
), between
FB
by a discrete jump from I
60 ꢀ A and 80 ꢀ A.
to I
CS,max
CS,min
4. D version: this version includes the dual Over
Current Protection (OCP) level. When the
switching frequency imposed by the feedback loop
reaches around 50% of the maximum value set by
the Ct capacitor, the timer starts to count down. If
the fault disappears, the timer is reset. When the
fault is finally confirmed, the controller enters
auto-recovery mode, as with the B version.
• Then if IFB keeps on increasing, in a real fixed peak
current/variable frequency mode with reduced peak
current
For biasing purposes and noise immunity improvements,
we recommend to wire a pulldown resistor and a capacitor
in parallel from the FB pin to the controller ground
(Figure 17). Please keep these elements as close as possible
to the circuit. The pulldown resistor increases the
optocoupler current but also plays a role in standby. We
found that a 2.5 kꢂ resistor was giving a good tradeoff
between optocoupler operating current (internal pole
position) and standby power.
V
CC
V
CC
V
drv
FB
C1
100nF
R1
2.5k
Figure 18. Hiccup Occurs with the B Version Only,
the A Version Being Latched
The duty-burst in fault is around 7% in this particular
case.
Figure 17. The Recommended Feedback
Arrangement Around the FB Pin
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15
NCP1351
V
CC
D
I
aux
V
CC
timer
10ꢀ
Timer
20ꢀ s
Filter
+
CV
CC
L
+
aux
I
CC
C
timer
100nF
-
+
S
R
V
timer
5
Q
Q
V
CC
to DRV
Stage
P
on
Reset
-
+
FB
I
FB
+
I
FB
V
CC
VCC
==
I < 40 ꢀ A ? = Low
FB
Else = High
DRV Pulses
D
I
FB
R1
2.5k
FB
C1
100n
(min)
? Reset
Auto-Recovery - B Version
V
CC
D
I
aux
V
CC
timer
10ꢀ
20ꢀ s
Filter
Timer
+
CV
CC
L
aux
+
I
CC
C
timer
100nF
-
+
6V
V
timer
5
V
CC
P
on
Reset
-
+
SCR Delatches When
< ICC
I
FB
FB
+
I
FB
I
(Few ꢀ A)
SCR
latch
I < 40 ꢀ A ? = Low
FB
Else = High
D
I
FB
R1
2.5k
FB
C1
100n
Latched - A Version
Figure 19. The Internal Fault Management Differs Depending on the Considered Version
Knowing both the ending voltage and the charge current,
we can easily calculate the timer capacitor value for a given
delay. Suppose we need 40 ms. In that case, the capacitor is
simply:
designer select a 100 kHz maximum switching frequency,
then the error flag would raise and start the timer for an
operating frequency above ≈ 50 kHz. Below 50 kHz, the
timer pin remains grounded. If we consider a DCM
operation at full load, as the inductor peak current is kept
constant, these 50 kHz correspond to 50% of the maximum
delivered power. If the load stays between 50% and 100% of
its nominal value, the timer continues to charge until it
reaches the final level. In that case, the circuit latches off (C)
or enters auto-recovery (D). This behavior is particularly
well suited for applications where the converter delivers a
moderate average power but is subjected to sudden peak
loading conditions. For instance, a power supply is designed
to permanently deliver 20 W but is sized to deliver 80 W in
peak conditions. During these 80 W power excursions, the
timer will react but will not shut down the power supply. On
the contrary, if a short-circuit appends or if the transient
overload lasts too long, the timer will immediately start to
further shutdown the controller in order to protect both the
application and downstream load.
11.7ꢀꢀ 40ꢀm
I
T
timer
(eq. 16)
C
+
+
+ 94ꢀnF
timer
5
V
timer
Select a 100 nF value.
To let the designer understand the behavior behind the
four different options (A, B, C and D), we have graphed
important signals during a fault condition. In versions A and
B, an internal error flag is raised as soon the controller hits
the maximum operating frequency. At this moment, the
external timer capacitor charge begins. If the fault persists,
the timer capacitor hits the fault level and the circuit is either
latched (A) or enters auto-recovery burst mode (B). If the
fault disappears, the timer capacitor is simply reset to 0 V by
an internal switch.
On version C and D, the error flag is asserted as soon as
the current feedback imposes a switching frequency roughly
equal to half of the maximum limit. For instance, should the
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16
NCP1351
Depending on the design conditions (DCM or CCM), the
The figures below details circuits operation for the various
controller options.
error flag assertion will correspond to either 50% of the
maximum power (full load DCM design) or a value above
this number if the converter operates in CCM at full load and
remains in CCM at half the switching frequency.
Vcc
VccON
Pulldown
SCR action
Vccstop
Latched
state
ICC1
ICC1
Vzener
IFB
ICC < 20 μA
fault
User
reset
ok
ok
FB reacts
40 μA
Vtimer
Vtimer
startup
DRV
A version, latched
Figure 20. The A Version Latches-off in Presence of a Fault
Vcc
VccON
Vccstop
Pulses
stopped
Fault
still present
ICC4
ICC1
ICC1
Vzener
IFB
Vtimer
DRV
fault
ok
Auto-recovery
FB reacts
40 μA
Vtimer
startup
B version, auto-recovery
Figure 21. The B Version Enters an Auto-Recovery Burst Mode in Presence of a Fault
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17
NCP1351
Vcc
VccON
Vccstop
Pulldown
SCR action
User
reset
Latched
state
ICC1
Vzener
Pout
ICC < 20 μA
100% Pout
50% Pout
Pout>50%
Pout>50%
IFB
overload
overload
51 μA
Vtimer
Vtimer
startup
DRV
C version, latched dual OCP level
Figure 22. The C Version Latches if the Power Excursion Exceeds 50% of the Maximum Power Too Long
(DCM Full Load Operation)
Vcc
VccON
Pulses
stopped
Vccstop
ICC4
ICC1
Vzener
Pout
100% Pout
Pout>50%
Pout>50%
50% Pout
IFB
overload
overload
51 μA
Vtimer
Vtimer
startup
DRV
D version, auto-recovery dual OCP level
Figure 23. The D Version Enters Auto-Recovery Burst Mode if the Power Excursion Exceeds 50% of the
Maximum Power (DCM Full Load Operation)
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18
NCP1351
V
CC
Latch Input
The NCP1351 features a patented circuitry which
prevents the FB input to be of low impedance before the V
reaches the VCC level. As such, the circuit can work in
a primary regulation scheme. Capitalizing on this typical
option, Figure 24 shows how to insert a zener diode in series
with the optocoupler emitter pin. In that way, the current
biases the zener diode and offers a nice reference voltage,
appearing at the loop closure (e.g. when the output reaches
the target). Yes, you can use this reference voltage to supply
a NTC and form a cheap OTP protection.
CC
OVP
D2
ON
5V
FB
Latch
C2
100n
C3
100nF
R1
2.5k
C1
100nF
R
pulldown
Figure 24. The Latch Input Offers Everything Needed
to Implement an OTP Circuit. Another Zener Can
Help combining an OVP Circuit if Necessary
V
CC
V
CC
OUT
Aux
+
CV
CC
22ꢀ F
+
CV
CC
20ꢀ F
R4
2.2k
Sec
L
aux
U1B
U1A
D2
1N4937
Latch
R
Latch
OVP
D4
C1
100nF
C3
100nF
C4
100n
C5
1n
R
pulldown
Figure 25. You can either directly observe the VCC level or add a small RC filter to reduce the leakage inductance
contribution. The best is to directly sense the output voltage and reacts if it runs away, as offered on the right
side.
Design Example, a 19 V / 3 A
V
+ 600 0.85 + 510ꢀV
(eq. 17)
ds_max
A
Universal Mains Power Supply Designing a
Knowing a maximum bulk voltage of 375 V, the clamp
voltage must be set to:
Switch-Mode Power Supply using the NCP1351 does not
differ from a fixed frequency design. What changes,
however, is the regulation method via frequency variations.
In other words, all the calculations must be carried at the
lowest line input where the frequency will hit the maximum
V
clamp
+ 510 * 375 + 135ꢀV
(eq. 18)
Based on the above level, we decide to adopt a headroom
between the reflected voltage and the clamp level of 50 V. If
this headroom is too small, a high dissipation will occur on
the RDC clamp network and efficiency will suffer. A
leakage inductance of around 1% of the magnetizing value
value set by the C capacitor. Let us follow the steps:
t
V min = 100 Vdc (bulk valley in low-line conditions)
in
V max = 375 Vdc
in
V
= 19 V
out
= 3 A
Operating mode is CCM
should give good results with this choice (k = 1.6). The turn
c
ratio between primary and secondary is simply:
I
out
ǒ
Ǔ
) V ꢀ
f
ꢀV
out
V
clamp
ꢄ = 0.8
F
(eq. 19)
(eq. 20)
+
N
k
c
= 65 kHz
1. Turn Ratio. This is the first parameter to consider.
sw
Solving for N gives:
The MOSFET BV actually dictates the amount
dss
ǒ
Ǔ
V ) V
out f
k
(
)
1.6 19 ) 0.8
C
N
N
of reflected voltage you need. If we consider a
600 V MOSFET and a 15% derating factor, we
must limit the maximum drain voltage to:
s
N +
+
+
135
p
V
clamp
+ 0.234
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19
NCP1351
Let us round it to 0.25 or 1/N = 4
From Equation 17, a K factor of 0.8 (40% ripple) ensures a
good operation over universal mains. It leads to an
inductance of:
2
)
(
100 43
(eq. 23)
L +
+ 493ꢀꢀ H
65ꢀk 0.8 72
I
I
peak
V
d
in_min max
100 0.43
ꢅ I
L
+
+
(eq. 24)
LF
493ꢀu 65ꢀk
ꢅ I
L
I
1
SW
+ 1.34ꢀAꢀpeak-to-peak
valley
The peak current can be evaluated to be:
P
19 3
out
I
+
+
+ 712ꢀmA
(eq. 25)
(eq. 26)
in_avg
0.8 100
V
ꢄ in_min
I
avg
I
avg
0.712 1.34
ꢅ
I
L
I
+
)
+
)
+ 2.33ꢀA
peak
2
0.43
2
d
t
On Figure 26, I1 can also be calculated:
DT
1.34
2
ꢅ
I
SW
L
(eq. 27)
(eq. 28)
I + I
peak
*
+ 2.33 *
+ 1.65ꢀA
I
2
T
SW
The valley current is also found to be:
Figure 26. Primary Inductance Current Evolution
in CCM
I
+ I * ꢅ I + 2.33 * 1.34 + 1.0ꢀA
peak L
valley
4. Based on the above numbers, we can now evaluate
the RMS current circulating in the MOSFET and
the sense resistor:
2. Calculate the maximum operating duty-cycle for
this flyback converter operated in CCM:
V
ńN
out
19 4
19 4 ) 100
d
+
+
+ 0.43
1 ꢅ I
max
Ǹ
L
dǸ1 )
I
+ I
2
ǒ Ǔ
d_rms
I
V
ńN ) V
out in_min
3
2I
1
(eq. 21)
1.34
1
In this equation, the CCM duty-cycle does not exceed
50%. The design should thus be free of subharmonic
oscillations in steady-state conditions. If necessary,
negative ramp compensation is however feasible by the
auxiliary winding.
Ǹ
+ 1.65 0.65
2
Ǔ
ǒ
1 )
(eq. 29)
3 2 1.65
+ 1.1ꢀA
5. The current peaks to 2.33 A. Selecting a 1 V drop
across the sense resistor, we can compute its value:
3. To obtain the primary inductance, we can use the
following equation which expresses the inductance
in relationship to a coefficient k. This coefficient
actually dictates the depth of the CCM operation.
If it goes to 2, then we are in DCM.
1
1
R
+
+
+ 0.4ꢀꢂ
(eq. 30)
sense
2.5
I
peak
To generate 1 V, the offset resistor will be 3.7 kꢂ, as already
explained. Using Equation 29, the power dissipated in the
sense element reaches:
2
)
(
V
d
in_min max
KP
(eq. 22)
L +
F
SW in
2
2
P
+ R
ꢁI + 0.4 1.1 + 484ꢀmW
sense d_rms
sense
(eq. 31)
where K = ꢅI /I and defines the amount of ripple we want
L
I
in CCM (see Figure 26).
6. To switch at 65 kHz, the C capacitor connected to
t
• Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
pin 2 will be selected to 180 pF.
7. As the load changes, the operating frequency will
automatically adjust to satisfy either equation 5
(high power, CCM) or equation 6 in lighter load
conditions (DCM).
• Large K: approaching BCM where the RMS losses are
the worse, but smaller inductance, leading to a better
leakage inductance.
Figure 27 portrays a possible application schematic
implementing what we discussed in the above lines.
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20
NCP1351
R3
R4
47k
22
HV-Bulk
L = 500ꢀ H
P
N :N = 1:0.25
S
P
C2
R13
N :N
= 0.18
aux
D5
P
R7
1M
C5b
1.2mF
25V
10n
47k
L2
400V
MBR20200
2.2ꢀ
R2
1M
C5a
1.2mF
25V
C7
+
+
+
V
19V/3A
OUT
220ꢀ F
D2
D3
25V
MUR 1N4937
160
T1
C13
U1B
U2
2.2nF
GND
1
2
3
4
8
7
6
5
R8
1k
R12
4k
Type = Y1
OVP
D6
R15
3.7k
C12
Option
1N4148
+
25V
100ꢀ F
R10
62k
400V
6A/600V
M1
C15
22p
R16
10
NCP1351B
U1A
R14
2.2k
C6
100n
+
R18
47k
C17
C4
+
R5
2.5k
C10
0.1ꢀ
C9
100ꢀ
R9
R1
IC2
TL431
100n
100n
10k
2.2k
C8
270pF
R6
0.4
C3
C1
GND
4.7ꢀ 100nF
25V
Figure 27. The 19 V Adapter Featuring the Elements Calculated Above
88
On this circuit, the V capacitor is split in two parts, a
CC
low value capacitor (4.7 ꢀ F) and a bigger one (100 ꢀ F). The
4.7 ꢀ F capacitor ensures a low startup time, whereas the
86
84
82
80
78
76
74
72
V
in
= 230 Vac
second capacitor keeps the V alive in standby mode
CC
(where the switching frequency can be low). Due to D , it
does not hamper startup time.
6
V
in
= 100 Vac
Application Results
We assembled a board with component values close to
what is described on Figure 27. Here are the obtained
results:
P @ no-load = 152 mW, V = 230 Vac
in
in
P @ no-load = 164 mW, V = 100 Vac
in
in
0
0.5
1
1.5
2
2.5
3
3.5
The efficiency stays flat to above 80%, and keeps good
even at low output levels. It clearly shows the benefit of the
variable frequency implemented in the NCP1351.
I
(A)
out
Figure 28. Efficiency Measured at Various Operating
Points
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21
NCP1351
Another benefit of the variable frequency lies in the low
ripple operation at no-load. This is what confirms
Figure 29.
Finally, the power supply was tested for its transient
response, from 100 mA to 3 A, high and low line, with a
slew-rate of 1 A/ꢀ s (Figure 31). Results appear in
Figures 31 and 32 and confirm the stability of the board.
V
V
ds
200 V/div
ds
200 V/div
V
out
1.0 mV/div
V
out
1.0 mV/div
Figure 29. No-Load Output Ripple
(Vin = 230 Vac)
Figure 30. Same Conditions,
Pout = 5 W
V
out
50 mV/div
V
out
50 mV/div
Figure 31. Transient Step, Low Line
Figure 32. Transient Step, High Line
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22
NCP1351
CHARACTERIZATION CURVES
9.1
9
20
19
18
17
16
8.9
8.8
8.7
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. VCCON Level versus Junction
Temperature
Figure 34. VCCmin Level versus Junction
Temperature
71
69.5
68
274
270
266
262
258
66.5
65
-25
254
-25
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. ICSmin versus Junction
Temperature
Figure 36. ICSmax versus Junction
Temperature
11
10.8
10.6
10.4
517
515
513
511
509
10.2
-25
-25
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. Oscillator Offset Voltage versus
Junction Temperature
Figure 38. Timing Capacitor Charge-Current
Variation versus Junction Temperature
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23
NCP1351
534
531
528
525
522
990
980
970
960
950
940
930
125
-25
0
25
50
75
100
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. Fault Voltage Variations versus
Junction Temperature (A and B Versions)
Figure 40. Fault Voltage Variations versus
Junction Temperature (C and D Versions)
2.05
2
53
52.5
52
1.95
1.9
51.5
51
1.85
1.8
50.5
50
1.75
1.7
1.65
49.5
-25
0
25
50
75
100
125
-25
0
25
50
75
100
12
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. KFAULT Variations versus Junction
Temperature
Figure 42. IFAULT Current Variation versus
Junction Temperature (Versions C and D)
5.2
5.1
5
4.9
4.8
4.7
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 43. Latch Level Evolution versus Junction Temperature
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24
NCP1351
ORDERING INFORMATION
Device
Package Type
Shipping
†
NCP1351ADR2G
SOIC-8
(Pb-Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
NCP1351BDR2G
NCP1351CDR2G
NCP1351DDR2G
NCP1351APG
NCP1351BPG
NCP1351CPG
NCP1351DPG
SOIC-8
(Pb-Free)
SOIC-8
(Pb-Free)
SOIC-8
(Pb-Free)
PDIP-8
(Pb-Free)
PDIP-8
(Pb-Free)
50 Units / Rail
PDIP-8
(Pb-Free)
50 Units / Rail
PDIP-8
(Pb-Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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25
NCP1351
PACKAGE DIMENSIONS
SOIC-8
D SUFFIX
CASE 751-07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
-X-
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
S
M
M
B
0.25 (0.010)
Y
1
K
-Y-
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
-Z-
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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26
NCP1351
PACKAGE DIMENSIONS
PDIP-8
P SUFFIX
CASE 626-05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
-B-
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
-A-
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
C
K
L
7.62 BSC
0.300 BSC
M
N
---
0.76
10
_
1.01
---
0.030
10
_
0.040
J
-T-
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800-282-9855 Toll Free
ꢂUSA/Canada
Europe, Middle East and Africa Technical Support:
ꢂPhone: 421 33 790 2910
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ꢂPhone: 81-3-5773-3850
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Order Literature: http://www.onsemi.com/orderlit
ꢂLiterature Distribution Center for ON Semiconductor
ꢂP.O. Box 5163, Denver, Colorado 80217 USA
ꢂPhone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
ꢂFax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
ꢂEmail: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP1351/D
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