NCP1399BADR2G_技术文档

NCP1399 Series

High Performance Current

Mode Resonant Controller

with Integrated High-

Voltage Drivers

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The NCP1399 is a high performance current mode controller for half

bridge resonant converters. This controller implements 600 V gate

drivers, simplifying layout and reducing external component count. The

built−in Brown−Out input function eases implementation of the

controller in all applications. In applications where a PFC front stage is

needed, the NCP1399 features a dedicated output to drive the PFC

controller. This feature together with dedicated skip mode technique

further improves light load efficiency of the whole application. The

NCP1399 provides a suite of protection features allowing safe operation

in any application. This includes: overload protection, over−current

protection to prevent hard switching cycles, brown−out detection, open

optocoupler detection, automatic dead−time adjust, overvoltage (OVP)

and overtemperature (OTP) protections.

16

1

SOIC−16 NB

(LESS PINS 2 AND 13)

D SUFFIX

CASE 751DU

MARKING DIAGRAM

16

NCP1399xy

AWLYWWG

Features

• High−Frequency Operation from 20 kHz up to 750 kHz

• Current Mode Control Scheme

1

NCP1399= Specific Device Code

• Automatic Dead−time with Maximum Dead−time Clamp

• Dedicated Startup Sequence for Fast Resonant Tank Stabilization

• Skip Mode Operation for Improved Light Load Efficiency

• Off−mode Operation for Extremely Low No−load Consumption

• Latched or Auto−Recovery Overload Protection

• Latched or Auto−Recovery Output Short Circuit Protection

• Latched Input for Severe Fault Conditions, e.g. OVP or OTP

• Out of Resonance Switching Protection

x

y

A

WL

Y

= A or B

= A, B, C, F, G H, I, J, K, L, M, N, P

= Assembly Location

= Wafer Lot

= Year

= Work Week

WW

G

= Pb−Free Package

PIN CONNECTIONS

• Open Feedback Loop Protection

1

HV

16 VBOOT

15 HB

• Precise Brown−Out Protection

• PFC Stage Operation Control According to Load Conditions

• Startup Current Source with Extremely Low Leakage Current

• Dynamic Self−Supply (DSS) Operation in Off−mode or Fault Modes

• Pin to Adjacent Pin / Open Pin Fail Safe

14

3

4

5

6

VBULK/PFCFB

SKIP/REM

LLCFB

MUPPER

12 MLOWER

11

LLCCS

GND

10 VCC

PFCMODE

• These are Pb−Free Devices

OVP/OTP

PON/OFF

7

8

Typical Applications

9

• Adapters and Offline Battery Chargers

• Flat Panel Display Power Converters

• Computing Power Supplies

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information on page 12 of

• Industrial and Medical Power Sources

this data sheet.

1

Publication Order Number:

September, 2017 − Rev. 13

NCP1399/D

NCP1399 Series

Figure 1. Typical Application Example without PFC Stage − WLLC Design (Active OFF off−mode)

Figure 2. Typical Application Example with PFC Stage (Active OFF off−mode)

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2

NCP1399 Series

Figure 3. Typical Application Example with PFC Stage (Active ON off−mode)

PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

Function

Pin Description

1

HV

High*voltage startup

current source input

Connects to rectified AC line or to bulk capacitor to perform functions of

Start*up Current Source and Dynamic Self*Supply

2

3

NC

Not connected

Increases the creepage distance

VBULK /

PFC FB

Bulk voltage monitoring input Receives divided bulk voltage to perform Brown−out protection.

4

SKIP/REM

Skip threshold adjust /

Off−mode control input

Sets the skip in threshold via a resistor connected to ground – version

NCP1399Ay. Activates off−mode (or Standby) when pulled−up by external

auxiliary voltage source / deactivates off−mode when pull down by external

off−mode control optocoupler – version NCP1399By.

5

6

7

LLC FB

LLC CS

LLC feedback input

Defines operating frequency based on given load conditions. Activates skip

mode operation under light load conditions. Activates off−mode operation for

NCP1399Ay version.

LLC current sense input

Senses divided resonant capacitor voltage to perform on−time modulation, out

of resonant switching protection, over−current protection and secondary side

short circuit protection.

OTP / OVP

Over−temperature and

over−voltage protection input

Implements over−temperature and over−voltage protection on single pin.

8

9

P ON/OFF

PFC turn−off FB level adjust Adjusts the FB pin to a level below which the PFC stage operation is disabled.

PFC MODE

PFC and external HV

switch control output

Provides supply voltage for PFC front stage controller and/or enables Vbulk

sensing network HV switch.

10

11

VCC

GND

Supplies the controller

Analog ground

The controller accepts up to 20 V on VCC pin

Common ground connection for adjust components, sensing networks and

DRV outputs.

12

13

14

15

16

MLOWER

NC

Low side driver output

Not connected

Drives the lower side MOSFET

Increases the creepage distance

Drives the higher side MOSFET

MUPPER

HB

High side driver output

Half*bridge connection

Bootstrap pin

Connects to the half*bridge output.

The floating VCC supply for the upper stage

VBOOT

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3

NCP1399 Series

Figure 4. Internal Circuit Architecture

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

V

HV Startup Current Source HV Pin Voltage (Pin 1)

VBULK/PFC FB Pin Voltage (Pin3)

V

HV

−0.3 to 600

−0.3 to 5.5

−0.3 to 10

−0.3 to 5.5

−5 to 5

V

BULK/PFC FB

SKIP/REM Pin Voltage (Pin 4) NCP1399Ay Revision Only

SKIP/REM Pin Voltage (Pin 4) NCP1399By Revision Only

LLC FB Pin Voltage (Pin 5)

V

SKIP/REM

V

SKIP/REM

V

FB

V

LLC CS Pin Voltage (Pin 6)

V

CS

V

PFC MODE Pin Output Voltage (Pin 9)

VCC Pin Voltage (Pin 10)

V

−0.3 to V + 0.3

V

PFC MODE

CC

V

CC

−0.3 to 20

V

Low Side Driver Output Voltage (Pin 12)

High Side Driver Output Voltage (Pin 14)

V

−0.3 to V + 0.3

V

DRV_MLOWER

CC

V

HB

– 0.3 to

V

DRV_MUPPER

V

BOOT

+ 0.3

High Side Offset Voltage (Pin 15)

V

−20 to

V

HB

Boot

+0.3

Boot

High Side Floating Supply Voltage (Pin 16)

T = −40°C to +125°C

J

V

BOOT

−0.3 to 620

−0.3 to 618

J

T = −55°C to −40°C

High Side Floating Supply Voltage (Pin 15 and 16)

Allowable Output Slew Rate on HB Pin (Pin 15)

OVP/OTP Pin Voltage (Pin 7)

V

−0.3 to 20.0

50

V

V/ns

V

Boot–VHB

dV/dt

max

V

−0.3 to 5.5

−55 to 150

130

OVP/OTP

P ON/OFF

P ON/OFF Pin Voltage (Pin 8)

V

Junction Temperature

T

J

°C

Storage Temperature

T

STG

°C

Thermal Resistance Junction−to−air

R

°C/W

kV

θ

JA

Human Body Model ESD Capability per JEDEC JESD22−A114F (except HV Pin – Pin 1)

Charged−Device Model ESD Capability per JEDEC JESD22−C101E

−

4.5

1

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

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4

NCP1399 Series

ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 12 V unless otherwise noted.)

J

CC

Symbol

HV Startup Current Source

Rating

Min

Typ

Max

Unit

V

Minimum voltage for current source operation

(V = V −0.5 V, I drops to 95 %)

1

−

60

V

HV_MIN1

CC

CC_ON

START2

V

Minimum voltage for current source operation

(V = V −0.5 V, I drops to 5 mA)

HV_MIN2

CC

CC_ON

START2

I

Current flowing out of V pin (V = 0 V)

1, 10

1

0.2

6

0.5

9

0.8

13

10

8

mA

START1

CC

Current flowing out of V pin (V = V −0.5 V)

CC_ON

START2

CC

I

Off−state leakage current (V = 500 V, V = 15 V)

−

START_OFF

HV

CC

I

HV pin current when off−mode operation is active

(V = 400 V)

1

−

mA

HV_OFF−MODE

HV

Supply Section

V

Turn−on threshold level, V going up

10

15.3

11.5

15.8

12.0

16.3

12.3

V

CC_ON

CC

V

Turn−on threshold level, V going up

CC

(NCP1399AL, NCP1399AM)

V

Minimum operating voltage after turn−on

10

9.0

5.8

9.5

6.6

10

7.2

V

CC_OFF

V

CC

V

CC

level at which the internal logic gets reset

CC_RESET

CC_INHIBIT

V

level for I

to I

transition

10

0.40

100

10

0.80

125

27

1.25

150

40

V

START1

START2

V

Delay to generate DRVs pulses after V is reached

CC_ON

10

ms

mA

CC_ON_BLANK

CC_OFF−MODE

I

Controller supply current in off−mode,

10, 11

V

CC

= V

− 0.2 V (except NCP1399AG)

CC_ON

I

Controller supply current in skip−mode, V = 15 V

10, 11

mA

CC_SKIP−MODE

CC

(NCP1399AA, BA, AC, AH, AI, AK, AM, AN, AP)

(NCP1399AF, NCP1399AG, NCP1399AJ)

(NCP1399AL)

580

500

750

670

710

900

820

890

I

Controller supply current in latch−off mode,

10, 11

330

300

4.0

490

5.4

600

7.0

mA

CC_LATCH

V

CC

= V

− 0.2 V (except NCP1399AI, AN, AP)

CC_ON

I

Controller supply current in auto−recovery mode,

= V − 0.2 V (except NCP1399AF)

CC_AUTOREC

V

CC

CC_ON

I

Controller supply current in normal operation,

= 100 kHz, C = 1 nF, V = 15 V

mA

CC_OPERATION

f

sw

load

CC

Bootstrap Section

V

Startup voltage on the floating section (Note 5)

Cutoff voltage on the floating section

16, 15

8

9

10

9.0

V

BOOT_ON

V

7.2

30

8.2

75

BOOT_OFF

I

Upper driver consumption, no DRV pulses

130

2.00

mA

BOOT1

BOOT2

Upper driver consumption, C

= 1 nF between Pins 13 &

1.30

1.65

load

15 f = 100 kHz, HB connected to GND

sw

HB Discharger

I

HB sink current capability V = 30 V

15

5

1

−

mA

V

DISCHARGE1

DISCHARGE2

HB

I

HB sink current capability V = V

HB

HB_MIN

V

HB voltage @ I

changes from 2 to 0 mA

10

HB_MIN

DISCHARGE

Remote Input – NCP1399By

Remote pin voltage below which off−mode is deactivated

(V going down)

V

4

1.0

7.2

1.5

8.0

2.0

8.8

V

REM_ON

REM

V

Remote pin voltage above which off−mode is activated

(V going up)

REM_OFF

REM

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. The NCP1399Ay version has skip adjustable externally.

3. Guaranteed by design.

4. Minimal impedance on P ON/OFF pin is 1 kW

5. Minimal resistance connected in series with bootstrap diode is 3.3 W

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5

NCP1399 Series

ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 12 V unless otherwise noted.)

J

CC

Symbol

Remote Input – NCP1399By

Remote timer duration

Remote input leakage current (V

Rating

Min

Typ

Max

Unit

t

4

80

−

100

0.02

−

120

1.00

7

ms

mA

kW

REM_TIMER

I

= 10 V)

REM

REM_LEAK

R

Internal remote pull down switch resistance (V

= 8 V)

REM

3

SW_REM

Remote Control – NCP1399Ay (i.e. Off−mode is Sensed via FB Pin, except NCP1399AG)

V

FB pin voltage above which off−mode is deactivated

(V going up)

FB

5

1.5

0.36

1.0

2.0

0.40

2.3

2.5

0.44

4.0

V

FB_REM_ON

V

FB pin voltage below which off−mode is activated

(V going down)

FB

FB_REM_OFF

I

Pull−up FB pin bias current during off−mode

mA

FB_REM_BIAS

Driver Outputs

t

Output voltage rise−time @

C = 1 nF, 10−90% of output signal

L

12, 14

20

5

45

30

80

50

ns

r

t

Output voltage fall−time @

f

C = 1 nF, 10−90% of output signal

L

R

Source resistance

12, 14

4

1

−

16

5

32

11

−

W

A

OH

R

Sink resistance

OL

DRVSOURCE

I

Output high short circuit pulsed current

0.5

V

DRV

= 0 V, PW ≤ 10 ms

I

Output high short circuit pulsed current

= VCC, PW ≤ 10 ms

12, 14

−

1

−

5

A

DRVSINK

V

DRV

I

Leakage current on high voltage pins to GND

14, 15, 16

mA

HV_LEAK

Dead−time Generation

t

Maximum Dead−time value if no dV/dt falling/rising edge is

received

12, 14

720

−

800

8

880

−

ns

−

DEAD_TIME_MAX

N

Number of DT_MAX events to enters IC into fault

(NCP1399AA, NCP1399BA, NCP1399AH, NCP1399AK,

NCP1399AL)

12, 14, 16

DT_MAX

Number of DT_MAX events to enters IC into fault

(NCP1399AC, NCP1399AF, NCP1399AG, NCP1399AI,

NCP1399AJ, NCP1399AM, NCP1399AN, NCP1399AP)

12, 14, 16

−

16

−

dV/dt Detector

P

Positive slew rate on V

dead−time end is generated

pin above which automatic

16

−

210

−

V/ms

dV/dt_th

BOOT

N

Negative slew rate on V

pin above which automatic

dV/dt_th

BOOT

dead−time end is generated

PFC MODE Output and P ON/OFF Adjust

V

PFC MODE output voltage when V < V

P ON/OFF

(sink 1 mA current from PFC MODE output)

9

5.75

6.00

−

6.25

−

V

PFC_M_BO

PFC_M_ON

PFC_M_LIM

FB

PFC MODE output voltage when V > V

V

0.4

−

FB

P ON/OFF

CC

(sink 10 mA current from PFC MODE output)

I

PFC MODE output current limit (V < 2 V)

9

0.7

9.4

1.2

−

1.85

10.9

mA

s

PFC MODE

t

Delay to transition PFC MODE from V

to

5, 8, 9

P ON/OFF_TIMER

PFC_M_ON

after V drops below V

FB P ON/OFF

V

PFC_M_BO

I

Pull−up current source (Note 4)

8

18

20

22

mA

P ON/OFF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. The NCP1399Ay version has skip adjustable externally.

3. Guaranteed by design.

4. Minimal impedance on P ON/OFF pin is 1 kW

5. Minimal resistance connected in series with bootstrap diode is 3.3 W

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6

NCP1399 Series

ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 12 V unless otherwise noted.)

J

CC

Symbol

PFC MODE Output and P ON/OFF Adjust

Rating

Min

Typ

Max

Unit

P ON/OFF

P ON/OFF comparator hysteresis – percentage level of P

ON/OFF pin voltage

5, 8, 9

80

100

120

%

HYST

OVP/OTP

V

OVP threshold voltage (V

OTP threshold voltage (V

going up)

7

2.35

0.76

90

2.50

0.80

95

2.65

0.84

100

V

OVP

OTP

OVP/OTP

going down)

OVP/OTP

I

OTP/OVP pin source current for external NTC –

during normal operation

mA

I

OTP/OVP pin source current for external NTC –

during startup

7

180

190

200

mA

OTP_BOOST

t

Internal filter for OVP comparator

Internal filter for OTP comparator

7

32

200

7.3

37

330

8.0

44

500

8.7

ms

OVP_FILTER

t

OTP_FILTER

t

Blanking time for OTP input during startup (NCP1399AA,

NCP1399BA, NCP1399AK)

ms

BLANK_OTP

Blanking time for OTP input during startup (NCP1399AC,

NCP1399AF, NCP1399AG, NCP1399AH, NCP1399AI,

NCP1399AJ, NCP1399AL, NCP1399AM, NCP1399AN,

NCP1399AP)

7

14

16

18

ms

V

OVP/OTP pin clamping voltage @ I

= 0 mA

= 1 mA

7

1.0

1.8

1.2

2.4

1.4

3.0

V

CLAMP_OVP/OTP_1

OVP/OTP

V

CLAMP_ OVP/OTP_2

Start−up Sequence Parameters

t

Maximum on−time clamp (NCP1399AA, NCP1399BA,

NCP1399AK, NCP1399AL)

12, 14

7.3

7.7

8.4

ms

TON_MAX

Maximum on−time clamp (NCP1399AC, NCP1399AG,

NCP1399AI, NCP1399AM, NCP1399AN, NCP1399AP)

10.6

11.2

12.1

Maximum on−time clamp (NCP1399AF, NCP1399AJ)

Maximum on−time clamp (NCP1399AH)

12, 14

12

15.2

8.8

16.3

9.5

17.8

10.5

5.4

ms

t

Initial Mlower DRV on−time duration (NCP1399AA,

NCP1399BA, NCP1399AC, NCP1399AG, NCP1399AH,

NCP1399AI, NCP1399AK, NCP1399AL, NCP1399AM,

NCP1399AN, NCP1399AP)

4.7

4.9

1st_MLOWER_TON

Initial Mlower DRV on−time duration (NCP1399AF,

NCP1399AJ)

12

9.3

10

11

ms

1st_MLOWER_TON

t

Initial Mupper DRV on−time duration (NCP1399AM)

14

0.44

0.72

0.50

0.79

0.57

0.88

ms

1st_MUPPER_TON

t

Initial Mupper DRV on−time duration (NCP1399AA,

NCP1399BA, NCP1399AC, NCP1399AG, NCP1399AH,

NCP1399AI, NCP1399AK, NCP1399AL, NCP1399AN,

NCP1399AP)

1st_MUPPER_TON

t

Initial Mupper DRV on−time duration (NCP1399AF, NCP1399AJ)

14

0.99

17

1.10

20

1.21

22

ms

1st_MUPPER_TON

t

On−time period increment during soft−start (NCP1399AA,

NCP1399BA, NCP1399AC, NCP1399AG, NCP1399AH,

NCP1399AI, NCP1399AK, NCP1399AL, NCP1399AM,

NCP1399AN, NCP1399AP)

12, 14

ns

SS_INCREMENT

t

On−time period increment during soft−start (NCP1399AF,

NCP1399AJ)

12, 14

75

80

88

ns

SS_INCREMENT

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. The NCP1399Ay version has skip adjustable externally.

3. Guaranteed by design.

4. Minimal impedance on P ON/OFF pin is 1 kW

5. Minimal resistance connected in series with bootstrap diode is 3.3 W

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7

NCP1399 Series

ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 12 V unless otherwise noted.)

J

CC

Symbol

Start−up Sequence Parameters

Rating

Min

Typ

Max

Unit

K

Soft−Start increment division ratio (NCP1399AA,

NCP1399BA, NCP1399AK)

12, 14

−

4

−

SS_INCREMENT

Soft−Start increment division ratio (NCP1399AL)

Soft−Start increment division ratio (NCP1399AC,

12, 14

−

2

8

−

NCP1399AF, NCP1399AG, NCP1399AH, Ncp1399AI,

NCP1399AJ, NCP1399AM, NCP1399AN, NCP1399AP)

t

Time duration to restart IC if start−up phase is not finished

12, 14

0.45

0.50

0.55

ms

WATCHDOG

Feedback Section

R

Internal pull−up resistor on FB pin

5

15

18

25

kW

−

FB

K

V

FB

to internal current set point division ratio

1.92

4.60

4.4

2.00

4.95

4.6

2.08

5.30

4.8

V

Internal voltage reference on the FB pin

V

FB_REF

V

Internal clamp on FB input of On−time comparator referred

to external FB pin voltage

V

FB_CLAMP

V

Feedback voltage thresholds to enters in skip mode for

NCP1399By version (Note 2)

5

0.44

130

0.50

160

0.56

200

V

FB_SKIP_IN

V

mV

Skip comparator hysteresis (NCP1399AA, NCP1399BA,

NCP1399AC, NCP1399AG, NCP1399AH, NCP1399AK,

NCP1399AM, NCP1399AP)

FB_SKIP_HYST

Skip comparator hysteresis (NCP1399AF, NCP1399AJ,

NCP1399AL)

5

105

140

175

Skip comparator hysteresis (NCP1399AI, NCP1399AN)

5

0

23

50

st

t

On−time duration of 1 Mlower pulse when FB cross

5, 12

0.95

1.05

1.15

ms

1st_MLOWER_SKIP

V

+ V

threshold (NCP1399AA,

FB_SKIP_IN

FB_SKIP_HYST

NCP1399BA, NCP1399AK, NCP1399AL)

st

On−time duration of 1 Mlower pulse when FB cross

5, 12

1.8

1.9

2.1

V

+ V

threshold (NCP1399AC,

FB_SKIP_IN

FB_SKIP_HYST

NCP1399AG, NCP1399AI, NCP1399AM, NCP1399AN,

NCP1399AP)

st

On−time duration of 1 Mlower pulse when FB cross

1.08

1.20

1.32

ms

V

+ V

threshold (NCP1399AF,

FB_SKIP_IN

FB_SKIP_HYST

NCP1399AJ)

st

On−time duration of 1 Mlower pulse when FB cross

5, 12

2.1

−

2.4

2.7

−

ms

V

+ V

threshold (NCP1399AH)

FB_SKIP_IN

FB_SKIP_HYST

st

V

Internal FB level reduction during 1 Mupper pulse when FB

5, 6, 14

150

mV

1st_MUPPER_SKIP

cross V

+ V

threshold (NCP1399AA,

FB_SKIP_IN

FB_SKIP_HYST

NCP1399BA, NCP1399AC, NCP1399AG, NCP1399AI,

NCP1399AK, NCP1399AL, NCP1399AM, NCP1399AN,

NCP1399AP) (Note 3)

st

Internal FB level reduction during 1 Mupper pulse when FB

5, 6, 14

−

100

0

−

mV

cross V

+ V

threshold (NCP1399AF,

FB_SKIP_IN

FB_SKIP_HYST

NCP1399AJ) (Note 3)

st

FB_SKIP_HYST

Internal FB level reduction during 1 Mupper pulse when FB

cross V + V threshold

FB_SKIP_IN

(NCP1399AH) (Note 3)

Skip Input – NCP1399Ay version

Internal Skip pin current source

I

4

48

−

50

−

52

10

mA

SKIP

C

Maximum loading capacitance for skip pin voltage filtering

(Note 3)

nF

SKIP_LOAD_MAX

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. The NCP1399Ay version has skip adjustable externally.

3. Guaranteed by design.

4. Minimal impedance on P ON/OFF pin is 1 kW

5. Minimal resistance connected in series with bootstrap diode is 3.3 W

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8

NCP1399 Series

ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 12 V unless otherwise noted.)

J

CC

Symbol

Current Sense Input Section

On−time comparator delay to Mupper driver turn off

Rating

Min

Typ

Max

Unit

t

5, 6

−

250

ns

pd_CS

V

FB

= 2.5 V, V goes up from –2.5 V to 2.5 V with rising

CS

edge of 100 ns

I

Current sense input leakage current for V

=

3 V

6

−

1

mA

CS_LEAKAGE

CS

V

Current sense input offset voltage (NCP1399AA,

160

200

240

mV

CS_OFFSET

NCP1399BA, NCP1399AC, NCP1399AG, NCP1399AH,

NCP1399AI, NCP1399AK, NCP1399AL, NCP1399AM,

NCP1399AN, NCP1399AP)

Current sense input offset voltage (NCP1399AF, NCP1399AJ)

Leading edge blanking time of the on−time comparator output

6

110

360

150

440

190

540

mV

ns

t

5, 6, 14

LEB

Faults and Auto−Recovery Timer

t

FB fault timer duration (NCP1399AA, NCP1399BA,

NCP1399AK, NCP1399AL)

−

160

80

200

100

240

120

ms

FB_FAULT_TIMER

FB fault timer duration (NCP1399AC, NCP1399AF,

NCP1399AG, NCP1399AI, NCP1399AJ, NCP1399AM,

NCP1399AN, NCP1399AP)

FB fault timer duration (NCP1399AH)

−

5

−

6

240

−

300

1000

4.7

5

360

−

ms

−

N

Number of DRV pulses to confirm FB fault

FB voltage when FB fault is detected

FB_FAULT_COUNTER

V

4.5

−

4.9

−

V

FB_FAULT

CS_FAULT_COUNTER

N

Number of CS_fault cmp. pulses to confirm CS fault

−

V

CS voltage when CS fault is detected (NCP1399AA,

NCP1399BA, NCP1399AC, NCP1399AF, NCP1399AH,

NCP1399AI, NCP1399AK, NCP1399AL, NCP1399AM,

NCP1399AN, NCP1399AP)

V

CS_FAULT

2.5

3.2

2.7

3.4

2.9

3.6

(NCP1399AG)

(NCP1399AJ)

1.85

2.00

2.15

t

s

Auto−recovery duration, common timer for all fault condition

(NCP1399AA, NCP1399BA, NCP1399AC, NCP1399AG,

NCP1399AH, NCP1399AJ, NCP1399AK, NCP1399AL,

NCP1399AM, NCP1399AP)

−

0.8

1

1.2

A−REC_TIMER

Auto−recovery duration, common timer for all fault condition

(NCP1399AI, NCP1399AN)

1.6

1.9

2.4

Brown−Out Protection

V

Brown−out turn−off threshold

3

0.965

4.3

5

1.000

5.0

12

1.035

5.4

V

BO

I

Brown−out hysteresis current, V

< V

mA

mV

mA

ms

BO

VBULK/PFC_FB

BO

V

Brown*Out comparator hysteresis

Brown*Out input bias current

BO filter duration

25

BO_HYST

BO_BIAS

I

−

0.05

30

t

10

20

BO_FILTR

Ramp Compensation

RC

Ramp compensation gain (NCP1399AA, NCP1399BA,

NCP1399AC, NCP1399AF NCP1399AG, NCP1399AK,

NCP1399AM)

mV/ms

GAIN

−

58

82

108

Ramp compensation gain (NCP1399AI, NCP1399AN)

Ramp compensation gain (NCP1399AJ)

Ramp compensation gain (NCP1399AH)

Ramp compensation gain (NCP1399AL)

82

92

107

110

125

149

166

131

150

168

185

116

t

Ramp compensation time shift

−

0.6

−

ms

RC_SHIFT

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. The NCP1399Ay version has skip adjustable externally.

3. Guaranteed by design.

4. Minimal impedance on P ON/OFF pin is 1 kW

5. Minimal resistance connected in series with bootstrap diode is 3.3 W

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9

NCP1399 Series

ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 12 V unless otherwise noted.)

J

CC

Symbol

Temperature Shutdown Protection

Rating

Min

Typ

Max

Unit

T

TSD

Temperature shutdown T going up (NCP1399AA,

NCP1399BA, NCP1399AH, NCP1399AK)

−

124

137

−

°C

J

Temperature shutdown T going up (NCP1399AC,

J

NCP1399AF, NCP1399AG, NCP1399AI, NCP1399AJ,

NCP1399AL, NCP1399AM, NCP1399AN, NCP1399AP)

T

Temperature shutdown hysteresis

−

30

−

°C

TSD_HYST

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. The NCP1399Ay version has skip adjustable externally.

3. Guaranteed by design.

4. Minimal impedance on P ON/OFF pin is 1 kW

5. Minimal resistance connected in series with bootstrap diode is 3.3 W

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10

NCP1399 Series

IC Options

Option

Cumulative

FB fault

timer/

Dedicated

Soft_start_-

seq

FB fault

source

TON_MAX

fault

FB fault

counter

CS_FAULT

OVP fault

Latch

OTP fault

Auto−recovery

Latch

NCP1399AA Auto−recovery

NCP1399BA Auto−recovery

NCP1399AC Auto−recovery

Timer

NO

Auto−recovery Auto−recovery

ON

Latch

Auto−recovery

Latch

OFF

Latch

OFF

Latch

NCP1399AF

Latch

NCP1399AG Auto−recovery

NCP1399AH Auto−recovery

NCP1399AI Auto−recovery

NCP1399AJ Auto−recovery

NCP1399AK Auto−recovery

NCP1399AL Auto−recovery

NCP1399AM Auto−recovery

NCP1399AN Auto−recovery

NCP1399AP Auto−recovery

Auto−recovery

Latch

Auto−recovery

Auto−recovery Auto−recovery

Latch

Auto−recovery Auto−recovery Auto−recovery Auto−recovery

Auto−recovery Auto−recovery

Latch

Auto−recovery

Latch

Auto−recovery

OFF

Auto−recovery Auto−recovery

PFC_MODE Dead time

Dead time

fault

OFF−mode

version

OFF−mode

status

Ramp comp P ON/OFF

skip status

control

status

pull−up

ON

Option

BO status

ON

NCP1399AA

NCP1399BA

NCP1399AC

NCP1399AF

NCP1399AG

NCP1399AH

NCP1399AI

NCP1399AJ

NCP1399AK

NCP1399AL

NCP1399AM

NCP1399AN

NCP1399AP

ON

Auto−recovery

OFF

Active OFF

Active ON

Active OFF

−

ON

OFF

ON

OFF

ON

Auto−recovery

OFF

ON

Active OFF

ON

ZVS or

DT_max

Without ramp

shift

ON

Auto−recovery

OFF

ON

OFF

ON

Auto−recovery

OFF

ON

OFF

ON

OFF

ON

OFF

ON

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11

NCP1399 Series

ORDERING INFORMATION

Part Number

†

Marking

Package

Shipping

NCP1399AADR2G

NCP1399BADR2G

NCP1399ACDR2G

NCP1399AFDR2G

NCP1399AGDR2G

NCP1399AHDR2G

NCP1399AIDR2G

NCP1399AJDR2G*

NCP1399AKDR2G

NCP1399ALDR2G*

NCP1399AMDR2G

NCP1399ANDR2G

NCP1399APDR2G

NCP1399AA

NCP1399BA

NCP1399AC

NCP1399AF

NCP1399AG

NCP1399AH

NCP1399AI

NCP1399AJ

NCP1399AK

NCP1399AL

NCP1399AM

NCP1399AN

NCP1399AP

SOIC−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*Available upon request.

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12

NCP1399 Series

TYPICAL CHARACTERISTICS

0.30

0.25

0.20

0.15

0.10

1.05

0.95

0.85

0.75

0.65

0.55

0.45

0.05

0

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 5. I_{START_OFF}vs. Temperature

Figure 6. V_{CC_INHIBIT}vs. Temperature

0.55

0.54

0.53

0.52

9.4

9.3

9.2

9.1

9.0

8.9

8.8

0.51

0.50

8.7

8.6

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 7. I_START1vs. Temperature

Figure 8. I_START2vs. Temperature

9.45

9.43

9.41

15.85

15.80

15.75

9.39

9.37

15.70

15.65

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 9. V_{CC_OFF}vs. Temperature

Figure 10. V_{CC_ON}vs. Temperature

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13

NCP1399 Series

TYPICAL CHARACTERISTICS

6.48

6.47

6.46

6.45

820

800

780

760

740

6.44

6.43

720

700

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 11. V_{CC_RESET}vs. Temperature

Figure 12. I_{CC_SKIP−MODE}vs. Temperature

485

465

445

425

7.0

6.8

6.6

6.4

6.2

6.0

405

385

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 13. I_{CC_AUTOREC}vs. Temperature

Figure 14. I_{CC_OPERATION}vs. Temperature

475

455

435

35

32

29

26

415

395

23

20

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 15. I_{CC_LATCH}vs. Temperature

Figure 16. I_{CC_OFF−MODE}vs. Temperature

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14

NCP1399 Series

TYPICAL CHARACTERISTICS

9.20

9.15

9.10

9.05

9.00

8.4

8.3

8.2

8.1

8.0

7.9

8.95

8.90

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 17. V_{BOOT_ON}vs. Temperature

Figure 18. V_{BOOT_OFF}vs. Temperature

1.72

1.70

1.202

1.197

1.192

1.68

1.66

1.64

1.62

1.187

1.182

1.60

1.58

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 19. I_BOOT2vs. Temperature

Figure 20. V_{CLAMP_OVP/OTP_1}vs. Temperature

0.804

0.802

0.800

0.798

0.796

2.520

2.515

2.510

2.505

2.500

2.495

0.794

0.792

2.490

2.485

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 21. V_OTPvs. Temperature

Figure 22. V_OVPvs. Temperature

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15

NCP1399 Series

TYPICAL CHARACTERISTICS

96.0

95.5

95.0

94.5

94.0

22

21

20

19

18

17

16

93.5

93.0

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 23. I_OTPvs. Temperature

Figure 24. R_FBvs. Temperature

8.1

8.0

7.9

204

203

202

201

7.8

7.7

200

199

7.6

7.5

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 25. t_{ON_MAX}vs. Temperature

Figure 26. V_{CS_OFFSET}vs. Temperature

185

175

165

155

2.72

2.71

2.70

2.69

145

135

2.68

2.67

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 27. t_{pd_CS}vs. Temperature

Figure 28. V_{CS_FAULT}vs. Temperature

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16

NCP1399 Series

TYPICAL CHARACTERISTICS

1.010

1.005

1.000

5.00

4.95

4.90

4.85

0.995

0.990

4.80

4.75

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 29. V_BOvs. Temperature

Figure 30. I_BOvs. Temperature

4.70

4.69

4.68

4.67

4.66

50.2

50.0

49.8

49.6

49.4

4.65

4.64

49.2

49.0

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 31. V_{FB_FAULT}vs. Temperature

Figure 32. I_SKIPvs. Temperature

78

76

74

16

14

12

72

70

10

8

−55

−25

5

35

65

95

−55

−25

5

35

65

95

TEMPERATURE (°C)

Figure 33. RC_GAINvs. Temperature

Figure 34. I_DISCHARGE1vs. Temperature

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17

NCP1399 Series

TYPICAL CHARACTERISTICS

28

24

20

16

10

8

6

4

2

12

8

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

TEMPERATURE (°C)

Figure 35. ROH vs. Temperature

Figure 36. ROL vs. Temperature

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18

NCP1399 Series

VCC Management with High−voltage Startup Current Source

The NCP1399 controller features a HV startup current

source that allows fast startup time and extremely low

standby power consumption. Two startup current levels

failure mode that may occur in the application. The HV

startup current source is primarily enabled or disabled based

on V level. The startup HV current source can be also

CC

(I

and I

) are provided by the system for safety in

enabled by BO_OK rising edge, auto−recovery timer end,

REMote and TSD end event. The HV startup current source

charges the VCC capacitor before IC start−up.

start1

start2

case of short circuit between VCC and GND pins. In

addition, the HV startup current source features a dedicated

over−temperature protection to prevent IC damage for any

Figure 37. Internal Connection of the VCC Management Block

The NCP1399 controller disables the HV startup current

Figure 65 to find an illustration of the NCP1399 VCC

management system under all operating conditions/modes.

The HV startup current source features an independent

source once the VCC pin voltage level reaches V

CC_ON

threshold – refer to Figure 37. The application then starts

operation and the auxiliary winding maintains the voltage

bias for the controller during normal and skip−mode

operating modes. The IC operates in so called Dynamic Self

Supply (DSS) mode when the bias from auxiliary winding

over–temperature protection system to limit I

current

start2

when the die temperature reaches 130°C. At this

temperature, I will be progressively to prevent the die

start2

temperature from rising above 130°C.

is not sufficient to keep the V voltage above V

CC

CC_OFF

Brown−out Protection − VBULK/PFC FB Input

threshold (i.e. V voltage is cycling between V

and

CC

CC_ON

Resonant tank of an LLC converter is always designed to

operate within a specific bulk voltage range. Operation

below minimum bulk voltage level would result in current

and temperature overstress of the converter power stage.

The NCP1399 controller features a VBULK/PFC FB input

in order to precisely adjust the bulk voltage turn−ON and

turn−OFF levels. This Brown−Out protection (BO) greatly

simplifies application level design.

V

thresholds with no driver pulses on the output

CC_OFF

during positive V ramp). The HV source is also operated

in DSS mode when the low voltage controller enters

off−mode or fault−mode operation. In this case the VCC pin

CC

voltage will cycle between V

and V

CC_ON

CC_OFF

thresholds and the controller will not deliver any driver

pulse – waiting for return from the off−mode or latch mode

operation. Please refer to figures Figure 61 through

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19

NCP1399 Series

Figure 38. Internal Connection of the Brown−out Protection Block

The internal circuitry shown in Figure 38 allows

Note that the VBULK/PFC FB pin is pulled down by an

internal switch when the controller is in startup phase − i.e.

monitoring the high−voltage input rail (V ).

A

bulk

high−impedance resistive divider made of R

and R

when the V voltage ramps up from V < V

upper

lower

CC CC CC_RESET

resistors brings a portion of the V

rail to the

towards the V

level on the VCC pin. This feature

bulk

CC_ON

VBULK/PFC FB pin. The Current sink (I ) is active below

assures that the VBULK/PFC FB pin voltage will not ramp

BO

the bulk voltage turn−on level (V

). Therefore, the

up before the IC operation starts. The I hysteresis current

bulk_ON

BO

bulk voltage turn−on level is higher than defined by the

division ratio of the resistive divider. To the contrary, when

the internal BO_OK signal is high, i.e. the application is

sink is activated and BO discharge switch is disabled once

the

V

CC

voltage crosses

V

CC_ON

threshold. The

VBULK/PFC FB pin voltage then ramps up naturally

according to the BO divider information. The BO

comparator then authorizes or disables the LLC stage

running, the I sink is disabled. The bulk voltage turn−off

BO

threshold (V ) is then given by BO comparator

bulk_OFF

reference voltage directly on the resistor divider. The

advantage of this solution is that the V threshold

operation based on the actual V

level.

bulk

The low I hysteresis current of the NCP1399 brown out

bulk_OFF

BO

precision is not affected by I

tolerance.

hysteresis current sink

protection system allows increasing the bulk voltage divider

resistance and thus reduces the application power

consumption during light load operation. On the other hand,

the high impedance divider can be noise sensitive due to

capacitive coupling to HV switching traces in the

BO

The V

and V

levels can be calculated

bulk_ON

bulk_OFF

using equations below:

The I is ON:

BO

application. This is why a filter (t

) is added after the

BO_FILTR

(eq. 1)

V_BO) V_BOhyst

+

BO comparator in order to increase the system noise

immunity. Despite the internal filtering, it is also

recommended to keep a good layout for BO divider resistors

and use a small external filtering capacitor on the

VBULK/PFC pin if precise BO detection wants to be

achieved.

The bulk voltage HV divider can be also used by a PFC

front stage controller as a feedback sensing network (refer

again to Figure 38). The shared bulk voltage resistor divider

between PFC and LLC stage offers a way how to further

reduce power losses during off−mode and no−load

operation. The NCP1399 features a PFC MODE pin that

disconnects bias of the PFC stage during light load,

off−mode or fault mode operation. The signal from the PFC

MODE pin can be also used to control an external HV switch

in order to disconnect the bulk voltage divider from bulk

during off−mode operation. This technique further reduces

R_lower

R_lower) R_upper

R_lower@ R_upper

R_lower) R_upper

_@ǒ

Ǔ

V_{bulk_ON}

@

* I_BO

The I is OFF:

BO

R_lower

R_lower) R_upper

V_BO+ V_{bulk_OFF}

@

(eq. 2)

One can extract R

term from equation 2 and use it in

lower

equation 1 to get needed R

value:

upper

V_{bulk_ON}@V

^BO* V_BO* V_BOhyst

V_{bulk_OFF}

R_lower

+

(eq. 3)

(eq. 4)

V_BO

I_BO

@

ǒ

1 *

Ǔ

V_{bulk_OFF}

V_{bulk_OFF}* V_BO

R_upper+ R_lower

@

V_BO

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20

NCP1399 Series

the no−load power consumption down again since the power

losses of voltage divider are not affected by the bulk voltage

at all.

Please refer to Figure 61 through Figure 65 for an

illustration of NCP1399 Brown−out protection system in all

operating conditions/modes.

the operation, after filter time delay, when the OVP/OTP

input voltage is out of the no−fault window. The controller

then either latches−off or or starts an auto−recovery timer −

depending on the IC version − and triggered the protection

threshold (V

or V ).

OVP

OTP

The internal current source I

allows a simple OTP

OTP

implementation by using a single negative temperature

coefficient (NTC) thermistor. An active soft clamp

Over−voltage and Over−temperature Protection

The OVP/OTP pin is a dedicated input to allow for a

simple and cost effective implementation of two key

protection features that are needed in adapter applications:

over−voltage (OVP) and over−temperature (OTP)

protections. Both of these protections can be either latched

or auto−recovery– depending on the version of NCP1399.

The OVP/OTP pin has two voltage threshold levels of

composed from V

and R

components prevents the

clamp

OVP/OTP pin voltage from reaching the V

threshold

OVP

when the pin is pulled up by the I

current. An external

OTP

pull−up current, higher than the pull*down capability of

the internal clamp (V

pull the OVP/OTP pin above V

), has to be applied to

threshold to activate the

CLAMP_OVP/OTP

OVP

OVP protection. The t

and t

filters

OVP_FILTER

OTP_FILTER

detection (V

and V ) that define a no−fault window.

OTP

OVP

are implemented in the system to avoid any false triggering

of the protections due to application noise and/or poor

layout.

The controller is allowed to run when OVP/OTP input

voltage is within this working window. The controller stops

Figure 39. Internal Connection of OVP/OTP Input

The OTP protection could be falsely triggered during

controller startup due to the external filtering capacitor

• IC returns to operation from skip−mode (V

+

FB_SKIP_IN

V

threshold was reached)

FB_SKIP_HYST

charging current. Thus the t

period has been

BLANK_OTP

• IC returns to operation from off−mode (V

or

REM_ON

implemented in the system to overcome such behavior. The

OTP comparator output is ignored during t

V

signal is received by off−mode control

FB_REM_ON

BLANK_OTP

block)

period. In order to speed up the charging of the external

filtering capacitor C connected to OVP/OTP pin,

The I

current source is disabled when:

OTP

OVP_OTP

• V falls below V

threshold

CC

CC_OFF

the I

current has been doubled to I . The

OTP_BOOST

OTP

• BO OK signal goes to low state (i.e. Brown−out

condition occurs on the mains)

maximum value of filtering capacitor is 47 nF.

The OVP/OTP ON signal is set after the following events:

• the V voltage exceeds the V threshold during

• Fault signal is activated (Auto−recovery timer starts

counting or Latch fault is present)

CC

CC_ON

first start−up phase (after VCC pin voltage was below

threshold)

• IC goes into the skip−mode operation (V

V

FB_SKIP_IN

CC_RESET

threshold was reached)

• BO OK signal is received from BO block

• Auto−recovery timer elapsed and a new restart occurs

• IC goes into the off−mode operation (V

or

REM_OFF

) signal was reached)

(V

& V

FB_REM_OFF

CC_OFF

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21

NCP1399 Series

The latched OVP or OTP versions of NCP1399 enters

latched protection mode when V voltage cycles between

• Active OFF off−mode control − available on the

CC

NCP1399Ay device family

V

CC_ON

and V

thresholds and no pulses are provided

CC_OFF

These two off−mode operation control techniques differ in

the way the off−mode operation is started on the primary

side controller. Both of these methods are described

separately hereinafter.

by drivers. The controller VCC pin voltage has to be cycled

down below V threshold in order to restart

CC_RESET

operation. This would happen when the power supply is

unplugged from the mains.

Active ON Off−mode Control – NCP1399B Device

Family

SKIP/REM Input and Off−mode Control

The NCP1399 implements an ultra−low power

consumption mode of operation called off−mode. The

application output voltage is cycled between the nominal

and lower levels that are defined by the secondary side

off−mode controller (like NCP435x secondary off−mode

controller). The output voltage is thus not regulated to

nominal level but is always kept at a high enough voltage

level to provide bias for the necessary circuits in the target

application – for example this could be the case of

microcontroller with very low consumption that handles

VCC management in a notebook or TV. The no−load input

power consumption could be significantly reduced when

using described technique. The NCP1399 implements two

different off−mode control system approaches:

The NCP1399B device family uses a SKIP/REM pin only

for off−mode operation control– i.e. the pin is internally

connected to the Active ON off−mode control block and the

skip mode threshold level is not adjustable externally. The

skip mode comparator threshold can be adjusted only

internally (by IC option) in this package option. The

SKIP/REM pin when used for off−mode control allows the

user to activate the ultra−low consumption mode during

which the IC consumption is reduced to only very low HV

pin leakage current (I ) and very low VCC pin

HV_OFF−MODE

consumption (I

). The off*mode is activated

CC_OFF−MODE

when SKIP/REM pin voltage exceeds V

threshold.

REM_OFF

Normal operating mode is resumed when SKIP/REM pin

voltage drops below V threshold – refer to

REM_ON

• Active ON off−mode control − available on the

Figure 40 for an illustration.

NCP1399By device family

Figure 40. SKIP/REM Input Internal Connection – Active ON Version

The off−mode operation is activated by the secondary side

off−mode controller. The auxiliary bias for primary side

off−mode control is provided by a circuit composed from

switching between ON−mode and OFF−mode states when

off−mode control is implemented. The OFF mode period

last significantly longer time (tens of seconds or more)

compared to the secondary capacitor refilling period (few

tens of milliseconds) – this explains why the no−load input

power consumption can be drastically reduced. The

auxiliary off−mode supply capacitor C1 can stay charged

while the secondary bias is lost – this can happen during

overload or other fault mode conditions. A REM TIMER is

thus implemented in the system to allow fast application

components D , C , R , R and C . The SKIP/REM pin is

2

1

2

pulled up by this auxiliary supply circuit once the REM

optocoupler (REM OK) is released. The application then

operates in off−mode until the secondary side off−mode

controller activates the REM optocoupler or until the

auxiliary bias on C is lost. Normal operation mode is then

1

recovered via power stage startup. The application is thus

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22

NCP1399 Series

restart in such cases. The controller blanks the SKIP/REM

input information and pulls down the SKIP/REM input for

time during controller restart so that the

secondary side bias can be restored and the secondary

off−mode controller can activate the REM optocoupler. This

REM TIMER blank sequence is activated each time the

The bias on VCC pin needs to be assured when off−mode

operation takes place. The auxiliary winding is no more able

to provide any bias thus the HV startup current source is

operated in DSS mode – i.e. the VCC pin voltage is cycling

t

REM_TIMER

between V

and V

thresholds. This approach

CC_ON

CC_OFF

keeps IC biasing in order to memorize the current operation

sate.

VCC pin voltage reaches V

threshold – except in the

CC_ON

situation when after IC left off−mode operation by standard

Please refer to Figure 64 for an illustration on how the

NCP1399 Active ON off−mode system works under all

operating conditions/modes.

way and V is restored – i.e. when the REM optocoupler

CC

is activated by the secondary off−mode controller.

The SKIP/REM input blanking is activated in following

cases:

Active OFF Off−mode Control – NCP1399A Device

Family

The NCP1399A device family uses LLC FB pin voltage

information for off−mode operation detection − refer to

Figure 41. The SKIP/REM pin is internally connected to the

• VCC pin voltage reaches V

threshold during first

CC_ON

start−up phase (i.e. when V was below V

CC

CC_RESET

threshold before)

• Auto−recovery timer elapsed and new start is initiated

skip mode block in this case and serves as a V

FB_SKIP_IN

threshold voltage adjust pin. The secondary off−mode

controller reuses the LLC stage regulation optocoupler in

order to reduce total system cost. The off−mode operation is

initiated once the LLC FB pin is pulled down below

The REM TIMER helps to assure fast application re−start

from fault conditions by forcing controller operation after

t

. However, the secondary controller drives the

REM_TIMER

remote pin via REM optocoupler during normal operating

conditions in order to switch between ON and OFF

operating modes. The controller is active for very short time

during no−load conditions − just during the time needed to

re−fill the secondary side capacitors to the nominal output

voltage level. In this case we do not use REM TIMER

because it would increase the no−load power consumption

by forcing the application to run for a longer time than

necessary. The REM TIMER blank period is thus not

activated in no−load conditions.

V

threshold and the VCC pin voltage drops below

threshold in the same time. The optocoupler has to

REM_ON

CC_OFF

be active at all time the application is held in off−mode. No

biased is then provided by the secondary off−mode

controller during normal operation – this is why this

approach is called Active OFF off−mode operation. The

application no−load input power consumption is slightly

higher compared to Active ON off−mode solution,

previously described, because the optocoupler needs to be

biased during off mode operation

Figure 41. Active OFF Off−mode Internal Detection Based on the LLC FB Pin Voltage

The controller monitors the LLC FB pin voltage level and

restarts via regular startup sequence (including VCC pin

voltage is cycling between V

and V

CC_ON CC_OFF

thresholds. This approach keeps IC biased so that the actual

operation sate is memorized. The LLC FB pin pull−up

resistor is disconnected when off−mode operation is

activated in order to reduce IC power consumption and also

needed current for optocoupler driving from secondary side.

voltage ramp−up to V

level and soft−start) once the

CC_ON

FB pin is released by the secondary off−mode controller.

The HV startup current source is working in DSS mode

during application off−mode operation – i.e. the VCC pin

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23

NCP1399 Series

Please refer to Figure 65 for an illustration on how the

NCP1399 active ON off−mode system works under all

operating conditions/modes.

P ON/OFF pin is 1 kW. The PFC stage operation can thus be

disabled/enabled via external logic signal. This option

should be used with the wide range input voltage LLC tank

designed to assure correct operation of the LLC stage

through whole bulk voltage range. The PFC MODE output

pin can be used for two purposes:

PFC MODE Output and P ON/OFF Control Pin

The NCP1399 has two pins P ON/OFF and PFC MODE

that can be used to disable or enable PFC stage operation

based on actual application operating state – please refer to

Figure 46. The PFC MODE pin voltage is changed

1. to control the external small signal HV MOSFET

switch that connects the bulk voltage divider to the

VBULK/PFC FB input

2. to control the PFC front stage controller operation

via PFC controller supply pin

(V

or V

) based on the actual P ON/OFF

PFC_M_ON

PFC_M_BO

input logic signal state. Minimum impedance connected to

5 V

0.1 V

Figure 42. Internal Connection of the PFC MODE and P ON/OFF Blocks

There are three possible states of the PFC MODE output

that can be placed by the controller based on the application

operating conditions:

connects VCC pin voltage to PFC MODE output

with minimum dropout (V ). This state of

the PFC MODE output appears in case an external

signal on the P ON/OFF pin is at “low” state.

PFC_M_ON

1. The PFC MODE output pin is pulled−down by an

internal MOSFET switch before controller startup.

This technique ensures minimum VCC pin current

The output power level is derived internally from the

actual FB pin voltage. This information could be compared

on external comparator with the reference level and control

the P ON/OFF input, thus the user has possibility to adjust

power below which the PFC stage is disabled in order to

increase efficiency in light load conditions. The P ON/OFF

consumption in order to ramp V voltage in a

CC

short time from the HV startup current source

which speeds up the startup or restart process. The

PFC MODE output pin is also pulled−down in

off−mode or protection mode during which the HV

startup current source is operated in DSS mode.

This reduces the application power consumption in

both cases.

comparator features an hysteresis (P ON/OFF

)

HYST

proportional to the set P ON/OFF level in order to overcome

PFC power stage oscillations (periodical ON/OFF

2. The pull−down switch is disabled and the internal

regulator enabled by the controller to provide

operation). The P ON/OFF timer (t

) is

P ON/OFF_TIMER

implemented to ensure a long enough propagation delay

from the PFC turn OFF detection to PFC MODE output

deactivation. This timer is unidirectional so that it resets

immediately after PFC ON condition is detected by the

P ON/OFF comparator. This technique is used in order to

avoid a PFC stage deactivation during load or line transients.

The PFC MODE pin output current is limited when the VCC

to PFC MODE bypass switch is activated. The current

limitation avoids bypass switch damage during PFC VCC

decoupling capacitor charging process or short circuit. A

minimum value PFC VCC decoupling capacitance should

be used in order to speed up PFC stage startup after it is

enabled by the NCP1399 controller.

V

reference when an external logic

PFC_M_BO

signal on the P ON/OFF pin is at “high” state. An

internal regulator includes current limitation for

the PFC MODE output that is set to I

PFC_M_LIM

when V

reference is provided. The PFC

PFC_M_BO

MODE pin drives external small signal HV

MOSFET switch to keep bulk voltage divider

connected. The LLC power stage Brown−out

protection system thus works when the LLC stage

is switching while PFC stage disabled.

3. The pull−down switch is disabled and the internal

regulator is switched to bypass mode in which it

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NCP1399 Series

Please refer to Figure 61 through Figure 65 for an

illustration of NCP1399 PFC operation control.

2. Precise VCO (or CCO) is needed to assure

frequency modulation with good reproducibility,

f

and f

clamps need to be adjusted for each

min

max

ON−time Modulation and Feedback Loop Block

Frequency modulation of today’s commercially available

resonant mode controllers is based on the output voltage

regulator feedback only. The feedback voltage (or current)

of output regulator drives voltage (or current) controlled

oscillator (VCO or CCO) in the controller. This method

presents three main disadvantages:

design ≥ need for an adjustment pin(s).

3. Dedicated overload protection system, requiring

an additional pin, is needed to assure application

safety during overload and/or secondary short

circuit events.

The NCP1399 resolves all disadvantages mentioned

above by implementing a current mode control scheme that

ensures best transient response performance and provides

inherent cycle−by−cycle over−current protection feature in

the same time. The current mode control principle used in

this device can be seen in Figure 43.

nd

1. The 2 order pole is present in small signal

gain−phase characteristics ≥ the lower cross over

frequency and worse transient response is imposed

by the system when voltage mode control is used.

There is no direct link to the actual primary current

– i.e. no line feed forward mechanism which

results in poor line transient response.

Figure 43. Internal Connection of the NCP1399 Current Mode Control Scheme

The basic principle of current mode control scheme

implementation lies in the use of an ON−time comparator

that defines upper switch on−time by comparing voltage

ramp, derived from the current sense input voltage, to the

divided feedback pin voltage. The upper switch on−time is

then re−used for low side switch conduction period. The

switching frequency is thus defined by the actual primary

current and output load conditions. Digital processing with

10 ns minimum on−time resolution is implemented to

ensure high noise immunity. The ON−time comparator

is divided down by capacitive divider (Ccs1, Ccs2, Rcs1,

Rcs2) before it is provided to the CS input. The capacitive

divider division ratio, which is fully externally adjustable,

defines the maximum primary current level that is reached

in case of maximum feedback voltage – i.e. the capacitive

divider division ration defines the maximum output power

of the converter for given bulk voltage. The CS is a bipolar

input pin which an input voltage swing is restricted to 5 V.

A fixed voltage offset is internally added to the CS pin signal

in order to assure enough voltage margin for operation the

feedback optocoupler − the FB optocoupler saturation voltage

is ~ 0.15 V (depending on type). However, the CS pin useful

signal for frequency modulation swings from 0 V, so current

mode regulation would not work under light load conditions

if no offset would be added to the CS pin before it is stabilized

to the level of the on−time comparator input. The CS pin

signal is also used for secondary side short circuit detection

– please refer to chapter dedicated to short circuit protection.

output is blanked by the leading edge blanking (t

) after

LEB

the Mupper switch is turned−on. The ON−time comparator

LEB period helps to avoid false triggering of the on−time

modulation due to noise generated by the HB pin voltage

transition.

The voltage signal for current sense input is prepared

externally via natural primary current integration by the

resonant tank capacitor Cs. The resonant capacitor voltage

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NCP1399 Series

The second input signal for the on−time comparator is

passes through the FB processing block before it is brought

to the ON−time comparator input. The FB processing block

derived from the FB pin voltage. This internal FB pin signal

is also used for the following purposes: skip mode operation

detection, PFC MODE control, off−mode detection (in

NCP1399A device family) and overload / open FB pin fault

detection. The detailed description of these functions can be

found in each dedicated chapters. The internal pull−up

resistor assures that the FB pin voltage increases when the

optocoupler LED becomes less biased – i.e. when output

load is increased. The higher FB pin voltage implies a higher

reference level for on−time comparator i.e. longer Mupper

switch on−time and thus also higher output power. The FB

pin features a precise voltage clamp which limits the internal

FB signal during overload and startup. The FB pin signal

scales the FB signal down by a K ratio in order to limit the

FB

CS input dynamic voltage range. The scaled FB signal is

then further processed by subtraction of

a ramp

compensation generator signal in order to ensure stability of

the current mode control scheme. The divided internal FB

signal is overridden by a Soft−start generator output voltage

during device starts−up.

The actual operation frequency of the converter is defined

based on the CS pin and FB pin input signals. Please refer to

Figure 44 and below description for better understanding of

the NCP1399 frequency modulation system.

Figure 44. NCP1399 On−time Modulation Principle

The Mupper switch is activated by the controller after

dead−time (DT) period lapses in point A. The frequency

processing block increments the ON−time counter with

10 ns resolution until the internal CS signal crosses the

internal FB set point for the ON−time comparator in point B.

A DT period is then introduced by the controller to avoid any

shoot−through current through the power stage switches.

The DT period ends in point C and the controller activates

the Mlower switch. The ON−time processing block

decrements the ON_time counter down until it reaches zero.

The Mlower switch is then turned−OFF at point D and the

DT period is started. This approach results in perfect duty

cycle symmetry for Mlower and Mupper switches. The

Mupper switch on−time naturally increases and the

operating frequency drops when the FB pin voltage is

increased, i.e. when higher current is delivered by the

converter output – sequence E.

skip mode is not used or adjusted correctly. The current

mode operation is not possible in such case because the

ON−time comparator output stays active for several

switching cycles. Thus a special logic has been implemented

in NCP1399 in order to repeat the last valid on−time until the

current mode operation recovers – i.e. until the CS pin signal

balance is restored by the system.

Overload and Open FB Protections

The overload protection and open FB pin detection are

implemented via FB pin voltage monitoring in this

controller. The FB fault comparator is triggered once the FB

pin voltage reaches its maximum level and the V

FB_FAULT

threshold is exceeded. The fault timer or counter (depending

on IC option) is then enabled – refer to Figure 43. The time

period to the FB fault event confirmation is defined by the

preselected t

parameter when the fault

FB_FAULT_TIMER

timer option is used. The FB fault counter, once selected as

a FB fault confirmation period source, defines the fault

confirmation period via Mupper DRV pulses counting. The

The resonant capacitor voltage and thus also CS pin

voltage can be out of balance in some cases – this is the case

during transition from full load to no−load operation when

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26

NCP1399 Series

FB fault confirmation time is thus dependent on switching

option is also available on request. The FB fault

timer/counter is not reset when the FB fault condition

diminishes in this case. The FB fault timer/counter is

disabled and memorizes the fault period information. The

cumulative FB fault timer/counter integrates all the FB fault

events over the IC operation time. The Fault timer/counter

can be reset via skip mode or VCC UVLO event.

frequency. The fault timer/counter is reset once the FB fault

condition diminishes. A digital noise filter has been added

after the FB fault comparator to overcome false triggering of

the FB fault timer/counter due to possible noise on the FB

input. The noise filter has a period of 2 ms for FB fault

timer/counter activation and 20 ms for reset/deactivation to

assure high noise immunity. A cumulative timer/counter IC

Figure 45. Internal FB Fault Management

The controller disables driver pulses and enters protection

mode once the FB fault event is confirmed by the FB fault

timer or counter. Latched or auto−recovery operation is then

triggered – depends on selected IC option. The controller

primary current is naturally limited by the NCP1399

on−time modulation principle in this case. But the primary

current increases when the output terminals are shorted. The

NCP1399 controller will maintain zero voltage switching

operation in such case, however high currents will flow

through the power MOSFETS, transformer winding and

secondary side rectification. The NCP1399 implements a

dedicated secondary side short circuit protection system that

will shut down the controller much faster than the regular FB

fault event in order to limit the stress of the power stage

components. The CS pin signal is monitored by the

dedicated CS fault comparator − refer to Figure 43. The CS

fault counter is incremented each time the CS fault

comparator is triggered. The controller enters

auto−recovery or latched protection mode (depending on IC

option) in case the CS fault counter overflows refer to

Figure 46. The CS fault counter is then reset once the CS

fault comparator is inactive for at least 50 Mupper upcoming

pulses. This digital filtering improves CS fault protection

system noise immunity.

adds an auto−recovery off−time period (t ) and

A−REC_TIMER

restarts the operation via soft start in case of auto−recovery

option. The application temperature runaway is thus

avoided in case of overload while the automatic restart is still

possible once the overload condition disappears. The IC

with latched FB fault option stays latched−off, supplied by

the HV startup current source working in DSS mode, until

the V

threshold is reached on the VCC pin – i.e.

CC_RESET

until user re−connects power supply mains.

Please refer to Figure 61 and Figure 62 for an illustration

of the NCP1399 FB fault detection block.

Secondary Short Circuit Detection

The protection system described previously, implemented

via FB pin voltage level detection, prevents continuous

overload operation and/or open FB pin conditions. The

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NCP1399 Series

Figure 46. NCP1399 CS Fault Principle

Dedicated Startup Sequence and Soft−Start

Hard switching conditions can occur in a resonant SMPS

application when the resonant tank operation is started with

50% duty cycle symmetry – refer to Figure 47. This hard

switching appears because the resonant tank initial

conditions are not optimal for the clean startup.

Figure 47. Hard switching cycle appears in the LLC application when resonant tank is

excited by 50% duty cycle during startup

The initial resonant capacitor voltage level can differ

resonant tank is low when the output is loaded and/or the

output voltage is low enough to made secondary rectifies

conducting during first switching cycles of startup phase.

The resonant frequency of the resonant tank is given by the

resonant capacitor capacitance and resonant inductance

−note that the magnetizing inductance does not participate

in resonance in this case. However, if the application

starts−up when the output capacitors is charged and there is

no load connected to the output, the secondary rectification

diodes is not conducting during each switching cycle of

startup sequence and thus the resonant frequency of resonant

tank is affected also by the magnetizing inductance. In this

case, the resonant frequency is much lower than in case of

startup into loaded/discharged output.

depending on how long delay was placed before application

operation restart. The resonant capacitor voltage is close to

zero level when application restarts after very long delay –

for example several seconds, when the resonant capacitor is

discharged by leakage to the power stage. However, the

resonant capacitor voltage value can be anywhere between

Vbulk and 0 V when the application restarts operation after

a short period of time – like during periodical SMPS

turn−on/off. Another factor that plays significant role during

resonant power supply startup is the actual load impedance

seen by the power stage during the first pulses of startup

sequence. This impedance is not only defined by resonant

tank components but also by the output loading conditions

and actual output voltage level. The load impedance of

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NCP1399 Series

These facts show that a clean, hard switching free and

charged before the first high−side driver pulse is introduced

by the controller. The first Mupper switch on−time Tup1

period is fixed and depends on the application parameters.

This period can be adjusted internally – various IC options

parasitic oscillation free, startup of an LLC converter is not

an easy task, and cannot be achieved by duty cycle imbalance

and/or simple resonant capacitor pre−charge to Vbulk/2 level.

These methods only work in specific startup conditions.

This explains why the NCP1399 implements a proprietary

startup sequence − see Figure 48 and Figure 49. The resonant

capacitor is discharged down to 0 V before any application

restart − except when restarting from skip mode.

are available. The Mupper switch is released after T

up1

period and it is not followed by the Mlower switch

activation. The controller waits for a new ZVS condition for

Mupper switch instead and measures actual resonant tank

conditions this way. The Mupper switch is then activated

again after the Mlower blank period is used for measurment

purposes. The second Mupper driver conduction period is

then dependent on the previously measured conditions:

1. The Mupper switch is activated for 3/2 of previous

Mupper conduction period in case the measured

time between previous Mupper turn−off event and

upper ZVS condition detection is twice higher than

the the previous Mupper pulse conduction period

2. The Mupper switch is activated for previous

Mupper conduction period in case the measured

time between previous Mupper turn−off event and

upper ZVS condition detection is twice lower than

the previous Mupper pulse conduction period

The startup period then depends on the previous

condition. Another blank Mlower switch period is placed by

the controller in case condition 1 occurred. A normal

Mlower driver pulse, with DC of 50% to previous Mupper

DRV pulse, is placed in case condition 2 is fulfilled.

The dedicated startup sequence is placed after the

resonant capacitor is discharged (refer to Figure 48 and

Figure 49) in order to exclude any hard switching cycles

during the startup sequence. The first Mupper switch cycle

in startup phase is always non−ZVS cycle because there is

no energy in the resonant tank to prepare ZVS condition.

However, there is no energy in the resonant tank at this time,

there is also no possibility that the power stage MOSFET

body diodes conducts any current. Thus the hard

commutation of the body diode cannot occur in this case.

The IC will not start and provide regular driver output

pulses until it is placed into the target application, because

the startup sequence cannot be finished until HB pin signal

is detected by the system. The IC features a startup watchdog

Figure 48. Initial Resonant Capacitor Discharge

before Dedicated Startup Sequence is Placed

timer (t

) which activates a dedicated startup

WATCHDOG

Figure 49. Dedicated Startup Sequence Detail

sequence periodically in case the IC is powered without

application (during bench testing) or in case the startup

sequence is not finished correctly. The IC will provide the

first Mlower and first Mupper DRV pulses with a

The resonant capacitor discharging process is simply

implemented by activating an internal current limited switch

connected between the HB pin and IC ground – refer to

Figure 48. This technique assures that the resonant capacitor

energy is dissipated in the controller without ringing or

oscillations that could swing the resonant capacitor voltage

to a positive or negative level. The controller detects that the

discharge process is complete via HB pin voltage level

monitoring. The discharge switch is disabled once the HB

t

off−time in−between startup attempts.

WATCHDOG

Soft−start

The dedicated startup sequence is complete when

condition 2 from previous chapter is fulfilled and the

controller continues operation with the soft−start sequence.

A fully digital non−linear soft−start sequence has been

implemented in NCP1399 using a soft−start counter and

D/A converter that are gradually incremented by the Mlower

driver pulses. A block diagram of the NCP1399 soft−start

system is shown in Figure 50.

pin voltage drops below the V

threshold.

HB_MIN

The dedicated startup sequence continues by activation of

the Mlower driver output for Tl1 period (refer to Figure 49).

This technique ensures that the bootstrap capacitor is fully

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NCP1399 Series

Figure 50. Soft−start Block Internal Implementation

The soft−start block subsystems and operation are

described below:

1. The Soft−Start counter is a unidirectional counter

power switches as afore mentioned. The ON−time

counter count−up mode can be switched to the

count−down mode by either of two events: 1

st

that is loaded with the last Mupper on−time value

that is reached at the dedicated startup sequence

end (i.e. during condition b occurrence explained

in previous chapter). The on−time period used in

the initial period of the soft−start sequence is

affected by the first Mupper on−time period

selection and the dedicated startup sequence

processing. The Soft−Start counter counts up from

this initial on time period to its maximum value

which corresponds to the IC maximum on−time.

The Soft−Start counter is incremented by the

when the ON−time counter value reaches the

nd

maximum on−time value (t

) or 2 when

TON_MAX

the actual Mupper on−time is terminated based on

the current sense input information.

3. The Maximum ON−time comparator compares

the actual ON−time counter value with the

maximum on−time value (t

) and

TON_MAX

immediately activates the latch (or auto−recovery)

protection mode. The minimum operating

frequency of the controller is defined the same

way. The Maximum ON−time comparator

soft−start increment number (t

)

reference is loaded by the Soft−Start counter value

on each switching cycle during soft−start. The

Maximum ON−time fault signal is ignored during

Soft−Start operation. The converter Mupper switch

on−time (and thus operating frequency) is thus

defined by the Soft−Start counter value indirectly

– via Maximum ON−time comparator. The

Mupper switch on−time is increased until the

SS_INCREMENT

during each Mlower switch on−time period. The

soft−start start increment, selectable via IC option,

thus affects the soft−start time duration. The

Mlower clock signal for the Soft−Start counter can

be divided down by the SS clock divider

(K ) in case the soft−start period

SS_INCREMENT

needs to be prolonged further – this can be also

done via IC option selection. The Soft−Start period

is terminated (i.e. the counter is loaded to its

maximum) when the FB pin voltage drops below

Soft−Start counter reaches t

period and

TON_MAX

Maximum on−time protection is activated, or until

ON−time comparator takes action and overrides

the Maximum ON−time comparator.

V

level.

FB_SKIP_IN

2. The ON−time counter is a bidirectional counter

that is used as a main system counter for on−time

modulation during soft−start, normal operation or

overload conditions. The ON−time counter

4. The Soft−Start D/A converter generates a

soft−start voltage ramp for ON−time comparator

input synchronously with Soft−Start counter

incrementing. The internal FB signal for ON−time

comparator input is artificially pulled−down and

then ramped−up gradually when soft−start period

is placed by the system – refer to Figure 51. The

FB loop is supposed to take over at certain point

counts−up during Mupper switch conduction

period and then counts down to zero – defining

Mlower switch conduction period. This technique

assures perfect 50 % duty cycle symmetry for both

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NCP1399 Series

when regulation loop is closed and output gets

operating frequency. The Soft−Start period is

regulated so that soft−start has no other effect on

the on−time modulation. The Soft−Start counter

continues counting−up until it reaches its

terminated (i.e. counter is loaded to its maximum)

when the FB pin voltage drops below V

level. The D/A converter output evolve

FB_SKIP_IN

maximum value which corresponds to the IC

maximum on−time value – i.e. the IC minimum

accordingly to the Soft−Start counter as it is

loaded from its output data bus.

Figure 51. Soft Start Behavior

The Controller Operation during Soft−start Sequence

Evolves as Follows:

ON−time comparator reference voltage. This reference

voltage thus also increases non−linearly from initial zero

level until the level at which the current mode regulation

starts to work. The on−time of the Mupper and Mlower

switch is then defined by the ON−time comparator action

instead of the Maximum ON−time comparator. The

soft−start then continues until the regulation loop is closed

and the on−time is fully controlled by the secondary

regulator. The Soft−Start counter then continues in counting

and saturates at its maximum possible value which

corresponds to IC minimum operating frequency. The

maximum on−time fault detection system is enabled when

The Soft−Start counter is loaded by last Mupper on−time

value at the end of the dedicated startup sequence. The

ON−time counter is released and starts count−up from zero

until the value that is equal to the actual Soft−Start counter

state. The Mupper switch is active during the time when

ON−time counter counts−up. The Maximum ON−time

comparator then changes counting mode of the ON−time

comparator from count−up to count−down. A dead−time is

placed and the Mlower switch is activated till the ON−time

counter reaches zero value. The Soft−Start counter is

incremented by selected increment during corresponding

Mlower on−time period so that the following Mupper switch

on−time is prolonged automatically – the frequency thus

drops naturally. Because the operating frequency of the

controller drops and Mlower DRV signal is used as a clock

source for the Soft−start counter, the soft−start speed starts

to decrease on each (or on each N−th) Mlower driver pulse

Soft−Start counter value is equal to t

value.

TON_MAX

The previous on−time repetition feature, described above

in the ON−time modulation and feedback loop chapter, is

disabled in the beginning of soft start period. This is because

the ON−time comparator output stays high for several cycles

of soft start period – until the current mode regulation takes

over. The previous on−time repetition feature is enabled

once the current modulation starts to work fully, i.e. in the

time when the ON−time comparator output periodically

drops to low state within actual Mupper switch on−time

period. Typical startup waveform of the LLC application

driven by NCP1399 controller can be seen in Figure 52.

(where N is defined by K ) of switching cycle.

SS_INCREMENT

So we have non−linear soft−start that helps to speed up

output charging in the beginning of the soft−start operation

and reduces the output voltage slope when the output is close

to the regulation level. The output bus of the Soft−Start

counter addresses the D/A converter that defines the

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NCP1399 Series

major primary current component during light load

conditions, circulates in the resonant tank and creates power

losses in the power switches despite minimum energy

transfer to the secondary side. This is why the majority of

resonant converter controllers implement skip mode

operation under light load conditions.

The NCP1399 controller implements a proprietary skip

mode technique that assures maximum light−load efficiency

and low acoustic noise. The FB pin voltage level below

which the application enters skip mode operation is fully

user adjustable for the NCP1399A device family − via

SKIP/REM adjust pin or via IC option for the NCP1399B

device family. The skip mode operation can be initiated by

the skip comparator only during actual Mupper driver

on−time period. This technique assures defined and

synchronous transition from normal to skip mode operation.

The SKIP/REM pin voltage (NCP1399Ay) or internal

voltage level (NCP1399By) defines the FB pin voltage

threshold under which is the skip mode initiated – the

maximum operating frequency of the converter is thus

defined indirectly.

The Mlower switch is always activated for a defined

on−time period at the beginning of each skip burst to

re−charge the bootstrap capacitor and thus assure enough

charge for high side driver powering during the following

Mupper pulse. The resonant capacitor average voltage level

is maintained below Vbulk/2 level during the skip mode

operation. This technique helps to minimize power loses

during the initial Mlower MOSFET switch activation – refer

to Figure 53.

Figure 52. Application Startup with NCP1399 −

Primary Current − green, V_out− magenta

Skip Mode Operation

An LLC resonant converter efficiency reaches high values

under medium and full load conditions thanks to ZVS

operation for the primary MOSFETs and ZCS operation for

the secondary rectifiers. The light−load and no−load

efficiency however drops unacceptably when a normal

frequency modulation control technique is used. This is

because the converter operating frequency needs to be

increased quite a lot compared to nominal load operating

frequency in order to maintain regulation under light load

conditions. High operating frequency increases driving

losses in the controller and also losses in the converter power

stage. Moreover, the magnetizing current that becomes

Figure 53. The average voltage of resonant capacitor is maintained below Vbulk/2 during the skip mode operation

to reduce turn−on losses during 1st Mlower skip burst pulse

The first pulse in the skip burst is always non−ZVS

because there is no magnetizing energy in the resonant tank

that could prepare ZVS condition for lower MOSFET

switch turn−on. The reduced resonant capacitor voltage thus

helps to decrease C*V^2 losses related to the total HB line

capacitance (composed from output capacitances of the

power stage MOSFETs and stray capacitance seen by the

HB line). However, too low of a resonant capacitor voltage,

The reduced resonant capacitor average voltage

requirement imposes a specific turn−off sequence to be used

at the end of each skip burst and also during transition from

normal operation mode to skip mode– refer to Figure 54.

The Mlower driver is always activated the latest during

transition to skip mode. However, the latest Mlower driver

activation on−time is equal to 3/2 of previous Mupper pulse

width when the skip mode is entered. This technique

naturally imbalances the resonant tank so that the average

resonant capacitor voltage stays below Vbulk/2 level. – i.e.

application is prepared for optimal initialization of the

following skip burst.

st

during 1 Mlower driver pulse initiation, would result in a

too low resonant tank current at the end of the first Mlower

switch conduction period and thus a non ZVS condition for

the following Mupper switch turn−on process. This is why

a full discharge of resonant capacitor is not needed before

skip mode.

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NCP1399 Series

Figure 54. Drivers turn−off sequence during transition to skip−mode from normal operation mode

The voltage level across the resonant capacitor after the

transition to skip mode depends on several factors:

• Actual previous Mupper switch on−time − i.e. actual

operating frequency when skip mode comparator

provides skip mode operation request to the internal

logic via its output

device family) and fixed hysteresis (V

skip out level is thus given by

). The

FB_SKIP_HYST

V

+

FB_SKIP_IN

V

value – refer to Figure 55. The controller

FB_SKIP_HYST

disables drivers and enters a low consumption mode once

the FB voltage drops below V threshold. The IC

FB_SKIP_IN

operation is restarted once the

V

+

FB_SKIP_IN

V

level is exceeded on the FB pin. As

FB_SKIP_HYST

• Resonant tank components used in the application

aforementioned, the controller then activates Mlower driver

first for a predefined time (t ) to re−charge

• Actual current flowing through the resonant tank when

1st_MLOWER_SKIP

last Mlower driver pulse is initiated

the bootstrap capacitor. The first Mupper driver pulse is then

placed by the controller after DT period elapsed. The

on−time of the first Mupper pulse is dictated by the ON−time

comparator – i.e. the on−time depends on the actual FB pin

voltage and CS pin input signal. The internal FB signal is

It should be noted that the oscilloscope probe discharges the

resonant capacitor by its resistance when connected to the

HB pin! The probe discharge effect to the resonant capacitor

is obvious when no−load is applied to the converter output

and the application enters deep skip mode. This has to be

taken into account when probing HB pin and operating

application in skip mode.

artificially reduced by V

via the ramp

1st_MUPPER_SKIP

compensation block during this first Mupper driver pulse.

This method helps reduce the primary current peak and

acoustic noise during return from skip mode. The amount of

internal FB signal and thus primary peak current

compression is adjustable via IC option.

The NCP1399 detects skip mode operation via FB voltage

level. The skip comparator features an adjustable

V

threshold (externally with the NCP1399A

FB_SKIP_IN

device family or internally by IC option with the NCP1399B

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NCP1399 Series

Figure 55. NCP1399 Light−load Operating Modes versus Feedback Pin Voltage

Detail Description of the Skip Mode Operation:

b2) the second Mlower pulse with on−time longer

than previous Mupper driver pulse period is placed in

case that the ON−time comparator output is high in

the end of regular Mlower period. The second

Mlower pulse is prolonged in such case until the

ON−time comparator output gets low. This technique

ensures that the current mode operation is not lost due

to resonant capacitor voltage imbalance that naturally

occurs during burst operation. The application works

with asymmetrical duty cycle in this case.

During operation under certain load conditions in normal

PFM mode (driving the resonant tank with 50% DC

symmetry), if the load drops, then the load current is reduced

and the converter operation evolves as follows:

1. The FB voltage falls below the V

FB_SKIP_IN

threshold. This event can be detected by the system

only during the Mupper switch on−time execution.

The actual Mupper pulse on−time is stored into the

dedicated t_Mu_on−time register. The last Mlower

pulse with t_Ml_on−time = 3/2* t_Mu_on−time is

introduced by the system to finish operation and

will keep the resonant capacitor out of balance at a

voltage below 1/2 of Vbulk. The controller then

enters a low consumption mode in which all

3. The dead time is placed by the system again and

situation from point b) repeats. The b2) case

repeats in a given skip burst pulse until the duty

cycle symmetry of 50% is reached i.e. until the b1)

case is reached by the system. The asymmetrical

operation is then disabled until the new

unnecessary blocks are turned off to reduce power

consumption and the IC will waits as long as the

V

threshold crossing event, i.e. until the

FB_SKIP_IN

feedback pin voltage stays above V

+

application enters skip mode again.

FB_SKIP_IN

V

level.

4. Application continues with given skip burst until

FB_SKIP_HYST

2. The FB pin voltage rises above V

+

the V

threshold is reached on the FB

FB_SKIP_IN

V

threshold. The first Mlower period

pin. This situation is monitored during each

Mupper driver period. The dead time is then

placed by the driver followed by last Mlower

driver pulse with on−time equal to 3/2 of previous

Mupper driver period. The controller consumption

is then minimized by turning−off all the blocks

that are not needed. The skip comparator is

FB_SKIP_HYST

with pre−defined on−time width

(t ) is placed in order to recharge

1st_MLOWER_SKIP

the bootstrap capacitor. The first Mupper pulse is

then initiated after a dead−time period that lasts

until termination by the CS comparator. The

dead−time period is then followed by second

Mlower pulse which on−time period could differ

based on the actual application conditions:

b1) the second Mlower pulse with on−time equal to

previous Mupper driver pulse period is placed in

case that the ON−time comparator output is low

before end of regular Mlower period.

monitoring FB pin voltage – waiting for new skip

burst initialization.

Example of imbalanced operation during the skip mode

burst beginning can be seen in Figure 56. One can see that

the ON−time comparator output (Yelow) is high while

Mlower on−time is equal to the previous Mupper pulse

width – thus the Mlower on−time period is prolonged until

the ON−time comparator output drops.

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34

NCP1399 Series

Figure 56. The on−time comparator prolongs Mlower periods in case it output is high after previous Mupper

period is already exceeded on Mlower so imbalanced operation is placed by the system in order to keep current

mode operation working. This functionality is active until the duty cycle symmetry reaches 50%.

Fast transition to skip mode can occur when the load

current diminishes abruptly and the application is working

in full load. The frequency then quickly increases which can

result in resonant capacitor imbalance that could lead to a

loss of current mode operation – refer to Figure 57 for

illustration. This is why the NCP1399 repeats previous

Mupper on−time period in case the ON−time comparator

output does not drop low within this time period (i.e. within

the time equal to last Mupper on−time).

Figure 57. Mupper on−time repetition in case of transient loading when resonant capacitor imbalance occurs and

on−time comparator output stays high for several periods.

Summary of the NCP1399 Skip Mode System Operation:

When the load slowly diminishes and the operating

frequency of the LLC converter increases, skip mode with

wide skip bursts is naturally placed by the system first − refer

to Figure 58. The off−time between skip bursts increases and

the number of pulses in skip burst drops when load is

reducing further i.e. FB voltage starts to trigger the

V

+ V

thresholds with lower

FB_SKIP_IN

FB_SKIP_HYST

frequency. The single pulse burst operation could be reached

under no load on the output in systems with very fast

feedback loop response. The skip burst composes only from

single Mupper and two Mlower pulses in such case. The

initial Mlower pulse width of skip burst is defined by device

option and is used for bootstrap capacitor pre−charge and

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NCP1399 Series

ZVS condition preparation for following Mupper switch

1. FB voltage skip in threshold adjust

2. FB voltage skip hysteresis

3. First Mlower DRV pulse width when IC is

returning from skip mode

4. First Mupper pulse internal FB voltage reduction

factor when IC is returning from skip mode

5. Actual bulk voltage value

activation. The skip burst is always finished by the Mlower

driver pulse with period prolonged to 3/2 of previous

Mupper switch on time period in order to reduce resonant

capacitor voltage and prepare system for another skip burst

initialization.

The overall skip mode operation of the application is

affected by several factors:

Figure 58. NCP1399 Operation when Load Current Drops Down to No−load Conditions

The High Voltage Half−bridge Driver

The driver features a traditional bootstrap circuitry,

requiring an external high voltage diode with resistor in

series for the capacitor refueling path. Minimum series

resistor Rboot value is 3.3 W. Figure 59 shows the internal

architecture of the drivers section. The device incorporates

an upper UVLO circuitry that makes sure enough V is

GS

available for the upper side MOSFET.

HV

Vboot

Pulse

Trigger

Internal Mupper

Level

Shifter

S

R

Cboot

Mupper

HB

Q

dV/dt_P signal

dV/dt_N signal

dV/dt

detector

UVLO

Rboot

HB

discharger

HB disch. activation

Dboot

Vcc

Mlower

GND

aux

Vcc

Fault

Internal Mlower

Delay

Figure 59. The NCP1399 Internal DRVs Structure

The internal dV/dt sensor, connected to the VBOOT pin,

detects the HB pin voltage transitions in order to setup the

optimum DT period – please refer to Dead−Time chapter.

The internal HV discharge switch is connected to the HB pin

and discharges resonant capacitor before application

startup. The current through the switch is regulated to

As stated in the maximum ratings section, the floating

portion can go up to 620 VDC on the BOOT pin. This

voltage range makes the IC perfectly suitable for offline

applications featuring a 400 V PFC front stage.

Automatic Dead−time Adjust

The dead−time period between the Mupper and Mlower

drivers is always needed in half bridge topologies to prevent

any cross conduction through the power stage MOSFETs

that would result in excessive current, high EMI noise

I

level until the V

threshold voltage is

DISCHARGE

HB_MIN

reached on the HB pin. The discharge system assures always

the same startup conditions for application – regardless of

previous operating state.

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36

NCP1399 Series

generation or total destruction of the application. Fixed

other protections would prevent such a situation. The

NCP1399 implements maximum DT period clamp that

dead−time period is often used in the resonant converters

because this approach is simple to implement. However, this

method does not ensure optimum operating conditions in

resonant topologies because the magnetizing current is

changing with line and load conditions. The optimum

dead−time, under a given operating conditions, is equal to

the time that is needed for bridge voltage to transition

between upper and lower states and vice versa – refer to

Figure 60.

limits driver’s off−time period to the t

DEAD_TIME_MAX

value. The corresponding MOSFET driver is forced to

turn−on by the internal logic regardless of missing dV/dt

sensor signal. This situation does not occur during normal

operation and will be considered a fault state by the device.

There are several possibilities on how the controller

continues operation after this event occurrence – depending

on the IC option:

1. The opposite MOSFET switch is forced to turn−on

when t

period elapses and no

DEAD_TIME_MAX

fault is generated

2. The controller is latched−off in case the ZSV

condition is not detected within selected

t

period

DEAD_TIME_MAX

3. The controller stops operation and restarts

operation after auto−recovery period in case the

ZSV condition has not been detected within the

selected t

period

DEAD_TIME_MAX

A DT fault counter option is available. Selected number

(N ) or DT fault events have to occur in order to

DT_MAX

confirm DT fault in this case.

A fixed DT option is also available for this device. The

internal dV/dt sensor signal is not used for this device option

and the t

period is used as a regular DT

DEAD_TIME_MAX

period instead. The DT fault detection is disabled in this

case.

Figure 60. Optimum Dead−time Period Adjust

Temperature Shutdown

The NCP1399 includes

protection at 150°C. The typical TSD hysteresis is 30°C.

When the temperature rises above the upper threshold, the

controller stops switching instantaneously, and goes into the

The MOSFET body diode conduction time is minimized

when optimum dead−time period is used which results in

maximum efficiency of a resonant converter power stage.

There are several methods to determine the optimum

dead−time period or to approximate it (for example using

auxiliary winding on main transformer or modulating

dead−time period with operating frequency of the

converter). These approaches however require a dedicated

pin for nominal dead−time adjust or auxiliary winding

voltage sensing. The NCP1399 uses a dedicated method that

senses the VBOOT pin voltage internally and adjusts the

optimum dead−time period with respect to the actual

operating conditions of the converter. The high−voltage

dV/dt detector, connected to the VBOOT pin, delivers two

internal digital signals that are indicating Mupper to Mlower

and Mlower to Mupper transitions that occur on the HB and

VBOOT pins after the corresponding MOSFET switch is

turned−off. The controller enables the opposite MOSFET in

the power stage once the corresponding dV/dt sensor output

provides information about HB (or VBOOT) pin transition

ends.

a temperature shutdown

off−mode with extremely low power consumption. The V

CC

supply is maintained (by operating the HV start−up in DSS

mode) in order to memorize the TSD event information.

When the temperature falls below the lower threshold, the

full restart (including soft−start) is initiated by the controller.

The HV startup current source features an independent

over−temperature protection which limits its output current

in case the DIE temperature exceeds 150°C to avoid damage

to the HV startup silicon structure.

APPLICATION INFORMATION

Controller Operation Sequencing of NCP1399xy LLC

Controller

The paragraphs below describe controller operation

sequencing under several typical cases as well as transitions

between them. The NCP1399By version is used in the

description of most operation sequences (except last

paragraph, Figure 65 that describe NCP1399Ay version).

The main behavior of NCP1399Ay is as same as

NCP1399By version except for the off−mode behavior

(REM pin function).

The ZVS transition on the bridge pin (HB) could take a

longer time or even does not finish in some cases – for

example with extremely low bulk voltage or when some

critical failure occurs. This situation should not occur

normally in correctly designed application because several

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NCP1399 Series

1. Application start, Brown−out off and restart,

OVP/OTP latch and then restart – Figure 61

to hold the latch−up state memorized while the application

remains plugged−in to the mains.

Application is connected to the mains at point A thus the

HV input of the controller becomes biased. The HV startup

The power supply is removed from the mains at point H

and the VCC voltage drops down below V

level

CC_RESET

current source starts charged VCC capacitor until V

CC

thus the low voltage controller is released from latch. A new

application start occurs when the user plugs the application

the mains again.

reaches V

threshold.

CC_ON

The VCC pin voltage reached V

threshold in point

CC_ON

B. The BO, FB, OVP/OTP and PFC MODE blocks are

2. Application start, Brown−out off and restart, output

short fault with auto−recovery restart – Figure 62

Operating waveforms descriptions for this figure is

similar to one for Figure 61 from point A till point G – with

enabled. The REM input is internally pulled down for

t_{REM_TIMER}to assure that the secondary side will have enough

time to recover normal operation and pulls down the remote

optocoupler after the LLC stage restart. The VBULK/PFC

FB pin starts to receive divided bulk voltage as the external

HV switch is activated by PFC MODE output. The REM

one difference. The skip mode operation (FB

<

V

) blocks the IC startup after first V event

FB_SKIP_IN

CC_ON

instead of BO_fault.

timer is activated during each V

event except during

CC_ON

The LLC converter operation is stopped in point G

because the controller detects an overload condition (short

circuit event in this case as the Vout drops abruptly). The

controller disables all blocks except for the FB block and the

fault logic. The HV startup DSS operation is initiated in

order to keep enough VCC level for all internal blocks that

need to be biased. Internal auto−recovery timer counts down

the off−mode operation. The V blank is also activated

CC

during each V

event to ensure that the internal logic

CC_ON

ignores all fault inputs until the internal blocks are fully

biased and stabilized after a V event. The IC DRVs

CC_ON

were not enabled after first V blank period in this case as

CC

the voltage on VBULK/PFC FB is below V level. The IC

BO

keeps all internal blocks biased and operates in the DSS

(Dynamic Self−Supply) mode as long as the fault conditions

is still present.

the recovery delay period t

.

A−REC_TIMER

The auto−recovery restart delay period lapses at point H.

The HV startup current source is activated to recharge VCC

capacitor before a new restart.

The BO_OK condition is received (voltage on

VBULK/PFC FB reach V level) at point C. The IC

BO

The V

threshold is reached in point I and all the

CC_ON

activates the startup current source to refill VCC capacitor

in order to assure sufficient energy for a new startup. The

internal blocks are biased. The V blank, REM timer and

CC

OVP/OTP blank period are started at the same time. The

LLC converter operation is enabled, including a dedicated

startup and soft−start period. The output short circuit is

removed in between thus the Vout ramped−up and the FB

loop took over during the LLC converter soft−start period.

VCC capacitor voltage reaches V

level again and the

CC_ON

VCC blank period is started. The REM timer is activated

again on this V event as well. The DRVs are enabled

CC_ON

and the application is started after V blank period lapses

because there is no faults condition at that time.

CC

Line and also bulk voltage drops at point D so the BO_OK

signal become low (voltage on VBULK/PFC FB drops

3. Startup, skip−mode operation, low line detection

and restart into skip−mode – Figure 63

The application is plugged into the mains at point A thus

the HV input of the controller becomes biased. The HV

startup current source starts charging the VCC capacitor

below V level). The LLC DRVs are disabled as well as

BO

OVP/OTP block bias. The PFC MODE output stay high to

keep the bulk voltage divider connected, so the BO block

still monitors the bulk voltage. The controller activates the

HV startup current source into DSS mode to keep enough

VCC voltage for operation of all blocks that are active while

the IC is waiting for BO_OK condition.

until V reaches the V

threshold.

CC

CC_ON

The VCC pin voltage reaches the V

threshold at

CC_ON

point B. The BO, FB, OVP/OTP and PFC MODE blocks are

enabled. The REM input is pulled down for t to

REM_TIMER

The line voltage and thus also bulk voltage increase at

point E so the Brown−out block provide the BO_OK signal

assure that the secondary side will have enough time to

recover to normal operation and pulls down the remote

optocoupler after the LLC stage restarts. The VBULK/PFC

FB pin begins to receive divided bulk voltage as the external

once the V level is reached. The startup current source is

BO

activated after BO_OK signal is received to charge the VCC

capacitor for a new restart.

HV switch is activated by the PFC MODE output. The V

CC

The V

level is reached in point F. The OVP/OTP

CC_ON

blank period is activated during each V

events. This

CC_ON

block is biased, REM timer and the VCC blank period is

started at the same time. The controller restores operation

via the regular startup sequence and soft−start after VCC

blank period lapses since there is no fault condition detected.

The application then operates normally until the

OVP/OTP input is pulled−up at point G. The controller then

enters latch−off mode in which all blocks are disabled except

for the feedback block. The VCC management controls the

HV startup in DSS mode in order to keep enough VCC level

blank ensures that the internal logic ignores all fault inputs

until the internal blocks are fully biased and stabilized after

V

CC_ON

event. The IC DRVs are not enabled even after V

CC

blank period ends because the OVP fault condition is

present. The OVP fault condition disappears after some time

so the HV startup current source is enabled to prepare

enough V for a new startup attempt. The new V blank,

CC

OTP blank and REM timer periods are placed after the

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NCP1399 Series

V

event is detected. The controller authorizes DRVs

detected. The application then enters skip mode again as the

load current is low.

CC_ON

at point C as there are no faults conditions present after the

blank period lapses.

V

CC

5. Start−up, normal operation, transition to off−mode

operation and output re−charge in off−mode

(NCP1399By versions) – Figure 64

Application is connected to the mains at point A thus the

HV input of the controller become biased. The HV startup

The application is operating under certain load conditions

between points C and D. The load current is reduced thus the

FB loop reduces the primary controller FB pin voltage. The

PFC controller is disabled (via reduced voltage on the PFC

MODE pin to V

value) in point D when the FB pin

PFC_M_BO

current source starts charging the VCC capacitor until V

CC

voltage drops below set voltage level on P ON/OFF pin.

The load diminished further and the FB skip threshold is

reached in point E. The controller turns−off all the blocks

that are not essential for the controller operation during

skip−mode – i.e. all blocks except FB block and VCC

management. This technique is used to minimize the device

consumption when there are no driver pulses during

skip−mode operation. The output voltage then drops

naturally and the FB loop reflects this change into the

primary FB pin voltage that increases accordingly. The

auxiliary winding is refilling VCC capacitor during each

skip burst thus the controller is supplied from the application

during the skip mode operation.

The controller FB skip−out threshold is reached in point

F; the controller enables all blocks and LLC DRVs to refill

the output capacitor. The controller did not activate the HV

startup current source because there is enough voltage

present on the VCC pin during skip mode. The OTP blank

periods is activated at the beginning of the skip burst to mask

possible OTP faults.

reaches V

The VCC pin voltage reached V

threshold.

CC_ON

threshold at point

CC_ON

B. The BO, FB, OVP/OTP and PFC MODE blocks are

enabled. The REM input is pulled down for t to

ensure that the secondary side has enough time to recover

normal operation and pull down the remote optocoupler

after LLC stage restarts. The VBULK/PFC FB pin starts to

receive the divided bulk voltage as the external HV switch

is activated by the PFC MODE output. The V blank

period is activated during each V

ensures that the internal logic ignores all fault inputs until the

internal blocks is fully biased and stabilized after V

event.

REM_TIMER

CC

event. This blank

CC_ON

The IC DRVs are enabled immediately after V blank

CC

period ends as there was no fault present at that time. The

application is operating under certain load conditions

between points C and D. The load current is reduced thus the

FB loop lowers the primary controller FB pin level. The PFC

controller is disabled (via reduced voltage on the PFC

MODE pin to V

voltage drops below the set voltage level on the P ON/OFF

pin.

value) at point D when the FB pin

PFC_M_BO

Note: The VCC capacitor needs to be chosen with a value

high enough to ensure that V will not drop below the

CC

V

level during skip mode. The device would

CC_OFF

The secondary controller activates off−mode operation

thus the REM input voltage exceeds the V

otherwise restart operation via standard startup sequence in

such a case (i.e. ramp−up the V to V level first and

REM_OFF

CC

CC_ON

threshold at point E. The controller turns−off all the blocks

that are not essential for controller operation during

off−mode – i.e. all blocks including FB block and a large

portion of the VCC management. This technique is used to

minimize device consumption when there are no driver

pulses during off−mode operation. The output voltage is

then dropped naturally due to secondary controller and

resistive dividers consumption. The primary controller is

supplied from the HV startup current source that is operated

in DSS.

enable drivers afterwards) for NCP1399By version or enters

into off−mode for NCP1399Ay (refer to Figure 65).

The line voltage drops in point G, but the bulk voltage is

dropping slowly as there is nearly no consumption from the

bulk capacitor during skip mode – only some refilling bursts

are provided by the controller. The application thus

continues in skip mode operation for several skip burst

cycles.

The bulk voltage level less than V threshold is detected

BO

by the controller in point H during one of the skip burst

pulses. The controller thus disabled DRVs and enters DSS

mode of operation in which the OVP/OTP block is disabled

and the controller is waiting for BO_OK event. The PFC

The secondary controller interrupts off−mode operation

by activating a remote optocoupler and pulling down the

REM pin at point F. The controller activates HV startup

current source and recharges the VCC capacitor to prepare

MODE provides the V

voltage in this case to

PFC_M_ON

enough V voltage for new startup.

CC

allow the PFC stage to refill bulk capacitors.

The V voltage reaches V

threshold at point G

CC

CC_ON

The line voltage is increased at point I thus the controller

receives the BO_OK signal. The BO_OK signal is received

during the period in which the HV startup current source is

active and refills the VCC capacitor.

and the LLC converter starts (including soft−start)

immediately after a V blank period ends as there is no

CC

fault detected at the end of this period.

The output voltage is ramped up while the FB loop is not

This V

threshold is reached by the VCC pin at point

CC_ON

closed yet as the V

is still below regulation level. The

OUT

J. The V blank period, OVP/OTP blank and REM timer

CC

output voltage then reaches regulation level and the FB pin

voltage drops abruptly on the primary – hitting the FB

period are started at the same time. The full startup sequence

is enabled at the end of the V blank period as no fault is

CC

www.onsemi.com

39

NCP1399 Series

skip−in threshold at point H. The LLC drivers are thus

all blocks including FB block and big portion of the VCC

management. This technique is used to minimize device

consumption when there are no drive pulses during

off−mode operation. The output voltage is then dropped

naturally due to secondary controller and resistive dividers

consumption. The primary controller is supplied from the

HV startup current source that operates in DSS mode.

The secondary controller interrupts off−mode operation

by releasing the optocoupler and allowing the voltage on FB

pin to ramp−up by the internal pull−up current source at

point G. The controller activates the HV startup current

source and recharges the VCC capacitor to prepare enough

disabled by skip comparator. The FB then increased

naturally – calling for new skip burst (refer to skip mode

operation description in previous part).

Secondary controller activates the off−mode operation by

releasing the remote optocoupler while the primary

controller is operating in skip−mode. The REM pin voltage

thus increases slowly up and hit the V

threshold

REM_OFF

where the primary controller enters off−mode operation

again at point I.

6. Start−up, normal operation, transition to off−mode

operation and output re−charge in off−mode

(NCP1399Ay versions) – Figure 65

Operating waveforms descriptions for this figure are the

same as for Figure 64 from point A until point D – Please

refer to Figure 64 for details regarding operation between

these time events.

V

CC

voltage for a new startup.

The V voltage reaches V

threshold at point H

CC_ON

CC

and the LLC converter starts (including soft−start)

immediately after a V blank period ends as there is no

CC

fault detected at the end of the period.

The output voltage is ramped up while the FB loop is not

The secondary controller activates off−mode operation by

closed yet as the V

is still below regulation level. The

OUT

pulling FB pin below V

level, thus the IC goes

FB_REM_OFF

output voltage then reaches regulation level and the FB pin

voltage drops abruptly on the primary – hitting the FB

skip−in threshold at point I. The LLC drivers are thus

disabled by the skip comparator. The FB then increases

naturally – calling for new skip burst (refer to skip mode

operation description in previous text).

into skip−mode for long time at point E. The controller

turns−off all the blocks that are not essential for controller

operation during skip−mode – i.e. all blocks except FB, BO

and VCC management blocks. This technique is used to

minimize device consumption when there are no driver

pulses during skip−mode operation.

The secondary controller activates off−mode operation by

The V

drops naturally by IC consumption below

CC

pulling−down FB pin and V

voltage naturally drops

CC

V

threshold at point F – i.e. the off−mode is

CC_OFF

below V

threshold. The primary controller enters

CC_OFF

confirmed. The controller turns−off all the blocks that are

not essential for controller operation during off−mode – i.e.

off−mode operation again at point J.

www.onsemi.com

40

NCP1399 Series

Figure 61. Application Start, Brown−out Off and Restart, OVP/OTP Latch and then Restart

www.onsemi.com

41

NCP1399 Series

Figure 62. Application Start, Brown−out Off and Restart,

Output Short Fault with Auto−recovery Restart

www.onsemi.com

42

NCP1399 Series

Figure 63. Startup, Skip−mode Operation, Low Lone Detection and Restart into Skip

www.onsemi.com

43

NCP1399 Series

Figure 64. Start−up, Normal Operation, Transition to Off−mode Operation

and Output Re−charge in Off−mode – NCP1399By Version

www.onsemi.com

44

NCP1399 Series

Figure 65. Start−up, Normal Operation, Transition to Off−mode Operation

and Output Re−charge in Off−mode – NCP1399Ay Version

www.onsemi.com

45

NCP1399 Series

PACKAGE DIMENSIONS

SOIC−16 NB MISSING PINS 2 AND 13

CASE 751DU

ISSUE O

NOTE 5

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

D

A

2X

16

9

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS

OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE.

DIMENSIONS D AND E ARE DETERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING

PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.

0.10 C D

F

NOTE 4

E

E1

NOTE 6

A1

L

L2

1

8

0.20 C

SEATING

PLANE

C

MILLIMETERS

B

NOTE 5

14X b

DETAIL A

2X 4 TIPS

DIM MIN

MAX

1.75

0.25

0.49

0.25

10.00

M

0.25

C A-B D

A

A1

b

1.35

0.10

0.35

0.17

9.80

TOP VIEW

2X

c

0.10 C A-B

0.10 C

DETAIL A

D

E

6.00 BSC

0.10 C

E1

e

3.90 BSC

1.27 BSC

L

0.40

1.27

0.203 BSC

L2

e

END VIEW

A

SEATING

C

PLANE

SIDE VIEW

RECOMMENDED

SOLDERING FOOTPRINT

14X

1.52

16

1

9

7.00

8

14X

0.60

1.27

PITCH

DIMENSIONS: MILLIMETERS

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NCP1399/D

www.onsemi.com

46


型号：	NCP1399BADR2G
厂家：	ONSEMI
描述：	High Performance Current Mode Resonant Controller
文件：	总46页 (文件大小：693K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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