NCP1526 [ONSEMI]
400 mA, 1.2 V, High−Efficiency, Step−Down Converter with Low Noise Voltage Regulator Optimized for RF Module; 400毫安， 1.2 V，高效率，降压型转换器，具有低噪声稳压器优化的RF模块
| 型号： | NCP1526 |
| 厂家： | 
ONSEMI |
| 描述： | 400 mA, 1.2 V, High−Efficiency, Step−Down Converter with Low Noise Voltage Regulator Optimized for RF Module |
| 文件： | 总16页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1526
400 mA, 1.2 V,
High−Efficiency, Step−Down
Converter with Low Noise
Voltage Regulator
Optimized for RF Module
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The NCP1526 product is a monolithic integrated circuit combining
step−down PWM DC−DC converter dedicated to the portable
applications powered from one cell Li−ion or three cell Alkaline/
NiCd/NiMH batteries and a low noise output voltage regulator
dedicated to supply RF sensitive module in the portable applications.
The DC−DC converter operates with a fixed output voltage of
1.2 V and delivers up to 400 mA. It uses synchronous rectification to
increase efficiency and reduces external part count. The device also
has a built−in 3.0 MHz (nominal) oscillator which reduces
component size by allowing small inductor and capacitors. It
includes an integrated soft−start, cycle−by−cycle current limiting,
and thermal shutdown protection.
MARKING
DIAGRAM
1526
ALYWG
G
10 PIN DFN
MU SUFFIX
CASE 506AT
1526
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
The additional 2.80 V very low noise, low drop output regulator, is
available with 150 mA current capability, current limitation and
overtemperature protection.
= Pb−Free Package
(Note: Microdot may be in either location)
Finally, the NCP1526 is available in a space saving, ultra low
profile 3x3 mm 10 pin UDFN package (thickness 0.55 mm max).
PIN CONNECTIONS
Features
• Step−Down Converter
FB
EN1
VIN1
LX
− Up to 85% Efficiency
GND1
VIN2
V1
EN2
GND2
BYPASS
− Output Current Capability 400 mA
− 3.0 MHz Switching Frequency
− 1.2 V Fixed Output Voltage
− Synchronous Rectification for Higher Efficiency
• LDO Regulator
(Top View)
− 2.80 V Output Voltage
− Up to 150 mA Output Current Capability
ORDERING INFORMATION
− Very Low Noise: 45 mV
RMS
†
Device
NCP1526MUTXG
Package
Shipping
• All Pins are Fully ESD Protected
• 2.7 V to 5.5 V Input Voltage Range
• Thermal Limit Protection
UDFN−10 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• 3.0 mm x 3.0 mm x 0.55 mm UDFN Package
• This is a Pb−Free Device
Typical Applications
• Cellular Phones, Smart Phones and PDAs
• Digital Still Cameras
• MP3 Players and Portable Audio Systems
• Wireless and DSL Modems
• Portable Equipment
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 0
NCP1526/D
NCP1526
Vbattery
C1
L1
1
2
3
4
5
10
9
FB
VIN1
LX
BUCK
LDO
OFF ON
OFF ON
EN1
V
BUCK
out
GND1
VIN2
V1
8
EN2
C3
GND2
BYPASS
7
V
out
LDO
6
C2
C5
C4
Figure 1. Typical Applications Circuit
Vbattery
ILIMIT
FB
VIN1
VIN1
LX
4.7 mF
1
2
10
9
REFERENCE
VOLTAGE
V
out
2.2 mH
BUCK
1.20 V,
400 mA
EN1
PWM
CONTROL
OFF ON
OFF ON
Q1
LOGIC
CONTROL
Buck Converter
VIN1
4.7 mF
GND1
VIN2
EN2
Q2
3
4
8
7
VIN2
LOGIC
CONTROL
LDO
Thermal
Shutdown
Vbattery
GND2
4.7 mF
V
LDO
out
V1 BLOCK
2.80 V, 150 mA
BYPASS
V1
5
6
100 nF
1 mF
Figure 2. Simplified Block Diagram
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2
NCP1526
PIN FUNCTION DESCRIPTION (Pin out provided for concept purpose only and might change in the final product.)
Pin No.
Symbol
Function
Description
1
FB
Analog Input
Feedback voltage from the output of the power supply. This is the input to
the error amplifier.
2
3
4
5
EN1
EN2
Digital Input
Digital Input
Enable for DC−DC converter. This pin is active high. It is turned off by logic
LOW on this pin. Do not float this pin.
EN2 enables the LDO.A HIGH level on this pin activates the voltage
regulator. It is turned off by logic LOW on this pin. Do not float this pin.
GND2
BYPASS
Power Ground
Ground connection for the LDO section and must be connected to the
system ground.
Bypass is the bandgap reference for the LDO. This pin requires a 100 nF
bypass capacitor for low noise. This pin cannot be used for an external
source.
6
7
V1
VIN2
GND1
LX
Output Power
Power Input
This pin provides the output voltage supplied by the LDO. This pin requires
1.0 mF decoupling capacitor.
Input battery voltage to supply voltage regulator blocks. The pin requires a
4.7 mF decoupling capacitor.
8
Power Ground
Analog Output
Power Input
This pin is the GROUND reference for the DC−DC converter and the output
control. The pin must be connected to the system ground.
9
Connection from Power MOSFETs to the inductor. An output discharge
circuit sinks current from this pin.
10
VIN1
Input battery voltage to supply the analog and digital blocks of the DC−DC
converter. The pin must be decoupled to ground by a 4.7 mF ceramic
capacitor.
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3
Unit
V
Minimum Voltage All Pins
V
min
Maximum Voltage All Pins (Note 2)
Maximum Voltage EN1, EN2, FB, LX
UDFN10 Package (Note 5)
V
7.0
V
max
V
VIN + 0.3
240
V
max
R
°C/W
q
JA
Thermal Resistance, Junction−to−Air
Operating Ambient Temperature Range
Storage Temperature Range
T
−40 to 85
−55 to 150
−40 to 125
_C
_C
_C
mA
A
T
stg
Junction Operating Temperature
T
J
Latch−up Current Maximum Rating (T = 85°C) (Note 4) FB pin
Lu
"70
A
Latch−up Current Maximum Rating (T = 85°C) (Note 4) Other pins
"100
A
ESD Withstand Voltage (Note 3)
Human Body Model
Machine Model
Vesd
2.0
200
kV
V
Maximumratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T = 25°C.
A
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114.
Machine Model (MM) per JEDEC standard: JESD22−A115.
4. Latchup current maximum rating per JEDEC standard: JESD78.
5. The exposed flag shall be connected to ground.
6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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3
NCP1526
ELECTRICAL CHARACTERISTICS, DC/DC Converter (Typical values are referenced to T = +25°C, Min and Max values are
A
referenced −40°C to +85°C ambient temperature, unless otherwise noted, operating conditions V = 3.6 V, unless otherwise noted.)
IN
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
VIN1 PIN
Input Voltage Range
10
8
V
2.7
−
5.2
V
in
Quiescent Current, I = 0 mA, No Switching
I
−
−
250
550
350
−
mA
out
q ON
Quiescent Current, I = 0 mA, Oscillator Running
out
Quiescent Current, EN Low
8
I
−
−
−
0.2
2.5
100
1.5
−
mA
V
q OFF
Undervoltage Lockout (V Increase)
10
10
V
UVLO
IN
Undervoltage Lockout Hysteresis
V
−
mV
HUVLO
EN1, EN2 PIN
Positive Going Input High Voltage Threshold, EN0 Signal
2, 3
2, 3
V
1.2
−
−
−
V
V
IH
Negative Going Input High Voltage Threshold, EN0 Signal
V
−
0.4
IL
DC−DC CONVERTER SECTION
Peak Inductor Current
9
1
I
−
1000
1.2
−
mA
V
LIM
Feedback Voltage Threshold
Overtemperature
V
FB
1.164
1.236
Load Transient Response, Rise/Fall Time 1.0 ms
1.0 mA to 300 mA Load Step
1.0 mA to 400 mA Load Step
−
V
OUT
mV
−
−
30
35
−
−
Line Transient Response, I = 100 mA, 3.0 V to 3.6 V Line Step
−
−
V
V
−
"5.0
−
mVpp
%
out
OUT
Output Voltage Load Regulation
OUT
I
I
= 1.0 mA to 300 mA
= 1.0 mA to 400 mA
−
−
0.2
0.5
−
−
out
out
Output Voltage Line Regulation, I = 100 mA, V = 2.7 V to 5.2 V
−
−
9
1
1
1
1
−
V
V
−
−
0.1
5.0
−
−
%
mV
MHz
mW
mW
mA
out
IN
OUT
OUT
OSC
Output Voltage Ripple, I = 300 mA
out
Oscillator Frequency
P−Ch On−Resistance
N−Ch On−Resistance
P−Ch Leakage Current
N−Ch Leakage Current
Soft−Start Time
F
2.4
−
3.0
3.6
−
RLxH
RLxL
400
400
0.05
0.01
100
−
−
ILeakH
ILeakL
Tstart
−
−
−
−
mA
−
300
ms
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NCP1526
ELECTRICAL CHARACTERISTICS for LDO (Typical values are referenced to T = +25°C, Min and Max values are referenced
A
−40°C to +85°C ambient temperature, unless otherwise noted, operating conditions 3 V < V < 5.2 V, unless otherwise noted.)
IN
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
VIN2 PIN
Input Voltage Range
7
4
V
3
−
5.2
95
V
in
Quiescent Current On State
I
−
70
mA
q ON
VIN2 = 4.2 V, I = 0 mA
out
Quiescent Current Off State
4
I
−
0.2
−
mA
q OFF
LDO SECTION
Output Voltage, I = 0 mA to 150 mA
6
6
6
6
6
V1
2.716
150
−
2.80
−
2.884
V
out
Maximum Output Current
I
−
−
−
mA
mV
mV
dB
out
Output Voltage Line Regulation, I = 10 mA
V1
V1
10
20
out
Load Regulation, I = 1.0 mA to 150 mA, V = 3.6 V
−
out
IN
Power Supply Ripple Rejection on V1, (0.2 Vp−p),
= 1.0 mF, V = 3.6 V
PSRR
C
out
in
1.0 kHz I
100 kHz, I
= 100 mA
−
−
67
45
−
−
out1
= 100 mA
out1
Dropout Voltage, I = 150 mA
VINA−V1
−
250
−
−
150
−
mV
mA
out
Output Short Circuit Current
6
6
6
ISC
300
45
Output Noise Voltage, 100 Hz to 100 kHz, I = 10 mA, C = 1.0 mF
V
N
−
mVrms
ms
out
out
Turn ON Output Voltage, V = 3.6 V
Ton
−
80
150
in
BYPASS PIN
Output Voltage, Cby = 100 nF
5
V
BY
−
1.5
−
V
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NCP1526
TYPICAL CHARACTERISTICS
NCP1526 circuit on Figure 2, V = 3.6 V, T = 25°C, unless otherwise noted
in
A
100
90
100
90
80
70
60
50
V
in
= 2.7 V
T = −40°C
A
80
70
60
50
V
in
= 3.6 V
T = 25°C
A
T = 85°C
A
V
in
= 5.2 V
40
30
40
30
0
100
200
300
400
0
100
200
300
400
I
, OUTPUT CURRENT (mA)
I
(mA)
out
out
Figure 3. Step Down Converter Efficiency vs.
Output Current
Figure 4. Step Down Converter Efficiency vs.
Temperature Vin = 3.6 V
3.0
1.225
1.215
2.0
1.0
0
T = −40°C
T = 25°C
A
A
V
in
= 2.7 V
T = 85°C
A
V
in
= 3.6 V
−1.0
1.205
1.195
V
in
= 5.2 V
0
−2.0
−3.0
0
100
200
300
400
−50
−25
25
50
75
100
125
I
(mA)
TEMPERATURE (°C)
out
Figure 5. Step Down Converter Load
Regulation vs. Temperature Vin = 3.6 V
Figure 6. Step Down Converter Output Voltage
vs. Temperature at Iout = 100 mA
5.0
4.0
3.0
2.0
1.0
100
90
I
= 100 mA
out
T = −40°C
A
80
70
60
50
T = 25°C
A
T = 85°C
A
0
−1.0
−2.0
−3.0
40
30
−4.0
−5.0
2.7
3.2
3.7
4.2
4.7
5.2
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V , INPUT VOLTAGE (V)
in
V , INPUT VOLTAGE (V)
in
Figure 7. Step Down Converter Switching
Frequency vs. Input Voltage
Figure 8. Step Down Converter Efficiency vs.
Input Voltage at Iout = 100 mA
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NCP1526
TYPICAL CHARACTERISTICS
NCP1526 circuit on Figure 2, V = 3.6 V, T = 25°C, unless otherwise noted
in
A
2.0
1.0
0
1.0
0.5
0
I
= 400 mA
= 100 mA
out
T = −40°C
A
I
out
out
T = 85°C
A
T = 25°C
I
= 0.1 mA
A
−1.0
−2.0
−0.5
−1.0
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
V (V)
in
4.7
5.2
V , (V)
in
Figure 9. Step Down Converter Line
Regulation vs. Output Current
Figure 10. Step Down Converter Line
Regulation vs. Temperature at Iout = 100 mA
I
out
V
200 mA / Div
EN
1 V / Div
V
out
V
out
20 mV / Div
500 mV / Div
20 ms / Div
40 ms / Div
Figure 11. Step Down Converter
Soft Start Time
Figure 12. Step Down Converter Load
Transient Response
V
LX
2 V / Div
V
in
V
in
200 mV / Div
2 V / Div
V
out
V
out
10 mV / Div
10 mV / Div
I
out
200 mA / Div
10 ms / Div
100 ms / Div
Figure 13. Step Down Converter PWM Mode of
Operation
Figure 14. Step Down Converter Line Transient
Response
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NCP1526
TYPICAL CHARACTERISTICS
NCP1526 circuit on Figure 2, V = 3.6 V, T = 25°C, unless otherwise noted
in
A
1.0
0.6
1.0
0.5
T = 85°C
A
T = 25°C
A
V
in
= 3.6 V
V
= 2.7 V
= 5.2 V
in
0.2
V
in
0
T = −40°C
A
−0.2
−0.5
−1.0
−0.6
−1.0
0
50
100
150
0
30
60
90
120
150
I
, OUTPUT CURRENT (mA)
I
, (mA)
out
out
Figure 15. LDO Load Regulation
Figure 16. LDO Load Regulation vs.
Temperature
I
out
V
out
200 mA / Div
1 V / Div
V
out
EN
20 mV / Div
2 V / Div
100 ms / Div
10 ms / Div
Figure 17. LDO Turn On Time from Enable
Figure 18. LDO Load Transient Response
100
90
10,000
1,000
Band Power
100 Hz to 100 KHz: 17 mVrms
80
70
100
10
60
50
3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2
(V)
100
1,000
10,000
100,000
V
in
FREQUENCY (Hz)
Figure 19. LDO Quiescent Current vs. Input
Voltage
Figure 20. LDO Noise (DC/DC Converter Off)
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NCP1526
TYPICAL CHARACTERISTICS
NCP1526 circuit on Figure 2, V = 3.6 V, T = 25°C, unless otherwise noted
in
A
1,000
100
100
90
80
70
60
50
40
30
20
T = −40°C
A
T = 25°C
A
T = 85°C
A
10
Band Power
100 Hz to 100 KHz: 27 mVrms
10
0
1.0
100
1,000
10,000
100,000
0
30
60
90
120
150
FREQUENCY (Hz)
I
, (mA)
out
Figure 21. LDO Noise (DC/DC Converter On)
Figure 22. LDO Dropout Voltage vs. Output
Current
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
10
100
1,000
10,000
100,000 1,000,000
(Hz)
Figure 23. LDO PSRR at Iout = 100 mA, Vin = 3.6 V
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NCP1526
DC−DC OPERATION DESCRIPTION
Detailed Description
at a fixed 3.0 MHz frequency. The switching of the PMOS
Q1 is controlled by a flip−flop driven by the internal
oscillator and a comparator that compares the error signal
from an error amplifier with the PWM ramp. At the
beginning of each cycle, the main switch Q1 is turned ON
by the rising edge of the internal oscillator clock. When the
PWM ramp becomes higher than the error voltage
amplifier the PWM comparator resets the flip−flop, Q1 is
turned OFF and the synchronous switch Q2 is turned ON.
Q2 replaces the external Schottky diode to reduce the
conduction loss and improve the efficiency. To avoid
overall power loss, a certain amount of dead time is
introduced to ensure Q1 is completely turned OFF before
Q2 is being turned ON.
The NCP1526 uses a constant frequency, voltage mode
step−down architecture. Both the main (P−Channel
MOSFET) and synchronous (N−Channel MOSFET)
switches are internal.
It delivers a constant voltage from either a single Li−Ion
or three cell NiMH/NiCd battery to portable devices such
as cell phones and PDA. The output voltage accuracy is
well within 3% of the 1.20 V. The NCP1526 can source at
least 400 mA.
PWM Operating Mode
The output voltage of NCP1526 is regulated by
modulating the on−time pulse width of the main switch Q1
3.6040
3.6000
3.5960
V
in
I
PFET
400 m
200 m
0.00
400 m
300 m
200 m
I
L
I
NFET
400 m
100 m
−200 m
1.205
1.200
1.195
V
V
O
LX
3.70
1.35
−1.00
Figure 24. Waveforms During PWM Operation
Soft−Start
Cycle−by−Cycle Current Limitation
The NCP1526 uses soft−start to limit the inrush current
when the device is initially powered up or enabled.
Soft−start is implemented by gradually increasing the
reference voltage until it reaches the full reference voltage.
During startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference
voltage will switch to the regular reference voltage.
From the block diagram (Figure 2), an ILIM comparator
is used to realize cycle−by−cycle current limit protection.
The comparator compares the LX pin voltage with the
reference voltage, which is biased by a constant current. If
the inductor current reaches the limit, the ILIM comparator
detects the LX voltage falling below the reference voltage
and releases the signal to turn off the switch Q1. The
cycle−by−cycle current limit is set at 1000 mA (nom).
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NCP1526
Shutdown Mode
Due to the nature of the buck converter, the output L−C
filter must be selected to work with internal compensation.
For NCP1526, the internal compensation is internally fixed
and it is optimized for an output filter of L = 2.2ĂmH and
When the EN1 pin has a voltage applied of less than
0.4 V, the DC−DC converter block will be disabled. In
shutdown mode, the internal reference, oscillator and most
of the control circuitries are turned off. Therefore, the
typical current consumption will be 0.2 mA (typical value).
Applying a voltage above 1.2 V to EN1 pin will enable the
DC−DC converter for normal operation. The device will go
through soft−start to normal operation.
C
= 4.7ĂmF
OUT
The corner frequency is given by:
1
1
f +
c
+
+ 49.5 KHz
Ǹ
Ǹ
2p L C
out
2p 2.2 mH 4.7 mF
The device operates with inductance value between 1 mH
and maximum of 4.7 mH.
Thermal Shutdown
If the corner frequency is moved, it is recommended to
check the loop stability depending of the output ripple
voltage accepted and output current required. For lower
frequency, the stability will be increase; a larger output
capacitor value could be chosen without critical effect on
the system. On the other hand, a smaller capacitor value
increases the corner frequency and it should be critical for
the system stability. Take care to check the loop stability.
The phase margin is usually higher than 45°.
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. If the junction
temperature exceeds 160_C, the device shuts down. In this
mode switch Q1 and Q2 and the control circuits are all
turned off. The device restarts in soft−start after the
temperature drops below 135°C. This feature is provided
to prevent catastrophic failures from accidental device
overheating and it is not intended as a substitute for proper
heatsinking.
Table 2. L−C Filter Example
Undervoltage Lockout
Inductance(L)
1 mH
Output Capacitor (C
)
out
The input voltage VIN1 must reach 2.5 V (typ) before the
NCP1526 enables the DC−DC converter output to begin
the startup sequence (see soft−start section). The UVLO
threshold hysteresis is typically 100 mV.
10 mF
4.7 mF
2.2 mF
2.2 mH
4.7 mH
APPLICATION INFORMATIONS
Inductor selection
The inductor parameters directly related to device
performances are saturation current and DC resistance and
Input Capacitor Selection
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is IO, max/2.
For NCP1526, a low profile ceramic capacitor of 4.7 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to the VIN Pin.
inductance value. The inductor ripple current (DI )
L
decreases with higher inductance:
V
L f
V
out
out
sw
ǒ1 *
Ǔ
V
in
DI
L
+
DI peak to peak inductor ripple current
L
L inductor value
f
Switching frequency
sw
The Saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
DI
2
L
I
+ I )
O(MAX)
L(MAX)
Table 1. List of Input Capacitors
IL(MAX) Maximum inductor current
IO(MAX) Maximum Output current
The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3 W for good efficiency.
GRM188R60J475KE
Murata
GRM21BR71C475KA
Taiyo Yuden
TDK
JMK212BY475MG
C2012X5ROJ475KB
C1632X5ROJ475KT
Output L−C filter Design Considerations:
The NCP1526 is built in 3ĂMHz frequency and uses
voltage mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
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11
NCP1526
LDO Operation
Table 3. List of Inductors
Voltage Regulator V1
FDK
TDK
MIPW3226series
VLF3010AT series
LQ CBL2012
V1 is a 2.80 V, 3% low drop voltage regulator dedicated
to RF sensitive module. It can deliver up to 150 mA and is
totally protected against short to ground (current
limitation) and overtemperature (thermal shutdown circuit
with hysteresis).
Taiyo Yuden
DO1605−T series
LPO3008
Coil craft
The PSRR of the reference is in excess of 67 dB at
1.0 kHz. The output of the V1 requires a 1.0 mF capacitor
for stability. An additional 100 nF capacitor is necessary on
the BYPASS pin for a low output noise. If the BYPASS pin
is supporting an additional load, the stability and
performance of the V1 will be diminished. Since the input
voltage can go as low as 3.0 V, the reference output will be
affected and can drop as low as 150 mV below the input
voltage at 150 mA output current. During this low dropout,
the PSRR of the reference is reduced. V1 is active when
logic high is applied to the EN2 pin. It is turned off by a
logic low on the EN2 pin.
Output capacitor selection
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.
The output ripple voltage in PWM mode is given by:
1
sw
ǒ
) ESRǓ
out
DV
out
+ DI
L
4 f C
Table 4. List of Output Capacitors
Murata
GRM188R60J475KE
4.7 mF
Reference Bypass Capacitor Node (Bypass)
An optional 100 nF BYPASS capacitor creates a low pass
filter for LDO noise reduction. The output voltage noise is
GRM21BR71C475KA
GRM188R60OJ106ME
JMK212BY475MG
JMK212BJ106MG
10 mF
4.7 mF
10 mF
4.7 mF
45 mV
with C
= 0.1 mF and C
= 1.0 mF. If the
RMS
BYPASS
OUT
Taiyo Yuden
TDK
BYPASS pin is supporting an additional load, the stability
and performance of the NCP1526 will be diminished.
C2012X5ROJ475KB
C1632X5ROJ475KT
C2012X5ROJ106K
Current Limiting
The output voltage regulator limits the output current to
I
= 300 mA (typ). If the LDO output current exceeds I ,
SC
SC
10 mF
the output voltage drops.
OUTPUT VOLTAGE OPTIONS AVAILABLE UPON
REQUEST
Shutdown Mode
When the EN2 pin has a voltage applied of less than
0.4 V, the output voltage regulator will be disabled. In
shutdown mode, the internal reference and most of the
control circuitries are turned off. Therefore, the typical
current consumption will be 0.2 mA (typical value).
Applying a voltage above 1.2 V to EN2 pin will enable the
LDO for normal operation.
DC/DC Converter
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.5
2.7
3.0
3.3
OUTPUT VOLTAGE OPTIONS AVAILABLE UPON
REQUEST
LDO
2.5
Fixed Output Voltage (V)
2.6
2.7
2.8
Fixed Output Voltage (V)
2.85
3.0
3.1
3.3
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12
NCP1526
APPLICATION BOARD
PCB Layout Recommendations
Good PCB layout plays an important role in switching
mode power conversion. Careful PCB layout can help to
minimize ground bounce, EMI noise and unwanted
feedback that can affect the performance of the converter.
Hints suggested below can be used as a guideline in most
situations.
2. Place the power components (i.e., input capacitor,
inductor and output capacitor) as close together
as possible for best performance. All connecting
traces must be short, direct, and wide to reduce
voltage errors caused by resistive losses through
the traces.
1. Use star−ground connection to connect the IC
ground nodes and capacitor GND nodes together
at one point. Keep them as close as possible, and
then connect this to the ground plane through
several vias. This will reduce noise in the ground
plane by preventing the switching currents from
flowing through the ground plane.
3. Separate the feedback path of the output voltage
from the power path. Keep this path close to the
NCP1526 circuit. And also route it away from
noisy components. This will prevent noise from
coupling into the voltage feedback trace.
The following shows the NCP1526 demo board
schematic and layout and bill of materials:
V
battery
C1
1
2
3
4
10
9
FB
VIN1
LX
L1
BUCK
LDO
OFF ON
OFF ON
EN1
V
BUCK
out
C3
8
EN2
GND1
7
GND2
BYPASS
VIN2
V1
V
out
LDO
C2
5
6
C4
C5
Figure 25. NCP1526 Board Schematic
Figure 26. NCP1526 Board Layout
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13
NCP1526
J5
HEADER 2
2
1
EN1
V
in
V
in
T POINT A
J10
0
1
2
3
J9
en2
4.7 m C1
CON3
BNC H
U1
NCP1526
1
2
3
4
5
10
9
8
7
6
HEADER 2
1
FB
EN1
EN2
GND2
BYPASS V1
EP
VIN1
LX
GND1
2.2 mH
L1
2
V
out
1
lx
en1
en2
0
0
EN2
2
HEADER 2
VIN2
V
J6
in
T POINT A
bp
V
out
J13
1
2
3
0
1
2
J12
C5
4.7 m
11
en2
C4
4.7 m
C3
1 m
C2
100 n
J7
J8
CON3
0
BNC H
2
1
0
JUMPER1
J11
0
0
0
2
1
JUMPER1
0
0
Figure 27. Schematics
Figure 28. Board Layout (Top View)
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14
NCP1526
Figure 29. Board Layout (Bottom View)
Bill of Materials
Manufacturer
Reference
Item
Part Description
Ref
U1
PCB Footprint
UDFN
Manufacturer
ON Semiconductor
Murata
1
NCP1526
NCP1526
2
3
4
4.7 mF ceramic capacitor 6.3 V X5R
1 mF ceramic capacitor 6.3 V X5R
C1, C4, C5
C3
0805
GRM21 series
GRM21 series
GRM19 series
0805
Murata
100 nF ceramic capacitor
10 V X7R
C2
0805
Murata
6
7
SMD Inductor
L1
1605
Coilcraft
DO1605 series
SL5.08/2/90B
I/O connector, it can be plugged by
BLZ5.08/2 (Weidmüller reference)
J5, J6, J7
−
Weidmüller
8
9
Jumper Header vertical mount 3*1, 2.54 mm
Jumper connector, 400 mils
J10, J13
J8, J11
−
−
Tyco electronics/AMP
Harwin
5−826629−0
D3082−B01
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15
NCP1526
PACKAGE DIMENSIONS
10 PIN UDFN
CASE 506AT−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
B
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM
A
MIN
0.45
0.00
NOM
0.50
MAX
0.55
0.05
PIN ONE
REFERENCE
A1
A3
b
0.03
0.127 REF
0.25
0.18
2.40
1.70
0.30
2.60
1.90
D
3.00 BSC
2.50
0.15
C
2X
D2
E
3.00 BSC
1.80
E2
e
2X
0.15
C
0.50 BSC
0.19 TYP
0.40
K
L
0.30
0.50
A3
0.10
0.08
C
A
SOLDERING FOOTPRINT*
10X
C
A1
SEATING
PLANE
2.6016
C
D2
10X
8X
L
e
1
5
1.8508
3.3048
2.1746
E2
10X
10X
K
10
6
0.5651
10X
b 10X
0.5000 PITCH
0.3008
0.10
0.05
C
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1526/D
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