NCP1547MNR2G [ONSEMI]
1.5 A, 340 kHz, Low Voltage Buck Regulator with Synchronization Capability;型号: | NCP1547MNR2G |
厂家: | ONSEMI |
描述: | 1.5 A, 340 kHz, Low Voltage Buck Regulator with Synchronization Capability |
文件: | 总17页 (文件大小:349K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCP1547
1.5 A, 340 kHz, Buck
Regulator with
Synchronization Capability
The NCP1547 is a 1.5 A buck regulator IC operating at a
2
fixed−frequency of 340 kHz. The device uses the V ™ control
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architecture to provide unmatched transient response, the best overall
regulation and the simplest loop compensation for today’s high−speed
logic. The NCP1547 accommodates input voltages from 4.0 V to 40 V
and contains synchronization circuitry.
The on−chip NPN transistor is capable of providing a minimum of
1.5 A of output current, and is biased by an external “boost” capacitor
to ensure saturation, thus minimizing on−chip power dissipation.
Protection circuitry includes thermal shutdown, cycle−by−cycle
current limiting and frequency foldback.
MARKING
DIAGRAM
1
18
18
NCP1547
AWLYYWW G
G
1
18−LEAD DFN
MN SUFFIX
CASE 505
Features
2
• V Architecture Provides Ultra−Fast Transient Response, Improved
8
Regulation and Simplified Design
SOIC−8
D SUFFIX
CASE 751
P1547
ALYWE
8
• Wide Operating Range: 4 V to 40 V
• 2.0% Error Amp Reference Voltage Tolerance
1
G
1
• Switch Frequency Decrease of 4:1 in Short Circuit Conditions
Reduces Short Circuit Power Dissipation
A
= Assembly Location
WL, L
YY, Y
WW, W = Work Week
= Wafer Lot
= Year
• BOOST Lead Allows “Bootstrapped” Operation to Maximize
Efficiency
• Sync Function for Parallel Supply Operation or Noise Minimization
• Shutdown Lead Provides Power−Down Option
• 1.0 mA Quiescent Current During Power−Down
• Thermal Shutdown
• Soft−Start
• These are Pb−Free Devices
E
G
= Automotive Grade
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
Package
Shipping
NCP1547DG
SOIC−8
98 Units / Rail
(Pb−Free)
NCP1547DR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCP1547MNR2G
DFN18 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
December, 2013 − Rev. 6
NCP1547/D
NCP1547
R6
100k
D1
L1
18 mH
C1
1 mF
U1
Vout (3.3 V)
Vsw
Vin
Vin (7 V to 16 V)
SHDNB
NC
BOOST
NC
NC
NC
C5
0.1 mF
NC
NC
R3
162
D2
NC
NC
SYNC
Vc
+
C2
330 mF
C3
100 mF
+
GNDNCP1547Vfb
C4
0.1 mF
R2
100
SHDNB
SYNC
Figure 1. Application Diagram, 4.5 V − 16 V to 3.3 V @ 1.0 A Converter
MAXIMUM RATINGS*
Rating
Peak Transient Voltage (31 V Load Dump @ V = 14 V)
Value
45
Unit
V
IN
Operating Junction Temperature Range, T
−40 to 150
°C
°C
J
Lead Temperature Soldering:
Reflow: (Note 1)
260 peak
(Note 2)
Storage Temperature Range, T
ESD
−65 to +150
°C
S
(Human Body Model)
(Machine Model)
(Charge Device Model)
2.0
200
>1.0
kV
V
kV
Package Thermal Resistance
18−Lead DFN Junction−to−Ambient, R
35
100
°C/W
q
JA
SO−8 Junction−to−Ambient, R
(Note 3)
q
JA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. 60 second maximum above 183°C.
2. −5°C/0°C allowable conditions.
2
3. 1 in , 1 oz copper area used for heatsinking.
MAXIMUM RATINGS (Voltages are with respect to GND)
Pin Name
(DC)*
V
V
I
I
SINK
Max
MIN
SOURCE
V
IN
40 V
40 V
40 V
7.0 V
7.0 V
7.0 V
7.0 V
−0.3 V
−0.3 V
N/A
4.0 A
100 mA
10 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
BOOST
N/A
V
SW
−0.6 V/−1.0 V, t < 50 ns
−0.3 V
4.0 A
V
C
1.0 mA
1.0 mA
1.0 mA
1.0 mA
SHDNB
SYNC
−0.3 V
−0.3 V
V
FB
−0.3 V
*See table above for load dump.
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2
NCP1547
PACKAGE PIN DESCRIPTION
PIN SYM-
BOL
SO−8
DFN−18
FUNCTION
1
1
BOOST
The BOOST pin provides additional drive voltage to the on−chip NPN power transistor. The
resulting decrease in switch on voltage increases efficiency.
2
3
2−4
5−7
V
This pin is the main power input to the IC.
IN
V
SW
This is the connection to the emitter of the on−chip NPN power transistor and serves as the
switch output to the inductor. This pin may be subjected to negative voltages during switch off−
time. A catch diode is required to clamp the pin voltage in normal operation. This node can
stand −1.0 V for less than 50 ns during switch node flyback.
4
8
SHDNB
The shutdown pin is active low and TTL compatible. The IC goes into sleep mode, drawing less
than 1.0 mA when the pin voltage is pulled below 1.0 V.
This pin should be pulled up to V with a resistor.
CC
5
6
7
10
13
16
SYNC
GND
This pin provides the synchronization input.
Power return connection for the IC.
V
FB
The FB pin provides input to the inverting input of the error amplifier. If V is lower than 0.29 V,
the oscillator frequency is divided by four, and current limit folds back to about 1 A. These fea-
tures protect the IC under severe overcurrent or short circuit conditions.
FB
8
17
V
C
The V pin provides a connection point to the output of the error amplifier and input to the PWM
C
comparator. Driving of this pin should be avoided because on−chip test circuitry becomes active
whenever current exceeding 0.5 mA is forced into the IC.
−
−
9, 11, 12,
14, 15, 18
NC
No Connection
−
−
Exposed die attach pad. Internally connected to GND. External connection to GND is optional.
PIN CONNECTIONS
BOOST
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
NC
1
8
V
IN
V
C
BOOST
V
V
C
V
V
V
FB
IN
V
IN
FB
NC
NC
GND
NC
NC
IN
Vsw
V
SW
GND
V
V
SW
SHDNB
SYNC
SW
SHDNB
NC
SO−8
SYNC
18−Lead DFN
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3
NCP1547
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C, 4.5 V< V < 40 V; unless otherwise specified.)
J
IN
Characteristic
Test Conditions
Min
Typ
Max
Unit
Oscillator
Operating Frequency
Frequency Line Regulation
Maximum Duty Cycle
−
−
−
−
306
−
340
0.05
90
374
0.15
95
kHz
%/V
%
85
V
FB
Frequency Foldback Threshold
0.29
0.32
0.36
V
PWM Comparator
Slope Compensation Voltage
Minimum Output Pulse Width
Power Switch
Fix V DV /DT
11
22
34
mV/ms
FB,
C
ON
V
FB
to V
−
100
200
ns
SW
Current Limit
V
V
> 0.36 V
< 0.29 V
= 1.5 A, V
1.6
0.9
0.4
−
2.3
1.5
0.7
120
3.0
2.1
1.0
160
A
A
FB
Foldback Current
FB
Saturation Voltage
I
= V + 2.5 V
V
OUT
BOOST
IN
Current Limit Delay
Error Amplifier
(Note 4)
ns
Internal Reference Voltage
Reference PSRR
−
−
1.244
−
1.270
40
1.296
−
V
dB
(Note 4)
FB Input Bias Current
Output Source Current
Output Sink Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth
Open Loop Amplifier Gain
Amplifier Transconductance
Sync
−
0.02
25
0.1
35
35
1.53
60
−
mA
V
V
V
V
= 1.270 V, V = 1.0 V
15
15
1.39
5.0
−
mA
C
FB
= 1.270 V, V = 2.0 V
25
mA
C
FB
= 1.0 V
= 2.0 V
1.46
20
V
FB
FB
mV
kHz
dB
(Note 4)
(Note 4)
(Note 4)
500
70
−
−
−
6.4
−
mA/V
Sync Frequency Range
Sync Pin Bias Current
Sync Threshold Voltage
Shutdown
−
−
−
377
−
−
710
485
1.9
kHz
mA
V
V
= 5.0 V
360
1.5
SYNC
0.9
Shutdown Threshold Voltage
Thermal Shutdown
Overtemperature Trip Point
Thermal Shutdown Hysteresis
1.0
1.3
1.6
V
(Note 4)
(Note 4)
175
185
42
195
°C
°C
−
−
4. Guaranteed by design, not 100% tested in production.
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4
NCP1547
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C, 4.5 V< V < 40 V; unless otherwise specified.)
J
IN
Characteristic
Test Conditions
Min
Typ
Max
Unit
General
Quiescent Current
I
= 0 A
−
−
4.0
1.0
15
−
7.5
5.0
40
mA
mA
SW
Shutdown Quiescent Current
Boost Operating Current
Minimum Boost Voltage
Startup Voltage
V
V
= 0 V
SHDNB
BOOST
− V
= 2.5 V
6.0
−
mA/A
V
SW
(Note 5)
2.5
4.0
12
−
−
3.0
−
3.5
7.0
V
Minimum Output Current
mA
5. Guaranteed by design, not 100% tested in production.
SHDNB
SYNC
V
IN
Shutdown
Comparator
2.9 V LDO
Voltage
Regulator
+
Thermal
Shutdown
Artificial
Ramp
Oscillator
BOOST
−
+
−
1.3 V
Output
Driver
S
R
Q
V
SW
∑
+
Current
Limit Com-
parator
−
+
PWM Com-
parator
I
REF
1.46 V
SHDNB
−
−
V
FB
−
+
I
FOLDBACK
+
−
Frequency
+
GND
0.32 V
and Current
Limit Foldback
+
1.27 V
Error
−
Amplifier
V
C
Figure 2. Block Diagram
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NCP1547
APPLICATIONS INFORMATION
THEORY OF OPERATION
current of the inductor L1 and the ESR (equivalent series
resistor) of the output capacitor C1.
V2 Control
The slope compensation signal is a fixed voltage ramp
provided by the oscillator. Adding this signal eliminates
subharmonic oscillation associated with the operation at
duty cycle greater than 50%. The artificial ramp also ensures
the proper PWM function when the output ripple voltage is
inadequate. The slope compensation signal is properly sized
to serve it purposes without sacrificing the transient
response speed.
Under load and line transient, not only the ramp signal
changes, but more significantly the DC component of the
feedback voltage varies proportionally to the output voltage.
FFB path connects both signals directly to the PWM
comparator. This allows instant modulation of the duty cycle
to counteract any output voltage deviations. The transient
response time is independent of the error amplifier
bandwidth. This eliminates the delay associated with error
amplifier and greatly improves the transient response time.
The error amplifier is used here to ensure excellent DC
accuracy.
The NCP1547 buck regulator provides a high level of
integration and high operating frequencies allowing the
layout of a switch−mode power supply in a very small board
area. This device is based on the proprietary V control
architecture. V control uses the output voltage and its ripple
as the ramp signal, providing an ease of use not generally
associated with voltage or current mode control. Improved
line regulation, load regulation and very fast transient
response are also major advantages.
2
2
S1
L1
V
IN
V
O
R1
C1
Duty Cycle
D1
Buck
Controller
Slope
Comp
Oscillator
)
FFB
Error Amplifier
The NCP1547 has a transconductance error amplifier,
whose non−inverting input is connected to an Internal
Reference Voltage generated from the on−chip regulator.
Latch
R
S
R2
+
SFB
The inverting input connects to the V pin. The output of
−
FB
−
V
C
the error amplifier is made available at the V pin. A typical
C
+
V
REF
frequency compensation requires only a 0.1 mF capacitor
PWM Com-
parator
+
connected between the V pin and ground, as shown in
−
C
Error
Amplifier
Figure 1. This capacitor and error amplifier’s output
2
V
Control
resistance (approximately 8.0 MW) create a low frequency
pole to limit the bandwidth. Since V control does not
2
require a high bandwidth error amplifier, the frequency
compensation is greatly simplified.
Figure 3. Buck Converter with V2 Control.
The V pin is clamped below Output High Voltage. This
allows the regulator to recover quickly from over current or
short circuit conditions.
C
As shown in Figure 3, there are two voltage feedback
paths in V control, namely FFB(Fast Feedback) and
2
SFB(Slow Feedback). In FFB path, the feedback voltage
connects directly to the PWM comparator. This feedback
path carries the ramp signal as well as the output DC voltage.
Artificial ramp derived from the oscillator is added to the
feedback signal to improve stability. The other feedback
path, SFB, connects the feedback voltage to the error
Oscillator and Sync Feature
The on−chip oscillator is trimmed at the factory and
requires no external components for frequency control. The
high switching frequency allows smaller external
components to be used, resulting in a board area and cost
savings. The tight frequency tolerance simplifies magnetic
components selection. The switching frequency is reduced
amplifier whose output V feeds to the other input of the
C
PWM comparator. In a constant frequency mode, the
oscillator signal sets the output latch and turns on the switch
S1. This starts a new switch cycle. The ramp signal,
composed of both artificial ramp and output ripple,
to no more than 25% of the nominal value when the V pin
FB
voltage is below Frequency Foldback Threshold. In short
circuit or over−load conditions, this reduces the power
dissipation of the IC and external components.
The oscillator frequency varies with junction
temperature, as seen in the following graph.
eventually comes across the V voltage, and consequently
C
resets the latch to turn off the switch. The switch S1 will turn
on again at the beginning of the next switch cycle. In a buck
converter, the output ripple is determined by the ripple
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6
NCP1547
102.5
100
97.5
95
Power Switch and Current Limit
The collector of the built−in NPN power switch is
connected to the V pin, and the emitter to the V pin.
IN
SW
When the switch turns on, the V voltage is equal to the
SW
V
IN
minus switch Saturation Voltage. In the buck regulator,
the V
voltage swings to one diode drop below ground
SW
when the power switch turns off, and the inductor current is
commutated to the catch diode. Due to the presence of high
pulsed current, the traces connecting the V pin, inductor
SW
and diode should be kept as short as possible to minimize the
noise and radiation. For the same reason, the input capacitor
92.5
90
should be placed close to the V pin and the anode of the
IN
diode.
−40 −20
0
20 40 60 80 100 120 140
The saturation voltage of the power switch is dependent
on the switching current, as shown in Figure 7.
T , JUNCTION TEMPERATURE (°C)
J
Figure 4. Oscillator Frequency Versus Junction
Temperature
0.7
0.6
0.5
0.4
0.3
0.2
An external clock signal can sync the NCP1547 to a higher
frequency. The SYNC pin equivalent input circuit is shown
in Figure 5.
10k
33%
Sync
50k
33%
V = 11V
to 20V
Z
50k
33%
GND
0.1
0
Figure 5.
0
0.5
1.0
1.5
The rising edge of the sync pulse turns on the power
switch to start a new switching cycle, as shown in Figure 6.
There is approximately 0.5 ms delay between the rising edge
SWITCHING CURRENT (A)
Figure 7. The Saturation Voltage of the Power Switch
Increases with the Conducting Current
of the sync pulse and rising edge of the V pin voltage. The
SW
sync threshold is TTL logic compatible, and duty cycle of
the sync pulses can vary from 10% to 90%. The frequency
foldback feature is disabled during the sync mode.
The NCP1547 contains pulse−by−pulse current limiting
to protect the power switch and external components. When
the peak of the switching current reaches the Current Limit,
the power switch turns off after the Current Limit Delay. The
switch will not turn on until the next switching cycle. The
current limit threshold is independent of switching duty
cycle. The maximum load current, given by the following
formula under continuous conduction mode, is less than the
Current Limit due to the ripple current.
V (V * V )
O
IN
O
I
+ I *
LIM
O(MAX)
2(L)(V )(f )
IN
s
where:
f = switching frequency,
S
I
= current limit threshold,
LIM
V = output voltage,
O
V
IN
= input voltage,
L = inductor value.
When the regulator runs under current limit, the
subharmonic oscillation may cause low frequency
Figure 6. A NCP1547 Buck Regulator is
Synchronized to an External 443 kHz Pulse Signal
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7
NCP1547
30
25
20
15
oscillation, as shown in Figure 8. Similar to current mode
control, this oscillation occurs at the duty cycle greater than
50% and can be alleviated by using a larger inductor value.
The current limit threshold is reduced to Foldback Current
when the FB pin falls below Foldback Threshold. This
feature protects the IC and external components under the
power up or over−load conditions.
10
5
0
0
0.5
1.0
1.5
SWITCHING CURRENT (A)
Figure 9. The Boost Pin Current Includes 7.0 mA
Pre−Driver Current and Base Current when the
Switch is Turned On. The Beta Decline of the
Power Switch Further Increases the Base
Current at High Switching Current
Shutdown
The internal power switch will not turn on until the V
IN
pin rises above the Startup Voltage. This ensures no
switching will occur until adequate supply voltage is
provided to the IC. Refer to Figure 10 for the SHDNB
(shutdown−bar) pin input circuit.
Figure 8. The Regulator in Current Limit
BOOST Pin
The BOOST pin provides base driving current for the
power switch. A voltage higher than V provides required
IN
SHDNB
headroom to turn on the power switch. This in turn reduces
IC power dissipation and improves overall system
efficiency. The BOOST pin can be connected to an external
boost−strapping circuit which typically uses a 0.1 mF capacitor
and a 1N914 or 1N4148 diode, as shown in Figure 1.
When the power switch is turned on, the voltage on the
BOOST pin is equal to
V
IN
20k
33%
-
+
1.2V
V = 6V to 8V
Z
V
+ V ) V * V
IN F
BOOST
O
GND
where:
V = diode forward voltage.
Figure 10.
F
The anode of the diode can be connected to any DC
voltage as well as the regulated output voltage (Figure 1).
However, the maximum voltage on the BOOST pin shall not
exceed 40 V.
As shown in Figure 9, the BOOST pin current includes a
constant 7.0 mA pre−driver current and base current
proportional to switch conducting current. A detailed
discussion of this current is conducted in Thermal
Consideration section. A 0.1 mF capacitor is usually
adequate for maintaining the Boost pin voltage during the on
time.
The IC enters a sleep mode when the SHDNB pin is pulled
below the Shutdown Threshold Voltage. In sleep mode, the
power switch is kept open and the supply current reduces to
Shutdown Quiescent Current (1 mA typically). This pin has
an internal pull−down current. When not in use, pull this pin
up to V with a resistor (See Figure 1). A 100 kW pullup
CC
resistor will ensure safe operation from below 9 V and
during a 40 V load dump condition.
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NCP1547
Startup
minimum duty cycle by extending the switching cycle. This
During power up, the regulator tends to quickly charge up
the output capacitors to reach voltage regulation. This gives
rise to an excessive in−rush current which can be detrimental
to the inductor, IC and catch diode. In V control , the
compensation capacitor provides Soft−Start with no need
for extra pin or circuitry. During the power up, the Output
Source Current of the error amplifier charges the
compensation capacitor which forces V pin and thus output
voltage ramp up gradually. The Soft−Start duration can be
protects the IC from overheating, and also limits the power
that can be transferred to the output. The current limit
foldback effectively reduces the current stress on the
inductor and diode. When the output is shorted, the DC
current of the inductor and diode can approach the current
limit threshold. Therefore, reducing the current limit by 40%
can result in an equal percentage drop of the inductor and
diode current. The short circuit waveforms are captured in
Figure 12, and the benefit of the foldback frequency and
current limit is self−evident.
2
C
calculated by
V
C
C
I
COMP
T
+
SS
SOURCE
where:
V = V pin steady−state voltage, which is approximately
C
C
equal to error amplifier’s reference voltage.
C
COMP
= Compensation capacitor connected to the V pin
C
I
= Output Source Current of the error amplifier.
SOURCE
Using a 0.1 mF C , the calculation shows a T over
COMP SS
5.0 ms which is adequate to avoid any current stresses.
Figure 11 shows the gradual rise of the V , V and envelope
C
O
of the V during power up. There is no voltage over−shoot
SW
after the output voltage reaches the regulation. If the supply
voltage rises slower than the V pin, output voltage may
C
over−shoot.
Figure 12. In Short Circuit, the Foldback Current and
Foldback Frequency Limit the Switching Current to
Protect the IC, Inductor and Catch Diode
Thermal Considerations
A calculation of the power dissipation of the IC is always
necessary prior to the adoption of the regulator. The current
drawn by the IC includes quiescent current, pre−driver
current, and power switch base current. The quiescent
current drives the low power circuits in the IC, which
include comparators, error amplifier and other logic blocks.
Therefore, this current is independent of the switching
current and generates power equal to
W
+ V I
IN
Q
Q
where:
I = quiescent current.
Figure 11. The Power Up Transition of NCP1547
Regulator
Q
The pre−driver current is used to turn on/off the power
switch and is approximately equal to 12 mA in worst case.
During steady state operation, the IC draws this current from
the Boost pin when the power switch is on and then receives
Short Circuit
When the V
pin voltage drops below Foldback
FB
Threshold, the regulator reduces the peak current limit by
40% and switching frequency to 1/4 of the nominal
frequency. These features are designed to protect the IC and
external components during over load or short circuit
conditions. In those conditions, peak switching current is
clamped to the current limit threshold. The reduced
switching frequency significantly increases the ripple
current, and thus lowers the DC current. The short circuit can
cause the minimum duty cycle to be limited by Minimum
Output Pulse Width. The foldback frequency reduces the
it from the V pin when the switch is off. The pre−driver
IN
current always returns to the V pin. Since the pre−driver
SW
current goes out to the regulator’s output even when the
power switch is turned off, a minimum load is required to
prevent overvoltage in light load conditions. If the Boost pin
voltage is equal to V + V when the switch is on, the power
IN
O
dissipation due to pre−driver current can be calculated by
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9
NCP1547
2
Ǹ
D(1 * D)
O
V
V
I
+ I
O
RMS
W
+ 12 mA (V * V
IN
)
O
)
DRV
IN
where:
D = switching duty cycle which is equal to V /V .
I = load current.
O
The base current of a bipolar transistor is equal to collector
current divided by beta of the device. Beta of 60 is used here
to estimate the base current. The Boost pin provides the base
current when the transistor needs to be on. The power
dissipated by the IC due to this current is
O
IN
2
V
V
I
S
60
O
W
+
BASE
IN
where:
I = DC switching current.
S
When the power switch turns on, the saturation voltage
and conduction current contribute to the power loss of a
non−ideal switch. The power loss can be quantified as
V
O
W
+
I V
S SAT
SAT
V
IN
where:
Figure 13. Input Voltage Ripple in a Buck Converter
V
SAT
= saturation voltage of the power switch which is
shown in Figure 7.
To calculate the RMS current, multiply the load current
with the constant given by Figure 14 at each duty cycle. It is
a common practice to select the input capacitor with an RMS
current rating more than half the maximum load current. If
multiple capacitors are paralleled, the RMS current for each
capacitor should be the total current divided by the number
of capacitors.
The switching loss occurs when the switch experiences
both high current and voltage during each switch transition.
This regulator has a 30 ns turn−off time and associated
power loss is equal to
I
S
V
IN
W
+
30 ns f
S
S
2
The turn−on time is much shorter and thus turn−on loss is
not considered here.
0.6
The total power dissipated by the IC is sum of all the above
0.5
W
+ W ) W
) W
) W
) W
SAT S
IC
Q
DRV
BASE
0.4
The IC junction temperature can be calculated from the
ambient temperature, IC power dissipation and thermal
resistance of the package. The equation is shown as follows,
0.3
0.2
T + W R
IC
) T
A
J
qJA
Minimum Load Requirement
As pointed out in the previous section, a minimum load is
required for this regulator due to the pre−driver current
feeding the output. Placing a resistor equal to V divided by
0.1
0
O
0
0.2
0.4
0.6
0.8
1.0
12 mA should prevent any voltage overshoot at light load
conditions. Alternatively, the feedback resistors can be
valued properly to consume 12 mA current.
DUTY CYCLE
Figure 14. Input Capacitor RMS Current can be
Calculated by Multiplying Y Value with Maximum Load
Current at any Duty Cycle
COMPONENT SELECTION
Selecting the capacitor type is determined by each
design’s constraint and emphasis. The aluminum
electrolytic capacitors are widely available at lowest cost.
Their ESR and ESL (equivalent series inductor) are
relatively high. Multiple capacitors are usually paralleled to
achieve lower ESR. In addition, electrolytic capacitors
usually need to be paralleled with a ceramic capacitor for
filtering high frequency noises. The OS−CON are solid
aluminum electrolytic capacitors, and therefore has a much
lower ESR. Recently, the price of the OS−CON capacitors
has dropped significantly so that it is now feasible to use
Input Capacitor
In a buck converter, the input capacitor witnesses pulsed
current with an amplitude equal to the load current. This
pulsed current and the ESR of the input capacitors determine
the V ripple voltage, which is shown in Figure 13. For V
IN
IN
ripple, low ESR is a critical requirement for the input
capacitor selection. The pulsed input current possesses a
significant AC component, which is absorbed by the input
capacitors. The RMS current of the input capacitor can be
calculated using:
http://onsemi.com
10
NCP1547
them for some low cost designs. Electrolytic capacitors are
physically large, and not used in applications where the size,
and especially height is the major concern.
The output ripple voltage is the sum of a triangular wave
caused by ripple current flowing through ESR, and a square
wave due to ESL. Capacitive reactance is assumed to be
small compared to ESR and ESL. The peak to peak ripple
current of the inductor is:
Ceramic capacitors are now available in values over 10 mF.
Since the ceramic capacitor has low ESR and ESL, a single
ceramic capacitor can be adequate for both low frequency
and high frequency noises. The disadvantage of ceramic
capacitors are their high cost. Solid tantalum capacitors can
have low ESR and small size. However, the reliability of the
tantalum capacitor is always a concern in the application
where the capacitor may experience surge current.
V (V * V )
O
IN
O
I
+
P * P
(V )(L)(f )
IN
S
V , the output ripple due to the ESR, is equal
RIPPLE(ESR)
to the product of I
and ESR. The voltage developed
P−P
across the ESL is proportional to the di/dt of the output
capacitor. It is realized that the di/dt of the output capacitor
is the same as the di/dt of the inductor current. Therefore,
Output Capacitor
when the switch turns on, the di/dt is equal to (V − V )/L,
IN
O
In a buck converter, the requirements on the output
capacitor are not as critical as those on the input capacitor.
The current to the output capacitor comes from the inductor
and thus is triangular. In most applications, this makes the
RMS ripple current not an issue in selecting output
capacitors.
and it becomes V /L when the switch turns off. The total
O
ripple voltage induced by ESL can then be derived from
VO
L
V
IN
* V
L
V
L
O
IN
V
+ ESL( ) ) ESL(
) + ESL(
)
RIPPLE(ESL)
The total output ripple is the sum of the V
and
RIPPLE(ESR)
V
.
RIPPLE(ESL)
Figure 15. The Output Voltage Ripple Using Two 10 mF
Figure 16. The Output Voltage Ripple Using One
Ceramic Capacitors in Parallel
100 mF POSCAP Capacitor
Figure 17. The Output Voltage Ripple Using
Figure 18. The Output Voltage Ripple Using
One 100 mF OS−CON
One 100 mF Tantalum Capacitor
http://onsemi.com
11
NCP1547
Figure 15 to Figure 18 show the output ripple of a 5.0 V
The worse case of the diode average current occurs during
maximum load current and maximum input voltage. For the
diode to survive the short circuit condition, the current rating
of the diode should be equal to the Foldback Current Limit.
See Table 1 for Schottky diodes from ON Semiconductor
which are suggested for use with the NCP1547 regulator.
to 3.3 V/500 mA regulator using 22 mH inductor and various
capacitor types. At the switching frequency, the low ESR
and ESL make the ceramic capacitors behave capacitively
as shown in Figure 15. Additional paralleled ceramic
capacitors will further reduce the ripple voltage, but
inevitably increase the cost. “POSCAP”, manufactured by
SANYO, is a solid electrolytic capacitor. The anode is
sintered tantalum and the cathode is a highly conductive
polymerized organic semiconductor. TPC series, featuring
low ESR and low profile, is used in the measurement of
Figure 16. It is shown that POSCAP presents a good balance
of capacitance and ESR, compared with a ceramic capacitor.
In this application, the low ESR generates less than 5.0 mV
of ripple and the ESL is almost unnoticeable. The ESL of the
through−hole OS−CON capacitor give rise to the inductive
impedance. It is evident from Figure 17 which shows the
step rise of the output ripple on the switch turn−on and large
spike on the switch turn−off. The ESL prevents the output
capacitor from quickly charging up the parasitic capacitor of
the inductor when the switch node is pulled below ground
through the catch diode conduction. This results in the spike
associated with the falling edge of the switch node. The D
package tantalum capacitor used in Figure 18 has the same
footprint as the POSCAP, but doubles the height. The ESR
of the tantalum capacitor is apparently higher than the
POSCAP. The electrolytic and tantalum capacitors provide
a low−cost solution with compromised performance. The
reliability of the tantalum capacitor is not a serious concern
for output filtering because the output capacitor is usually
free of surge current and voltage.
Inductor Selection
When choosing inductors, one might have to consider
maximum load current, core and copper losses, component
height, output ripple, EMI, saturation and cost. Lower
inductor values are chosen to reduce the physical size of the
inductor. Higher value cuts down the ripple current, core
losses and allows more output current. For most
applications, the inductor value falls in the range between
2.2 mH and 22 mH. The saturation current ratings of the
inductor shall not exceed the I
, calculated according to
L(PK)
V (V * V )
O
IN
O
)
I
+ I
)
L(PK)
O
2(f )(L)(V
S
IN
The DC current through the inductor is equal to the load
current. The worse case occurs during maximum load
current. Check the vendor’s spec to adjust the inductor value
under current loading. Inductors can lose over 50% of
inductance when it nears saturation.
The core materials have a significant effect on inductor
performance. The ferrite core has benefits of small physical
size, and very low power dissipation. But be careful not to
operate these inductors too far beyond their maximum
ratings for peak current, as this will saturate the core.
Powered Iron cores are low cost and have a more gradual
saturation curve. The cores with an open magnetic path, such
as rod or barrel, tend to generate high magnetic field
radiation. However, they are usually cheap and small. The
cores providing a close magnetic loop, such as pot−core and
toroid, generate low electro−magnetic interference (EMI).
There are many magnetic component vendors providing
standard product lines suitable for the NCP1547. Table 2
lists three vendors, their products and contact information.
Diode Selection
The diode in the buck converter provides the inductor
current path when the power switch turns off. The peak
reverse voltage is equal to the maximum input voltage. The
peak conducting current is clamped by the current limit of
the IC. The average current can be calculated from:
I (V * V )
IN
O
O
I
+
D(AVG)
V
IN
Table 1.
Part Number
1N5817
V
(V)
I
(A)
V
(F)
(V) @ I
AVERAGE
Package
Axial Lead
Axial Lead
Axial Lead
SOD−123
SOD−123
SOD−123
SMB
BREAKDOWN
AVERAGE
20
1.0
0.45
0.55
0.6
1N5818
30
40
20
30
40
20
30
40
1.0
1.0
0.5
0.5
0.5
1.0
1.0
1.0
1N5819
MBR0520
MBR0530
MBR0540
MBRS120
MBRS130
MBRS140
0.385
0.43
0.53
0.55
0.395
0.6
SMB
SMB
http://onsemi.com
12
NCP1547
Table 2.
Vendor
Product Family
Web Site
Telephone
Coiltronics
UNI−Pac1/2: SMT, barrel
THIN−PAC: SMT, toroid, low profile
CTX: Leaded, toroid
www.coiltronics.com
(516) 241−7876
Coilcraft
Pulse
DO1608: SMT, barrel
DS/DT 1608: SMT, barrel, magnetically shielded
DO3316: SMT, barrel
DS/DT 3316: SMT, barrel, magnetically shielded
DO3308: SMT, barrel, low profile
www.coilcraft.com
www.pulseeng.com
(800) 322−2645
(619) 674−8100
−
V2 is a trademark of Switch Power, Inc.
http://onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN18 6x5, 0.5P
CASE 505−01
ISSUE D
18
DATE 17 NOV 2006
1
NOTES:
A
SCALE 2:1
D
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
B
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1 LOCATION
2X
E
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.15
C
A
A1
A3
b
D
D2
E
E2
e
K
L
0.80
0.00
2X
0.20 REF
0.18
0.30
0.15
C
TOP VIEW
SIDE VIEW
6.00 BSC
3.98
2.98
4.28
5.00 BSC
(A3)
0.10
0.08
C
C
3.28
0.50 BSC
A
18X
0.20
0.45
−−−
0.65
A1
C
GENERIC
SEATING
PLANE
MARKING DIAGRAM*
D2
e
18X L
1
1
9
XXXXXXXX
XXXXXXXX
AWLYYWW
E2
18X K
18
10
XXXXX = Specific Device Code
18X b
A
= Assembly Location
= Wafer Lot
0.10 C A
B
WL
YY
WW
G
BOTTOM VIEW
0.05
C
NOTE 3
= Year
= Work Week
= Pb−Free Package
SOLDERING FOOTPRINT
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
5.30
18X
0.75
1
0.50
PITCH
4.19
18X
0.30
3.24
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11920D
18 PIN DFN, 6X5 MM. 0.5 MM PITCH
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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TECHNICAL PUBLICATIONS:
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