NCP1566MNTXG_技术文档

DATA SHEET

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Highly Integrated

Dual-Mode Active Clamp

PWM Controller

SCALE 2:1

QFN24, 4 x 4, 0.5P

MTNTXG SUFFIX

CASE 485CW

NCP1566

The NCP1566 is a highly integrated dual−mode active−clamp PWM

controller targeting next−generation high−density, high−performance

and small to medium power level isolated dc−dc converters for use in

telecom and datacom industries. It can be configured in either voltage

mode control with input voltage feed−forward or peak current mode

control. Peak current mode control may be implemented with input

voltage feedforward as well. Adjustable adaptive overlap time

optimizes system efficiency based on input voltage and load

conditions.

MARKING DIAGRAM

1

1566

ALYWG

G

This controller integrates all the necessary control and protection

functions to implement an isolated active clamp forward or

asymmetric half−bridge converter. It integrates a high−voltage startup

bias regulator. The NCP1566 has a line undervoltage detector,

cycle−by−cycle current limiting, line voltage dependent maximum

duty ratio limit, over voltage protection, and programmable

overtemperature protection using an external thermistor. It also

includes a dual−function FLT/SD pin used for communicating the

presence of a fault but also for shutting down the controller. A

dedicated dual−function synchronization pin eases operations when

associating bricks together.

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

PIN CONNECTIONS

QFN24 (Top View)

General Features

• Support Voltage Mode Control and Peak Current Mode Control

• Line Feedforward

• Adaptive Overlap time Control for Improved Efficiency

• Integrated 120−V High Voltage Startup Circuit with Self−Supply

Operation

• Line Undervoltage Lockout (UVLO) with Adjustable Hysteresis

• Cycle by Cycle Peak Current Limiting

• Adjustable Over Power Protection

• Overcurrent Protection Based on Average Current

• Short Circuit Protection

• Programmable Maximum Duty Ratio Clamp

• Programmable Soft−Start

ORDERING INFORMATION

See detailed ordering and shipping information on page 36 of

this data sheet.

• External Over−temperature Protection Using a Thermistance

• Over Voltage Protection through a dedicated pin

• FLT/SD pin Used for Fault reporting and Shutdown Input

• Programmable Oscillator with a 1 MHz Maximum Frequency and

Synchronization Capability

• 5 V/2% Voltage Reference

• Main Switch Drive Capability of −2 A / 3 A

• Active Clamp Switch Drive Capability of −2 A / 1 A

• V Range: from 6.5 V to 20 V

cc

• This is a Pb and Halogen Free Device

1

Publication Order Number:

September, 2022 − Rev. 6

NCP1566/D

NCP1566

Typical Applications

• High−Efficiency Isolated Dc−Dc Converters

• Server Power Supplies

• 24 V and 48 V Telecom Systems

• 42 V Automotive Applications

Figure 1. Typical Application Circuit in Voltage Mode Control

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NCP1566

Figure 2. Typical Application Circuit in Current Mode Control

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3

NCP1566

OPP

OVP

Sync

OVP

V_OVP

Clock synchronizaᖝon

V_DD

UVLO

Figure 3. Functional Block Diagram

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NCP1566

Table 1. DETAILED PIN DESCRIPTION

Pin Number

Name

Function

1

RAMP

PWM modulator ramp. In voltage mode an external R−C circuit from V sets the PWM

in

Ramp slope to implement feedforward. In current mode control, the resistor of the

external R−C circuit connects to REF for ramp compensation

2

SS

Soft−start control. A 20 μA current source charges the external capacitor connected to

this pin. Duty ratio is limited during startup by comparing the voltage on this pin to a

level−shifted VSCLAMP signal. Under steady state conditions, the SS voltage is

approximately 4.5 V. Once a fault is detected the SS capacitor is discharged and the

controller is disabled

3

4

5

6

DLMT

DT

Maximum duty ratio limit. A resistor between this pin and AGND sets the maximum duty

ratio of the controller

Dead time control. An external resistor between this pin and AGND sets the overlap

time delay between OUTM and OUTA

RT

Oscillator frequency setting pin. The total external resistance connected between the

RT and AGND pins sets the internal oscillator frequency

AGND

Analog circuit ground reference. All control and timing components that connect to

AGND should have the shortest loop possible to this pin to improve noise immunity. It

should be tied to PGND at the return of the power stage

7

8

COMP

RES

Input to the pulse width modulator. An external optocoupler connected between the REF

and COMP pin sources current into an internal current mirror. The maximum duty ratio

is achieved when no current is sourced by the optocoupler. The duty cycle reduces to

zero once the source current exceeds 850 μA. The internal current mirror improves the

frequency response by reducing the ac voltage across the optocoupler transistor

Restart time control. A capacitor between this pin and AGND set the shutdown delay

and hiccup mode restart delay time. If a restart fault is detected, a pull−up current

source, I

, typically 20 μA is enabled. If the RES pin voltage, V

, exceeds

RES(SRC1)

RES

the restart threshold, V

, typically 1 V, the controller enters restart mode.

RES(TH)

I

is disabled once in restart mode and a second pull up current source,

RES(SRC1)

RES(SRC2)

RES(peak)

, typically 5 μA enabled. I

is disabled once V

reaches

RES(SRC2)

RES

V

, typically 4 V. A pull−down current source, I

, typically 5 μA, is en-

RES(SNK)

abled until VRES falls below V

typically 2 V. The controller restarts after 32

RES(valley)

V

RES

charge/discharge cycles

9

OVP

CS

When this pin is biased beyond 1.25 V, all pulses immediately stop and the controller

resumes operations after 32 V charge/discharge cycles

RES

10

Current sense input. The current sense signal is used for current−mode control,

adaptive dead time control, cycle−by−cycle current limiting, over−current protection and

short circuit protection, etc.

If the CS voltage exceeds the cycle by cycle current limit threshold, V

, typically 0.45

ILIM

V, the drive pulse is terminated. Internal leading edge blanking prevents triggering of the

cycle by cycle current limit during normal operation. A short circuit condition exists if

V

CS

exceeds the short−circuit threshold, V , typically set to 0.7 V, during two

ILIM(SC)

consecutive clock pulses. By inserting a resistor in series with the sense current

information, it is possible to create a voltage offset proportional to the input voltage and

thus affects the maximum power the converter delivers at high line

11

REF

Precision 5 V reference. Maximum output current is 12 mA. It is required to bypass the

reference with a capacitor. The recommended capacitance ranges between 0.1 to 0.47

μF

12

13

OTP

VCC

Over−temperature protection. A voltage divider containing a NTC connects to this pin

Positive input supply. This pin connects to an external capacitor for energy storage. An

internal current source, I

, supplies current from V to this pin. Once V reaches

start

in CC

V

, typically 9.5 V, the startup current source is disabled. The current source is

CC(on)

enabled once V falls below V

, typically 9.4 V, while faults are present. Once

CC(off1)

CC

faults are removed and the controller is operating, the startup current source turn−on

threshold is reduced to V , typically 7.5 V

CC(off2)

14

15

16

OUTM

PGND

OUTA

Main switch gate control. OUTM can source 2 A and sink 3 A

Ground connection for OUTM and OUTA. Tie to the power stage return with a short loop

Active clamp switch gate control. OUTA has an adjustable leading and trailing edge

overlap delay against OUTM. OUTA can source 2 A and sink 1 A

17

FLT/SD

Fault report and shutdown control. This is a dual−function bi−directional pin. This pin is

an open−collector output with a 10 kΩ internal pull−up resistance connected to REF

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NCP1566

Table 1. DETAILED PIN DESCRIPTION (continued)

Pin Number

Name

REFA

UVLO

Function

18

19

Internally connected to REF

Input voltage undervoltage detector. The input voltage is scaled down and sampled by

means of a resistor divider. The controller enters standby mode once the UVLO voltage,

V

, exceeds the standby threshold, V

, typically 0.4 V. The controller enters

UVLO

STBY

shutdown mode if V

falls below V

by the shutdown hysteresis level. The

UVLO

STBY

controller is enabled once V

exceeds the enable threshold, V

, typically 1.25

UVLO

enable

V. Hysteresis is provided by an internal pull−down current source, I

μA. The current source is disabled once the controller is enabled

, typically 20

20

SYNC

NC

This bi−directional pin is used to synchronize the controller or synchronize another

controller driven by this pin

21

22

No connect (creepage distance)

V

IN

High voltage startup circuit input. Connect the input line voltage directly to this pin to

enable the internal startup regulator. A constant current source supplies current from

this pin to the capacitor connected to the VCC pin, eliminating the need for a startup

resistor. The minimum charge current is 40 mA. The operating voltage range of the

startup circuit is 13 V to 120 V

23

24

NC

No connect (creepage distance)

VSCLAMP

Volt−second clamp. An external R−C divider from the input line generates a voltage

ramp. This ramp is compared to a voltage reference, V

, typically 1.5 V. The OUTM

SLIMIT

pulse is terminated once the ramp voltage exceeds V

, thus limiting the maximum

volt−second product of the main transformer. In voltage mode, VSCLAMP and RAMP

pins can be tied together to share one external R−C circuit

Table 2. MAXIMUM RATINGS

Rating

Symbol

Value

−0.3 to 120

70

Unit

V

High Voltage Startup Circuit Input Voltage – Continuous operation (Note 1)

High Voltage Startup Circuit Input Current

UVLO Input Voltage

V

IN

I

mA

V

−0.3 to V

CC

UVLO

OTP Input Voltage

V

OTP

−0.3 to 7

1

V

Ramp Input Voltage

V

Ramp

OVP Input Voltage

V

OVP

V

Sync Input Voltage

V

Sync

V

Ramp Peak Input Current

VSClamp Input Voltage

VSClamp Input Current

RT Input Voltage

I

A

Ramp

V

−0.3 to 7

0.5

V

SCLAMP

I

mA

V

RT

−0.3 to 7

2

RT Input Current

I

RT

mA

V

COMP Input Voltage

V

−0.3 to 5.5

1

COMP

COMP Input Current

I

mA

V

Reference Input Voltage

Reference Input Current

Supply Input Voltage

V

−0.3 to 7

20

REF

I

mA

V

−0.3 to 20

70

CC(MAX)

Supply Input Current

I

mA

V

Main Driver Maximum Voltage

Main Driver Maximum Current

V

OUTM

−0.3 to V

CC

I

2

3

A

OUTM(SRC)

OUTM(SNK)

Active Clamp Driver Maximum Voltage

V

OUTA

−0.3 to V

V

CC

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NCP1566

Table 2. MAXIMUM RATINGS (continued)

Rating

Symbol

Value

Unit

Active Clamp Driver Maximum Current

I

2

1

A

OUTA(SRC)

OUTA(SNK)

I

Current Sense Input Voltage

Current Sense Peak Input Current

Soft−Start Input Voltage

V

−0.3 to 7

0.5

V

A

CS

I

CS

V

−0.3 to 7

0.1

V

SS

Restart Input Voltage

V

RES

Restart Peak Input Current

I

A

FLT/SD Input Voltage

V

−0.3 to 7

0.1

V

FLT/SD

FLT/SD Peak Input Current

I

A

Deadtime Input Voltage

V

−0.3 to 7

2

V

DT

Maximum Duty Ratio Control Input Voltage

Maximum Duty Ratio Control Input Current

Maximum Operating Junction Temperature

Storage Temperature Range

Lead Temperature (Soldering, 10 s)

Moisture Sensitivity Level

V

DLMT

V

I

mA

_C

−

T

−40 to 150

–60 to 150

300

J

T

STG

T

L(MAX)

MSL

1

Power Dissipation (TA = 25_C, 1 Oz Cu (35 μm), 0.155 Sq Inch (100 mm2)

MNTXG Suffix, Plastic Package (QFN−24)

P

mW

D

Printed Circuit Copper Clad (Note 3)

760

131

Thermal Resistance, Junction to Ambient 1 Oz Cu (35 μm) 2−Layer 100 mm2

Printed Circuit Copper Clad (Note 3)

MNTXG Suffix, Plastic Package (QFN−24)

R

_C/W

θ

JA

Thermal Resistance, Junction to Case 2 Oz Cu (70 μm) 2−Layer 100 mm@

R

Printed Circuit Copper Clad (Note 3)

MNTXG Suffix, Plastic Package (QFN−24)

115

22

Junction to Top Psi (ψ) 1 Oz Cu (35 μm) 2−Layer 100 mm²

Printed Circuit Copper Clad (Note 3)

MNTXG Suffix, Plastic Package (QFN−24)

ψ

_C/W

V

θ

JT

JB

Junction to Board Psi (ψ), 1 Oz Cu (35 μm) 2−Layer 100 mm²

Printed Circuit Copper Clad (Note 3)

MNTXG Suffix, Plastic Package (QFN−24)

θ

5.4

ESD Capability

Human Body Model per JEDEC Standard JESD22−A114F

Charge Device Model per JEDEC Standard JESD22−C101F

2000

1500

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device contains Latch−Up protection and exceeds 100 mA per JEDEC Standard JESD78.

2. As specified for a JEDEC EIA/JESD 51.3 conductivity test. Test conditions were under natural convection of zero air flow.

3. V is the exception.

IN

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NCP1566

Table 3. ELECTRICAL CHARACTERISTICS

(C

= 0.1 μF, V = 48 V, V

= 2 V, V = 10 V, V = 0.25 V, R

= 49.9 kΩ, R = 100 kΩ, R = 15.4 kΩ, for typical values T

REF

in

UVLO

CC

CS

DLMT DT T

J

= 25 _C, for min/max values, T is – 40 _C to 125 _C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

STARTUP AND SUPPLY CIRCUITS

Supply Voltage

V

Upper Regulation Level

Lower Regulation While

Disabled

V

CC

increasing

decreasing

V

9.1

9.0

9.5

9.4

9.9

9.8

CC

CC(on)

V

CC(off1)

Lower Regulation While Enabled

Minimum Operating Voltage

Reset Voltage

V

CC

V

CC

V

CC

decreasing

V

7.3

6.2

6.1

7.5

6.5

6.4

7.7

6.8

6.7

CC(off2)

CC(MIN)

CC(reset)

V

Startup Delay

Delay from V

to Enable

t

30

–

3

125

10

μs

CC(on)

delay(start)

Delay in turning start−up source

off

V

cc

> V

t

CC(off2)

Vcc(off2)

Delay in turning start−up

V

< V

t

15

55

–

30

–

μs

mA

μA

V

cc

CC(off2)

Vcc(on2)

source on

Startup Current

V

= V

– 0.2 V,

I

start

40

–

CC

CC(on)

V

= 48 V

in

Startup Circuit Off−State

Leakage Current

V

= 120 V

I

100

15

in

Vin(off)

Minimum Startup Voltage

I

= 15 mA,

CC(on)

V

–

start

= V

in(MIN)

V

– 0.2 V

CC

Supply Current

Disabled mode current

Standby

mA

UVLO below 0.4 V

I

–

2

4

5

CC1

CC2

CC3

CC4

V

CC

= 10 V, V

= 1 V

–

CC

UVLO

COMP

f = 200 kHz,

= C = open

No Switching

V

= 10 V, I

= 850 μA

Operating Current

C

OUTM

OUTA

REFERENCE

Reference Voltage

Load Regulation

Step Load Response

I

= 0 mA

V

4.9

5.0

5.1

V

REF

I

= 0 to 10 mA

V

4.85

5.00

5.15

REF

REF(load−reg)

REF(step−reg)

I

= 5 to 10 mA,

REF

d /d = 100 mA / μs

I

t

Source Current

V

REF

= 4.75 V

I

12

–

mA

REF(MAX)

Minimum Decoupling

Capacitance

C

0.1

μF

REF(range)

Reference Undervoltage

Threshold

V

increasing

decreasing

V

4.5

4.75

V

REF

REF(UVLO)

Reference Undervoltage

Hysteresis

V

REF

V

200

mV

REF(HYS)

LINE VOLTAGE UVLO

Standby Decreasing

Enable Threshold

V

decreasing

V

0.2

1.23

0.5

18

0.3

1.25

–

0.4

1.27

1

V

UVLO

STBY

V

increasing

V

UVLO

enable

enable(delay2)

Disable Filter Delay

V

= V

– 400 mV

t

μs

μA

UVLO

enable

Pull−Down Current in Standby

Mode

V

= V

– 0.1 V

enable

< V

I

STBY

20

22

UVLO

SHDN

< V

UVLO enable

Pull−Down Resistor while I

V

UVLO

= 1.25 V

R

UVLO

22.4

32.0

41.6

kΩ

STBY

is Disabled

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NCP1566

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(C = 0.1 μF, V = 48 V, V = 2 V, V = 10 V, V = 0.25 V, R

= 49.9 kΩ, R = 100 kΩ, R = 15.4 kΩ, for typical values T

REF

in

UVLO

CC

CS

DLMT

DT

T

J

= 25 _C, for min/max values, T is – 40 _C to 125 _C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

MAIN GATE DRIVE

Rise Time (10−90%)

Fall Time (90−10%)

from 10 to 90% of V

,

t

–

8.8

6.0

17.6

12

ns

A

OUTM

OUTM(rise)

C

= 2.2 nF

OUTM

90 to 10% of V

,

t

OUTM(fall)

OUTM

C

= 2.2 nF

OUTM

Current Capability

Source

Sink

V

OUTM

= 4 V

CC

= 850 μA

I

2

3

−

OUTM

OUTM(SRC)

OUTM(SNK)

V

= 4 V, V = 7.5 V,

I

COMP

High State Voltage Offset

V

CC

− V

OUTM

, V = 8 V,

V

OUTM(offset)

–

0.2

V

OUTM

CC

C

= 2.2 nF

Low Stage Voltage

V

UVLO

= 1 V

V

OUTM(low)

ACTIVE CLAMP GATE DRIVE

Rise Time (10−90%)

from 10 to 90% of V

,

t

–

8.8

17.6

35.2

ns

A

OUTA

OUTA(rise)

C

= 2.2 nF

OUTA

Fall Time (90−10%)

90 to 10% of V

,

t

17.6

OUTA

OUTA(fall)

C

= 2.2 nF

OUTA

Current Capability

Source

Sink

V

OUTA

= 4 V

CC

I

2

1

–

OUTA

OUTA(SRC)

OUTA(SNK)

V

= 4 V, V = 7.5 V

I

High State Voltage Offset

V

CC

− V

OUTA

, V = 8 V,

V

OUTA(offset)

–

0.2

V

OUTA

CC

C

= 2.2 nF

Low Stage Voltage

V

UVLO

= 1 V

V

OUTA(low)

–

0.2

CURRENT SENSE

Average Current Limit Threshold

V

288

23

300

30

312

37

mV

ns

ILIM(ave)

Average Current Limit Leading

Edge Blanking Duration

t

ILIMAVE(LEB)

Average Current Limit

Propagation Delay

t

–

40

450

180

0

–

ns

mV

ms

μA

ns

ILIMAVE(delay)

Cycle by Cycle Current Limit

Threshold

V

ILIM

432

150

468

Over Current Timer when V

is reached

t

OVLD

ILIM

Current Sourced by CS low line

Over Power Protection

current – V = 1.4 V

CS

OVPL

OVPH

UVLO

Current Sourced by CS high line

Over Power Protection

current – V = 2.8 V

CS

90

42

–

100

55

110

68

56

721

37

56

–

UVLO

Cycle by Cycle Current Limit

Leading Edge Blanking Duration

t

ILIM(LEB)

Cycle by Cycle Current Limit

Propagation Delay

Step V to 0.7 V to OUTM

t

40

ns

CS

ILIM(delay)

falling edge, dV/dt = 20 V/μs

Short Circuit Current Limit

Threshold

V

679

23

–

700

30

mV

ns

ILIM(SC)

Short Circuit Current Limit

Leading Edge Blanking Duration

t

ILIMSC(LEB)

Short−Circuit Current Limit

Propagation Delay

Step V to 0.9 V to OUTM

t

40

ns

CS

ILIMSC(delay)

falling edge, dV/dt = 10 V/μs

Short Circuit Counter

Step V to V

+ 0.2 V

n

ILIMSC

–

2

–

CS

ILIM(SC)

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NCP1566

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(C = 0.1 μF, V = 48 V, V = 2 V, V = 10 V, V = 0.25 V, R

= 49.9 kΩ, R = 100 kΩ, R = 15.4 kΩ, for typical values T

REF

in

UVLO

CC

CS

DLMT

DT

T

J

= 25 _C, for min/max values, T is – 40 _C to 125 _C, unless otherwise noted)

J

Characteristics

CURRENT SENSE

Discharge Switch On Resistance

Conditions

Symbol

Min

Typ

Max

Unit

V

= 2 V,

R

–

35

Ω

SCLAMP

CSswitch(on)

V

= 100 mV

CS

OVERTEMPERATURE PROTECTION (OTP)

Overtemperature Detection

Threshold

V

increasing

V

1.23

10

1.25

20

1.27

30

V

OTP

OTP(TH)

Overtemperature Detection

Delay

V

= V

– 20 mV

t

OTP(delay)

μs

μA

OTP

OTP(TH)

Pull−up Current in OTP Mode

V

= V

+ 0.1 V

I

OTP

18

20

22

OTP

OTP(TH)

OVERVOLTAGE PROTECTION (OVP)

Overvoltage Detection Threshold

Time Constant to Confirmation

Hysteresis current

V

increasing

V

1.23

18

1.25

0

1.27

22

V

OVP

OVP(TH)

t

μs

μA

OVP(TH)

Active when OVP is

acknowledged

I

20

HYS

SOFT−START

Soft−Start Charge Current

Soft−Start Onset Threshold

Clamp Voltage

V

= 1.5 V to 3 V

I

18

20

1.35

0.85

–

22

μA

V

SS

V

SS(offset)

SS(clamp)

V

Discharge Switch On Resistance

Disable Threshold

V

= 100 mV

R

–

30

Ω

V

SS

SSswitch(on)

V

decreasing

V

0.4

0.5

0.6

SS

SS(disable)

RESTART

Restart Delay Threshold

Peak Voltage

V

increasing

V

0.96

3.8

1.00

4.0

1.04

4.2

V

RES

RES(TH)

V

> V

V

RES(peak)

CS

ILIMAVE

V

RES

increasing

Valley Voltage

V

RES

> V

V

I

1.9

4

2.0

5

2.1

6

V

CS

ILIMAVE

RES(valley)

RES(SNK)

V

decreasing

Discharge Current

V

< V

RES

μA

CS

ILIMAVE

V

= 100 mV

Charge Current

V

> V

,

I

18

4

20

5

22

6

CS

ILIMAVE

RES(SRC1)

= V

– 50 mV

RES

RES(valley)

V

CS

> V

,

ILIMAVE

RES(SRC2)

V

= V

+ 50 mV

RES(valley)

Restart Counter

V

> V

n

RES

32

100

–

OTP

OTP(TH)

Discharge Voltage

V

50

–

150

mV

RES(DIS)

Discharge Switch On Resistance

V

= 200 mV

R

110

Ω

RES

ESswitch(on)

FAULT REPORT AND REMOTE SHUTDOWN

Enable Threshold

V

= increasing

= decreasing

V

1.37

1.23

8.5

–

1.45

1.25

10.0

–

1.53

1.27

11.5

120

V

FLT/SD

FLT(enable)

Fault Threshold

V

faultFLT/SD

FLT/SD

Internal Pull−Up Resistor

Discharge Switch On Resistance

V

= 3 V

R

kΩ

Ω

FLT/SD

FAULT/SD

FAULTswitch(on)

R

www.onsemi.com

10

NCP1566

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(C = 0.1 μF, V = 48 V, V = 2 V, V = 10 V, V = 0.25 V, R

= 49.9 kΩ, R = 100 kΩ, R = 15.4 kΩ, for typical values T

REF

in

UVLO

CC

CS

DLMT

DT

T

J

= 25 _C, for min/max values, T is – 40 _C to 125 _C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

OSCILLATOR

Operating Frequency Range

Oscillator Frequency

f

100

–

1000

kHz

range

t

≈ 100 ns

D

R

= 42.2 kΩ, R = 69.8 kΩ,

f

186

558

200

600

214

642

T

DT

OSC1

R

= 47.5 kΩ

DLMT

t

D

≈ 75 ns

R

= 13 kΩ, R = 52.3 kΩ,

DT

T

OSC2

R

= 17 kΩ

DLMT

SYNCHRONIZATION

Sync Pin Input Voltage to “1”

level

Acknowledged high level

Acknowledged low level

V

2.8

1.4

50

3

3.4

1.8

V

syncH

Sync Pin Input Voltage to “0”

level

V

1.6

syncL

Sync Input Pulse Width

Minimum input width for

proper sync operation

t

ns

synicw

Sync Pullup Current

–

I

0.45

1.4

26

0.6

1.6

32

0.75

1.8

38

mA

syncPU

Sync Pulldown Current

syncPD

Sync Permanent Pulldown

Current

I

syncPPD

Sync Output Width

Output Pulse Width

t

130

180

32

230

50

ns

syncow

t

syncdel

Sync to Output Delay

Rising edge of sync pulse to

OUTM rising edge

MAXIMUM DUTY RATIO

Maximum Duty Ratio

Internal spec is +/− 3%,

%

V

= 1.4 V

D

76.5

47.8

80.5

50.3

84.5

52.8

UVLO

(MAX1a)

(MAX2a)

f = 200 kHz

R

= 15.4 kΩ, R = 69.8 kΩ,

T

DT

R

= 75 kΩ

DLMT

= 42.2 kΩ, R = 69.8 kΩ,

T

DT

R

= 47.5 kΩ

DLMT

f = 600 kHz

D

76.2

46.8

80.2

49.3

84.2

51.8

(MAX1b)

(MAX2b)

R

= 4.02 kΩ, R = 52.3 kΩ,

DT

T

R

= 26.1 kΩ

DLMT

R

= 13 kΩ, R = 52.3 kΩ,

DT

T

R

= 16.9 kΩ

DLMT

Minimum Duty Ratio

I

= 850 μA

D

–

0

%

COMP

(MIN)

VOLT−SECOND CLAMP

Volt Second Limit Voltage

Threshold

I

= 0 μA

V

1.44

1.50

40

1.56

60

V

COMP

SLIMIT

Volt−Second Propagation Delay

Step V

to 2 V to

t

ns

SCLAMP

VSCLAMP

OUTM falling edge,

dV/dt = 10 V/μs

VSCLAMP Switch On

Resistance

V

= 100 mV

R

I

–

45

Ω

SCLAMP

VSCLAMPswitch(

on)

VSCLAMP Input Leakage

Current

V

= 1.4 V

100

nA

SCLAMP

VSCLAMP(leak)

OVERLAP TIME DELAY

Overlap Delay Range (Note 4)

t

20

–

500

ns

D(range)

Overlap Delay from OUTA to

OUTM rising Edges

R

DT

R

= 52.3 kΩ, V = 0.4 V

t

84

112

138

150

185

587

727

140

174

187

231

734

909

DT

CS

Da

Db

R

= 52.3 kΩ, V = 50 mV

104

112

139

440

545

CS

= 69.8 kΩ, V = 0.4 V

t

CS

Dc

Dd

De

R

= 69.8 kΩ, V = 50 mV

t

DT

CS

R

= 274 kΩ, V = 0.4 V

DT

CS

R

= 274 kΩ, V = 50 mV

t

DT

CS

Df

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11

NCP1566

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(C = 0.1 μF, V = 48 V, V = 2 V, V = 10 V, V = 0.25 V, R

= 49.9 kΩ, R = 100 kΩ, R = 15.4 kΩ, for typical values T

REF

in

UVLO

CC

CS

DLMT

DT

T

J

= 25 _C, for min/max values, T is – 40 _C to 125 _C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

RAMP

PWM Propagation Delay

Step V

to 2 V to OUTM

t

40

60

ns

RAMP

PWM

falling edge, dV/dt = 10 V/μs

PWM Offset Voltage

V

1.35

–

V

Ω

PWM(offset)

Discharge Switch On Resistance

RAMP Input Leakage Current

THERMAL SHUTDOWN

Thermal Shutdown

V

= 100 mV

R

–

25

RAMP

AMPswitch(on)

V

= 1.8 V

I

–

100

nA

RAMP

RAMP(leak)

Temperature increasing

Temperature decreasing

150

–

165

20

–

_C

Thermal Shutdown Hysteresis

T

SHDN(HYS)

4. Guaranteed by Design.

5. Guaranteed by Design. Not Tested.

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12

NCP1566

V

CC(ON

)

V

)

CC(OFF2

9.82

9.72

9.62

9.52

9.42

9.32

9.22

9.12

9.02

7.66

7.61

7.56

7.51

7.46

7.41

7.36

7.31

7.26

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature (°C)

V

)

V

CC(RESET)

CC(MIN

6.64

6.54

6.44

6.34

6.24

6.14

6.04

6,74

6.64

6.54

6.44

6.34

6.24

6.14

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature (°C)

I

START

−44

−49

−54

−59

−64

−69

−74

−79

−84

−45

−20

5

30

55

80

105

130

Junction Temperature (°C)

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13

NCP1566

I

(UVLO = 0 V)

I

(V

UVLO

= 1 V)

CC1

CC2

1.8

1.3

1.8

1.3

0.8

0.3

−0.2

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

I

(200 kHz No Load)

I

(I

= 850 mA)

CC4

CC3 COMP

3.6

3.1

2.6

2.1

1.6

1.1

0.6

0.1

−0.4

4.5

3.5

2.5

1.5

0.5

−0.5

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

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14

NCP1566

V

REF

I

Vref = 4.75 V

REF(Max)

5.08

5.03

28.2

26.2

24.2

22.2

20.2

18.2

16.2

14.2

12.2

10.2

4.98

4.93

4.88

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

V

ILIM

ILIM, AVE

310.6

305.6

300.6

295.6

290.6

285.6

463.4

458.4

453.4

448.4

443.4

438.4

433.4

428.4

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

t

ILIM_LEB

ILIM(DELAY)

49.9

39.9

29.9

19.9

9.9

64.4

59.4

54.4

49.4

44.4

39.4

−0.1

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

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15

NCP1566

V

t

ILIMSC(DELAY)

ILIMSC

719.8

714.8

709.8

704.8

699.8

694.8

689.8

684.8

679.8

674.8

49.9

39.9

29.9

19.9

9.9

−0.1

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

I

F

OSC1

OTP

216

211

206

201

196

191

186

181

176

21.6

21.1

20.6

20.1

19.6

19.1

18.6

18.1

17.6

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

F

OSC2

D

(200 kHz)

MAX1a

83.7

82.7

81.7

80.7

79.7

78.7

77.7

76.7

75.7

604

594

584

574

564

554

544

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

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16

NCP1566

D

(600 kHz)

MAX1b

D

(200 kHz)

MAX2a

52.3

51.3

50.3

49.3

48.3

47.3

83.4

82.4

81.4

80.4

79.4

78.4

77.4

76.4

75.4

−45

−20

5

30

55

80

105

130

−45

−20

5

30

55

80

105

130

Junction Temperature °C

D

(600 kHz)

VS

MAX2b

Limit

1.548

1.528

1.508

1.488

1.468

1.448

1.428

51.3

50.3

49.3

48.3

47.3

46.3

−45

5

30

55

80

−45

−20

5

30

55

80

105

130

Junction Temperature °C

CS

OVP, HL

CS

OVP, LL

0.8

0.3

108

103

98

−0.3

−0.7

−1.2

93

88

−45

−20

5

30

55

80

105

130

5

30

55

80

Junction Temperature °C

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17

NCP1566

Introduction

The NCP1566 is a highly−integrated dual−mode active

clamp PWM controller targeting next−generation

high−density, high−performance and small to medium

power level isolated dc−dc converters for use in telecom and

datacom applications. Operating up to 1 MHz, the part can

be configured in either voltage mode control with input

voltage feedforward or peak−current mode control. An

adjustable adaptive overlap time between the main power

and the active clamp MOSFETs optimizes system efficiency

based on load conditions enabling higher efficiency and

greater power density solutions.

fault state or in lack of auxiliary V : in this mode, as no

external supply is present, the DSS block permanently

cc

maintains the controller supply until the auxiliary V comes

cc

back. This is the case for instance in deep DCM mode when

the part skips cycle. V can no longer be maintained

CC

(pulses are too narrow) and V collapses until it hits 7.5 V.

CC

At this point, the DSS takes over.

It is important to realize that the average current absorbed

from the high−voltage rail V in DSS mode is roughly the

IN

average current I

self−supplying the chip. As

STARTUP, AVG

such, the power dissipated by the chip in DSS mode is V

IN

This controller integrates all the necessary control and

protection functions to implement an isolated active−clamp

forward or asymmetric half−bridge converter with

synchronous rectification. It integrates a high−voltage

startup bias regulator directly connected to the dc input up

to 120 V. The NCP1566 protection features include:

× I

and can be quite high for high input

STARTUP, AVG

voltages. For this reason, it is not advised to enter in DSS

mode when the circuit operates at its maximum current

consumption. That being said, if the DSS mode is

temporarily entered while the controller skips cycles (in a

no−load situation), this is fine as long as the junction

temperature remains within the data−sheet upper limit.

Please make sure power dissipation in this mode always

respects the maximum power dissipation capability of the

controller. If the controller is supposed to operate along its

entire input voltage range, DSS mode operation must be

prevented.

• A line undervoltage detector to stop operation in case

the input rail collapses below a programmable level

• A two−threshold cycle−by−cycle current limit which

allows to detect short circuit situations but also

overload conditions on the dc−dc converter output

• A line voltage−dependent maximum duty ratio limit to

safely operate the forward transformer

A typical startup sequence commences with the charge of

the V capacitor up to the startup threshold V

typically. When V

delivers its 5 V nominal voltage.

, 9.5 V

CC(on)

cc

• A programmable over temperature protection using an

external NTC sensor

crosses 7.5 V, the reference pin

CC

• An over voltage protection (OVP) input in case of

voltage runaway

• An over power protection (OPP) scheme which reduces

the available power at high line

• An adjustable re−start time to force an auto−recovery

hiccup mode in presence of the above faults

Once this threshold is reached, the current source turns off

and the part starts its own internal initialization: it resets all

registers, charges the soft−start capacitor above 0.5 V, makes

sure all the fault inputs are cleared (FLT/SD is high, the Over

Temperature Protection (OTP) input is low and the input

voltage sensed by the UVLO input is within acceptable

limits). As the V capacitor is alone to supply the controller

CC

The part includes a dedicated pin FLT/SD for signaling the

presence of a fault condition. The pin can be used as an input

to shutdown the controller using an external signal. The

controller also features an adjustable restart time.

during this startup time, the level across its terminals falls

and eventually reaches V , typically 9.4 V, especially

CC(off1)

if some faults are still present at startup. At this point, the

current source turns back on until V reaches V

,

CC(on)

cc

again: a hiccup takes place and lasts until the part is ready to

switch, i.e. all faults are cleared. Once internal flags are

ready, an extra delay is added, t_delay(start), before the part is

actually enabled and switches. After the enable signal has

High−Voltage Startup Circuit

The NCP1566 integrates a high voltage startup circuit

accessible by the V pin. The startup circuit is rated up to

IN

a maximum voltage of 120 V. The startup regulator consists

of a constant current source that supplies current from a

high−voltage rail to the capacitor on the V pin (CV ).

been asserted, the V UVLO level drops to V

,

CC

CC(off2)

typically 7.5 V

CC

During the initialization sequence, the main power

MOSFET is not switching, OUTM is low. On the opposite,

to allow the immediate availability of the low−side

P−channel active clamp switch, its dedicated output OUTA

The startup circuit current (I ) is 40 mA minimum. The

start

internal high voltage startup circuit eliminates the need for

external startup components. In addition, this regulator

reduces no−load power and increases the system efficiency

as it uses negligible power in the normal operation mode.

The startup circuit is configured to operate in the

so−called Dynamic Self−Supply (DSS) mode in certain

is raised to V when the 9.5V threshold is reached. This is

CC

to allow the pre−charge of the P−channel charge pump

capacitor and makes it ready for operation.

While the part is enabled, the voltage on the soft−start (SS)

capacitor is slowly rising up and when it crosses the internal

1.35 V offset, OUTM starts to produce low duty ratio pulses,

driving the forward converter main power MOSFET. Please

conditions. In this DSS mode, V hiccups between two

cc

levels (9.5 and 9.4 V typically) and self supplies the IC in

lack of auxiliary supply. This mode can be briefly entered at

startup (fault clearance delay) but it is mainly activated in a

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18

NCP1566

note that while the internal enable flag is not asserted (during

current) is well below 40 mA. During this mode, the average

the initialization sequence or during a fault), the voltage on

the SS pin is clamped to 0.85 V, naturally putting the part in

ready−to−pulse mode whenever enable gets asserted.

At the end of the initialization sequence, the controller

current absorbed by the V pin is roughly the average

IN

current consumed by the part. Care must be taken to ensure

that a low current is absorbed while in the upper input

voltage range. Failure to respect this fact will damage the

controller by thermal runaway.

stops the high−voltage startup source and V drops as the

cc

auxiliary voltage did not build up yet. Before reaching the

In case an accidental overload of the DSS would occur

lower regulation threshold, V , typically 7.5 V, the

CC(off2)

(you consume too much on the V pin and the DSS cannot

cc

auxiliary winding must have appeared to take over the

maintain V ), the voltage would drop to V

,

CC

CC(MIN)

controller supply. You will size the V capacitor in that

way. If for any reason the auxiliary winding did not build up

typically 6.5 V. In this mode, the reference voltage is turned

off and the part restarts after a start−up sequence. When V

CC

cc

before V reaches 7.5 V, the current source turns back on

crosses 7.5 V again, the reference voltage is turned back on.

CC

again to maintain the controller supply in a kind of

non−regulated hysteretic mode. In this DSS mode, the

current capability is 40 mA at minimum and you have to

make sure the internal IC consumption (including driving

A typical successful start−up sequence appears in Figure 4

while it fails in Figure 5 as the current absorbed from the V

cc

is too high. In this case, the part restarts again for another

attempt.

V

CC

All cleared

Enabled

9.5 V

9.4 V

7.5 V

6.5 V

PWM

pulses

V

SS

4 V

1.35 V

0.5 V

Figure 4. A Typical Startup Sequence in which the Auxiliary Voltage Builds Up in Time

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19

NCP1566

V

CC

Too much

current for

DSS

Aux winding

does not build-up

9.5 V

9.4 V

7.5 V

6.5 V

UVLO

PWM

pulses

PWM

pulses

PWM

stops

PWM

stops

t

V

SS

Internal reset

Fault cleared

4 V

SS reset

1.35 V

1 V

0.5 V

t

Figure 5. In this Figure, the Auxiliary Voltage did not Build Up in Time, Aborting the Startup Sequence

V

CC

Aux winding

does not build-up

Aux winding

builds up

9.5 V

9.4 V

7.5 V

6.5 V

DSS takes over

for a moment.

UVLO

PWM

pulses

t

V

SS

Internal reset

Fault cleared

4 V

1.35 V

1 V

0.5 V

t

Figure 6. In this Figure, the V_CCCapacitor is Small and is Getting Help from the DSS

until the Auxiliary Voltage Eventually Takes Off

The V capacitor must be sized such that a V voltage

and the DSS is activated. This is what Figure 6 shows. DSS

CC

greater than V

is maintained while the auxiliary

takes over until V aux builds up. Again, care must be

CC(off2)

CC

supply voltage is building up. However, if the capacitance

has adversely dropped because of extreme temperatures

taken to ensure that part power dissipation remains within

acceptable limits.

conditions for instance, it can happen that V drops too fast

CC

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20

NCP1566

The operating IC bias current, I , and gate charge load

internal controller consumption, I (4 mA at 200

CC4

at the drive outputs must be considered to correctly size

kHz)

CV . To size this capacitor, you must account for the

MOSFET drive current. The average current absorbed from

CC

• The time taken by the auxiliary winding to build up is

more difficult to assess given the numerous parameters

at play: primary−side current limit, soft−start duration,

output capacitance and so on. Simulations in

worst−case give us an estimated time of 5 ms for the

auxiliary supply to reach 8 V

the V

capacitor at startup depends on the switching

CC

frequency F and the total gate charge Q as follows:

SW

G

I_DRV+ F_SWQ_G

(eq. 1)

Assume we picked a 40 nC gate−charge MOSFET

operated at 200 kHz. The average current absorbed by the

driver will be:

With these parameters on hand, the V capacitor can be

CC

evaluated:

I_DRV+ 200k 40n + 8 mA

(eq. 2)

(I_DRV) I_CC4) t_startup

12 m 1 m

(eq. 3)

+ 6 mF

CV_CC

≥

+

The capacitor value depends on several parameters:

• The allowed voltage drop before the controller activates

the DSS at 7.5 V. This drop is 2 V, from 9.5 to 7.5 V

• The current sourced by the capacitor while the auxiliary

winding is building up. It is made of (1) plus the

2

DV

A 10 μF capacitor is a possible choice. Figure 7 illustrates

a typical startup sequence.

V

CC

V

SS

= 1.3 V

9.5 V

9.4 V

ΔV = 2 V

7.5 V

6.5 V

t

startup

PWM

pulses

t

Figure 7. This Sketch Shows how the V_CCCapacitor can be Sized to Avoid Tripping the DSS Circuit at Start Up

If power dissipation is under control during start up, you

can reduce the capacitor value given by (3) and implement

the start−up scheme shown in Figure 6.

power off sequence, the OUTA pin will remain high and

follow the V as it slowly discharges. This is to avoid

CC

observing a glitch in the output voltage if OUTA would go

low at the V under−voltage lockout point. Figure 8 shows

how the output evolves with time when shutting off the

controller.

CC

Active−Clamp MOSFET Turn−off Sequence

The NCP1566 drives an external P−type MOSFET

through a capacitive link via the OUTA pin. During the

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21

NCP1566

Figure 8. When OUTA Gently Follows V_CCat Turn Off, the P−channel MOSFET

no Longer Conducts at the V_CCUVLO and the Output Voltage is Glitch−free

Line Undervoltage Detector

that keeps V

mode.

above 0.4 V, putting the part into standby

UVLO

The NCP1566 monitors the line voltage and enables the

controller when the input voltage is within the required

range. The input voltage is sampled using a resistor divider

and applied to the UVLO pin. A small bypass capacitor is

recommended for noise filtering. The UVLO input can be

used as an enable/disable function. Figure 9 shows the

UVLO detector architecture.

The controller transitions into the enable mode once

exceeds V , typically 1.25 V. Once in enable

V

UVLO

enable

mode, the controller is allowed to start if no other faults are

present. An internal pull−down current source, I

provides hysteresis. It is typically 20 μA. I

once the controller is enabled, allowing V

,

STBY

turns off

STBY

to rise above

UVLO

By monitoring the voltage on the UVLO pin, the

controller can be put in three different modes: disable,

standby and enable. The controller enters standby mode

V

by the hysteresis level set by R . The controller is

enable

1

disabled if V

falls below V , at which point

ENABLE

UVLO

I

is re−enabled creating a voltage drop on the UVLO

STBY

once the UVLO voltage, V

, exceeds the standby

pin. A maximum delay of 1 μs, t

Comparator provides noise immunity. I

while V is below V

below V

shows how the part enters the disable mode as the input

voltage collapses. It restarts 1 second later when the input

voltage comes back again.

, on the Enable

is disabled

UVLO

ENABLE(delay)

threshold, V , typically 0.4 V. The standby mode

STBY

features a 100 mV hysteresis, V

, which, added to

during power up or if V falls

STBY(HYS)

CC

CC(off2)

CC

a 1.5 μs delay, provides adequate noise immunity. In standby

after I

has been enabled. Figure 11

CC(reset)

STBY

mode, V hiccups between 9.5 and 9.4 V, the reference

CC

voltage is maintained. The FLT/SD pin is pulled low to

signal the UVLO. Figure 10 illustrates an input voltage drop

Figure 9. UVLO Block Diagram

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22

NCP1566

The resistor divider is selected such that V

exceeds

R₁) R₂

ǒ Ǔ

R₂

UVLO

(eq. 5)

V_in(min)+ V_enable

V

at the desired input voltage. Equation 4 is used to

enable

calculate the startup voltage level, V . Equation 5 is

IN(start)

A pull−down transistor and resistor combination,

used to calculate the minimum operating voltage, V

.

IN(min)

SW

and R

, ensure V is below V

UVLO ENABLE

UVLO

R₁) R₂

while I

is disabled. This prevents the controller from

STBY

(eq. 4)

ǒ Ǔ

V_in(start)+ V_enable

) R₁I_STBY

R₂

incorrectly turning on while V

settles.

UVLO

V

(t)

OUTA

V

OUTM

FLT/SD

4.5

4

V

RES

(t)

3.5

3

2.5

2

V

UVLO

(t)

32 cycles

1.5

1

0.5

stop

.

−0

9

8

7

6

5

4

V

RCC

(t)

V

REF

(t)

PWM

pulses

1−V clamp

3

2

1

V

SS

(t)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0

Figure 10. The Input Voltage is going Down and Puts the Part in Standby Mode.

It cannot Restart Prior to Cycling the RES Capacitor 32 Times

V

(t)

OUTA

V

OUTM

4

3

2

1

FLT/SD

(t)

UVLO

V

RES

(t)

0

stop

8

6

4

V

CC

(t)

V

REF

(t)

PWM pulses

0.6

PWM pulses

2

0

V

SS

(t)

0

0.2

0.4

0.8

1

1.2

1.4

1.6

1.8

Figure 11. The Part Starts Up while V_INis ok. V_INnow Decreases to 0, Shutting off the Part.

_INis Back Again Shortly After, Restarting the Part.

V

The UVLO input is also used to adjust an Over Power

Protection (OPP) current source. In a forward converter

affected by magnetizing current and propagation delay, the

maximum output current the converter can deliver at the

maximum input voltage depends on the line input level:

power is maximum at high line. To prevent output current

runaway, the NCP1566 includes the possibility to generate

a voltage offset on the CS pin proportional to the level sensed

by the UVLO pin. By injecting a current out of the CS pin,

the designer can insert a resistance in series with the sensed

voltage and calibrate the offset to his exact needs at the

highest input level. At the lowest input voltage, e.g. 36 V

(V

= 1.4 V), the current generator delivers 0 A and

UVLO

linearly increases to a maximum of 100 μA when V

reaches 2.8 V.

UVLO

Soft−start

Soft−start slowly increases the duty ratio during power up,

allowing the controller to gradually reach steady−state

operation by slowly increasing the output voltage while

reducing startup circuit stress. The duty ratio is controlled by

comparing the SS pin voltage, V , to the VSCLAMP pin

voltage, V

SS

. V

SCLAMP

is level−shifted by 1.35 V

SCLAMP

www.onsemi.com

23

NCP1566

before comparing it to V . This ensures a minimum duty

used to calculate the average primary current to modulate

the drivers overlap time and implement overcurrent

protection (OCP). It is also used for cycle by cycle peak

current limit control and detecting a short circuit condition.

Figure 12 shows the block diagram of the current limit

circuitry.

SS

ratio of 0%.

is slowly increased by charging the soft−start

V

SS

capacitor with a fixed current source, I , typically 20 μA.

SS

OUTM is disabled once the peak voltage of V

SCLAMP

exceeds V . The soft−start pin is internally grounded while

SS

a fault is present.

Current Sense

A signal proportional to the current across the main switch

is applied to the CS pin. The current sense information is

Start the fault timer

UVLO V_dd

OPP circuitry

Figure 12. The Current Limit Circuitry Implements Three Distinct Comparators.

The controller can identify three different types of

overcurrent conditions:

• Short−circuit pulse: if an abnormally−high current pulse

is detected (0.7 V) for two consecutive clockpulses, the

part shuts off and goes into restart mode. This can

happen during a winding short circuit or in presence of

a defective component in the secondary side

• Overcurrent condition: in case the converter’s output is

overloaded, the average input current will increase,

reflecting the average input power increase. The

NCP1566 averages the primary−side current sense

information and when it exceeds a certain value, a

shutdown delay starts. When this delay elapses, the part

shuts off and goes into restart mode

• Regular current pulse: in a forward converter normal

operation, the primary current is made of the reflected

inductor current to which adds the primary magnetizing

current. When the voltage image of this current exceeds

the feedback setpoint (in current mode) or the

maximum sense voltage (0.45 V typical in voltage

mode), the current pulse is terminated. When this

comparator trips, a 150 ms fault timer starts counting

and shuts the controller down upon completion if the

overload remains present

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24

NCP1566

Fault is

acknowledged

150 ms

Timer

on

elapses

off

Auto−restart

V

OUT

(t)

End of SS

End of

startup

Severe

transient

Overload

Power on

Figure 13. A Fault Timer Forces Auto−restart when the Cycle−by−cycle Current Limit is Tripped for 150 ms

An Internal leading edge blanking (LEB) circuitry masks

the current sense information before applying it to the

current monitoring circuitry. The LEB prevents unwanted

noise from terminating the drive pulses prematurely. It is

recommended to place a small RC filter close to the CS pin

blanked by the t

cycle−by−cycle comparator propagation delay, t

timer, typically 55 ns. The

ILIM(LEB)

,

ILIM(delay)

is typically 40 ns. Cycle−by−cycle peak current limit

protection is available in all operating modes. When the 0.45

V comparator toggles high, an internal error flag is asserted

and a 150 ms timer starts elapsing. As long as the 0.45 V

comparator terminates a switching cycle, the counter keeps

advancing. When the 0.45 V no longer trips (meaning the

overload is momentarily gone), the counters counts

backwards until a) it definitively resets or b) a new overload

comes back and brings it back up counting until it

completely elapses. When the counter has reached 150 ms,

all pulses are immediately stopped and an auto−restart

sequence is initiated. Figure 13 describes a typical fault

sequence.

to suppress noise. The LEB period begins once V

OUTM

reaches approximately 2 V. To improve the pin noise

immunity, an internal switch, R , discharges and

CS(switch)

holds the CS pin low at the conclusion of every cycle. The

switch is enabled while the main driver is low. The

maximum resistance of the switch, is 20 Ω..

The average information is reconstructed from the CS

information and used to determine the OCP shutdown delay.

Once the average current information, C , exceeds

S(AVG)

V

, typically 0.3 V, the 5 μA pull−down current

RES(SNK)

ILIM(AVE)

source, I

, is disabled and the 20 μA pull−up current

The short circuit comparator protects the controller during

a winding short circuit condition for instance. The

comparator terminates the drive pulse if the CS voltage

, is enabled to charge the RES capacitor.

RES(SRC1)

The average current information is blanked by the

timer, typically 30 ns. As long as an

t

exceeds V , typically 0.7 V. The short circuit current

ILIM(SC)

ILIMAVE(LEB)

overcurrent is sensed, the capacitor connected to the RES

pin continues its charge. If the overcurrent disappears, the 20

μA source stops and the capacitor discharges with the 5 μA

pull−down source. If the overcurrent comes back again, the

20 μA source takes over and lifts the capacitor voltage

towards the 1−V threshold. When it is reached, the part stops

all operations and goes into restart mode: 32 up/down

voltage cycles between 2/4 V are counted on the RES pin

before an attempt to restart occurs.

information is blanked by the t

timer, typically

ILIMSC(LEB)

30 ns. The short circuit comparator propagation delay,

, is typically 40 ns. Two consecutive short

t

ILIMSC(delay)

circuit conditions cause the controller to enter restart mode

without a shutdown delay or shutdown pulse.

Figure 14 shows simulation waveforms during a short

circuit fault. Once the overcurrent fault is detected the main

driver operates at minimum on time. At the third internal

clock cycle, the short circuit condition is confirmed and a

Cycle by cycle peak current limit protection is

implemented using the cycle−by−cycle comparator. It

restart sequence is initiated. In restart mode, V

is

CC

hiccupping between V

and V

and the soft−start

CC(on)

CC(off1)

terminates the drive pulse if the CS voltage exceeds V

,

capacitor is discharged.

ILIM

typically 0.45 V. The cycle−by−cycle current information is

www.onsemi.com

25

NCP1566

Short circuit

V

(t)

OUTA

V

OUTM

4

3

2

1

V

SS

(t)

V

RES

(t)

Beginning of the 32 cycles

−0

10

8

V

CC

(t)

V

REF

(t)

6

4

2

0

FLT/SD

1

1.05

1.1

1.15

1.2

Figure 14. A Short Circuit Occurs and Shuts Down the Part after two Consecutive Pulses

Over Power Protection

The current sense signal is generated using either a current

sense resistor or current sense transformer. In both instances,

good PCB layout practices are required to ensure correct

operation of the current sense detection circuitry. A few are

listed below:

The maximum continuous output current delivered by a

CCM−operated forward converter depends on the

maximum peak current authorized in the primary side.

However, some parameters such as input voltage,

propagation delay and magnetizing current can have an

impact on the maximum available current. In some designs,

the maximum current limit at high line (72 V) can be larger

than that at low line (36 V) and problems can arise from this

discrepancy. To prevent or limit this overpower

phenomenon, a current source is connected to the CS pin and

sources current out of the pin. This is what is shown in Figure

15.

1. The current sense filter capacitor must be placed

as close as possible to the IC and referenced to the

AGND pin

2. When using a current sense transformer both leads

of the transformer secondary should be routed to

the filter network located very close to the IC

3. Low current signals should all be connected to the

AGND net. AGND should connect to the power

ground at the return terminal of the input capacitor

4. If using a current sense resistor, the return path

should be connected to PGND and not AGND

V

DD

I

PWM

RST

V

UVLO

OPP

I

R

OPP

CS

R

SENSE

Figure 15. A Current Source Proportional to the Voltage on the UVLO Pin Creates a Variable Voltage

Offset on the Current−sense Pin

www.onsemi.com

26

NCP1566

I

OPP

V

IN

100 μA

51 kΩ

2 kΩ

19

UVLO

37 V

74 V

0 A

V

UVLO

1.4 V

2.8 V

Figure 16. The Voltage Offset on the CS Pin is Made Proportional to the UVLO Pin Level

In Figure 16, you can see the curve linking the current

source value and the UVLO level. Using the left−side

resistor values, for a 37 V input voltage, the offset current is

0 A and there is no overpower: the converter delivers its full

power. As the UVLO voltage increases, the offset current

also grows and builds an offset on the CS pin. This offset is

maximal for a 74 V input for the selected resistors.

The maximum output current an active−clamp forward

converter can deliver is difficult to analytically predict as

several parameters play a role there. If experimentally you

determine that adding a 48 mV offset on the CS pin trips the

protection at a 72 V input, then insert a resistor whose value

is 48 m / 100 μ = 480 Ω. In case you do not want any offset,

just drive the CS pin with a low resistance and the offset

disappears.

Over Voltage Protection

The circuit includes an auto−recovery over−voltage

protection pin. You have to bias the pin above 1.25 V

typically to immediately stop switching pulses and force an

auto−restart mode. At that moment, a 20 μA current source

activates and lifts the pin to provide hysteresis. At the end of

the auto−restart mode, the controller monitors the OVP pin

and if its voltage has gone back below 1.25 V, the IC resumes

operations. Figure 17 shows the internal configuration.

V

DD

V

IN

I

HYS

R

UPPPER

9

Auto

restart

R

LOWER

V

OVP

Figure 17. When the OVP Pin is Lifted above 1.25 V, the IC Immediately Enters the Auto−restart Mode

R_lower

R_lower) R_upper

When the current source is silent, the comparator will

(eq. 7)

V_OVP+ V_in2

) I_HYS(R_lowerø T_upper)

satisfy the following expression for an input voltage V

:

IN1

R_lower

R_lower) R_upper

Assume you monitor the input voltage and want to cutoff

(eq. 6)

V_OVP+ V_in1

pulses at V

= 80 V and restart for V

= 70 V. You

IN1

IN2

calculate the resistances as follows:

When the current source activates, we can use

V_in1* V_in2

superposition to obtain the second input level V at which

the fault is released:

IN2

80 * 70

20 m

(eq. 8)

R_upper

+

+ 500 kW

I_HYS

www.onsemi.com

27

NCP1566

V_OVP

V_in1* V_in2

(R

−C

) from the input line generates the

1.25

80 * 70

VSCLAMP VSCLAMP

(eq. 9)

+ 62.5 kW

R_lower+ R_upper

+ 500 k

VSCLAMP ramp to control the volt−second limit of the

converter. The slope of the ramp is proportional to the input

voltage and controls the maximum on−time during a line

voltage transition. The ramp prevents from exceeding the

maximum volt−second of the transformer by clamping the

duty ratio excursion during the transient input. As NCP1566

can be configured to operate in both voltage mode and peak

current mode control, Figure 18 and Figure 19 respectively

show the recommended clamp configuration for these

operating modes.

A small capacitor can be added between pin 9 and ground

to improve noise immunity.

Volt−Second Clamp

A volt−second clamp is an important safety feature in any

forward converter, especially active clamp type where the

duty ratio excursion can easily exceed 50%. A clamp helps

preventing magnetizing current runaway and transformer

saturation in faulty situations. An external RC divider

Figure 18. The VSCLAMP Configuration in Voltage−mode Control

Figure 19. The VSCLAMP Configuration in Peak Current−mode Control

The PWM drive pulse terminates once the VSCLAMP

ramp reaches V , typically 1.5 V. The RC divider is

The volt−second limit depends on the transformer you

have. Assume the transformer specification allows a

maximum volt−second product of 111.6 V−μs for a 200 kHz

operation (62% duty ratio max at a 36 V input voltage). It

means that maximum on−times at low and high line cannot

respectively exceed:

SLIMIT

selected such that the VSCLAMP ramp peak voltage

reaches V at the desired maximum volt−second limit.

SLIMIT

The VSCLAMP pin is pulled down by SW

at the

VSCLAMP

end of every cycle and is held low until the next drive pulse.

www.onsemi.com

28

NCP1566

V * ms_max

normalized capacitor value of 1 nF for instance. In this case,

if we consider a near−linear charging current (the series

resistor is of high value), then the necessary current will be:

111.6

36

(eq. 10)

(eq. 11)

t_on,maxLL

t

+

+ 3.1 ms

v_in,min

V * ms_max

v_in,max

111.6

76

t_on,maxHL

+ 1.47 ms

C_VSclamp

t_on,maxHL

1.5 ln

1.47 m

(eq. 12)

I_chargeu V_limi

+

+ 1.02 mA

The RC network is thus dimensioned so that the ramp hits

the 1.5 V limit in less than 1.47 μs when the input voltage is

76 V or 3.1 μs when the input is 36 V. Let us select a

A 1 mA current provides adequate noise immunity. In this

case, R

is simply obtained by:

VSclamp

t_on,max

1.47 m

R_VSclamp+ *

+ *

+ 73.74 kW

1.5

76

(eq. 13)

V_Slimit

V_in,max

_{ln ln}ǒ_{1 *}

Ǔ

_lnǒ Ǔ

C_VSclamp

It is recommended to keep R

and C

generated and compared to a regulation ramp. The on−time

terminates once the ramp exceeds the internal error voltage.

In voltage−mode control the VSCLAMP ramp signal is used

for regulation (see Figure 18). In current mode control the

sum of the current sense ramp and the voltage compensation

ramp is used for regulation.

The internal error voltage is generated by applying a

current into the COMP pin as shown in Figure 20. The

COMP current is internally mirrored with a 10−to−1 ratio.

The mirrored current pulls down on a 50−k pull−up resistor

VSCLAMP

close to the controller and away from high dv/dt signals such

as drive outputs or swinging high−voltage nodes.

C

must be connected to AGND for a reliable

VSCLAMP

operation.

Comp Input

The PWM comparator modulates the duty ratio to regulate

the output voltage. A signal proportional to the loop error

signal is applied to this pin using an optocoupler. A voltage

proportional to the error signal, V

, is internally

ERROR

from V

.

REF

PWM comp

1.35 V

Ramp

OUTM

Vref

Comp

400

50 k

Figure 20. COMP Input Architecture

Frequency

An almost constant voltage across the optocoupler is

achieved when using a current−based feedback input. This

results in a faster system response because duty ratio adjusts

without the need to charge/discharge the large optocoupler

parasitic capacitance. In the frequency domain, the

optocoupler pole is moved to a higher frequency allowing

the system to operate at a higher crossover frequency. The

COMP pin dynamic resistance is 400 Ω. This resistance does

not play a role in the loop gain but enters the picture if you

plan to place a capacitor across the COMP pin to ground.

Maximum duty ratio is achieved when the COMP current

is 0 A or when the pin is left open. A duty ratio of 0% is

achieved when the COMP current is approximately 850 μA.

The oscillator frequency, F , is set by placing a resistor,

SW

R , between the RT and AGND pins. The NCP1566 is

T

optimized for operation between 200 kHz and 1 MHz.

Equation 14 shows the relationship between F and R .

SW

T

9 DC_max*9

1.188 m )

F_sw

(eq. 14)

R_T+ *

486p

R should be placed directly across the RT and AGND

T

pins. Assuming a 200 kHz switching frequency with a 63%

max duty ratio, then R should be:

T

9 0.63*9

1.188 m )

200 k

R_T+ *

+ 31.8 kW

(eq. 15)

486p

www.onsemi.com

29

NCP1566

Maximum Duty Ratio

Synchronization

The maximum duty ratio of the oscillator is set by placing

a resistor, R , between the DLMT and AGND pins. The

adjustable duty ratio range is between 50 and 80%. The

maximum duty ratio accuracy is 3%. The resistor that sets

the maximum duty ratio depends on the timing resistance

calculated in (14). It depends on the timing resistance but

The NCP1566 offers a bi−directional synchronization pin

which allows either controlling another switching controller

or be controlled by an external clock signal. When operating

in standalone, the SYNC pin delivers narrow pulses of 150

ns width and a 3 V minimum amplitude. When driving

another controller, the master frequency must be higher than

the slave frequency, typically by a maximum of 20%. The

closer frequencies are the faster synchronization occurs.

When connected to another controller, the master delivers a

first 600 μA pull−up pulse (0 to 1 transition) followed 150

ns later by a second 150 ns 1.2 mA pull−down pulse. The rest

of the time, the pin maintains 0 V through a 30 μA

pull−down. Please note that the synchronization operation

respects the maximum duty ratio and volt−second set by the

slave controller. In applications where synchronization is

not needed, the SYNC pin can be safely grounded to the

closest controller quiet ground.

DLMT

also on an overlap delay, t . The overlap time (t ) between

D1

OUTA and OUTM reduces the effective duty ratio of

OUTM. Please look in the electrical characteristics table to

know what overlap value to use.

9 DC_max) 828n F_sw

R_DLMT

+

(eq. 16)

F_sw 486p

Assume our transformer specification states a maximum

duty ratio of 63%. Our circuit operates at a 200 kHz

frequency and the overlap time is set to 100 ns. We should

place a resistance of the following value:

9 0.63 ) 828n 200 k

R_DLMT

+

[ 60 kW

(eq. 17)

200 k 486p

R

DLMT

should be placed directly across the DLMT and

AGND pins.

start

locked

V

OUTM1

Master

V

OUTA1

V

OUTM2

Slave

V

OUTA2

sync

Figure 21. A Typical Synchronization Sequence between a Master Controller and a Slave

A typical synchronization sequence appears in Figure 21.

A few pulses are necessary before synchronization is

effective. This locking sequence will last longer if

frequencies between master and slave are away from each

other.

During the initialization sequence, the shutdown

detection pin is released once V reaches its regulation

REF

level. The controller considered that the FLT/SD pin is

cleared from a fault when the pin voltage, V exceeds

FLT/SD,

the enable threshold, V

, typically 1.45 V, and V

FLT(enable)

SS

exceeds V

disabled once V

, typically 0.5 V. The controller is

SS(disable)

Fault Reporting and Shutdown Input

, falls below the shutdown threshold,

FLT/SD

The FLT/SD pin reports the presence of a fault to an

external supervisory circuitry. It also can be used to

shutdown the controller if externally brought down. This pin

has an open collector output with a 10 kΩ internal pull−up

V , typically 1.25 V. While the controller is in shutdown

fault

state, V is hiccupping between 9.5/9.4 V typically and

CC

V

REF

is kept high. When the FLT/SD pin is brought low, the

part activates the restart delay (RES is cycled up and down

32 times) before a new restart is authorized when the

FLT/SD pin is released.

Figure 22 gathers all the possible events that can activate

the fault pin.

resistor (R

) connected to the 5 V reference. The

FLT/SD

FLT/SD pin is internally pulled low (to indicate a fault) by

an internal transistor, , when an overcurrent, short circuit,

V , OVP, OTP or low input voltage fault is

CC(UVLO)

detected. The pin is also pulled low when the controller is in

restart mode.

www.onsemi.com

30

NCP1566

Pull Low

FLTSD

Internally

Shutdown

Cause

Auto−

Restart

Shutdown

Delay

Restart

Delay

V

< V

Yes

No

Yes

No

Yes

No

IN

ENABLE

V

IN

< V

STANDBY

V

< V

No

Yes

No

CC

CC(MIN)

< V

No

CC

CC(reset)

No

Yes

No

REF UVLO

OCP

Yes

No

SCP

OTP

OVP

Built−in Thermal

Shutdown

Yes

No

FLT/SD

SS low

Figure 22. This Table Gathers All the Possible Events which Pull the Fault Pin Low

Restart Mode

• Overvoltage fault (OVP)

The NCP1566 incorporates a restart timer to disable the

controller for a certain amount of time and initiate a hiccup

mode operation if a fault is detected. In short circuit

operations, this technique limits the overall dissipated

power. Once the fault is gone, the controller automatically

resumes operations. A restart event occurs if one of the

following faults is detected:

• Two consecutive short−circuit pulses (SCP)

• Overtemperature fault detected on OTP pin

• Internal thermal shutdown fault

• The FLT/SD pin has been externally pulled low

Please note that the pin is internally held low during the

duration of the restart timer. The simplified architecture of

the restart timer is shown in Figure 23.

• Overcurrent fault (OCP)

Figure 23. Restart Timer Architecture

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31

NCP1566

A pull−down current source, I

holds the RES pin at a low level when no faults are present.

The restart timer sequentially charges and discharges 32

, typically 5 μA,

pin to charge from 0 to 1 V. This charge is initiated by the

average input current reconstruction. When this internal

averaged current exceeds 0.3 V, the capacitor on the RES pin

is charged by the 20 μA source. If the over current goes

away, the capacitor slowly discharges via a 5 μA pull−down

current sink. If the fault comes back, the 5 μA sink turns off

and the 20 μA is reactivated. When the capacitor voltage

eventually reaches 1 V, all pulses are stopped, a shutdown

pulse is issued and the part enters auto−recovery hiccup

mode via the restart delay.

RES(SNK)

times the capacitor on the RES pin, C , between 2 V and

RES

4 V to set the restart or hiccup duration. A fault triggers a

restart or hiccup delay with the exception of an overcurrent

fault. An overcurrent fault starts the shutdown delay timer

before drive pulses are cut. A restart sequence initiates once

the shutdown delay expires.

The RES pin combines two functions: the restart delay

and the shutdown delay. As explained, the restart delay is

made of 32 up/down cycles between 2/4 V on the RES pin.

The shutdown delay is actually the time taken by the RES

Figure 24 shows operating waveforms during an overload

condition. A SHDN pulse is generated and the controller is

disabled once V

exceeds 1 V.

RES

V

OUTA

(t)

V

OUTM

(t)

4

3.5

3

2.5

V

RES

(t)

2

Stop!

1.5

1

0.5

−0

800

V

CS

(t)

700

600

500

400

300

200

100

−0

Internal

signal

V

(t)

CS(AVG)

840

850

860

870

880

890

900

910

920

930

Figure 24. Overload Condition Operating Waveforms

Hiccup is ensured by charging and discharging the

capacitor connected to the RES pin C between 2 and 4

disabled once V

falls below the discharge level,

RES

V

, typically 100 mV. Once C

is fully discharged

RES

RES(DIS)

RES

V. Charge and discharge currents are equal to 5 μA and

a new startup sequence commences and soft−start is

released.

respectively correspond to parameters I and

RES(SRC2)

I

. The restart mode ends after 32 consecutive

During the restart delay, the VCC pin is maintained by the

controller operating the high−voltage current source in the

DSS mode: the voltage hiccups between 9.4 and 9.5 V.

RES(SNK)

charge/discharge cycles. C

internal pull down transistor, SW . The transistor is

is then pulled low using an

RES

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32

NCP1566

V

(t)

OUTA

V

OUTM

4

V

SS

(t)

V

RES

(t)

3

2

V

UVLO

(t)

1

V

OTP

(t)

−0

9

8

7

6

5

4

3

2

1

0

V

CC

(t)

V

(t)

REF

FLT/SD

2.1

2.15

2.2

2.25

2.3

2.35

2.4

2.45

Figure 25. Timing Diagram Exiting Restart

Gate Drive Outputs

The NCP1566 has two in−phase output drivers with an

adaptive overlap delay (t ). The main output, OUTM, can

spikes. This can be achieved by reducing the connection

length between the drivers and their loads and using wide

traces for connections.

D

sink a minimum of 3 A and source a minimum of 2 A. The

secondary output, OUTA, can sink a minimum of 1 A and

source a minimum of 2 A.

Overlap Time

In an active clamp forward converter, there are two delays

involved in the driving signals. Both deal with Zero Voltage

Switching (ZVS) operations. When the main N−channel

MOSFET turns off, the magnetizing current finds an

immediate path in the P−channel body diode. The

conduction of this diode forces a low voltage across the

drain−source terminals of the considered MOSFET. Once

this condition is obtained, the P−channel can be turned on.

This delay ensures ZVS is present for the P−channel. To

limit switching losses on the main N−channel MOSFET, you

also want to ensure quasi or full ZVS operation. To meet this

requirement, the P−channel will be turned off slightly before

turning on the N−channel so that the drain−source voltage

can swing down to ground or approach it: this is the second

delay.

OUTM is configured to drive an N−channel MOSFET as

the main switch. OUTA is configured to drive a P−channel

MOSFET which source is grounded. OUTA is purposely

sized smaller than OUTM because the active clamp

MOSFET only sees the magnetizing current in an active

clamp forward topology. Therefore, a smaller active clamp

MOSFET with less input capacitance is used compared to

the main switch. Also, on−losses associated with this

P−channel have a beneficial damping effect on the

L

C

resonating network.

mag clamp

Once V reaches V

, the internal startup circuit is

CC(on)

CC

disabled and OUTA goes high to pre−charge the P−channel

charge pump capacitor. OUTA goes low following OUTM

after the overlap delay expires. OUTA remains high while

A simplified block diagram and waveforms of an active

clamp forward converter with a low side active clamp switch

are shown in Figure 26. Driver OUTM drives the main

switch where as OUTAC drives the active clamp switch.

Overlap time between the drive signals is required to achieve

zero or near zero volts switching (ZVS) on the switches.

the controller is disabled or until V falls below V

.

CC

CC(reset)

The outputs are biased directly from V and their high

CC

state voltage is approximately V . Therefore, the auxiliary

CC

supply voltage should not exceed the maximum gate voltage

of the main and active clamp MOSFETs.

The inductance between the drivers and its load should be

kept to a minimum to minimize current-induced voltage

www.onsemi.com

33

NCP1566

Figure 26. Active−clamp Forward Topology

OUTA leads OUTM during a low to high transition by a

the overlap time delays between the OUTA and OUTM

drive signals.

time duration given by t . OUTA trails OUTM during a high

D

to low transition by the same time duration. Figure 27 shows

V

DS

(t)

t

D1

V

(t)

OUTM

N−channel

t

D2

V

OUTA

P−channel

t

Figure 27. Overlap Time Waveforms

The overlap time is usually optimized for full−load

efficiency. However, the optimum overlap time required to

achieve ZVS varies with line and load conditions. In light

load, the magnetizing energy is reduced slowing down the

drain voltage transitions. Keeping the same overlap

regardless of loading conditions can affect the converter’s

efficiency along its operating range. NCP1566 adaptively

adjusts the overlap times to optimize the system efficiency

across operating conditions. The current sense information

(representative of load) is used to adjust the overlap times.

The overlap times are essentially constant at mid to high

load. In light load conditions, overlap times are inversely

proportional to load current. The adaptive overlap time

adjustment becomes active around 30 % of the maximum

load.

www.onsemi.com

34

NCP1566

A resistor, R , between the DT and AGND pins adjusts

For our 200 kHz dc−dc converter, the dead−time

DT

the overlap time. The minimum trailing delay is 20 ns.

resistance R is calculated using the maximum value at a

DT

Equations 18 shows the relationship between overlap delays

0.4 V CS bias. Assuming a 100 ns dead time, we have:

and R , the scaled−down input voltage and the current

sense voltage.

DT

DT 77.8 m

1.66 10^*16

100 n 77.8 m

1.66 10^*16

(eq. 19)

R_DT

+

+ 46.85 kW

R_DR 1.66 10^*16

If we plot (18) using Mathcad as V varies from 0 to 0.45

V, we obtain Figure 28 graph:

t_D(V_CS) +

CS

(eq. 18)

V_CS

1.4 V

37 k

1.4 V

_) minimumǒ

Ǔ

,

2 k 35 k

−7

2×10

−7

1.5×10

t (V

)

2

CS

−7

1×10

0

0.1

0.2

0.3

0.4

0.5

V

CS

Figure 28. The Dead Time Evolution with the Sensed Current

Reference Voltage

prevent the auxiliary voltage from properly building up,

aborting the startup sequence. V and V capacitors

A 5.0 V 2% reference is provided on the REF pin. It

provides current up to 12 mA. This reference can be used for

biasing an external circuitry. A bypass capacitor is required

for stability. The recommended minimum capacitance is 0.1

CC

REF

should be sized such that the charging of V

does not

REF

cause V to fall below V

. Otherwise, the reference

CC

CC(reset)

will be disabled and an unexpected hiccup can be observed.

μF. The reference is enabled once V

exceeds V

CC

If too much current is drawn from the REF pin, V will

UVLO

STBY

CC

and V exceeds 7.5 V. It is disabled once V falls below

collapse. Once V falls V

a shutdown pulse on

CC

CC(min)

V

, typically 6.4 V. The reference pin incorporates an

OUTM and forcing OUTA high. Once OUTM goes low, the

CC(reset)

undervoltage detector. The reference is disabled if it falls

below its undervoltage lockout threshold, V

controller is disabled resulting in a discharge of the soft−start

,

capacitor. V

and OUTA are disabled once V falls

REF(UVLO)

REF

CC

typically 4.5 V. The reference undervoltage lockout has

hysteresis, V , typically 200 mV. The controller is

below V

. Once V

is disabled, the overload

REF

CC(reset)

condition is removed allowing V to charge back up.

REF(HYS)

CC

immediately disabled if a V

undervoltage lockout fault

When the part is operated up to 120 V, it is important to

limit the current absorbed from the REF pin during the

start−up sequence or the hiccup mode.

REF

is detected. A 1.5 μs filter delay provides noise immunity.

V

REF

is biased directly from V . Therefore, if a load is

CC

applied to V while V

is charging, chances exist to

CC

REF

www.onsemi.com

35

NCP1566

Power Dissipation

The controller junction−to−ambient thermal resistance

Once the PCB layout is done and a prototype exists, it is

important to characterize the junction−to−ambient thermal

resistance and make sure the junction temperature remains

within limits, especially if the part is continuously biased up

to 120 V.

R

qJA

depends on the available copper surface it is soldered

upon. Below are characterization data that link R

with

J−A

copper surface and number of layers. 1 and 2 oz copper

respectively correspond to 35 and 70 μm PCB copper

thickness.

Temperature Shutdown

An internal thermal shutdown circuit monitors the

junction temperature of the IC. The controller is disabled

without a shutdown pulse if the junction temperature

Table 4. QFN PACKAGE 2 LAYER JEDEC EIA/JESD

51.3 (Copper area R

= 35 μm)

θ

JA

exceeds the thermal shutdown threshold, T

, typically

SHDN

2

Cu Area mm

100

1.0 oz

131

122

115

105

93

2.0 oz

115

107

101

93

165_C. The controller restarts once the IC temperature

drops below below T

hysteresis, T

by the thermal shutdown

SHDN

, typically 20_C and V

has

125

SHDN(HYS)

CC

charged to V

mode.

at least once while in thermal shutdown

CC(on)

150

200

A thermal shutdown fault is cleared if V drops below

CC

300

82

V

, or if V

falls below V

by its hysteresis

CC(reset)

UVLO

STBY

level. A power−up sequence commences at the next V

CC(on)

400

85

75

if all faults are removed.

500

79

69

600

74

66

Table 5. QFN PACKAGE 4 LAYER JEDEC EIA/JESD

51.7 (Copper area R

= 70 μm)

θ

JA

2

Cu Area mm

100

1.0 oz

48

2.0 oz

46

125

48

46

150

48

46

200

48

46

300

48

46

400

47

46

500

47

45

600

47

45

Ordering Information

Table 6. ORDERING INFORMATION TABLE

Device

Package

Shipping †

NCP1566MNTXG

QFN24

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

www.onsemi.com

36

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN24, 4x4, 0.5P

CASE 485CW

ISSUE O

DATE 15 NOV 2012

SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.25 AND 0.30 MM

FROM THE TERMINAL TIP.

A

B

A3

D

EXPOSED Cu

MOLD CMPD

PIN ONE

REFERENCE

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

A1

E

DETAIL B

MILLIMETERS

ALTERNATE

DIM MIN

MAX

1.00

0.05

CONSTRUCTIONS

2X

0.15

C

A

A1

A3

b

0.80

0.00

2X

0.15

C

0.20 REF

TOP VIEW

0.21

0.31

L

D

4.00 BSC

D2

E

2.10

2.30

(A3)

DETAIL B

4.00 BSC

A

L1

E2

e

2.10

2.30

0.10

0.08

C

0.50 BSC

L

0.30

---

0.50

0.15

DETAIL A

L1

C

ALTERNATE

CONSTRUCTIONS

SEATING

PLANE

NOTE 4

A1

GENERIC

MARKING DIAGRAM*

C

SIDE VIEW

1

D2

DETAIL A

XXXXXX

24X L

XXXXXX

ALYWG

G

7

13

E2

XXXXXX = Specific Device Code

1

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

24

24X b

0.10 C A B

0.05

e

e/2

C

NOTE 3

BOTTOM VIEW

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

RECOMMENDED

SOLDERING FOOTPRINT*

4.30

24X

0.55

2.90

1

2.90

4.30

PKG

OUTLINE

24X

0.32

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON85293E

QFN24, 4X4, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

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www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

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


型号：	NCP1566MNTXG
厂家：	ONSEMI
描述：	高度集成的双模式有源箝位 PWM 控制器控制器开关
文件：	总38页 (文件大小：2430K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1566MNTXG [ONSEMI]

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