NCP1618HDR2G_技术文档

DATA SHEET

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High-Voltage, Multimode

Power Factor Controller

10

1

SOIC−9 NB

CASE 751BP

NCP1618

The NCP1618 is an innovative multimode power factor controller.

The circuit naturally transitions from one operation mode to another

depending the switching period duration so that the efficiency is

optimized over the line/load range. In very−light−load conditions, the

circuit can enter the soft−SKIP mode for minimized losses.

Housed in a SO−9 package, the circuit further incorporates the

features necessary for robust and compact PFC stages, with few

external components.

MARKING DIAGRAM

10

NCP1618X

ALYW

G

1

NCP1618X = Specific Device Code

Multimode Operation

A

L

= Assembly Location

= Wafer Lot

• Multimode Operation for Optimized Operation over the Line/Load

Y

W

G

= Year

= Work Week

= Pb−Free Package

Range:

♦ Continuous Conduction Mode (CCM) in Heavy−Load Conditions

♦ Frequency−Clamped Critical Conduction Mode (FCCrM) in

Medium− and Light−Load Conditions

♦ FCCrM: Critical Conduction Mode (CrM) when the CrM

Switching Frequency is Lower than 130 kHz, Discontinuous

Conduction Mode (DCM) at 130 kHz Otherwise

♦ DCM Frequency Reduction in Light Load Conditions

♦ Minimum DCM Frequency Forced above 25 kHz

♦ Valley Turn−On in FCCrM

PIN CONNECTIONS

FB

1

2

3

4

5

10

HV

pfcOK

Vm

♦ Soft−SKIP Mode in Very Light Load Conditions

8

7

6

Vcc

• Near−Unity Power Factor in All Modes (Except Soft−SKIP Mode)

• Firm Control of the Switching Frequency between 25 kHz and

CS

Driver

Ground

130 kHz

ZCD

General Features

• High−Voltage Start−Up Current Source for V Capacitor Charge at

CC

Startup

ORDERING INFORMATION

See detailed ordering and shipping information on page 29 of

this data sheet.

• Internal Compensation of the Regulation Loop

• X2 Cap Discharge Function

• Fast Line / Load Transient Compensation (Dynamic Response

Enhancer)

• Large V Operating Range (9.5 V to 35 V)

CC

• Line Range Detection

• pfcOK Signal For Enabling/Disabling the Downstream Converter

• Jittering for Easing EMI Filtering

Protection Features

Typical Applications

• Soft− and Fast−Overvoltage Protection

• Line−Sag and Brown−Out Detection

• 2−Level Over Current Detection

• Bulk Under−Voltage Detection

• PC Power Supplies

• All Off−Line Appliances Requiring Power

Factor Correction

• OVP2: Redundant Over−Voltage Protection Using the ZCD Pin

• Thermal Shutdown

This document contains information on some products that are still under development.

onsemi reserves the right to change or discontinue these products without notice.

1

Publication Order Number:

August, 2022 − Rev. 7

NCP1618/D

NCP1618

Table 1. SELECTION TABLE

NCP1618A

65 kHz

130 kHz

YES

NCP1618B

NCP1618C

65 kHz

130 kHz

NO

NCP1618D

65 kHz

130 kHz

NO

NCP1618F

65 kHz

NONE

NO

NCP1618H

65 kHz

NONE

NO

NCP1618J

65 kHz

NONE

NO

NCP1618K

125 kHz

250 kHz

NO

f

65 kHz

130 kHz

NO

CCM

f

clamp

OVP2

V

CC(on)

17.0 V

10.5 V

17.0 V

V

/

111 V / 100 V 95 V / 87 V 111 V / 100 V 111 V / 100 V 95 V / 87 V

95 V / 87 V 111 V / 100 V 111 V / 100 V

BO(start)

BO(stop)

V

2

NONE

12% @ V_{in, rms}6% @ V_{in, rms}12% @ V_{in, rms}12% @ V_{in, rms}

12% @ V_{in, rms}

L @ f_CCM

ǒ_P_{FF, th}Ǔ

LL

L @ f_CCM

Current

criterion for

CCM

YES

NO

YES

NO

detection and

confirmation

at high line

Operation

mode

Multi Mode

NO

Multi Mode

NO

Multi Mode

YES

Multi Mode

NO

CCM only

NO

CCM only

NO

CCM only

NO

Multi Mode

YES

X2 cap

discharger

NOTES:

• f

is the switching frequency when the circuit operates in continuous conduction mode (CCM)

CCM

is the maximum level to which the switching frequency is clamped when the circuit operates in FCCrM (frequency−clamped critical

clamp

conduction mode). Practically, considering all modes, the circuit maintains the switching frequency above 25 kHz and below f

.

clamp

• V

and V

respectively are the upper and the lower thresholds of the brown−out protection (Table 1 provides their typical

BO(start)

BO(stop)

value)

• V

is the V startup threshold, that is, the V voltage at which the circuit starts to operate (Table 1 provides the typical value)

CC CC

CC(on)

• OVP2: if an image of the output voltage is provided to the ZCD pin during the off−time, the circuit can detect an overvoltage of the output

voltage and provide a redundant protection

• (P

)

is the expression of the power below which the circuit enters the frequency foldback operation at low line. This threshold varies

FF,th LL

as a function of the line rms voltage square and depends on the selected inductor value (L). In high line conditions, the power threshold

are obtained by dividing the power expression by two (see the frequency foldback section).

• See the CCM detection section for more information regarding the current criterion for CCM detection and confirmation at high line

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2

NCP1618

TYPICAL APPLICATION SCHEMATIC DIAGRAMS

Figure 1. NCP1618 with ZCD_OVP2 Typical Application Schematic Diagram

Note that several circuitries exist for lossless redundant OVP2 as discussed in application note AND90011.

Figure 2. NCP1618 AC Start−up Typical Application Schematic Diagram

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3

NCP1618

PIN FUNCTION DESCRIPTION

Pin No. Pin Name

Function

Description

1

FB

Feedback Pin This pin receives a portion of the PFC output voltage for regulation and the Dynamic Response

Enhancer (DRE) function which drastically speeds−up the loop response when the output voltage

drops below 95.5% of the desired output level. V is also the input signal for the soft− and

FB

fast−overvoltage (OVP) and under−voltage (UVP) comparators. A 250 nA sink current is built−in

to trigger the UVP protection and disable the part if the feedback pin is accidently open.

2

3

pfcOK

PFC OK Pin This pin is grounded until the PFC output has reached its nominal level. It is also grounded if the

NCP1618 detects a major fault like a brown−out situation. A resistor is to be placed between the

pfcOK pin and ground to form a voltage representative of the output voltage which can be used

to enable the downstream converter and provide it with a feedforward signal.

Multiplier

Output

This pin provides a voltage V for duty cycle modulation when the circuit operates in continuous

M

V

M

conduction mode. The external resistor R applied to the V pin, adjusts the maximum power

M

which can be delivered by the PFC stage. The device operates in average−current mode if an

external capacitor C is further connected to the pin. Otherwise, it operates in peak−current mode

M

4

5

CS

Current

This pin sources a current I which is proportional to the inductor current. The NCP1618 uses

CS

CS CS

detection, abnormal current detection and overcurrent protection (OCP).

Sense Pin

I

to adjust the PFC duty ratio in CCM operation. I is also used for protection: inrush current

ZCD

Zero Current This pin is designed to monitor a signal from an auxiliary winding and to detect the core reset

Detection

when this voltage drops to zero. This function ensures valley turn on in discontinuous and critical

conduction modes (DCM and CrM). The NCP1618 can further use the ZCD voltage to detect an

over−voltage condition of the bulk voltage, reduce the power delivery and if the FB pin voltage

is low, latch off the part in such an event.

6

7

GND

DRV

Ground Pin Connect this pin to the PFC stage ground.

Driver Output The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to

effectively drive high gate charge power MOSFETs.

8

V

IC Supply

This pin is the positive supply of the IC.

Removed for creepage distance.

CC

9

−

10

HV

High Voltage The circuit senses the HV pin voltage for line range detection and line−sag and brownout

protections. This pin is also the input for the high voltage start−up circuit.

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4

NCP1618

INTERNAL CIRCUIT ARCHITECTURE

HV

V

HV

BONOK

OFF

BUV

FB

OFF

BUV

idle_phase

TSD

SKIP2

Major Faults

Management

pfcOK

UVLO

pfcOK and

Skip control

VCC

Management

VDD

pfcOK_H

UVP

STDWN

soft−stop

reset UVLO

Line−sag End_skip_burst

pfcOK−H HL CCM

VCC

SKIP1

fastOVP

SoftOVP

idle_phase

SKIP2

soft−SKIP

control

CCM

End_skip_burst

End_idle_phase

pfcOK−H

Regulation, UVP,

softOVP,

FB

UVP

fastOVP, DRE,

Soft−Start,

staticOVP

StaticOVP,

SKIPout and BUV

V

REGUL

pfcOK−H HL

OFF idle_phase

BUV

DRV

clamp

SoftOVP

DRE1

fastOVP

OCP

DRE

Output

Buffer

OUTon

DRV

GND

soft−stop Line_recovery

OVS

DT

Internal Ramp

and

V

multimode

HV

V

DMG

Ics

management

(CCM, CrM, DCM

and soft−SKIP)

BONOK

HL

SKIP

In−rush

staticOVP

OVP2

Line Range Control

Line_sag

DRE1

Line_recovery

Line−sag

DRE

ZCDfault CSfault

OVP2 is version dependent

CCM OVP

V

REGUL

In−rush

OUTon

OVP2

Ics

V

Zero

M

V

DMG

ZCD

In−rush

current

detection

and OVP2

STDWN

S

R

DT

Q

V

< V

DRE−H

FB

OCP

OVS

Current Sense

Block

ZCDfault

CS

CSfault

SKIP1

reset

(V < V

)

CC(reset)

CC

Figure 3. Internal Circuit Architecture

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5

NCP1618

MAXIMUM RATINGS

Symbol

Rating

Value

Unit

V

High Voltage Start*Up Circuit Input Voltage

*0.3 to 700

V

HV(MAX)

V

Maximum Power Supply voltage, V pin, continuous voltage

−0.3 to 35

Internally limited

V

mA

CC(MAX)

CC

I

Maximum current for V pin

CC

V

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3, V

(Note 1)

V

mA

DRV(MAX)

DRV

I

−500, +800

V

Maximum voltage on low voltage pins (except DRV and V pins)

−0.3, 5.5 (Note 2)

−2, +5

V

mA

MAX

CC

I

Current range for low voltage pins (except DRV and V pins)

CC

R

Thermal Resistance Junction−to−Air

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

180

°C/W

°C

−

q

J−A

T

150

J(MAX)

T

−40 to +125

J

T

−60 to +150

S

MSL

Moisture Sensitivity Level

1

3.5

1

ESD Capability, HBM model (Notes 3 and 4)

ESD Capability, CDM model (Note 4)

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. V

is the DRV clamp voltage V

when V is higher than V

. V

is V otherwise.

DRV

DRV(high)

CC

DRV(high) DRV CC

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages

can be applied if the pin current stays within the −2 mA / 5 mA range.

3. Except HV pin

4. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114F,

Charged Device Model 1000 V per JEDEC Standard JESD22−C101F

5. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78E.

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max

J

CC

HV

values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted)

J

CC

HV

Symbol

Description

Test Condition

Min

Typ

Max

Unit

STARTUP AND SUPPLY CIRCUITS

V

Startup Threshold

NCP1618A, C, D, F, H, J, K

NCP1618B

V

rising

15.8

9.75

8.5

17.0

10.5

9.0

18.2

11.25

9.5

−

V

CC(on)

CC

V

Minimum Operating Voltage

V

CC

V

CC

decreasing

CC(off)

V

Hysteresis V

– V

NCP1618A, C, D, F H, J, K

6.0

8.0

CC(HYS)

CC(on)

CC(off)

,

NCP1618B

0.5

3.5

1.5

5.0

−

V

CC

level below which the circuit resets

V

decreasing

6.0

CC(reset)

CC

Start−Up Current when the V Pin is Grounded,

= 0 V, V = 130 V

mA

CC

HV

NCP1618A

I

Sourced by the V Pin

0.7

−

1.0

−

1.3

start1

CC

I

Sunk by the HV pin

HV1

Start−Up Current when the V Pin is Grounded

V

= 0 V, V = 130 V

CC

CC HV

(Except NCP1618A)

I

Sourced by the V Pin

1.0

−

1.6

−

2.2

start1

CC

I

Sunk by the HV pin

HV1

Start*Up Current

V

CC

V

HV

= V

− 0.5 V,

CC(on)

I

Sourced by the V Pin

= 130 V

6.5

−

12.0

−

16.5

18.0

start2

CC

I

Sunk by the HV pin

HV2

V

Threshold for I

to I

transition

V

HV

increasing,

0.4

–

0.8

–

1.2

V

CC(inhibit)

CC

start1

start2

CC

I

> 6.5 mA

HV

Minimum Voltage for Start−Up Circuit ensuring

_start2= 6.5 mA

V_CC= V_CC(on)– 0.5 V

V_CC= 9.6 V, F = 65 kHz

38

(MIN)

I

Supply Current

mA

sw

I

Device Disabled / Fault (no switching)

Device Enabled (switching) / No output load on pin 5

Soft−SKIP Idle Phase

0.80

−

1.20

2.20

0.25

1.40

4.00

0.50

CC1

CC2

CC3

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6

NCP1618

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max

J

CC

HV

values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)

J

CC

HV

Symbol

Description

Test Condition

Min

Typ

Max

Unit

GATE DRIVE

t

Output voltage rise−time

Output voltage fall−time

C = 1 nF

−

45

30

−

ns

R

L

10 − 90% of output signal

t

C = 1 nF

F

L

10 − 90% of output signal

R

Source resistance

−

8

11

7

−

W

OH

R

Sink resistance

OL

SOURCE

I

Peak source current (Note 6)

Peak sink current (Note 6)

V

= 0 V

500

800

−

mA

V

DRV

I

= 12 V

SINK

DRV

V

DRV pin level at V close to V

= V

+ 200 mV

DRVlow

CC

CC(off)

CC

CC(off)

10 kW resistor to GND

V

DRV pin level at V = 35 V

R = 33 kW, C = 220 pF

10

12

14

V

DRVhigh

CC

L

RAMP

f

CCM switching frequency

60

65

70

kHz

%

CCM

NCP1618K

over Switching Frequency for CCM

CCM

115.4

125

134.6

R

Ratio f

−

112

−

CCM

detection

t

Blanking Time for CCM mode end detection

Clamp Frequency (DCM Frequency)

315

360

415

ms

CCMend

f

No frequency foldback

−

130

250

−

kHz

clamp

NCP1618K

f

over f ratio

CCM

1.90

2.00

2.05

−

clamp_ratio

clamp

(t

)

On−Time below which Frequency Foldback is Engaged

NCP1618A, C, D Low line

High line

ms

on,FF LL

(t

)

−

3.75

1.87

0.94

2

−

on,FF HL

NCP1618B Low line

High line

NCP1618K Low line

High line

1

f

Minimum DCM Frequency

25.0

30.5

36.0

kHz

min

t

Maximum On−Time (CCM)

fCCM = 65 kHz

fCCM = 125 kHz

−

15

7.8

−

ms

on,max

R

Ramp Frequency Jittering

Jittering Frequency

−

10

−

%

jit

f

jit

119

Hz

REGULATION BLOCK

Feedback Voltage Reference

V

REF

T = 25°C

J

2.46

2.44

2.50

2.54

2.56

V

J

T = −40°C to +125°C

V

L / V

Ratio (V

Low Detect Lower Threshold / V )

REF

95.0

97.5

2

95.5

98.0

−

96.0

98.5

−

%

−

DRE

REF

OUT

V

DRE

H / V

Ratio (V

Low Detect Higher Threshold / V

)

REF

OUT

REF

H

/ V

Ratio (V

Low Detect Hysteresis / V

)

DRE

OUT

REF

K

Loop Gain Increase due to Dynamic Response

Enhancer

pfcOK high

pfcOK low

−

10

5

−

DRE1

DRE0

t

Soft−Stop Duration for Gradual Discharge of the

Control Voltage from Max to Min

−

140

−

ms

SSTOP,max

StaticOVP

D

Duty Ratio

V

FB

= 3 V

−

0

%

MIN

SOFT SKIP CYCLE MODE BLOCK

CrM/DCM V pin Current Capability

I

400

−

mA

VM

M

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7

NCP1618

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max

J

CC

HV

values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)

J

CC

HV

Symbol

Description

Test Condition

Min

Typ

Max

Unit

SOFT SKIP CYCLE MODE BLOCK

Pin SKIP Threshold

V

M

1.2

0.4

24

1.5

0.5

29

1.8

0.6

33

V

SKIP(th)

V

SKIP2

pfcOK SKIP Threshold

t

pfcOK Minimum Negative Pulse Duration for SKIP

Detection

ms

V

/V

V

Upper Value (V ) During a Soft−SKIP Burst

REFX

102.5

103.0

103.5

%

REFX REF

FB

Cycle (defined as a V

percentage)

REF

(R

)

V

FB

Lower Value During a Soft Skip Cycle Burst

96.5

98.5

98.0

100

99.5

FB recover

(defined as a percentage of V

)

REF

for NCP1618C, D, H, J

101.5

CURRENT SENSE BLOCK

V

Current Sense Voltage Offset

I

= −100 mA

= −10 mA

−10

44

−

15

10

mV

mA

ns

CSoff100

CS

V

CSoff10

CS

I

Minimum I current for CCM detection

50

30

200

40

56

CCM−H

CS

I

Minimum I current for CCM confirmation

26

35

CCM−L

CS

I

Low−Line Over−Current Protection Threshold

High−Line Over−Current Protection Threshold

Low−Line Over−current Protection Delay from (I

V

= 130 V

= 290 V

= 130 V

185

−

215

100

ILIMIT1(LL)

ILIMIT1(HL)

HV

I

t

>

CS

OCP1(LL)

I ) to DRV low

ILIMIT1(LL)

t

High−Line Over−current Protection Delay from (I

ILIMIT1(HL)

>

V

HV

= 290 V

−

40

100

ns

OCP1(HL)

CS

I

) to DRV low

I

Low−Line Threshold for Abnormal Current Protection

High−Line Threshold for Abnormal Current Protection

V

= 130 V

= 290 V

270

150

300

260

330

350

mA

ns

ILIMIT2(LL)

HV

I

ILIMIT2(HL)

HV

t

Leading Edge Blanking Time for the Over−Current and

Abnormal Current Detection Comparators (Note 6)

LEB,CS

I

Threshold for In−rush Current Detection

CS Fault Threshold

7.5

180

1

10.0

250

2

12.5

320

3

mA

mV

ms

in−rush

CS(fault)

V

t

CS Fault Blanking Time

I

Source Current for CS pin testing

−

235

−

mA

kW

CS(test)

R

Minimum Impedance to apply to the CS pin not to Trig

the CS Short−to−Ground Protection (Note 6)

−

1.5

OCP,min

ZERO VOLTAGE DETECTION CIRCUIT

ZCD Leading Edge Blanking Time

t

70

0.90

0.40

0.35

0.5

−

100

1.00

0.50

−

130

1.10

0.60

−

ns

V

LEB,ZCD

V

Zero Current Detection, V

rising

falling

ZCD(th)H

ZCD

V

Zero Current Detection, V

V

ZCD(th)L

ZCD

V

Hysteresis of the Zero Current Detection Comparator

ZCD Pin Bias Current, V = V

V

ZCD(hyst)

I

2.0

85

mA

ns

ms

mA

kW

ZCD(bias)H

ZCD

ZCD(th)H

I

ZCD Pin Bias Current, V

= V

ZCD(th)L

−

ZCD(bias)L

ZCD

t

(V

ZCD

< V ) to (DRV high)

ZCD(th)L

50

ZCD

t

Minimum ZCD Pulse Width

−

50

−

SYNC

t

Watch Dog Timer in “Overstress” Situation

Source Current for ZCD pin testing

710

−

815

230

−

950

−

WDG(OS)

I

ZCD(test)

R

Minimum Impedance to apply to the ZCD pin not to

Trig the ZCD Short−to−Ground Protection (Note 6)

−

7.5

ZCD,min

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8

NCP1618

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max

J

CC

HV

values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)

J

CC

HV

Symbol

Description

Test Condition

Min

Typ

Max

Unit

UNDER− AND OVER−VOLTAGE PROTECTION

V

R

UVP Threshold

Ratio (UVP Threshold) over V

V

FB

V

FB

V

FB

V

FB

V

FB

falling

rising

−

8

0.3

12

−

16

4

V

%

V

UVP

(V

/ V

)

REF

UVP

REF

R

Ratio (UVP Hysteresis) over V

2

3

UVP(HYST)

REF

V

Soft OVP Threshold

Ratio (Soft OVP Threshold) over V

−

2.625

105

−

softOVP

R

(V

softOVP

/

104

106

%

softOVP

REF

V

REF

)

R

Ratio (Soft OVP Hysteresis) over V

V

FB

V

FB

V

FB

falling

rising

1.5

−

2.0

2.7

2.5

−

%

V

softOVP(H)

REF

V

Fast OVP Threshold

fastOVP

R

Ratio (Fast OVP Threshold) over (Soft OVP Upper

102

103

104

%

fastOVP1

Threshold) (V / V

)

fastOVP

softOVP

R

Ratio (Fast OVP Threshold) over V

REF

(V

/

V

rising

falling

107.0

108.3

109.5

%

fastOVP2

REF

fastOVP

FB

V

)

V

FB Threshold for Recovery from a Soft or Fast OVP

−

2.575

210

4.0

−

V

nA

V

OVPrecover

FB

(I )

FB bias Current @ V = V

50

3.9

70

450

4.1

130

B FB1

FB

softOVP

FB bias Current @ V = V

FB UVP

(I )

B FB2

V

ZCD OVP2 Threshold (NCP1618A only)

OVP2 Blanking Time (NCP1618A only)

V

ZCD

rising

OVP2

t

100

ns

V

M

V

Pin Voltage in FCCrM (CrM or DCM)

2.0

2.5

3.0

V

M,FCCrM

M

(V

)

PWM Comparator Reference Voltage for CCM

Operation

V

rising

3.50

3.75

4.00

ramp pk

M

I

V

M

Pin Source Current

= 2 V, I = −100 mA

31

8.4

66

39

10.4

82

46

12.4

96

mA

mS

mA

mS

mA

mS

M1(LL)

FB

CS

low line

I

(V

/

I

over (V

)

ratio

V

= 2 V, I = −100 mA

M1(LL)

ramp pk

FB CS

)

low line

V = 2 V, I = −200 mA

FB

ramp pk

I

V

M

Pin Source Current

M2(LL)

CS

low line

I

(V

/

I

over (V

)

ratio

V

FB

= 2 V, I = −200 mA

17

22

26

M2(LL)

ramp pk

CS

)

low line

ramp pk

I

V

M

Pin Source Current

V

FB

= 2 V, I = −100 mA

131

35

163

43

194

52

M1(HL)

CS

high line

V = 2 V, I = −100 mA

FB

I

/

I

over (V

)

ratio

M1(HL)

ramp pk

CS

(V

)

high line

ramp pk

BROWN−OUT, LINE SAG AND LINE RANGE DETECTION

V

Upper Threshold for Line Sag and Brown−Out

Detection NCP1618A, C, D, J, K

NCP1618B, F, H

V

HV

V

HV

V

HV

increasing

decreasing

increasing

V

BO(start)

BO(stop)

103

88

111

95

119

102

V

Lower Threshold for Line Sag and Brown−Out

Detection

NCP1618A, C, D, J, K

92

80

100

87

108

94

NCP1618B, F, H

V

Hysteresis

NCP1618A, C, D, J, K

NCP1618B, F, H

7

3.5

11

7.5

−

BO(HYS)

t

Brown−out Detection Blanking Time

Line Sag Detection Blanking Time

High−Line Level Detection Threshold

Low−Line Level Detection Threshold

V

HV

V

HV

V

HV

V

HV

decreasing

increasing

decreasing

550

22.8

220

207

650

26.0

236

222

750

30.2

252

237

ms

V

BO(blank)

t

Sag(blank)

V

HL

V

LL

V

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9

NCP1618

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max

J

CC

HV

values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)

J

CC

HV

Symbol

Description

Test Condition

Min

Typ

Max

Unit

BROWN−OUT, LINE SAG AND LINE RANGE DETECTION

V

t

Line Range Select Hysteresis

V

increasing

decreasing

9

−

V

LR(HYST)

blank(LL)

HV

High− to Low−Line Mode Selector Timer

Low− to High−Line Mode Selector Timer Filter

Lockout Timer for Low− to High−Line Mode Transition

22.8

300

450

26.0

360

515

30.2

420

600

ms

HV

t

filter(HV)

t

V

HV

increasing

ms

line(lockout)

X2 DISCHARGE

t

Line Voltage Removal Detection Timer

Upslope Detection Reset Timer (Note 6)

Downslope Detection Reset Timer (Note 6)

HV Discharge Current

83

−

100

1

100

27

ms

V/ms

mA

line(removal)

t

HV increasing

HV decreasing

HV(up)

t

−

14.0

4.5

−

1.89

6.5

34

HV(down)

I

2.5

−

HV(discharge)

V

HV Discharge Stop Level

V

HV(discharge)

pfcOK AND BUV PROTECTION

V

pfcOK Voltage in OFF Mode

1 mA being sunk by the

pfcOK pin

−

100

27

mV

pfcOK−L

I

pfcOK Current

V

FB

V

FB

= 2.5 V, V

= 1 V

pfcOK

23

25

mA

pfcOK

V

BUV

Bulk Under−Voltage Protection (BUV) Threshold

falling

1.71

1.52

0.95

1.80

1.6

1

1.89

1.68

1.05

V

NCP1618H

NCP1618K

t

BUV Delay Before Operation Recovery

450

515

600

ms

BUV

THERMAL SHUTDOWN

T

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

−

150

50

−

°C

LIMIT

TEMP

H

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. Guaranteed by Design

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10

NCP1618

STARTUP SEQUENCE / V MANAGEMENT

An internal high−voltage startup current source is enabled

V

) is provided to prevent erratic operation. The low

level makes it ideal in applications where the

CC(off)

CC

CC(on)

whenever V drops below V

(9 V, typically), to

controller is fed by an external power source (typically from

an auxiliary power supply). Its maximum start−up level

(11.25 V) is set low enough to be powered from traditional

12−V rails.

CC

CC(off)

charge the V capacitor, in particular when the PFC stage

CC

is plugged to the mains outlet. When V

exceeds the

CC

V

CC(on)

level, the current source turns off and the circuit

starts operating. The energy stored by the V capacitor

must be large enough to feed the controller and maintain

The startup current source being off when the PFC stage

is in operation, the HV pin virtually draws no current. This

helps minimize the losses in light−load conditions and

hence, meet the most stringent standby requirements.

CC

V

CC

above V

(that is, the level below which the circuit

CC(off)

turns off) until an auxiliary power supply takes over. The

large 8−V UVLO typical hysteresis (V

minus

CC(on)

HV

10

I_start2

I_start1

−

V

CC(inhibit)

+

UVLO

−

+

Vcc

V

CC(on)

/ V

CC(off)

External

Power

8

Source

GND

6

(When high, “UVLO” indicates that the circuit

is not properly fed and sets off mode)

Figure 4. Internal Startup Current Source

The startup current sourced by the V pin (I

12 mA typically. As shown by Figure 4, the startup current

) is

that moment, as detailed in the next paragraph, the circuit

operates in discontinuous conduction mode with valley

turn−on.

CC

start2

is limited to I

(1 mA typically) when the V voltage is

start1

CC

belowV

(0.8 V typically). This feature prevents the

Note that the circuit can transition from CrM to DCM and

vice versa within half−line cycles. Typically DCM is

obtained near the line zero crossing where current cycles

tend to be shorter and CrM, at the top of the line sinusoid

where the current cycles are longer. This is because the

circuit enters DCM operation when the current cycle is

CC(inhibit)

circuit from overheating if the V

grounded.

Thus, the following equation provides the V capacitor

charge time:

pin is accidentally

CC

C

_Vcc@ V_CC(inhibit)

C

_Vcc@ (V_CC(on)* V_CC(inhibit))

t_ch

+

)

shorter than T

(clamp period corresponding to f

:

clamp

(eq. 1)

I_start1

I_start2

T

clamp

= 1 / f

) as it can easily be the case near the line

clamp

As an example, using 17 V for V

typical V startup threshold) and their typical values for

the other parameters in play (V

it comes for a 100−mF V capacitance:

(NCP1618A

CC(on)

zero crossing and in light−load conditions. Conversely, if the

current cycle exceeds T , the system naturally enters the

CC

clamp

, I

and I

),

CC(inhibit) start1

start2

CrM operation mode. These transitions cause no

discontinuity in the operation and power factor remains

properly controlled.

CCM operation is obtained in heavy load conditions when

the current cycle is longer than 112% of the CCM switching

period. At that moment, the circuit operates as a CCM

controller in all parts of the line sinusoid (no transitions to

FCCrM) and remains in CCM for at least the CCM blanking

CC

*6

100 @ 10

@ (17 * 0.8)

100 @ 10

@ 0.8

(t

)

+

)

^

215 ms

ch*100mF typical

*3

12 @ 10

1 @ 10

(eq. 2)

THREE MODES OF OPERATION

Depending on the current cycle duration, the NCP1618

operates in either FCCrM or CCM. In FCCrM (or frequency

clamped critical conduction mode), the circuit operates in

critical conduction mode until the switching frequency

time (T

of 360 ms typically). This is because the

CCMend

circuit recovers the FCCrM mode only if it cannot detect 8

consecutive current cycles longer than the CCM switching

exceeds the f

clamp threshold (130 kHz typically). At

clamp

period for T

.

CCMend

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11

NCP1618

(t)

i_L

V_DS

V

ramp,pk

V

Internal

Ramp

Internal

Ramp

V

Internal

Ramp

clamp

T

T_CCM

clamp

T

cycle

< T

→ DCM

T

clamp

< T

→ CrM

T

> 112% * T

→ CCM

clamp

cycle

CCM

cycle

CCM

(FCCrM operation is recovered if

T

< T

for T

)

cycle

CCM

CCMend

Figure 5. Three Operation Modes (MOSFET Drain−source Voltage is in Red, the Internal Ramp is in Green)

Finally, depending on the conditions, the circuit operates

in CrM, DCM (with valley turn−on) or CCM.

Practically, the circuit compares the current cycle duration

delays the next cycle until the T

the circuit enters DCM operation. In DCM, the switching

period is actually a bit longer than T . This is because of

time has elapsed. Thus,

clamp

to two periods T

and T

:

the below discussed modulation method but mainly because

the next cycle is further delayed until the next valley is

detected (left plot of Figure 5). Doing so, valley turn−on is

obtained for minimized losses.

clamp

CCM

• If the current cycle duration is shorter than T

, T

clamp clamp

forces the switching frequency and the system operates in

DCM

Frequency−Clamped operation is controlled by a

proprietary circuitry which modulates the duty−ratio

cycle−by−cycle to prevent any discontinuity in operation

and ensure proper current shaping. Also, as shown by

Figure 6, it automatically varies the valley at which the

MOSFET turns on within the line sinusoid as necessary to

maintain valley switching and clamp the frequency over the

instantaneous input voltage range. For instance, DCM is

more likely to occur near the line zero crossing and CrM at

the top of the sinusoid. As the load further decays, current

cycles become shorter and DCM operation is obtained over

the entire line sinusoid. Furthermore, as detailed in the next

section and illustrated by Figure 6c and Figure 6d, the DCM

period clamp is increased below a certain load level for

frequency foldback (a longer minimum switching period is

forced causing frequency foldback). Anyway, in all cases,

the NCP1618 scheme ensures a clean control preventing that

repeated spurious changes in the turn−on valley possibly

cause current distortion and audible noise.

• If the current cycle duration is longer than T

but

clamp

shorter than 112% of T

, the system operates in CrM.

CCM

• If 8 consecutive current cycles happen to be longer than

112% of T , the system enters CCM mode with a

CCM

switching frequency set to f

= 1 / T

. The system

CCM

remains in this mode until the circuit cannot detect 8

consecutive current cycles longer than T

(360 ms typically).

for T

CCM

CCMend

Figure 5 provides a simplified description of the manner

the conduction mode is selected.

FREQUENCY−CLAMPED CRITICAL CONDUCTION

MODE

As aforementioned, the NCP1618 tends to operate in

critical conduction mode as long as the current switching

cycle is short enough not to enter the CCM mode. However,

if the current cycle happens to be shorter than the

frequency−clamp period (T

which is about 7.7 ms

clamp

typically leading to a 130 kHz DCM frequency), the circuit

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12

NCP1618

V

out

I_LINE

V_DS

a) 40% load, top of the sinusoid

b) 40% load, near the line zero crossing

V

out

I_LINE

V

out

I_LINE

V

DS

V_DS

c) 20% load, top of the sinusoid

d) 20% load,near the line zero crossing

Figure 6. Operation of the 500 W NCP1618 Evaluation Board @ 115 Vrms

FREQUENCY FOLDBACK IN DCM OPERATION

The frequency clamp (or DCM period) is gradually

decreased when the power demand drops below a certain

threshold. The expression of this power threshold depends

on the line range (see the “Line Range Detection” section).

The threshold also depends on the circuit version. Table 1

function can reduce the frequency to nearly 10 kHz.

However, a specific ramp ensures that the switching

frequency remains above audible frequencies.

This ramp generates a clock which overrides the clock

provided by the DCM ramp (it forces next DRV pulse even

if the DCM ramp clock is not generated yet). However, the

minimum−frequency ramp remains synchronized to the

drain source voltage for valley turn−on. Practically, as

shown by Figure 7, the minimum−frequency ramp typically

sets the clock signal when the switching period reaches

33 ms. The DRV output will then turn on back when the next

valley is detected. If no valley can be detected within a 3 ms

interval, DRV is forced high whatever the drain−source

voltage is. As a result, the minimum frequency is typically

between 30 kHz (33 ms switching period) if a valley is

immediately detected and 28 kHz (36 ms switching period)

if no valley can be detected.

provides the equation for Low line, where V

is the line

in,rms

rms voltage, L is the boost inductor of the PFC stage and

is the switching frequency in CCM operation (65 kHz

f

CCM

typically). The High Line power threshold is half Low Line

power threshold.

The frequency clamp level linearly reduces as the power

further decays to nearly reach (f

/ 10) when the power

clamp

is close to zero. The circuit however forces a minimum

25−kHz operation to prevent audible noise. See next section.

DCM MINIMUM FREQUENCY (FOR DCM ONLY)

As aforementioned, the DCM frequency is gradually

lowered in very light load conditions as a function of the

load, to optimize the efficiency. This frequency foldback

Note that the frequency clamp can force a new DRV pulse

only if the system is in dead−time. The minimum frequency

clamp cannot cause CCM operation.

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13

NCP1618

V

ZCD

time

DCM F_min

Ramp

DCM F_min

Ramp

DRV

time

33 ms (30 kHz)

36 ms (28 kHz)

Restart on the lowest ramp threshold

Restart on the highest ramp threshold

(synchronization to V case)

(no possibility to synchronize to V

)

DS

Figure 7. DCM Minimum Switching Frequency Ramp

JITTERING

• FCCrM recovery:

In CCM operation, the NCP1618 features the jittering

function which is an effective method to improve the EMI

signature. An internal low−frequency signal modulates the

oscillator swing which helps by spreading out energy in

conducted noise analysis.

Ǹ

0.50 @ V_in,rms²@ (V_out* 2 @ V_in,rms

)

(P_{in,avg CCM}

)

+

(eq. 4)

out

L @ f_CCM@ V_out

Where L is the value of the PFC inductor, V

is the line

is the CCM

in,rms

rms voltage, V is the output voltage and f

out

CCM

Practically, the CCM switching frequency is typically

varied as follows:

switching frequency (65 kHz typically).

NOTES:

• Jittering frequency: 119 Hz

• Pk to pk frequency variation: 10%

• The 8 current cycles longer than 112% of T

necessary

CCM

to detect CCM are not validated unless the inductor

current happens to exceed a minimum level within each

cycle. Practically, the second criterion consists of

Jittering is not implemented in frequency clamped critical

conduction mode (FCCrM including CrM and/or DCM

sequences) where valley turn−on operation naturally leads

to frequency variations.

comparing the internal current sense current (I ) to the

following internal current references:

CS

♦ I

(50 mA typically) when CCM is low.

(30 mA typically) when CCM is high.

CCM−H

CCM−L

CCM DETECTION

As aforementioned, the NCP1618 measures the duration

of each current cycle (the current cycle is the total duration

of the on−time + the demagnetization time) and compares it

• Some options (see Table 1) meet the second criterion in

low line only. In high line, it validates CCM cycles

regardless of the I current level.

CS

to T

, which is the CCM switching period. The circuit

CCM

enters CCM mode if it consecutively detects 8 current cycles

longer than 112% of T . Conversely, the circuit leaves the

CURRENT SENSE BLOCK

The NCP1618 is designed to monitor a negative voltage

proportional to inductor current (I ). As portrayed by

Figure 8, a current sense resistor (R

CCM

CCM mode if the circuit does not detect 8 consecutive cycles

exceeding T for the CCM blanking time (T of

L

CCM

CCMend

) is inserted in the

sense

360 ms typically). Some versions (see Table 1) do not wait

for conditions to enter CCM mode and CCM mode is forced,

i.e. DCM/CRM modes are omitted when CCM mode is

forced.

The following expressions provide the typical power

thresholds for:

return path to generate a negative voltage (V

)

Rsense

proportional to I . The circuit uses V

to detect when I

L

Rsense

L

exceeds its maximum permissible level. To do so, the circuit

incorporates an operational amplifier that sources the

current necessary to maintain the CS pin at 0 V (refer to

Figure 9). By inserting a resistor R

between the CS pin

OCP

• CCM entering:

and R

, we adjust the current that is sourced by the CS pin

sense

Ǹ

0.56 @ V_in,rms²@ (V_out* 2 @ V_in,rms

)

(I ) as follows:

CS

(P_{in,avg CCM}+

)

(eq. 3)

* (R_sense@ I_L) ) (R_OCP@ I_CS) + 0

in

(eq. 5)

L @ f_CCM@ V_out

Which leads to:

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14

NCP1618

2 @ 10³

30 @ 10^*3

R_sense

R_OCP

I_(L(max)

+

@ 200 @ 10^*6^ 13.3 A

I_CS

+

I_L

(eq. 6)

(eq. 8)

In other words, the CS pin current (I ) is proportional to

CS

In−rush Current Detection

The NCP1618 permanently monitors the input current

and when in FCCrM, can delay the MOSFET turn on until

the inductor current. Three protection functions use I : the

CS

over−current protection, the in−rush current detection and

the overstress detection. It is also used in CCM to control the

power−switch duty−ratio.

(I ) has vanished. This is one function of the I comparison

L

CS

to the I

threshold (10 mA typical). This feature helps

in−rush

IMPORTANT NOTES:

maintain proper FCCrM operation when the ZCD signal is

too distorted for accurate demagnetization detection like it

can happen at very high line. The inrush comparator also

serves to detect that the inductor current remains at a low

value, as necessary for some functions like the CS pin

short−to−ground accidental protection. Re−using above

• Resistor R

has to be located as close as possible to CS

pin. Please see recommended layout at the end of this

document

OCP

• As detailed below, two external resistors adjust the

current thresholds (R

and R ), thus offering some

OCP

sense

example (R

= 30 mW, R

= 2 kW), the inrush level of

sense

OCP

flexibility on the R

selection which can be chosen for

sense

the input current is typically set to:

an optimal trade−off between noise immunity and losses.

2 @ 10³

30 @ 10^*3

• However the R

resistance must be selected higher or

I_(L(inrush)

+

@ 10 @ 10^*6^ 0.67 A

(eq. 9)

OCP

equal to 1.5 kW. If not, the protection against accidental

short−to−ground failures of the CS pin may trip and thus,

prevent operation of the circuit.

Abnormal Current Detection (Overstress)

When the PFC stage is plugged to the mains, the bulk

capacitor is abruptly charged to the line voltage. The charge

current (named in−rush current) can be very huge even if an

in−rush limiting circuitry is implemented. Also, if the

inductor saturates, the input current can go far above the

current limitation due to the reaction time of the overcurrent

protection. If one of these cases leads the internal CS pin

Over−Current Protection (OCP)

If I exceeds the OCP threshold (I

which is

CS

ILIMIT1

200 mA typically) an over−current situation is detected and

the MOSFET is immediately turned off (cycle−by−cycle

current limitation). The maximum inductor current can

hence be limited as follows:

current (I ) to exceed I

(set to 150% of I

), an

CS

ILIMIT2

ILIMIT1

R_OCP

abnormal current situation is detected, causing the DRV

output to be kept low for 800 ms after the circuit has dropped

below the in−rush level.

I_L(max)

+

I_LIMIT1

(eq. 7)

R_sense

As an example, if R

= 30 mW and R

= 2 kW, the

sense

OCP

maximum inductor current is typically set to:

I _CS

Over Current Limit

C_IN

I _ILIMIT1

To PWM

reset

Overstress

input

I _CS

i_in(t)

S

I _CS

Q

I _ILIMIT2

S

R

Q

R

CS

Negative clamp

800 ms

I_CS

overstress delay

I _CS

Inrush

I _inrush

R_OCP

R_sense

i_in(t)

Figure 8. Current Protections

2 @ 10³

30 @ 10^*3

Re−using above example (R

the overstress level of the input current is typically set to:

= 30 mW, R

= 2 kW),

sense

OCP

I_in(OVS)

+

@ 300 @ 10^*6+ 20 A

(eq. 10)

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15

NCP1618

Duty Ratio Control in CCM Mode

capacitor C is to be added across R to filter and remove

M

The NCP1618 re−uses the proven “predictive method”

scheme implemented in NCP1653 and NCP1654 CCM PFC

controllers. In other words, it directly computes the power

switch on−time as a function of the inductor current.

the switching frequency component of the V pin voltage.

M

Hence, replacing I by its function of the inductor current

CS

given by Equation 6, it comes:

V_RAMP,pk

R_sence

R_OCP

Practically, the I current is modulated by the control signal

V_M+ 0.4 @ R_M

@

@ 〈I_L〉_TSW

CS

(eq. 12)

V_REGUL

and sourced by the V pin to build the CCM current

M

Now, 〈I 〉 , the inductor current averaged over the

information. The V pin signal is:

L Tsw

M

switching frequency is the input current. Thus, Equation 12

can be changed into:

V_RAMP,pk

V_M+ 0.4 @ R_M

@

@ I_CS

(eq. 11)

V_REGUL

V_RAMP,pk

R_M@ R_sense

Where V

, V

and R respectively are the

V_M+ 0.4 @

@

@ i_in(t)

REGUL

RAMP,pk M

(eq. 13)

R_OCP

V_REGUL

regulation voltage (derived from V

), the CCM

CONTROL

oscillator peak value and the V pin resistor. Actually, a

M

CCM Oscillator Ramp

Generation

V

of the V pin

M

RAMP,pk

current

RAMP

CLOCK

Clock

S

R

DRV

Q

V_RAMP,pk

v_RAMP

(t)

I_M+ 0.4 @ I_CS

@

V_REGUL

+

R_M

C_M

v

(t)

−

M

V_RAMP,pk

Figure 9. Duty Ratio Control in CCM Mode

Figure 9 sketches the manner the duty ratio is controlled

in CCM.

Like in the NCP1653/4 controllers, when the power

switch on−time starts, an oscillator ramp is added to the V

The CCM regulation voltage (V

the regulation control signal provided by the

“transconductance error amplifier and compensation”

) is proportional to

REGUL

internal block (V

) as follows:

M

CONTROL

pin voltage and the power switch opens when the sum

reaches the oscillator upper threshold. Doing so, if V

• (V

) in low−line conditions (see the “Line Range

Detection” section)

CONTROL

RAMP,pk

designates the peak value of the oscillator ramp, the V

M

• (V

/ 4) in high−line conditions (see the “Line

CONTROL

voltage and the on−time (t ) are linked as follows:

on

Range Detection” section)

Hence, the CCM input power expression is:

t_on

_@ǒ_{1 *}Ǔ

V_M+ V_RAMP,pk

(eq. 14)

T_SW

• Low−line conditions:

2

Now, the off−duty−ratio of a boost converter operated in

2.5 @ R_OCP@ V_in,rms

V_CONTROL

P_in,avg

+

@

CCM is:

(eq. 17)

(eq. 18)

R

_M@ Rsence

V_out

v_in(t)

V_out

t_on

• High−line conditions:

d_off+ 1 *

+

(eq. 15)

T_SW

2

0.625 @ R_OCP@ V_in,rms

V_CONTROL

Combining Equations 13, 14 and 15, the following

expression of the input current is obtained:

P_in,avg

+

@

R

_M@ Rsence

V_out

NOTE: The R resistance must be selected higher than

M

R

_OCP@ V_REGUL

R_M@ R_sence

v_in(t)

V_out

i_in(t) + 2.5 @

@

4.5 kW. If not, the circuit may not be able to

(eq. 16)

charge the V pin to SKIP threshold (V

).

M

SKIP(th)

The input current is as targeted proportional to the input

voltage.

www.onsemi.com

16

NCP1618

N_AUX

ZERO CROSSING DETECTION BLOCK

ǒ

_(t)Ǔ

@ v_in

The NCP1618 optimizes the efficiency by turning on the

MOSFET at the very valley when operating in critical and

discontinuous conduction modes. For this purpose, the

circuit is designed to monitor the voltage of a small winding

taken off of the boost inductor. This auxiliary winding

(called the “zero current detector” or ZCD winding) gives a

scaled version of the inductor voltage which is easily usable

by the controller. The PFC stage being a boost converter, this

auxiliary winding voltage provides:

N_P

during the on−time, so that during the demagnetization time,

capacitor C charges to

2

N_AUX

N_P

ǒǒ

_(t))Ǔ₎ǒ

_(t)ǓǓ

(V_out* v_in

@ v_in

N_P

,

that is,

N_AUX

ǒ

Ǔ

@ V_out

N_AUX

N_P

.

_•ǒ_*

_(t)Ǔ

@ v_in

N_P

This circuitry hence provides a solid ZCD signal even if the

input voltage is close to the output voltage. Also, a voltage

representative of the output is obtained for an accurate

over−voltage protection. As detailed in application note

AND90012 (http://www.onsemi.com/pub_link/Collateral/

AND90012−D.PDF), the time constants can be selected as

follows in the case of 50 or 60 Hz line:

during the MOSFET conduction time

N_AUX

_•ǒ

_(t))Ǔ

(V_out* v_in

N_P

during the demagnetization time. This voltage used to

detect the zero current detection can be small when the

input voltage is nearly the output voltage.

R

₇@ C₂^ 500 ns

• A voltage oscillating around zero during dead−times

Application note AND90011 discusses recommended

circuitries for an accurate ZCD and OVP2 detections. Figure

(eq. 19)

(R₇) R₆) @ C₂^ 600 ms

(eq. 20)

10 provides one of these circuitries. In this circuit, R being

7

Diode D ensures that when the auxiliary winding drops,

the ZCD/OVP2 pin gets below the ZCD lower threshold

2

small, capacitor C is charged to

2

(V

).

ZCD(th)L

D7

D6

N * V

out

+

C2

R7

−

DT

S

R

C5

I

< I

inrush

CS

Q

S

R

Q

V

/ V

R5

ZCD(th)H

f

sw,min

ZCD(th)L

ramp

D5

reset

D8

R6

ZCD

Auxiliary

winding

DRV

C3

OVP2 (NCP1618A only)

800 ms interruption

+

−

V

OVP2

Latch−off

V

FB

< V

DRE−L

Figure 10. Zero Current Detection Block

Figure 10 shows how the NCP1618 detects the valley.

An internal comparator detects when ZCD pin voltage

a signal that is low when the ZCD pin voltage is higher than

the V upper voltage reference of the ZCD comparator.

ZCDH

exceeds an upper threshold V

(1 V typically). When

As a result, V

that is the AND combination of both

ZCDH

DMG

this is the case, the inductor core is resetting and the ZCD

latch is set. This latch will be reset when the next driver pulse

occurs. Hence the output of the latch remains high during the

whole off−time (demagnetization time + any possible dead

time). The output of the comparator is also inverted to form

signals is high when the ZCD pin voltage drops below the

lower threshold of the ZCD comparator, that is, at the

auxiliary winding falling edge. It is worth noting that as

portrayed by Figure 11, V

is also representative of the

AUX

MOSFET drain−source voltage (“V ”). More specifically,

DS

www.onsemi.com

17

NCP1618

when V

voltagev (t)). That is why V

so that the MOSFET turns on when its drain−source voltage

is low. Valley switching reduces the losses and interference.

is below zero, V is minimal (below the input

DS

• If the pin is grounded, no falling edge of the auxiliary

winding can be detected. The DRV remains off until the

DCM minimum frequency ramp initiates a new cycle.

Before the new pulse is generated, the circuit senses the

pin impedance by sourcing 250 mA. No DRV pulses are

AUX

is used to enable the driver

in

DMG

IMPORTANT NOTES:

generated until the pin voltage exceeds V

the part is inhibited when the pin is grounded. Not to

trigger this protection, the pin impedance (for instance R

of Figure 10. must be higher than 7.5 kW).

. Hence,

• Some options (see Table 1) does not feature the OVP2

protection. In this case, a simple resistor (or two series

ones if required to pass safety tests) can be used between

the auxiliary winding and the ZCD pin as shown by Figure

ZCDH

3

The ZCD pin is shortly grounded when the MOSFET

turns off (ZCD leading edge blanking − LEB). The LEB of

100 ns typical, is implemented to prevent the OVP2

comparator from tripping due to turn−off noise.

2 where R

denotes this resistor.

ZCD1

• The ZCD pin impedance (for instance R of Figure 10),

3

must be higher than 7.5 kW not to trigger the ZCD pin

short−to ground protection.

If no ZCD can be detected when the circuit operates in

FCCrM mode, the circuit cannot use the valley detection to

start a new current cycle. In this case, the next DRV pulse is

OVP2

The ZCD pin signal (V

fault.

Practically, it is compared to V

) can be used to detect an OVP

ZCD

forced by the DCM minimum frequency ramp (f

of Figure 10) which acts as a watchdog.

ramp

sw,min

(4 V typically). If

OVP2

V

ZCD

exceeds V

, the PFC stage stops operating for

OVP2

800 ms. In addition, if when an OVP2 fault is detected, the

FB voltage is below V , that is the threshold below

DRE−L

which the dynamic response enhancer trips (95.5% of V

REF

typically), the circuit detects that one of two networks for

output voltage sensing is wrong. As a consequence, the

circuit latches off. See Figure 9.

OUTPUT VOLTAGE CONTROL (REGULATION

BLOCK)

The general structure is sketched by Figure 12.

A small 250 nA sink current is built−in to pull down the

pin if the FB pin is accidentally open. In this case, V being

FB

less than V

(300 mV typically), the UVP protection trips

UVP

and thus, protects the circuit if the FB pin is floating.

The fast OVP comparator is analogue and directly

monitors the feedback pin voltage. The rest of the block

which is digital, receives a digitized feedback value. The

sampling rate is 10 kHz.

The digital “transconductance error amplifier and

compensation” block provides the control signal V

(which is devoid of the PFC stage 120 or 100 Hz ripple) to

control the duty ratio.

CONTROL

Figure 11. Zero Current Detection Timing Diagram

(V_AUXis the Voltage Provided by the ZCD Winding)

Practically, the signal V

does dictate the on−time.

only in the case of a

REGUL

Note that the circuit can detect faulty conditions of the

ZCD pin:

• A permanent 1 mA current source pulls up the pin if it

happens to be floating. The circuit is hence maintained off

V

differs from V

REGUL

CONTROL

soft−OVP event (see “soft−OVP” paragraph) and in CCM

when in high line where (V

= V

/ 4). In all

REGUL

CONTROL

other cases, (V

= V

).

REGUL

CONTROL

www.onsemi.com

18

NCP1618

V

out

PWM latch

Fast OVP

Detection

SoftOVP

Soft OVP

Detection

R

FB1

Soft−Stop

HL

FB

Transconductance

Error Amplifier and

compensation

Regulation

Signal

Generation

V_CONTROL

staticOVP

V_REGUL

S/H

I

STBY

DRE

B(FB)

CCM

HL

R

FB2

Dynamic

Response

Enhancer

Bulk Under−

Voltage

BUV

Detection

OFF

UVP

To soft−SKIP block

Detection

To pfcOK block

Figure 12. Regulation Circuitry

StaticOVP

Output Voltage Levels

The regulation block and the soft−OVP, UVP and DRE

The circuit stops providing DRV pulses when V

CONTROL

comparators monitor the FB pin voltage. Based on the

reaches its bottom level.

typical value of their parameters and if (V

output voltage nominal value (e.g., 390 V), we can deduce

the following typical levels:

)is the

out,nom

fastOVP Comparator

+

• Output Regulation Level: V

= V

/ k

FB

−

107% Vref

out,nom

REF

fastOVP

S

Q

• Output Soft−OVP Level: V

• Output Fast−OVP Level: V

• Output UVP Level: V

= 105% · V

out,nom

out,SOVP

out,FOVP

Q

= 107% · V

= 12% · V

out,nom

OVPout Comparator

out,UVP

out,nom

R

−

• Output DRE Level: V

= 95.5% · V

out,nom

out,DRE

+

FB

103% Vref

• Output BUV Level: V

= 72% · V

out,nom

OVPout

out,BUV

• Output Upper Soft−SKIP Level:

(V ) = 103% · V

out,softSKIP H

out,nom

softOVP Comparator

• Output Lower Soft−SKIP Level:

(V ) = 98% · V

+

out,softSKIP L

out,nom

−

105% Vref

Where:

S

softOVP

Q

• V

is the regulation reference voltage (2.5 V typically)

REF

Q

• R

and R

are the feedback resistors (see Figure 1).

FB1

FB2

250 nA

• k is the scale down factor of the feedback resistors

R

FB

R_FB2

ǒ_k

Ǔ

.

+

OVPout

FB

R

_FB1) R_FB2

Figure 13. Fast and Soft OVP Protections

• V

and V

are the levels between

out,softSKIP−H

out,softSKIP−L

which the output voltage swings when in soft−SKIP mode

(see the “Soft−SKIP Mode” section)

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19

NCP1618

Soft−OVP

• Step 3: V

400 ms

drops to 25% of the V

value for

REGUL

CONTROL

As sketched by Figure 13, the soft−OVP trips when the

feedback voltage exceeds 105% of V and remains in this

mode until V drops below 103% of V . When the

soft−OVP trips, it reduces the power delivery down to zero

in 4 steps:

REF

• Step 4: V

drops and remains to 0 until the

REGUL

FB

REF

soft−OVP fault is over, that is, when the output voltage

drops below 103% of its regulation level.

• Step 1: V

400 ms

drops to 75% of the V

value for

FastOVP

REGUL

CONTROL

As sketched by Figure 13, the fast−OVP trips when the

feedback voltage exceeds 107% of V and remains in this

mode until V drops below 103% of V . The drive is

REF

• Step 2: V

400 ms

drops to 50% of the V

REGUL

FB

REF

immediately stopped when the fast OVP is triggered.

105% · V

OUT,NOM

V

OUT

103% · V

V

OUT,NOM

time

Soft−OVP

V

CONTROL

(V

)

CONTROL 0

The regulation loop decreases V

CONTROL

(V

)

(quantization steps are not shown)

CONTROL 1

time

75% · V

CONTROL

V

REGUL

50% · V

CONTROL

25% · V

CONTROL

V

= (V

)

REGUL

CONTROL 0

0% · V

CONTROL

400 ms

V

= (V

)

REGUL

CONTROL 1

400 ms

time

Figure 14. Soft−OVP

Dynamic Response Enhancer

• A line−sag or a brownout fault is detected

• A BUV fault is detected

• When in soft−SKIP mode, the output voltage reaches its

upper threshold, the active phase of the burst ends. At that

moment, soft−stop leads to a gradual stop of the power

delivery and a smooth idle phase start for a minimized risk

of audible noise.

The NCP1618 embeds a “dynamic response enhancer”

circuitry (DRE) which firmly contains under−shoots. An

internal comparator monitors the feed−back voltage on pin 1

(V ) and when V is lower than 95.5% of the regulation

FB

reference voltage (V ), it speeds−up the charge of the

REF

compensation network. Practically a 10x increase in the loop

gain is forced until the output voltage has reached 98% of its

nominal value.

A soft−skip sequence is terminated when V

CONTROL

reaches its bottom level. In the soft−SKIP case, the soft−stop

sequence is also immediately ended when the output voltage

drops below the restart level, so that the restart of operation

Soft−Stop Sequences

A soft−stop sequence is forced when the circuit must stop

operating in a smooth manner to prevent bouncing effects

possibly resulting from an abrupt interruption. Soft−stop

is not delayed until the total V

discharge.

CONTROL

gradually reduces V

to zero, in the following cases:

CONTROL

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20

NCP1618

SOFT−SKIP MODE

As detailed in application note AND90011

(http://www.onsemi.com/pub_link/Collateral/AND90011−

D.PDF), the circuit is designed to be externally forced to

enter the soft−SKIP mode by applying negative pulses on

either the pfcOK pin or the V pin. In CCM mode, the V

pin provides the current information necessary to modulate

The soft−SKIP mode can also be triggered by generating

a negative pulse on the pfcOK pin. To do so, the pfcOK pin

must be pulled down below V

(0.4 V min) for T

SKIP2

(33 ms max) or more. Note that in this case, the pfcOK signal

may have to be filtered before being applied to the

downstream converter so that the negative pulses do not stop

its operation. Figure 15 illustrates a possible implementation

with ON Semiconductor LLC controller NCP13992.

M

the duty−ratio. In CrM and DCM modes of operation, this

pin is pulled−up to V

(2.5 V typically). If the pin is

M,DCM

externally forced below V

(1.5 V typically) for 100 ms

SKIP(th)

or more, the circuit enters the soft−SKIP mode.

NCP13992

BO

R2

C3

NCP13992

Pmode

NCP1618

pfcOK

D2

C1

D1

4.7 V

C2

R1

Grounding pulses

generation

Figure 15. Circuitry to Control the Soft−SKIP Mode

When the V or pfcOK pins receive a grounding pulse, the

circuit detects a soft−SKIP condition. As a result, as

illustrated by Figure 16, the NCP1618:

• When the output voltage drops below 98% of its nominal

voltage (98% * V ), the circuit exits the deep idle

M

out,nom

mode. Operation resumes and the output voltage charges

up to 103% of its nominal voltage again.

• First charges up the output voltage to 103% of its nominal

voltage (103% V

).

out,nom

• When the output voltage reaches 103% of its nominal

• Then, enters a soft−stop sequence to gradually reduce the

line current and thus minimize the risk of audible noise.

If the output voltage reaches the soft−OVP level (105%

voltage, there are two possibilities:

♦ The V or the pfcOK pins have received a grounding

M

pulse during this latest charge to 103% V

. In this

out,nom

V

), the protection trips and the 4−step stop

case, the circuit remains in soft−SKIP mode, i.e., the

circuit enters a new deep idle mode phase at the end of

the soft−stop (or the 4−step stop) sequence.

out,nom

illustrated by Figure 14 takes place.

• When the soft−stop sequence (or the 4−step stop) is

finished, the circuit enters the deep idle mode: the part

stops switching and all the non−necessary circuitries are

turned off so that the circuit consumption is reduced to a

♦ The V or the pfcOK pins have not received a

M

grounding pulse during this latest charge to 103%

V

. In this case, the circuit recovers the normal

out,nom

operation until the V or pfcOK pins receive a

minimum (I = I

no energy is provided to the bulk capacitor, the output

voltage decays.

which is 250 mA typically). Since

M

CC

CC3

grounding pulse

103% V_out,nom

V_out

98% * V_out,nom

I_LINE

5 s

Figure 16. Soft−SKIP Operation

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21

NCP1618

NOTES:

is in nominal operation and grounded when the PFC stage is

in start−up phase or in a fault condition. Using the pfcOK

signal to enable/disable it, the downstream converter can be

optimally designed for the narrow voltage range nominally

provided by the PFC stage in normal operation.

Practically, the pfcOK pin is grounded when the PFC stage

enters operation and remains in low state until the output

voltage has nearly reached its nominal level (practically

• The circuit cannot enter the soft−SKIP mode when it

operates in CCM.

• The soft−stop sequence is interrupted if not finished when

the output voltage reaches the soft−SKIP bottom

threshold (V

) so that the circuit can resume normal

out,nom

operation.

• When in soft−SKIP mode, the NCP1618 is prevented

from entering CCM during the active burst. This is to

minimize the risk of audible noise by limiting burst

energy. However, if during the soft−SKIP active burst, a

sudden load increase causes the output voltage to drop

when V reaches 98%V ). At that moment, the pfcOK

FB

REF

pin sources a current proportional to the feedback voltage

(k · V ). See Figure 17. Placing an external resistor

FB

between the pfcOK and GND pins, we obtain a voltage

V

pfcOK

which is proportional to the bulk voltage and can

below the DRE level (95.5% of V

) while V pin is

out,nom

M

serve as a feedforward signal for the downstream converter.

k typical value is 10 mA/V so that the pfcOK pin typically

sources 25 mA when the FB voltage is 2.5 V (regulation

level).

Conversely, when a major fault is detected (brown−out,

UVLO, Thermal shutdown, OVP2 latch off, UVP and

BUV), the internal OFF signal turns high and the pfcOK pin

is grounded to prevent the downstream converter from

operating in the abnormal conditions causing these faults.

above 1.5 V, the circuit can enter CCM if necessary to

deliver the power. Such a situation normally occurring

when the application gets loaded, the circuit will leave the

soft−SKIP mode at the end of this burst when the output

voltage is charged to 103% V

.

out,nom

pfcOK SIGNAL

The pfcOK pin is designed to control the operation of the

downstream converter. It is in high state when the PFC stage

FB

VDD

−

+

k * V_FB

+

−

V_BUV

BUV

S

R

pfcOK_int

Q

LLC BO pin

C1

pfcOK

R1

V_STBY

+

STBY_init1

BUV Delay

−

pfcOK_in

V_FB> 98% V

pfcOK_int

REF

Line_Recovery

S

Q

R

OFF

Figure 17. pfcOK Block

In particular, when the feedback voltage drops below the

internal reference (1.8 V typically), a BUV fault is

detected (BUV stands for Bulk Under−voltage).

• When the soft−stop sequence ends, the PFC stops

operating until the T delay has elapsed (515 ms

V

BUV

typically). However, if the BUV protection trips during a

line sag condition, the T delay is bypassed and

Corresponding output voltage BUV threshold is:

BUV

V_BUV

operation immediately resumes when the line recovers.

The wakeup information is provided by signal

“Line_Recovery” generated by the line−sag block (see

Figure 20). This enables a rapid operation recovery when

the line fault is over.

V_out,BUV

+

@ V_out,nom

(eq. 21)

V_REF

When a BUV fault is detected:

• The pfcOK pin is grounded

• A soft−stop sequence is started during which the power

delivery gradually drops to zero

www.onsemi.com

22

NCP1618

INPUT VOLTAGE SENSING

The high voltage (HV) pin is a multi−functional pin,

which in addition to the startup current source, provides

access to the brownout, line sag, line range detectors and X2

capacitor discharge. The brownout / line−sag detector

detects too low line levels and the line range detector

determines the presence of either 110 V or 220 V ac mains.

Depending on the detected input voltage range, the

NCP1618 internally adjusts device parameters to optimize

the system performance. Line and neutral are diode “ORed”

before connecting to the HV pin as shown in Figure 17. The

diodes prevent the pin voltage from going below ground.

Whatever the HV input connection is, a small resistor (R

)

HV

in series with the diodes can limit the current during transient

events. This resistor (of 1 or 2 kW for instance, 3 kW

maximally), must be low enough. If not, the HV pin voltage

may drop below HV

(38 V) during the VCC charge

MIN

phase because of the voltage drop the start−up current

generates across R . In such a case, the start−up current

HV

source may reduce, leading to a longer V charge. Also,

CC

R

HV

must be able to dissipate the power produced by the

startup current when the NCP1618 charges up the V

capacitor.

CC

Ac line

FB

HV

FB

HV

1

2

3

4

5

10

1

2

3

4

5

10

EMI

Filter

EMI

Filter

Vcc

pfcOK

Vm

Vcc

pfcOK

Vm

8

7

6

8

7

6

DRV

GND

CS

DRV

GND

CS

ZCD

a) The line terminals are sensed

b) The input voltage is sensed

Figure 18. High−Voltage Input Connection

LINE−SAG DETECTION

The line−sag detection block detects short mains

interruption to prevent an excessive stress when the line is

back. As sketched by Figure 19, a line−sag situation is

Tests can be made which consist of rapidly and repeatedly

plug and unplug the power supply. If no specific function is

implemented, a huge current can take place when the power

supply is powered. This is because during the mains

detected when the input voltage remains below V

for

BO(stop)

T

.

SAG(blank)

interruption, V

dramatically rises since no more

CONTROL

power can be delivered to the output.

+

V

HV

BO_NOK

−

+

T

BO(blank)

V

if BO_NOK is high

if BO_NOK is low

BO(start)

V

reset

BO(stop)

+

SAG

−

T

SAG(blank)

V

if SAG is high

if SAG is low

BO(start)

V

reset

BO(stop)

Figure 19. Line−Sag and Brown−Out Detection

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23

NCP1618

When a line−sag condition is detected, the NCP1618 starts

a soft−stop sequence to gradually discharge V

Figure 21 shows typical power−up waveforms. The

brownout timer (t

) is enabled once V drops

CONTROL

BO(blank)

HV

down−to−zero and hence, to smoothly stop operation. It also

disables the CCM mode to reduce more rapidly the power

delivery during the line−sag period. When the line recovers,

it is required to restart the operation as soon as possible and

in a clean manner. Signal “Line_Recovery” of Figure 20

provides the wakeup information.

below the lower brownout threshold, V

and a

BO(stop)

brown−out fault is detected if V doesn’t exceed V

HV

before the brownout timer expires. The timer is set long

enough to pass line−dropout tests.

Figure 21 illustrates a line−dropout event.

The circuit operates normally and suddenly, the line

reduces to a low level. Due to the dropout, the HV voltage

drops below the V

is started and a brown−out fault is detected since the HV

voltage has remained below V until the timer

expires. As a result, the PFC stage stops operating and the

pfcOK pin is grounded. If as sketched in Figure 21, no

external power source maintains the V

swings between V

recovers, the circuit does not immediate resume operation

but first turns on the HV startup to charge V up to V

so that a clean restart is obtained. If V is already higher

level. The blanking time t

BO(stop)

BO(blank)

SAG

BO(start)

Line_Recovery

S

L_SAG

R

Q

voltage, V

CC

and V

.When the line

CC(off)

CC(on)

CC

CC(on)

Few ms delay

CC

than V

immediately.

when the line recovers, the NCP1618 restarts

CC(on)

Figure 20. “Line_Recovery” Signal

In Figure 21, it is assumed that V is maintained by the

downstream converter until pfcOK drops to zero. It is also

CC

The signal “Line_Recovery”:

supposed that the output voltage remains above the bulk

• Resets the BUV timer. It is because a long line−sag event

is likely to cause a BUV detection. When a BUV fault is

detected, no restart is possible until the BUV timer has

elapsed. If a BUV fault is detected during a line−sag

sequence, we want operation to be resumed as a soon as

the line recovers (see Figure 17).

under−voltage threshold – V

– when the BO fault is

out,BUV

detected. If a BUV fault had been detected before the

brown−out timer elapsed, the pfcOK pin would have already

been grounded when the BO fault is detected. The DRV

pulses shown after the line−sag illustrate the soft−stop

sequence. Note that when in high state, the pfcOK signal is

proportional to the output voltage. Its gradual decay during

the main dropout is representative of the output voltage drop

until the BO fault is detected causing the pfcOK grounding.

• Interrupts the soft−stop discharge if not completed and

ground V

for a clean start−up.

CONTROL

BROWN−OUT PROTECTION

The controller is enabled once V is above the upper

HV

brownout threshold, V

, and V reaches V

.

BO(start)

CC

CC(on)

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24

NCP1618

V

BO(start)

V

BO(stop)

HV

time

V

CC(on)

V

CC(off)

CC

time

t

BO(blank)

pfcOK

DRV

t

SAG(blank)

time

Figure 21. Brown−Out Sequence (In this Figure, it is Assumed that V_CCis Maintained by the Downstream

Converter until pfcOK Drops to Zero)

LINE RANGE DETECTION

The input voltage range is detected based on the peak

voltage measured at the HV pin.

X2 CAPACITORS DISCHARGE

Safety agency standards require the input filter capacitors

to be discharged once the ac line voltage is removed. A

resistors network is the most common method to meet this

requirement. Unfortunately, such a solution consumes

power across all operating modes and these losses are

generally unacceptable when high efficiency is required in

light− and no−load conditions.

The NCP1618 integrates an active circuitry to discharge

the input filter capacitors upon removal of the ac line

voltage. The line removal detection circuitry is always

active to ensure safety compliance.

The controller compares V

to the high−line select

HV

threshold, V

, typically 236 V. A blanking time

lineselect(HL)

T

of 300 ms typically, prevents erroneous detection

filter(HV)

due to noise. Once V

exceeds V

, the PFC

HV

lineselect(HL)

stage operates in “high−line” (Europe/Asia).

The controller switches back to “low−line” mode if V

HV

remains below V

(which is 222 V typically, i.e.,

lineselect(LL)

14 V less than V

, thus offering an hysteresis) for

lineselect(HL)

the t timer delay (25 ms typically).

line

If the controller transitions to “low−line”, it is prevented

from switching back to “high−line” until the lockout timer

The line removal is detected by digitally sampling the

voltage present at the HV pin, and monitoring its slope. As

t

(typically 500 ms), expires. The timer and logic

illustrated by Figure 22, a timer, t

, is used to

line(lockout)

line(removal)

is included to prevent unwanted noise from toggling the

operating line level.

The line range detection circuit optimizes the operation

for universal (wide input mains) applications. Practically, in

“high−line”:

detect when the slope of the input signal is below the

resolution level. The timer is reset any time a positive or

negative slope is detected. Once the timer expires, a line

removal condition is acknowledged initiating an X2

capacitor discharge. In this case, the HV pin sinks

I_{HV(discharge)}, the drive is disabled and the pfcOK signal

transitions low.

• The regulation bandwidth and the CCM gain are divided

by 4

• The V

below which frequency foldback starts is

CONTROL

reduced by 2.

www.onsemi.com

25

NCP1618

AC Line Unplug

V_HV

Downslope

Doesn¶t

Reset

Timer

time

Downslope

Doesn¶t

Reset

Upslope Downslope

Upslope

Resets

Timer

Upslope

Resets

Timer

Resets

Timer

Resets

Timer

Line Timer

Expires /

Discharge Begins

Timer

t_{line(removal )}

Figure 22. Line Removal Detection Timing

The discharging process continues until the voltage at HV

pin (across the X2 capacitor) is lower than the V

capacitors in the input line filter to a safe level – refer to

Figure 23.

HV(discharge)

level. This feature allows the device to discharge large X2

HV Capacitor

Discharge

V_HV

AC Line Unplug

Discharge Rate

Decreases

Discharge

Complete

V_{HV(discharge )}

time

Upslope Downslope

Upslope

Line

Resets

Timer

Resets

Timer

Resets

Timer

Expires

Timer

t_{line (removal )}

t_{line(removal )}

DRV

Discharge

Current

Pinches Off

time

HV Discharge

Device is stopped

HV Discharge

Current

I_{HV(discharge )}

Figure 23. X2 Discharge Timing

It is important to note that the HV pin cannot be connected

to any dc voltage due to this feature, i.e. directly to bulk

capacitor. The diodes connecting the AC line to the HV pin

must be placed after the system fuse.

www.onsemi.com

26

NCP1618

Figure 24. HV Pin Connection for X2 Capacitor Discharging Function

The HV pin can directly receive the voltage provided by

diodes as shown by Figure 3. However, it can be useful to

place a resistor (R ) in series with the HV pin to improve

• BONOK: a brown−out fault is detected (too low a line

voltage for proper operation).

• BUV: too low a bulk voltage is detected for proper

operation of the downstream converter.

HV

surge immunity. The R resistance must remain low. This

HV

is because as aforementioned the discharge phase ends when

• TSD: The thermal shutdown protection stops the circuit

the HV voltage goes below V

. At this point, still

HV(discharge)

operation when the junction temperature (T ) exceeds

J

considering the Figure 24 connection, the actual voltage

across the line filter capacitor is:

150°C typically. The controller remains off until T goes

J

below nearly 100°C.

V

+ (R * I

) + 2*V

HV(discharge)

HV HV(discharge) F

• UVLO: Incorrect feeding of the circuit (refer to the

STARTUP SEQUENCE / VCC MANAGEMENT

section)

where V is the forward voltage of the conducting diodes.

F

In the event that line voltage is reapplied during a

discharge phase, the circuit will simply continue to

discharge until the line zero crossing occurs, at which point

V_HVwill drop to V_{HV(discharge)}and a new start−up cycle will

commence.

• UVP: an Output Under−Voltage situation is detected

when V is less than V

(12% of V , typically)

REF

FB

UVP

• STDWN: if an OVP2 condition is detected on the ZCD

pin while the FB pin voltage is not above V (95.5%

DRE−H

of V , typically), the circuit latches off.

REF

OFF MODE

The circuit turns off when the circuit detects one of the

following major faults:

TSD

OFF

UVP

UVLO

STDWN

staticOVP

BONOK

BUV

S

Soft−Stop

Q

SKIP

R

StaticOVP

Figure 25. Faults Leading to the OFF Mode

www.onsemi.com

27

NCP1618

When one of the TSD, UVP, UVLO and STDWN faults

is detected, the part immediately turns off:

so that the UVP protection trips and prevents the circuit

from operating if this pin is floating. This current source

is small (450 nA maximum) so that its impact on the

output regulation and OVP levels remain negligible with

the resistor dividers typically used to sense the bulk

voltage.

• The DRV pin is disabled.

• The pfcOK pin is grounded

• The circuit consumption drops to I

CC1

When a BUV fault is detected, pfcOK immediately turns

low to disable the downstream converter but the part does

not stop operating. Instead, a soft−stop sequence is forced to

gradually decay the power delivery until the staticOVP level

is reached. At that moment, the circuit turns off.

• Improper connection of the ZCD pin

The ZCD pin sources a 1 mA current to pull up the pin

voltage and hence disable the part if the pin is floating. If

the ZCD pin is grounded before operation, the circuit

cannot monitor the ZCD signal and no DRV pulse can be

generated until the DCM minimum frequency ramp has

elapsed. At that moment, the circuit sources a 250 mA

current source to pull−up the ZCD pin voltage. No drive

pulse is initiated until the ZCD pin voltage exceeds the

ZCD 1 V threshold. Hence, if the pin is grounded, the

circuit stops operating. Circuit operation requires the pin

impedance to be 7.5 kW or more, the tolerance of the

NCP1618 impedance testing function being considered

over the −405C to 1255C temperature range.

When a BONOK fault is detected, pfcOK keeps high and

the part enters a soft−stop sequence to gradually decay the

power delivery until the staticOVP level is reached. At that

moment, the circuit turns off leading the drive pin to be

disabled, the pfcOK output to be grounded and the circuit

consumption to be reduced.

In the OFF mode, if it is not maintained by an external

power source, V cycles up and down between the V

CC

CC(on)

and V

levels. When the fault having caused the off

CC(off)

mode is removed, the circuit does not recover until V

CC

reaches V

. Practically:

• Improper connection of the CS pin

CC(on)

A comparator to 250 mV senses the CS pin. If the CS pin

exceeds this level for 1 or 2 ms, the part is off for the 800 ms

delay time. In addition, the CS pin sources a 1 mA current

to pull up the pin voltage and hence disable the part if the

pin is floating. The CS short−to−ground is also detected

as follows: whenever the input voltage is higher than the

• The circuit immediately restarts if V is above V

CC

CC(on)

• If when the fault is removed, V is below V

and the

CC

CC(on)

start−up current source is on, the circuit continues

charging V and resumes operation when V exceeds

CC

V

.

CC(on)

• If when the fault is removed, V is below V

and the

CC

CC(on)

brown−out threshold and no I current higher than

CS

start−up current source is off, the circuit immediately

(without waiting for the V < V condition) enters

I

is detected at the end of a MOSFET conduction

in−rush

CC

CC(off)

phase (DRV high), the circuit sources a 250 mA current

source to pull−up the CS pin voltage. No drive pulse is

initiated until the CS pin voltage exceeds the 250 mV fault

threshold. Hence, if the pin is grounded, the circuit stops

operating. Circuit operation requires the pin impedance

to be 1.5 kW or more, the tolerance of the NCP1618

impedance testing function being considered over the

−405C to 1255C temperature range.

a V charging phase and resumes operation when V

CC

exceeds V

.

CC(on)

Figure 21 illustrates this recovering process in the case of

a brown−out case.

FAILURE DETECTION

When manufacturing a power supply, elements can be

accidentally shorted or improperly soldered. Such failures

can also happen to occur later on because of the components

fatigue or excessive stress, soldering defaults or external

interactions. In particular, adjacent pins of controllers can be

shorted, a pin can be grounded or badly connected. Such

open/short situations are generally required not to cause fire,

smoke nor big noise. The NCP1618 integrates functions that

ease meeting this requirement. Among them, we can list:

RECOMMENDED LAYOUT

The correct layout is key step towards to reliable operation

of designed application. The recommended layout of

NCP1618 PFC controller is illustrated in Figure 26. The

most important part of layout is connection components

between CS pin of IC and sensing power resistor. The

components, especially R_OCP2 has to be placed as close as

possible to CS pin to limit possibility of noise coupling to

high impedance trace.

• Floating feedback pin

A 250 nA sink current source pulls down the FB voltage

www.onsemi.com

28

NCP1618

Figure 26. Recommended Layout of NCP1618 PFC Controller

ORDERING INFORMATION

Device Order Number

NCP1618ADR2G

†

Specific Device Marking

Package Type

Shipping

NCP1618A

SOIC−9 NB

(Pb−Free)

2500 / Tape & Reel

NCP1618BDR2G

NCP1618CDR2G

NCP1618DDR2G

NCP1618FDR2G

NCP1618HDR2G

NCP1618JDR2G

NCP1618KDR2G

NCP1618B

NCP1618C

NCP1618D

NCP1618F

NCP1618H

NCP1618J

NCP1618K

SOIC−9 NB

(Pb−Free)

SOIC−9 NB

(Pb−Free)

SOIC−9 NB

(Pb−Free)

SOIC−9 NB

(Pb−Free)

SOIC−9 NB

(Pb−Free)

SOIC−9 NB

(Pb−Free)

SOIC−9 NB

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

29

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−9 NB

CASE 751BP

ISSUE A

9

1

DATE 21 NOV 2011

SCALE 1:1

2X

NOTES:

0.10

C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

D

H

A

2X

0.20

C

4 TIPS

0.10 C A-B

F

10

6

E

1

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

5

L2

A3

L

SEATING

PLANE

C

0.20

C

9X b

DETAIL A

B

5 TIPS

M

MILLIMETERS

0.25

C A-B D

DIM MIN

MAX

1.75

0.25

0.51

5.00

4.00

TOP VIEW

A

A1

A3

b

D

E

1.25

0.10

0.17

0.31

4.80

3.80

9X

h

X 45

_

0.10

C

0.10

C

M

e

1.00 BSC

H

h

5.80

0.37 REF

6.20

A

L

L2

M

0.40

0

1.27

0.25 BSC

DETAIL A

e

SIDE VIEW

A1

SEATING

PLANE

C

8

_

END VIEW

GENERIC

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT*

9

1.00

PITCH

9X

0.58

XXXXX

ALYWX

G

1

XXXXX = Specific Device Code

6.50

A

L

= Assembly Location

= Wafer Lot

Y

W

G

= Year

= Work Week

= Pb−Free Package

1

9X

1.18

DIMENSION: MILLIMETERS

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON52301E

SOIC−9 NB

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCP1618HDR2G
厂家：	ONSEMI
描述：	Multimode (CrM-CCM) Power Factor Controller, Active X2
文件：	总31页 (文件大小：1136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1618HDR2G [ONSEMI]

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