NCP164CMT180TAG [ONSEMI]
LDO Regulator, 300mA, Low Dropout Voltage, Ultra Low Noise, High PSRR with Power Good;
| 型号： | NCP164CMT180TAG |
| 厂家： | 
ONSEMI |
| 描述： | LDO Regulator, 300mA, Low Dropout Voltage, Ultra Low Noise, High PSRR with Power Good |
| 文件： | 总15页 (文件大小：566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LDO Regulator, 300ꢀmA,
Low Dropout Voltage, Ultra
Low Noise, High PSRR with
Power Good
NCP164C
www.onsemi.com
The NCP164C is a 300 mA LDO, next generation of high PSRR,
ultra−low noise and low dropout regulators with Power Good open
collector output. Designed to meet the requirements of RF and
sensitive analog circuits, the NCP164C device provides ultra−low
noise, high PSRR and low quiescent current. The device also offer
excellent load/line transients. The NCP164C is designed to work with
a 1 mF input and a 1 mF output ceramic capacitor. It is available in
industry standard TSOP−5, WDFN6 0.65P, 2 mm x 2 mm and
DFNW8 0.65P, 3 mm x 3 mm.
MARKING
DIAGRAMS
5
TSOP−5
CASE 483
XXXAYWG
5
G
1
1
WDFN6 2x2, 0.65P
CASE 511BR
Features
XXMG
G
• Operating Input Voltage Range: 1.6 V to 5.0 V
• Available in Fixed Voltage Option: 1.2 V to 4.5 V
• Adjustable Version Reference Voltage: 1.1 V
1
P164
XXX
ALYWG
G
DFNW8 3x3, 0.65P
CASE 507AD
•
2% Accuracy Over Load and Temperature
• Ultra Low Quiescent Current Typ. 30 mA
• Standby Current: Typ. 0.1 mA
1
XXX
A
L
M
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Month Code
= Year
• Very Low Dropout: 110 mV at 300 mA for 3.3 V Variant
• Ultra High PSRR: Typ. 85 dB at 10 mA, f = 1 kHz
• Ultra Low Noise: 9 mV
(Fixed Version)
RMS
= Work Week
= Pb−Free Package
• Stable with a 1 mF Small Case Size Ceramic Capacitors
• Available in – TSOP−5 3 mm x 1.5 mm x 1 mm CASE 483
♦ WDFN6 2 mm x 2 mm x 0.75 mm CASE 511BR
♦ DFNW8 3 mm x 3 mm x 0.9 mm CASE 507AD
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
(Note: Microdot may be in either location)
PIN CONNECTONS
OUT
1
2
3
6
5
4
IN
Typical Applications
ADJ/SNS
PG
GND
GND
EN
• Communication Systems
• In−Vehicle Networking
• Telematics, Infotainment and Clusters
• General Purpose Automotive
WDFN6 2x2 mm
(Top View)
V
IN
IN
OUT
NCP164C
C
C
OUT
IN
1 mF
Ceramic
1 mF
Ceramic
EN
PG
GND
ON
OFF
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
January, 2020 − Rev. 1
NCP164C/D
NCP164C
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
TSOP−5
Pin No.
WDFN6
Pin No.
DFNW8
Pin
Name
Description
1
5
6
1
8
1
IN
Input voltage supply pin
OUT
Regulated output voltage. The output should be bypassed with small 1 mF
ceramic capacitor
3
4
3
7
3
EN
PG
Chip enable: Applying V < 0.2 V disables the regulator, Pulling V > 0.7 V
EN EN
enables the LDO
4 / −
Power Good, open collector. Use 10 kW to 100 kW pull−up resistor connected to
output or input voltage
2
− / 4
−
5
2
2
6
2
2
GND
ADJ
SNS
Common ground connection
Adjustable output feedback pin (for adjustable version only)
Sense feedback pin.
Must be connected to OUT pin on PCB (for fixed versions only)
−
−
−
4, 5
N/C
Not connected, pin can be tied to ground plane for better power dissipation
Expose pad should be tied to ground plane for better power dissipation
EPAD
EPAD
EPAD
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage (Note 1)
V
IN
−0.3 to 5.3
Output Voltage
V
OUT
−0.3 to V +0.3, max. 5.3
V
IN
Chip Enable Input
V
−0.3 to 5.3
−0.3 to 5.3
30
V
CE
PG
PG
Power Good Voltage
V
V
Power Good Current
I
mA
s
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
t
unlimited
150
SC
T
°C
°C
V
J
T
STG
−55 to 150
2000
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
ESD
ESD
HBM
1000
V
CDM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per EIA/JESD22−C101, Field Induced Charge Model
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2
NCP164C
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
THERMAL CHARACTERISTICS, TSOP−5 PACKAGE
Thermal Resistance, Junction−to−Ambient (Note 3)
Thermal Resistance, Junction−to−Case (top)
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
Thermal Resistance, Junction−to−Board
Characterization Parameter, Junction−to−Top
Characterization Parameter, Junction−to−Board
R
158
155
102
197
40
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
q
JA
R
q
JC(top)
R
q
JC(bot)
R
q
JB
Y
JT
JB
Y
82
THERMAL CHARACTERISTICS, WDFN6−2X2, 0.65 PITCH PACKAGE
Thermal Resistance, Junction−to−Ambient (Note 3)
Thermal Resistance, Junction−to−Case (top)
R
51
142
2.0
117
1.9
7.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
q
JA
R
R
q
q
JC(top)
JC(bot)
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
Thermal Resistance, Junction−to−Board
R
q
JB
Characterization Parameter, Junction−to−Top
Y
JT
JB
Characterization Parameter, Junction−to−Board
THERMAL CHARACTERISTICS, DFNW8−3X3, 0.65 PITCH PACKAGE
Thermal Resistance, Junction−to−Ambient (Note 3)
Thermal Resistance, Junction−to−Case (top)
Y
R
50
142
7.9
125
2.0
7.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
q
JA
R
R
q
q
JC(top)
JC(bot)
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
Thermal Resistance, Junction−to−Board
R
q
JB
Characterization Parameter, Junction−to−Top
Y
JT
Characterization Parameter, Junction−to−Board
Y
JB
3. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
4. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
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3
NCP164C
Table 4. ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 150°C; V = V
+ 0.5 V; I = 1 mA, C = C
OUT IN OUT
J
IN
OUT(NOM)
= 1 mF, V = V , unless otherwise noted. Typical values are at T = +25°C (Note 5))
EN
IN
J
Parameter
Test Conditions
Symbol
Min
1.6
−2
Typ
Max
5.0
+2
Unit
V
Operating Input Voltage
Output Voltage Accuracy
V
IN
V
IN
= V
+ 0.5 V to 5.0 V,
V
OUT
%
OUT(NOM)
0.1 mA ≤ I
≤ 300 mA
OUT
Reference Voltage (Adjustable Ver.
ADJ pin connected to OUT)
V
= 1.6 V to 5.0 V,
V
ADJ
1.078
1.1
1.122
V
IN
0.1 mA ≤ I
≤ 300 mA
OUT
Line Regulation
Load Regulation
V
+ 0.5 V ≤ V ≤ 5.0 V
Line
Reg
0.5
2
mV/V
mV
OUT(NOM)
IN
I
= 1 mA to 300 mA
Load
Reg
OUT
Dropout Voltage (Note 6)
TSOP−5, WDFN6
I
= 300 mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 1.5 V
= 1.8 V
= 2.5 V
= 2.8 V
= 3.0 V
= 3.3 V
= 4.5 V
= 1.5 V
= 1.8 V
= 2.5 V
= 2.8 V
= 3.0 V
= 3.3 V
= 4.5 V
V
DO
170
155
125
115
113
110
95
295
255
200
185
177
170
135
315
275
220
205
197
190
170
mV
OUT
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
Dropout Voltage (Note 6)
DFNW8
I
= 300 mA
V
DO
180
165
140
130
127
125
112
560
580
30
mV
OUT
Output Current Limit
Short Circuit Current
Quiescent Current
V
OUT
= 90% V
I
CL
350
0.7
mA
OUT(NOM)
V
= 0 V
I
OUT
SC
I
= 0 mA
I
Q
40
mA
mA
V
OUT
Shutdown Current
V
≤ 0.4 V
I
0.01
1.5
EN
DIS
EN Pin Threshold Voltage
EN Input Voltage “H”
EN Input Voltage “L”
V
ENH
V
ENL
I
EN
0.2
0.6
EN Pull Down Current
V
= 5.0 V
0.2
95
90
mA
EN
Power Good Threshold Voltage
Output Voltage Raising
Output Voltage Falling
V
%
PGUP
PGDW
V
Power Good Output Voltage Low
I
= 5 mA, Open drain
V
PGLO
0.3
V
PG
Turn−On Time (Note 7)
C
= 1 mF, From assertion of V
120
ms
OUT
EN
to V
= 95% V
OUT
OUT(NOM)
Power Supply Rejection Ratio
(Note 7)
V
= 3.3 V,
f = 100 Hz
P
83
85
80
61
9
dB
OUT(NOM)
OUT
SRR
I
= 10 mA
f = 1 kHz
f = 10 kHz
f = 100 kHz
Output Voltage Noise (Fixed Ver.)
f = 10 Hz to 100 kHz
Temperature rising
Temperature hysteresis
< 0.2 V, Version A only
I
= 10 mA
V
mV
RMS
OUT
N
Thermal Shutdown Threshold
(Note 7)
T
SDH
165
15
260
°C
°C
W
T
HYST
Active output discharge resistance
V
R
DIS
EN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization.
Production tested at T = T = 25°C.
J
A
6. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible. Dropout
voltage is characterized when V falls 3% below V
.
OUT(NOM)
OUT
7. Guaranteed by design and characterization.
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4
NCP164C
TYPICAL CHARACTERISTICS
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
1.830
1.825
1.820
1.815
1.810
1.805
V
= 1.7 V
= 1 mA
V
= 2.3 V
= 1 mA
= 1 mF
OUT
IN
IN
1.800
1.795
1.790
I
I
OUT
OUT
C
= 1 mF
C
OUT
−40 −20
0
20 40 60 80 100 120 140
−40 −20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 2. Output Voltage vs. Temperature −
OUT = 1.2 V
Figure 3. Output Voltage vs. Temperature −
V
VOUT = 1.8 V
3.330
3.325
3.320
3.315
3.310
3.305
3.300
3.295
3.290
350
325
300
275
250
225
200
175
150
125
100
V
= 3.8 V
= 1 mA
V
= 1.2 V
= 0.3 A
= 1 mF
OUT
IN
OUT
I
I
OUT
OUT
C
= 1 mF
C
OUT
−40 −20
0
20 40 60 80 100 120 140
−40 −20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 4. Output Voltage vs. Temperature −
OUT = 3.3 V
Figure 5. Dropout Voltage vs. Temperature −
V
VOUT = 1.2 V
270
250
230
210
190
170
150
130
110
90
170
160
150
140
130
120
110
100
90
V
= 1.8 V
= 0.3 A
= 1 mF
V
= 3.3 V
= 0.3 A
= 1 mF
OUT
OUT
OUT
I
I
OUT
OUT
C
C
80
OUT
70
−40 −20
70
−40 −20
0
20 40 60 80 100 120 140
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 6. Dropout Voltage vs. Temperature −
OUT = 1.8 V
Figure 7. Dropout Voltage vs. Temperature −
V
VOUT = 3.3 V
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NCP164C
TYPICAL CHARACTERISTICS (continued)
40
38
36
34
32
30
28
26
24
22
20
140
135
130
125
120
115
V
= 1.8 V
= 10 mA
= 1 mF
OUT
I
OUT
C
OUT
V
I
C
= nom.
= 0 mA
= 1 mF
OUT
110
105
100
OUT
OUT
−40 −20
0
20 40 60 80 100 120 140
−40 −20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 8. Quiescent Current va Temperature
Figure 9. Turn−on Time vs. Temperature
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
580
570
560
550
540
530
520
510
500
Output ON
V
C
= nom.
= 1 mF
OUT
OUT
Output OFF
−40 −20
0
20 40 60 80 100 120 140
−40 −20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 10. Current Limit vs. Temperature
Figure 11. Enable Thresholds vs Temperature
300
290
280
270
260
250
240
230
220
96,0
95,0
94,0
93,0
92,0
91,0
90,0
89,0
88,0
V
raising to nominal
OUT
EN = low
V
falling from nominal
OUT
C
= 1 mF
OUT
−40 −20
0
20 40 60 80 100 120 140
−40 −20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Figure 12. Power Good Threshold vs.
Temperature
Figure 13. Active Discharge Resistance vs.
Temperature
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NCP164C
TYPICAL CHARACTERISTICS (continued)
100
90
80
70
60
50
40
30
20
10
0
10000
-
I
= 10 mA
= 100 mA
= 200 mA
-
I
= 10 mA
= 100 mA
= 200 mA
OUT
OUT
- I
-
- I
- I
OUT
OUT
OUT
I
OUT
1000
100
10
V
V
= 3.2 V
IN
V
V
= 3.3 V
IN
= 2.8 V
OUT
= 2.8 V
OUT
T = 25°C
A
T = 25°C
A
C
= 1 mF
OUT
C
= 1 mF
OUT
1
0.01
0,1
1
10
100
1000
10000
0.01
0.1
1
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 14. Power Supply Rejection Ration
Figure 15. Output Voltage Noise Spectral Density
for VOUT = 2.8 V, COUT = 1 mF
for VOUT = 2.8 V, COUT = 1 mF
APPLICATIONS INFORMATION
The NCP164C is the member of new family of high output
current and low dropout regulators which delivers low
quiescent and ground current consumption, good noise and
power supply ripple rejection ratio performance. The
NCP164C incorporates EN pin and power good output for
simple controlling by MCU or logic. Standard features
include current limiting, soft−start feature and thermal
protection.
1 mA to obtain low saturation voltage. External pull−up
resistor can be connected to any voltage up to 5.0 V (please
see Absolute Maximum Ratings table).
Power Dissipation and Heat Sinking
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation junction temperature
should be limited to +125°C, however device is capable to
work up to junction temperature +150°C. The maximum
power dissipation the NCP164C can handle is given by:
Input Decoupling (CIN)
It is recommended to connect at least 1 mF ceramic X5R
or X7R capacitor between IN and GND pin of the device.
This capacitor will provide a low impedance path for any
unwanted AC signals or noise superimposed onto constant
input voltage. The good input capacitor will limit the
influence of input trace inductances and source resistance
during sudden load current changes. Higher capacitance and
lower ESR capacitors will improve the overall line transient
response.
ƪT
ƫ
J(MAX) * TA
(eq. 1)
PD(MAX)
+
RqJA
The power dissipated by the NCP164C for given
application conditions can be calculated from the following
equations:
(eq. 2)
PD [ VIN(IGND(IOUT)) ) IOUT (VIN * VOUT
)
Output Decoupling (COUT
)
or
The NCP164C does not require a minimum Equivalent
Series Resistance (ESR) for the output capacitor. The device
is designed to be stable with standard ceramics capacitors
with values of 1 mF or greater. The X5R and X7R types have
the lowest capacitance variations over temperature thus they
are recommended.
) ǒV
Ǔ
IOUT
PD(MAX)
OUT
(eq. 3)
VIN(MAX)
[
IOUT ) IGND
Hints
VIN and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCP164C, and
make traces as short as possible.
Power Good Output Connection
The NCP164C include Power Good functionality for
better interfacing to MCU system. Power Good output is
open collector type, capable to sink up to 10 mA.
Recommended operating current is between 10 mA and
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NCP164C
Adjustable Version
where V
is voltage of original fixed version (from
FIX
Not only adjustable version, but also any fixed version can
be used to create adjustable voltage, where original fixed
voltage becomes reference voltage for resistor divider and
feedback loop. Output voltage can be equal or higher than
original fixed option, while possible range is from 1.1 V up
to 4.5 V. Figure 16 shows how to add external resistors to
increase output voltage above fixed value.
1.2 V up to 4.5 V) or adjustable version (1.1 V). Do not
operate the device at output voltage about 4.7 V, as device
can be damaged.
In order to avoid influence of current flowing into SNS pin
to output voltage accuracy (SNS current varies with voltage
option and temperature, typical value is 300 nA) it is
recommended to use values of R1 and R2 below 500 kW.
Output voltage is then given by equation
VOUT + VFIX (1 ) R1ńR2)
(eq. 4)
V
IN
V
OUT
IN
OUT
NCP164C
ADJ or FIX version
SNS
R1
R2
1 mF
10 mF
Ceramic
C
C
OUT
IN
EN
Ceramic
GND
ON
OFF
Figure 16. Adjustable Variant Application
Please note that output noise is amplified by V
/ V
high fixed variant as possible – for example in case above it
is better to use 3.3 V fixed variant to create 3.6 V output
voltage, as output noise will be amplified only 3.6 / 3.3 =
1.09 × (9.8 mVrms).
OUT
FIX
ratio. For example, if original 1.2 V fixed variant is used to
create 3.6 V output voltage, output noise is increased 3.6 /
1.2 = 3 times and real value will be 3 × 9 mVrms = 27ĂmVrms.
For noise sensitive applications it is recommended to use as
ORDERING INFORMATION
Device Part No.
Voltage Variant
Marking
Package Option
Package
Shipping †
NCP164CSN180T1G
1.8 V
EJ
N/A
TSOP5
(Pb−Free)
3000 / Tape & Reel
NCP164CSN280T1G
NCP164CSN300T1G
NCP164CSN330T1G
NCP164CSNADJT1G
NCP164CMT180TAG
NCP164CMT280TAG
NCP164CMT300TAG
NCP164CMT330TAG
NCP164CMTADJTAG
NCP164CMLADJTCG
2.8 V
3.0 V
3.3 V
ADJ
EK
EQ
EL
E4
FJ
N/A
TSOP5
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
N/A
TSOP5
(Pb−Free)
N/A
TSOP5
(Pb−Free)
N/A
TSOP5
(Pb−Free)
1.8 V
2.8 V
3.0 V
3.3 V
ADJ
Non−Wettable
Non−Wettable
Non−Wettable
Non−Wettable
Non−Wettable
Wettable
WDFN6 2 x 2
(WF, Pb−Free)
FK
FQ
FL
F2
G2
WDFN6 2 x 2
(WF, Pb−Free)
WDFN6 2 x 2
(WF, Pb−Free)
WDFN6 2 x 2
(WF, Pb−Free)
WDFN6 2 x 2
(WF, Pb−Free)
ADJ
DFNW8 3 x 3
(WF, Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NCP164C
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
9
NCP164C
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM
THE TERMINAL TIP.
A3
EXPOSED Cu
MOLD CMPD
D
A
B
A1
ALTERNATE B−1
ALTERNATE B−2
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICES CONTAINING WETTABLE FLANK
OPTION, DETAIL A ALTERNATE CONSTRUCTION
A-2 AND DETAIL B ALTERNATE CONSTRUCTION
B-2 ARE NOT APPLICABLE.
DETAIL B
PIN ONE
ALTERNATE
REFERENCE
E
CONSTRUCTIONS
0.10
C
L
L
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
0.10
C
L1
TOP VIEW
A1
A3
b
ALTERNATE A−1
ALTERNATE A−2
0.20 REF
0.25
1.50
0.35
DETAIL A
A3
DETAIL B
D
2.00 BSC
0.05
C
C
ALTERNATE
D2
E
1.70
CONSTRUCTIONS
2.00 BSC
A
E2
e
0.90
1.10
0.65 BSC
L
0.20
---
0.40
0.15
0.05
6X
A1
L1
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
RECOMMENDED
MOUNTING FOOTPRINT
6X
0.45
DETAIL A
L
1.72
1
3
E2
1.12
2.30
6
4
6X b
M
M
0.10
0.05
C
C
A
B
e
PACKAGE
OUTLINE
NOTE 3
1
BOTTOM VIEW
0.65
PITCH
6X
0.40
DIMENSIONS: MILLIMETERS
www.onsemi.com
10
NCP164C
PACKAGE DIMENSIONS
DFNW8 3x3, 0.65P
CASE 507AD
ISSUE A
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L3
L3
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURE TO AID IN FILLET FORMA-
TION ON THE LEADS DURING MOUNTING.
L
L
ALTERNATE
CONSTRUCTION
DETAIL A
E
A
PIN ONE
REFERENCE
EXPOSED
COPPER
MILLIMETERS
DIM MIN
NOM
0.90
−−−
MAX
1.00
0.05
A4
A1
A
A1
A3
A4
b
0.80
−−−
0.20 REF
−−−
0.30
3.00
2.40
3.00
1.65
TOP VIEW
0.10
0.25
2.90
2.30
2.90
1.55
−−−
0.35
3.10
2.50
3.10
1.75
PLATING
A1
A4
ALTERNATE
CONSTRUCTION
DETAIL B
D
D2
E
E2
e
K
0.05
0.05
C
C
DETAIL B
A3
C
C
C
A4
0.65 BSC
0.28 REF
0.40
L
L3
0.30
0.50
SEATING
PLANE
NOTE 4
SIDE VIEW
0.05 REF
L3
PLATED
SURFACES
D2
DETAIL A
SECTION C−C
1
4
5
RECOMMENDED
SOLDERING FOOTPRINT*
8X
L
2.50
8X
0.58
2.35
E2
8
5
K
8
8X b
e/2
e
3.30 1.75
0.10 C A B
NOTE 3
C
0.05
PACKAGE
OUTLINE
BOTTOM VIEW
1
4
8X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
ON Semiconductor Website: www.onsemi.com
◊
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
5
1
5
0.074
0.95
XXXAYWG
XXX MG
0.037
G
G
1
Analog
Discrete/Logic
2.4
0.094
XXX = Specific Device Code XXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW8 3x3, 0.65P
CASE 507AD
ISSUE A
1
DATE 15 JUN 2018
SCALE 2:1
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURE TO AID IN FILLET FORMA-
TION ON THE LEADS DURING MOUNTING.
L3
L3
L
L
DETAIL A
ALTERNATE
CONSTRUCTION
E
A
PIN ONE
REFERENCE
EXPOSED
COPPER
MILLIMETERS
DIM MIN
NOM
0.90
−−−
MAX
1.00
0.05
A4
A1
A
A1
A3
A4
b
0.80
−−−
0.20 REF
−−−
0.30
3.00
2.40
TOP VIEW
0.10
0.25
2.90
2.30
2.90
1.55
−−−
0.35
3.10
2.50
3.10
1.75
PLATING
A1
A4
ALTERNATE
CONSTRUCTION
DETAIL B
D
D2
E
E2
e
K
0.05
0.05
C
C
DETAIL B
A3
C
3.00
1.65
C
C
A4
0.65 BSC
0.28 REF
0.40
L
L3
0.30
0.50
SEATING
PLANE
NOTE 4
SIDE VIEW
0.05 REF
L3
PLATED
SURFACES
GENERIC
D2
DETAIL A
SECTION C−C
MARKING DIAGRAM*
1
4
1
XXXXXX
8X
L
XXXXXX
ALYWG
G
E2
XXXXXX = Specific Device Code
K
A
L
= Assembly Location
= Wafer Lot
8
5
8X b
e/2
e
0.10
0.05
C
C
A B
Y
W
G
= Year
= Work Week
= Pb−Free Package
NOTE 3
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
2.50
8X
0.58
2.35
8
5
3.30 1.75
PACKAGE
OUTLINE
1
4
8X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON17792G
DFNW8 3x3, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE B
DATE 19 JAN 2016
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM
THE TERMINAL TIP.
A3
EXPOSED Cu
MOLD CMPD
D
A
B
A1
ALTERNATE B−1
ALTERNATE B−2
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICES CONTAINING WETTABLE FLANK
OPTION, DETAIL A ALTERNATE CONSTRUCTION
A-2 AND DETAIL B ALTERNATE CONSTRUCTION
B-2 ARE NOT APPLICABLE.
DETAIL B
PIN ONE
ALTERNATE
REFERENCE
E
CONSTRUCTIONS
0.10
C
L
L
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
0.10
C
L1
TOP VIEW
A1
A3
b
ALTERNATE A−1
ALTERNATE A−2
0.20 REF
0.25
1.50
0.35
DETAIL A
A3
DETAIL B
D
2.00 BSC
0.05
C
C
ALTERNATE
D2
E
1.70
CONSTRUCTIONS
2.00 BSC
A
E2
e
0.90
1.10
0.65 BSC
L
0.20
---
0.40
0.15
0.05
6X
A1
L1
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
1
DETAIL A
L
1
XX M
3
XX = Specific Device Code
M
= Date Code
E2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
6
4
6X b
M
M
0.10
0.05
C
C
A
B
e
RECOMMENDED
MOUNTING FOOTPRINT
NOTE 3
BOTTOM VIEW
6X
1.72
0.45
1.12
2.30
PACKAGE
OUTLINE
1
0.65
6X
0.40
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON55829E
WDFN6 2X2, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
ON Semiconductor Website: www.onsemi.com
◊
www.onsemi.com
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