NCP1652DWR2G_技术文档

NCP1652, NCP1652A

High-Efficiency Single

Stage Power Factor

Correction and Step-Down

Controller

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MARKING

The NCP1652 is a highly integrated controller for implementing

power factor correction (PFC) and isolated step down ac−dc power

conversion in a single stage, resulting in a lower cost and reduced part

count solution. This controller is ideal for notebook adapters, battery

chargers and other off−line applications with power requirements

between 75 W and 150 W. The single stage is based on the flyback

converter and it is designed to operate in continuous conduction

(CCM) or discontinuous conduction (DCM) modes.

The NCP1652 increases the system efficiency by incorporating a

secondary driver with adjustable nonoverlap delay for controlling a

synchronous rectifier switch in the secondary side, an active clamp

switch in the primary or both. In addition, the controller features a

proprietary Soft−Skip™ to reduce acoustic noise at light loads. Other

features found in the NCP1652 include a high voltage startup circuit,

voltage feedforward, brown out detector, internal overload timer, latch

input and a high accuracy multiplier.

DIAGRAMS

20

NCP1652

AWLYYWWG

SO−20 WB

DW SUFFIX

CASE 751D

1

NCP1652G

AWLYWW

SOIC−16

D SUFFIX

CASE 751B

NCP1652AG

AWLYWW

Features

• Dual Control Outputs with Adjustable Non Overlap Delay for

Driving a Synchronous Rectifier Switch, an Active Clamp Switch or

Both

• Voltage Feedforward Improves Loop Response

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

• Frequency Jittering Reduces EMI Signature

• Proprietary Soft−Skip™ at Light Loads Reduces Acoustic Noise

• Brown Out Detector

• Internal 150 ms Fault Timer

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 32 of this data sheet.

• Independent Latch−Off Input Facilitates Implementation of

Overvoltage and Overtemperature Fault Detectors

• Single Stage PFC and Isolated Step Down Converter

• Continuous or Discontinuous Conduction Mode Operation

• Average Current Mode Control (ACMC), Fixed Frequency Operation

• High Accuracy Multiplier Reduces Input Line Harmonics

• Adjustable Operating Frequency from 20 kHz to 250 kHz

• These are Pb−Free Devices

Typical Applications

• Notebook Adapter

• High Current Battery Chargers

• Front Ends for Distributed Power Systems

• High Power Solid State Lighting

1

Publication Order Number:

April, 2010 − Rev. 3

NCP1652/D

NCP1652, NCP1652A

SO−20 WB

SOIC−16

CT

1

Startup

GND

CT

Startup

16

15

14

13

12

11

10

9

20

19

18

17

16

15

14

13

12

11

1

2

Ramp Comp

AC IN

2

3

4

5

6

Ramp Comp

AC IN

NC

OUT B

OUT A

NC

3

4

FB

GND

Out B

Out A

V

FF

V

CC

CM

AC COMP

Latch−Off

I

spos

V

FF

5

6

I

7

8

avg

CM

R

delay

7

8

NC

V

CC

spos

avg

(Top View)

I

AC COMP

Latch−Off

9

R

10

delay

Figure 1. Pin Connections

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2

NCP1652, NCP1652A

Overload

Timer

OVLD

Enable

FB overload

comparator

Jitter

t

FB

+

−

+

S

Q

R

OVLD

CT

Adj.

V

OVLD

Clock

DC Max

Oscillator

DC Max

Startup

V

Brown−Out

Comparator

−

+

Enable

x 2

FF

Out

Sawtooth

counter

V

FF

Reset

+

Dual HV

start−up

current source

V

BO

Ramp. Comp.

Adj.

Ramp Comp

V

HV current

CC(off)

Reset

Start

V

CC

Management

GND

Ramp

Comp

V

AC In skip

comparator

CCOK

V

DD

+

−

+

V

DD

V

SSKIP(sync)

DD

Output

Driver

Clock

Soft−skip Ramp

R

FB skip

Delay

Adj.

FB

DC Max

Comparator

Delay

OUTB

t

SSKIP

+

−

Start

Terminate

+

Inst. current B

V

SSKIP

Delay

Transient Load Detect

Comparator

+

−

AC IN

S

+

Q

OUTA

Ramp Comp

Output

Driver

R

−

V

SSKIP(TLD)

V−to−I

PWM Skip

Comparator

FB

21.33kW

FB

Reference

Generator

+

−

V−to−I

+ inverter

gm

+

V

CC

−

AC error

Amplifier

PWM

comparator

V

FF

21.33kW

+

BO

OVLD

Latch

4V

CM

V

OK

CC

Inst. current A

Blanking

+

−

I

spos

t

gm

LEB

AC COMP

Blanking

Current sense

amplifier

Inst.

current B

t

LEB

V

DD

OVP Comparator

+

I

avg

−

+

I

latch(clamp)

V

latch(high)

blanking

(delay)

t

Latch

Latch−Off

OTP Comparator

S

Q

R

−

+

Latch

I

Delay

latch(shdn)

R

delay

+

V

latch(low)

V

latch(clamp)

Reset

Figure 2. Detailed Block Diagram

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3

NCP1652, NCP1652A

PIN FUNCTION DESCRIPTION

16 Pin

20 Pin

Symbol

Description

1

C

An external timing capacitor (C ) sets the oscillator frequency. A sawtooth between 0.2 V and 4

T

V sets the oscillator frequency and the gain of the multiplier.

2

RAMP COMP

A resistor (R ) between this pin and ground adjust the amount of ramp compensation that is

added to the current signal. Ramp compensation is required to prevent subharmonic oscilla-

tions. This pin should not be left open.

RC

3

4

3

4

AC IN

FB

The scaled version of the full wave rectified input ac wave is connected to this pin by means of

a resistive voltage divider. The line voltage information is used by the multiplier.

An error signal from an external error amplifier circuit is fed to this pin via an optocoupler or

other isolation circuit. The FB voltage is a proportional of the load of the converter. If the voltage

on the FB pin drops below V

the controller enters Soft−Skip™ to reduce acoustic noise.

SSKIP

5

6

5

6

VFF

CM

Feedforward input. A scaled version of the filtered rectified line voltage is applied by means of a

resistive divider and an averaging capacitor. The information is used by the Reference Generat-

or to regulate the controller.

Multiplier output. A capacitor is connected between this pin and ground to filter the modulated

output of the multiplier.

7

8

9

NC

7

AC COMP

Sets the pole for the ac reference amplifier. The reference amplifier compares the low fre-

quency component of the input current to the ac reference signal. The response must be slow

enough to filter out most of the high frequency content of the current signal that is injected from

the current sense amplifier, but fast enough to cause minimal distortion to the line frequency

information. The pin should not be left open.

8

9

10

11

12

Latch

Latch−Off input. Pulling this pin below 1.0 V (typical) or pulling it above 7.0 V (typical) latches

the controller. This input can be used to implement an overvoltage detector, an overtemperature

detector or both. Refer to Figure 69 for a typical implementation.

Rdelay

A resistor between this pin and ground sets the non−overlap time delay between OUTA and

OUTB. The delay is adjusted to prevent cross conduction between the primary MOSFET and

synchronous rectification MOSFET or optimize the resonant transition in an active clamp stage.

10

I

An external resistor and capacitor connected from this terminal to ground, to set and stabilizes

the gain of the current sense amplifier output that drives the ac error amplifier.

AVG

11

12

13

14

I

Positive current sense input. Connects to the positive side of the current sense resistor.

Positive input supply. This pin connects to an external capacitor for energy storage. An internal

Spos

V

CC

current source supplies current from the STARTUP pin V . Once the voltage on V reaches

CC

approximately 15.3 V, the current source turns off and the outputs are enabled. The drivers are

disabled once V reaches approximately 10.3 V. If V drops below 0.85 V (typical), the star-

CC

tup current is reduced to less than 500 mA.

13

14

15

16

OUTA

OUTB

Drive output for the main flyback power MOSFET or IGBT. OUTA has a source resistance of

13 W (typical) and a sink resistance of 8 W (typical).

Secondary output of the PWM Controller. It can be used to drive synchronous rectifier, and

active clamp switch, or both. OUTB has source and sink resistances of 22 W (typical) and 11

(typical), respectively.

15

16

17

18

19

20

GND

NC

Ground reference for the circuit.

NC

HV

Connect the rectified input line voltage directly to this pin to enable the internal startup regulator.

A constant current source supplies current from this pin to the capacitor connected to the V

CC

pin, eliminating the need for a startup resistor. The charge current is typically 5.5 mA. Maximum

input voltage is 500 V.

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4

NCP1652, NCP1652A

MAXIMUM RATINGS (Notes 1 and 2)

Rating

Symbol

Value

Unit

Start_up Input Voltage

Start_up Input Current

V

−0.3 to 500

$100

V

mA

HV

I

Power Supply Input Voltage

Power Supply Input Current

V

−0.3 to 20

$100

V

mA

CC

I

Latch Input Voltage

Latch Input Current

V

−0.3 to 10

$100

V

mA

Latch

I

OUTA Pin Voltage

OUTA Pin Current

V

outA

−0.3 to 20

$1.0

V

A

outA

I

OUTB Pin Voltage

OUTB Pin Current

V

outB

−0.3 to 20

$600

V

mA

outB

I

All Other Pins Voltage

All Other Pins Current

−0.3 to 6.5

$100

V

mA

Thermal Resistance, Junction−to−Air

0.1 in” Copper

0.5 in” Copper

q

°C/W

JA

130

110

Thermal Resistance, Junction−to−Lead

R

50

°C/W

W

ΘJL

Maximum Power Dissipation @ T = 25°C

P

MAX

0.77

A

Operating Temperature Range

Storage Temperature Range

T

−40 to 125

−55 to 150

°C

J

T

°C

STG

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

16 pin package:

Pin 1−15: Human Body Model 2000 V per JEDEC standard JESD22, Method A114.

Machine Model 200 V per JEDEC standard JESD22, Method A115.

Pin 16 is the high voltage startup of the device and is rated to the maximum rating of the part, 500 V.

20 pin package:

Pin 1−19: Human Body Model 2000 V per JEDEC standard JESD22, Method A114.

Machine Model 200 V per JEDEC standard JESD22, Method A115.

Pin 20 is the high voltage startup of the device and it is rated to the maximum

rating of the part, or 500 V.

2. This device contains Latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

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5

NCP1652, NCP1652A

VCC

EMI Filter

Latch

+

_

+

NTC

FB

1

CT

HV

GND

Ramp Comp

OUTB

OUTA

AC IN

FB

VCC

VFF

VCC

NCP1652

CM

Ispos

Iavg

AC COMP

10

11

Latch

LATCH

Rdelay

Figure 3. Typical Application Schematic

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6

NCP1652, NCP1652A

ELECTRICAL CHARACTERISTICS (V = 15 V, V

= 3.8 V, V = 2.0 V, V = 2.4 V, V

= open, V

= 49.9 kW,

= −100 mV,

CC

AC IN

FB

FF

Latch

ISPOS

C

= 1 nF, C = 470 pF, C

= 0.27 nF, C

= 0.1 nF, C = 10 nF, R

= 76.8 kW, R

OUTA

T

IAVG

Latch

M

IAVG

delay

= 330 pF, R = 43 kW, For typical Value T = 25°C, for min/max values T = −40°C to 125°C, unless otherwise noted)

OUTB

RC

J

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

OSCILLATOR

Frequency

f

90

–

100

6.8

110

–

kHz

%

osc

Frequency Modulation in Percentage

of f

OSC

Frequency Modulation Period

Ramp Peak Voltage

–

6.8

4.0

0.10

−

–

ms

V

CT(peak)

Ramp Valley Voltage

V

–

V

CT(valley)

Maximum Duty Ratio

R

= open

D

94

–

%

V

delay

Ramp Compensation Peak Voltage

AC ERROR AMPLIFIER

Input Offset Voltage (Note 3)

Error Amplifier Transconductance

Source Current

V

4

RCOMP(peak)

Ramp I

, V = 0 V

AVG FB

ACV

40

100

70

–

mV

mS

mA

IO

g

m

–

V

= 2.0 V, V

V

= 2.0 V,

I

EA(source)

25

AC COMP

AC IN

= 1.0 V

FF

Sink Current

V

= 2.0 V, V

V

I

EA(sink)

−25

−70

–

mA

AC COMP

A C_IN

= 5.0 V

FF

CURRENT AMPLIFIER

Input Bias Current

V

= 0 V

CAI

40

53

0

80

20

mA

mV

V

ISPOS

bias

Input Offset Voltage

Current Limit Threshold

V

= 5.0 V, V

= 0 V

CAV

−20

AC COMP

ISpos

IO

ILIM

force OUTA high, V

= 3.0 V,

= open

V

0.695

0.74

0.77

AC COMP

Ramp_Comp

ramp V

, V

ISPOS

Leading Edge Blanking Duration

Bandwidth

t

–

200

1.5

5.3

–

ns

LEB

MHz

V/V

PWM Output Voltage Gain

PWMk

ISVk

4.0

6.0

4

PWMk +

(V

* C

)

ILIM

AVIO

Current Limit Voltage Gain (See

Current Sense Section)

15.4

–

18.5

0.55

23

–

V/V

V

(AVG)

ISVK +

VI

SPOS

REFERENCE GENERATOR

Reference Generator Gain

k

2

V

@ V

AC_REF

FF

k +

V

@ V

AC_IN

FB

Reference Generator output voltage

(low input ac line and full load)

V

= 1.2 V, V = 0.765 V,

RG

3.61

1.16

1.85

0.55

−100

4.36

1.35

2.18

0.65

–

4.94

1.61

2.58

0.78

100

Vpk

mV

AC IN

FF

out1

out2

out3

out4

offset

V

= 4 V

FB

Reference Generator output voltage

(high input ac line and full load)

V

= 3.75 V, V = 2.39 V,

AC IN FF

V

FB

= 4.0 V

Reference Generator output Voltage

(low input as line and minimum load)

V

= 1.2 V, V = 0.765 V,

AC IN FF

V

FB

= 2.0 V

Reference Generator output voltage

(high input ac line and minimum load)

V

= 3.75 V, V = 2.39 V,

AC IN FF

V

FB

= 2.0 V

Reference Generator output offset

voltage

RG

3. Guaranteed by Design

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7

NCP1652, NCP1652A

ELECTRICAL CHARACTERISTICS (V = 15 V, V

= 3.8 V, V = 2.0 V, V = 2.4 V, V

= open, V

= 49.9 kW,

= −100 mV,

CC

AC IN

FB

FF

Latch

ISPOS

C

= 1 nF, C = 470 pF, C

= 0.27 nF, C

= 0.1 nF, C = 10 nF, R

= 76.8 kW, R

OUTA

T

IAVG

Latch

M

IAVG

delay

= 330 pF, R = 43 kW, For typical Value T = 25°C, for min/max values T = −40°C to 125°C, unless otherwise noted)

OUTB

RC

J

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

AC INPUT

Input Bias Current Into Reference

Multiplier & Current Compensation

Amplifier

I

–

0.01

–

mA

AC IN(IB)

DRIVE OUTPUTS A and B

Drive Resistance (Thermally Limited)

OUTA Sink

W

V

OUTA

= 1 V

R

SNK1

R

SRC1

–

8

10.8

18

24

OUTA

OUTA Source

I

= 100 mA

OUTB Sink

OUTB Source

V

OUTB

= 1 V

R

SNK2

R

SRC2

–

10

21

22

44

OUTB

I

= 100 mA

Rise Time (10% to 90%)

ns

OUTA

OUTB

t

r1

t

r2

–

40

25

–

Fall Time (90% to 10%)

OUTA

OUTB

t

f1

t

f2

–

20

10

–

DRV Low Voltage

OUTA

mV

I

= 100 mA

V

–

1.0

100

OUTA

OUTB

OUTA(low)

OUTB(low)

OUTB

I

Non−Overlap Adjustable Delay Range

(Note 3)

t

0.08

–

2.8

ms

delay(range)

Non−Overlap Adjustable Delay

Measured at 50% of V

,

ns

OUT

C

= C

= 100 pF

OUTA

OUTB

Leading

Trailing

OUTA Rising to OUTB falling

OUTB Rising to OUTA falling

t

250

450

420

550

delay(lead)

delay(trail)

t

Non−Overlap Adjustable Delay

Matching

OUTA Rising to OUTB Falling or OUTB

Rising to OUTA Falling

t

–

55

%

delay(match)

Soft−Skip]

Skip Synchronization to ac Line

Voltage Threshold

V

ACIN

Increasing, V = 1.5 V

V

210

–

267

40

325

–

mV

FB

SSKIP(SYNC)

Skip Synchronization to ac Line

Voltage Threshold Hysteresis

V

ACIN

Decreasing

V

SSKIP

(SYNCHYS)

Skip Ramp Period (Note 3)

t

−

2.5

–

ms

V

SSKIP

Skip Voltage Threshold

NCP1652

V

SSKIP

1.04

0.36

1.24

0.41

1.56

0.46

NCP1652A

Skip Voltage Hysteresis

V

45

90

140

mV

V

SSKIP(HYS)

Skip Transient Load Detect Threshold

(Note 3)

V

= V

+0.55 V

V

SSKIP(TLD)

−

1.75

−

SSKIP(TLD)

SSKIP

FEEDBACK INPUT

Pull−Up Current Source

Pull−Up Resistor

V

FB

= 0.5 V

I

600

–

750

6.7

5.7

920

–

mA

kW

V

FB

R

FB

FB(open)

Open Circuit Voltage

V

5.3

6.3

STARTUP AND SUPPLY CIRCUITS

Supply Voltage

V

Startup Threshold

V

Increasing

Decreasing

V

14.3

9.3

–

15.4

10.2

7.0

16.3

11.3

–

CC

CC(on)

V

CC(off)

Minimum Operating Voltage

Logic Reset Voltage

V

CC

V

CC

V

CC(reset)

Inhibit Threshold Voltage

3. Guaranteed by Design

V

HV

= 40 V, I

= 500 mA

V

inhibit

−

0.83

1.15

inhibit

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8

NCP1652, NCP1652A

ELECTRICAL CHARACTERISTICS (V = 15 V, V

= 3.8 V, V = 2.0 V, V = 2.4 V, V

= open, V

= 49.9 kW,

= −100 mV,

CC

AC IN

FB

FF

Latch

ISPOS

C

= 1 nF, C = 470 pF, C

= 0.27 nF, C

= 0.1 nF, C = 10 nF, R

= 76.8 kW, R

OUTA

T

IAVG

Latch

M

IAVG

delay

= 330 pF, R = 43 kW, For typical Value T = 25°C, for min/max values T = −40°C to 125°C, unless otherwise noted)

OUTB

RC

J

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

STARTUP AND SUPPLY CIRCUITS

Inhibit Bias Current

V

= 40 V, V = 0.8 * V

I

40

500

mA

HV

CC

inhibit

-

–

Minimum Startup Voltage

Startup Current

I

= 0.5 mA, V = V

– 0.5 V

V

start(min)

–

40

V

start

CC

CC(on)

V

= V

– 0.5 V, V = Open

I

start

3.0

5.62

8.0

mA

CC

CC(on)

FB

Off−State Leakage Current

V

= 400 V, T = 25°C

I

HV(off)

HV

J

T = −40°C to 125°C

–

17

15

40

80

Supply Current

Device Disabled (Overload)

Device Switching

mA

V

OSC

= Open

I

–

0.72

6.25

1.2

7.2

FB

CC1

CC2

f

[ 100 kHz

FAULT PROTECTION

Overload Timer

t

120

4.7

162

4.9

360

5.2

ms

V

OVLD

Overload Detect Threshold

V

OVLD

Brown−Out Detect Threshold (entering

V

Decreasing, V = 2.5 V,

V

0.41

0.45

0.49

V

FF

FB

BO(low)

BO(high)

BO(HYS)

fault mode)

V

= 2.0 V

AC IN

Brown−Out Exit Threshold (exiting

fault mode)

V

Increasing, V = 2.5 V,

V

0.57

0.63

174

0.69

V

FF

FB

= 2.0 V

V

AC IN

Brown−Out Hysteresis

V

−

mV

LATCH INPUT

Pull−Down Latch Voltage Threshold

Pull−Up Latch Voltage Threshold

Latch Propagation Delay

V

Decreasing

Increasing

V

0.9

5.6

30

42

2.5

−

0.98

7.0

56

1.1

8.4

90

58

4.5

−

V

Latch

latch(low)

latch(high)

latch(delay)

V

Latch

V

Latch

= V

t

ms

mA

V

latch(high)

Latch Clamp Current (Going Out)

V

= 1.5 V

I

51

Latch

latch(clamp)

Latch Clamp Voltage (I

Going In)

I

= 50 mA

V

I

3.27

95

Latch

latch(clamp)

Latch−Off Current Shutdown

(Going In)

V

Increasing

mA

Latch

latch(shdn)

3. Guaranteed by Design

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9

NCP1652, NCP1652A

110

105

100

95

8.0

7.5

7.0

6.5

6.0

90

−50

−25

0

25

50

75

100

125

150

−50

−25

0

25

50

75

100

125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 4. Oscillator Frequency (f_OSC) vs.

Junction Temperature

Figure 5. Oscillator Frequency Modulation in

Percentage of f_OSCvs. Junction Temperature

4.1

4.05

4.0

8.0

7.5

7.0

6.5

6.0

3.95

3.9

3.85

3.8

−50

−25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 6. Oscillator Frequency Modulation

Period vs. Junction Temperature

Figure 7. Ramp Peak Voltage vs. Junction

Temperature

4.1

4.05

4.0

100

98

96

94

92

90

3.95

3.9

3.85

3.8

−50

−25

0

25

50

75

100

125

150

−25

0

25

50

75

100 125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 8. Maximum Duty Ratio vs. Junction

Temperature

Figure 9. Ramp Compensation Peak Voltage

vs. Junction Temperature

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NCP1652, NCP1652A

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

−50

−25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 10. Error Amplifier Source Current vs.

Junction Temperature

Figure 11. Error Amplifier Sink Current vs.

Junction Temperature

60.0

57.5

55.0

52.5

50.0

47.5

45.0

42.5

40.0

−50

−25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

Figure 12. Current Amplifier Input Bias

Current vs. Junction Temperature

770

760

750

740

730

720

710

700

6.0

5.8

5.6

5.4

5.2

5.0

−50

−25

0

25

50

75

100

125 150

−50 −25

0

25

50

75

100

125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 13. Current Limit Threshold vs.

Junction Temperature

Figure 14. PWM Output Voltage Gain vs.

Junction Temperature

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11

NCP1652, NCP1652A

5.25

4.75

4.25

3.75

3.25

2.75

2.25

1.75

1.25

0.75

0.25

22

21

20

19

18

17

16

R

Gout1

Gout3

R

Gout2

Gout4

−50 −25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100

125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 15. Oscillator CS Limit Voltage Gain vs.

Junction Temperature

Figure 16. Oscillator Reference Generator

Output Voltage vs. Junction Temperature

14

12

16

14

10

12

8.0

6.0

4.0

10

8.0

6.0

−50 −25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 17. OUTA Sink Resistance vs. Junction

Temperature

Figure 18. OUTA Source Drive Resistance vs.

Junction Temperature

32

30

28

26

24

22

20

18

16

14

16

14

V

CC

= 15 V

V

= 15 V

CC

CI = 100 pF

12

10

8.0

6.0

−50

−25

0

25

50

75

100 125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 19. OUTB Sink Resistance vs.

Junction Temperature

Figure 20. OUTB Source Drive Resistance vs.

Junction Temperature

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12

NCP1652, NCP1652A

130

110

90

160

140

120

100

80

70

50

30

−50

60

−50

−25

0

25

50

75

100

125

150

−25

0

25

50

75

100

125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 21. OUTA Low Voltage vs. Junction

Temperature

Figure 22. OUTB Low Voltage vs. Junction

Temperature

600

550

500

450

400

350

300

9

7

5

3

1

OUTA Rising to OUTB Falling

OUTB Rising to OUTA Falling

−50

−25

0

25

50

75

100 125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 23. Non−Overlap Adjustable Delay vs.

Figure 24. Non−Overlap Adjustable Delay

Junction Temperature

Matching vs. Junction Temperature

300

280

260

240

220

200

1.25

1.24

1.23

1.22

1.21

1.20

−50

−25

0

25

50

75

100 125

150

−50

−25

0

25

50

75

100 125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 25. Skip Synchronization to ac Line

Voltage Threshold vs. Junction Temperature

Figure 26. Skip Voltage Threshold vs. Junction

Temperature

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NCP1652, NCP1652A

100

95

90

85

80

780

755

730

705

680

−50

−25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 27. Skip Voltage Hysteresis vs.

Junction Temperature

Figure 28. Feedback Pull−Up Current Source

vs. Junction Temperature

15.75

15.55

15.35

15.15

14.95

14.75

6.2

6.0

5.8

5.6

5.4

5.2

−50

−25

0

25

50

75

100

125

150

−50

−25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 29. Feedback Open Circuit Voltage vs.

Junction Temperature

Figure 30. Startup Threshold vs. Junction

Temperature

10.5

10.3

10.1

9.9

9.7

9.5

−50

−25

0

25

50

75

100 125

150

T , JUNCTION TEMPERATURE (°C)

J

Figure 31. Minimum Operating Voltage vs.

Junction Temperature

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NCP1652, NCP1652A

1000

950

900

850

800

750

700

650

350

330

310

290

270

250

−50

−25

0

25

50

75

100 125

150

−50 −25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 32. Inhibit Threshold Voltage vs.

Junction Temperature

Figure 33. Inhibit Bias Current vs. Junction

Temperature

25.0

24.5

24.0

23.5

23.0

22.5

22.0

6.0

5.8

5.6

5.4

5.2

5.0

V

= V − 0.5 V

CC

I

= 0.5 mA

start

−50

−25

0

25

50

75

100 125

150

−50

−25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 34. Minimum Startup Voltage vs.

Junction Temperature

Figure 35. Startup Current vs. Junction

Temperature

850

825

800

775

750

725

700

675

650

30

25

20

15

10

−50

−25

0

25

50

75

100

125

150

−50

−25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 36. Off−State Leakage Current vs.

Figure 37. Supply Current Device Disabled

(Overload) vs. Junction Temperature

Junction Temperature

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NCP1652, NCP1652A

200

6.75

6.55

6.35

6.15

5.95

5.75

180

160

140

120

100

−50 −25

0

25

50

75

100

125 150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 38. Supply Current Device Switching

vs. Junction Temperature

Figure 39. Overload Timer vs. Junction

Temperature

5.5

5.3

5.1

4.9

4.7

4.5

500

480

460

440

420

400

−50

−25

0

25

50

75

100

125

150

−50

−25

0

25

50

75

100

125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 40. Overload Detect Threshold vs.

Junction Temperature

Figure 41. Brown−Out Detect Threshold vs.

Junction Temperature

180

175

170

165

160

650

640

630

620

610

600

−50

−25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 42. Brown−Out Exit Threshold vs.

Figure 43. Brown−Out Hysteresis vs. Junction

Junction Temperature

Temperature

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NCP1652, NCP1652A

1000

980

960

940

920

900

7.5

V

CC

7.3

7.1

6.9

6.7

6.5

−50

−25

0

25

50

75

100

125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 44. Latch Pull−Down Voltage Threshold

Figure 45. Latch Pull−Up Threshold vs.

vs. Junction Temperature

Junction Temperature

7.5

7.3

7.1

6.9

6.7

6.5

60

58

56

54

52

50

−50

−25

0

25

50

75

100

125 150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 46. Latch Pull−Up Voltage Threshold

Figure 47. Latch Propagation Delay vs.

Junction Temperature

vs. Junction Temperature

55

54

53

52

51

50

−50 −25

0

25

50

75

100

125

150

T , JUNCTION TEMPERATURE (°C)

J

Figure 48. Latch Clamp Current vs. Junction

Temperature

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NCP1652, NCP1652A

3.5

3.4

3.3

3.2

3.1

3.0

100

98

96

94

92

90

−50

−25

0

25

50

75

100 125

150

−50 −25

0

25

50

75

100 125 150

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 49. Latch Clamp Voltage vs. Junction

Temperature

Figure 50. Latch−Off Current Shutdown vs.

Junction Temperature

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18

NCP1652, NCP1652A

DETAILED DEVICE DESCRIPTION

Introduction

designer familiarity and a vast range of available

components. But, because it processes the power twice, the

search is always on for a more compact and power efficient

solution.

The NCP1652 controller offers the convenience of

shrinking the front−end converter (PFC preregulator) and

the dc−dc converter into a single power processing stage as

shown in Figure 52.

The NCP1652 is a highly integrated controller combining

PFC and an isolated step down ac−dc power conversion in

a single stage, resulting in a lower cost and reduced part

count solution. This controller is ideal for notebook

adapters, battery chargers and other off−line applications

with power requirements between 75 W and 150 W with an

output voltage greater than 12 V. The single stage is based

on the flyback converter and it is designed to operate in CCM

or DCM modes.

NCP1652 Based

Single−Stage

Flyback Converter

Rectifier

&

Filter

AC

Input

V

out

Power Factor Correction (PFC) Introduction

Power factor correction shapes the input current of

off−line power supplies to maximize the real power

available from the mains. Ideally, the electrical appliance

should present a load that emulates a pure resistor, in which

case the reactive power drawn by the device is zero. Inherent

in this scenario is the freedom from input current harmonics.

The current is a perfect replica of the input voltage (usually

a sine wave) and is exactly in phase with it. In this case the

current drawn from the mains is at a minimum for the real

power required to perform the needed work, and this

minimizes losses and costs associated not only with the

distribution of the power, but also with the generation of the

power and the capital equipment involved in the process.

The freedom from harmonics also minimizes interference

with other devices being powered from the same source.

Another reason to employ PFC in many of today’s power

supplies is to comply with regulatory requirements. Today,

electrical equipment in Europe must comply with the

European Norm EN61000−3−2. This requirement applies to

most electrical appliances with input power of 75 W or

greater, and it specifies the maximum amplitude of

Figure 52. Single Stage Power Converter

This approach significantly reduces the component count.

The NCP1652 based solution requires only one each of

MOSFET, magnetic element, output rectifier (low voltage)

and output capacitor (low voltage). In contrast, the 2−stage

solution requires two or more of the above−listed

components. Elimination of certain high−voltage

components (e.g. high voltage capacitor and high voltage

PFC diode) has significant impact on the system design. The

resultant cost savings and reliability improvement are often

worth the effort of designing a new converter.

Single PFC Stage

While the single stage offers certain benefits, it is

important to recognize that it is not a recommended solution

for all requirements. The following three limitations apply

to the single stage approach:

• The output voltage ripple will have a 2x line frequency

component (120 Hz for North American applications)

that can not be eliminated easily. The cause of this

ripple is the elimination of the energy storage element

that is typically the boost output capacitor in the

2−stage solution. The only way to reduce the ripple is to

increase the output filter capacitance. The required

value of capacitance is inversely proportional to the

output voltage – hence this approach is not

th

line−frequency harmonics up to and including the 39

harmonic. While this requirement is not yet in place in the

US, power supply manufacturers attempting to sell products

worldwide are designing for compliance with this

requirement.

Typical Power Supply with PFC

A typical power supply consists of a boost PFC

preregulator creating an intermediate X400 V bus and an

isolated dc−dc converter producing the desired output

voltage as shown in Figure 51. This architecture has two

power stages.

recommended for low voltage outputs such as 3.3 V or

5 V. However, if there is a follow−on dc−dc converter

stage or a battery after the single stage converter, the

low frequency ripple should not cause any concerns.

• The hold−up time will not be as good as the 2−stage

approach – again due to the lack of an intermediate

energy storage element.

DC−DC

Converter

with isolator

Rectifier

&

Filter

AC

Input

PFC

Preregulator

V

out

• In a single stage converter, one FET processes all the

power – that is both a benefit and a limitation as the

stress on that main MOSFET is relatively higher.

Similarly, the magnetic component (flyback

Figure 51. Typical Two Stage Power Converter

A two stage architecture allows optimization of each

individual power stage. It is commonly used because of

transformer/inductor) can not be optimized as well as in

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19

NCP1652, NCP1652A

Active

Clamp

the 2−stage solution. As a result, potentially higher

leakage inductance induces higher voltage spikes (like

the one shown in Figure 53) on the MOSFET drain.

This may require a MOSFET with a higher voltage

rating compared to similar dc−input flyback

applications.

V

in

V

out

Figure 56. Active Clamp

The first two methods result in dissipation of the leakage

energy in the clamping circuits – the dissipation is

2

proportional to LI where L is the leakage inductance of the

transformer and I is the peak of the switch current at

turn−off. An RDC snubber is simple and has the lowest cost,

but constantly dissipates power. A TVS provides good

voltage clamping at a slightly higher cost and dissipates

power only when the drain voltage exceeds the voltage

rating of the TVS.

The active clamp circuit provides an intriguing alternative

to the other methods. It requires addition of a MOSFET and

a high voltage capacitor as part of the active clamp circuit,

thus adding complexity, but it results in a complete reuse of

the leakage inductance energy. As a result, the transformer

construction is no longer critical and one can use cheaper

cost solution. Also, the active clamp circuit reduces the

voltage stress on the primary switch and that can lead to

Figure 53. Typical Drain Voltage Waveform of a

Flyback Main Switch

There are a few methods to clamp the voltage spike on the

main switch, a resistor−capacitor−diode (RCD) clamp, a

transient voltage suppressor (TVS) or an active clamp using

a MOSFET and capacitor can be used as shown in

Figures 54 to 56.

usage of lower cost or lower on resistance (R

MOSFET. Finally, the turn−on switching losses are

eliminated because the active clamp circuit allows the

)

DS(on)

RCD

Clamp

V

in

V

out

discharge of the MOSFET C

turn−on. The energy stored in the leakage inductance is

utilized for this transition.

capacitance prior to the

OSS

R

C

D

In many applications, the added complexity of the active

clamp circuit may not be justified. However, the OUTB of

the NCP1652 is also usable for another purpose,

synchronous

rectification

control.

Synchronous

rectification for flyback converters is an emerging

requirement for flyback converters. The OUTB signal from

NCP1652 is ideal for interfacing with a secondary side

synchronous rectifier controller such as NCP4303 as shown

in Figure 57. As shown in Figure 57, using the OUTB

(coupled through pulse transformer or Y−capacitor) as a

trigger for the NCP4303 allows guaranteed turn−off of the

secondary side synchronous MOSFET prior to turn−on of

the primary switch. In any CCM flyback converter, this is a

critical requirement to prevent cross−conduction and

NCP1652 and NCP4303 combination is the first such

chipset that guarantees the operation without

cross−conduction.

Figure 54. RCD Clamp

TVS

Clamp

V

in

V

out

TVS

Figure 55. TVS Clamp

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20

NCP1652, NCP1652A

V

IN

V

OUT

DRV

TRIG

NCP4303

OUTB

NCP1652

OUTA

Figure 57. NCP1652 and NCP4302 based single stage PFC with synchronous rectification.

The NCP1652 incorporates a secondary driver, OUTB,

with adjustable non overlap delay for controlling a

synchronous rectifier switch in the secondary side, an active

clamp switch in the primary or both. In addition, the

controller features a proprietary Soft−Skip™ to reduce

acoustic noise at light loads. Other features found in the

NCP1652 include a high voltage startup circuit, voltage

feedforward, brown out detector, internal overload timer,

latch input and a high accuracy multiplier.

compensation is also added to the input signal to allow CCM

operation above 50% duty cycle.

High Voltage Startup Circuit

The NCP1652 internal high voltage startup circuit

eliminates the need for external startup components and

provides a faster startup time compared to an external

startup resistor. The startup circuit consists of a constant

current source that supplies current from the HV pin to the

supply capacitor on the V pin (C ). The startup current

CC

(I ) is typically 5.5 mA.

start

NCP1652 PFC Loop

The NCP1652 incorporates a modified version of average

current mode control used for achieving the unity power

factor. The PFC section includes a variable reference

generator, a low frequency voltage regulation error

amplifier (AC error AMP), ramp compensation (Ramp

Comp) and current shaping network. These blocks are

shown in the lower portion of the bock diagram (Figure 51).

The inputs to the reference generator include feedback

signal (FB), scaled AC input signal (AC_IN) and

The OUTA and OUTB drivers are enabled and the startup

current source is disabled once the V voltage reaches

CC

V , typically 15.3 V. The controller is then biased by

CC(on)

the V capacitor. The drivers are disabled if V decays to

CC

its minimum operating threshold (V ) typically 10.3 V.

CC(off)

Upon reaching V

the gate drivers are disabled. The

CC(off)

V

capacitor should be sized such V

is kept above

CC

while the auxiliary voltage is building up.

CC(off)

Otherwise, the system will not start.

feedforward input (V ). The output of the reference

The controller operates in double hiccup mode while in

FF

generator is a rectified version of the input sine−wave scaled

overload or V . A double hiccup fault disables the

CC(off)

by the FB and V values. The reference amplitude is

proportional to the FB and inversely proportional to the

drivers, sets the controller in a low current mode and allows

V to discharge to V . This cycle is repeated twice to

CC

FF

CC(off)

square of the V . This, for higher load levels and/or lower

input voltage, the signal would be higher.

The function of the AC error amp is to force the average

current output of the current sense amplifier to match the

reference generator output. The output of the AC error

amplifier is compensated to prevent response to fast events.

minimize power dissipation in external components during

a fault event. Figure 58 shows double hiccup mode

operation. A soft−start sequence is initiated the second time

FF

V

CC

reaches V . If the controller is latched upon

CC(on)

reaching V , the controller stays in hiccup mode.

CC(on)

During this mode, V never drops below V

, the

CC

CC(reset)

This output (V ) is fed into the PWM comparator through

controller logic reset level. This prevents latched faults to be

cleared unless power to the controller is completely

removed (i.e. unplugging the supply from the AC line).

error

a reference buffer. The PWM comparator sums the V

and

error

the instantaneous current and compares it to a 4.0 V

threshold to provide the desired duty cycle control. Ramp

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21

NCP1652, NCP1652A

V

CC

V

CC(on)

CC(off)

t

OUTA

t

Fault Timer

(internal)

Overload

applied

t

OVLD

Figure 58. V_CCDouble Hiccup Operation with a Fault Occurring while the Startup Circuit is Disabled

An internal supervisory circuit monitors the V voltage

typically 0.85 V. Once V

exceeds V , the startup

inhibit

CC

to prevent the controller from dissipating excessive power

current source is enabled. This behavior is illustrated in

Figure 59. This slightly increases the total time to charge

if the V

pin is accidentally grounded. A lower level

CC

current source (I

) charges C from 0 V to V

,

V , but it is generally not noticeable.

CC

inhibit

CC

inhibit

Figure 59. Startup Current at Various V_CCLevels

The rectified ac line voltage is provided to the power stage

to achieve accurate PFC. Filtering the rectified ac line

voltage with a large bulk capacitor distorts the PFC in a

single stage PFC converter. A peak charger is needed to bias

the HV pin as shown in Figure 60. Otherwise, the HV pin

follows the ac line and the startup circuit is disabled every

time the ac line voltage approaches 0 V. The V capacitor

CC

is sized to bias the controller during power up.

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NCP1652, NCP1652A

Peak Charger

V

OUT

V

IN

HV

OUTA

NCP1652

Figure 60. Peak charger

Adjustable Dead Time

The startup circuit is rated at a maximum voltage of 500 V.

Power dissipation should be controlled to avoid exceeding

the maximum power dissipation of the controller. If

dissipation on the controller is excessive, a resistor can be

placed in series with the HV pin. This will reduce power

dissipation on the controller and transfer it to the series

resistor.

OUTA and OUTB have an adjustable dead time between

transitions to prevent simultaneous conduction of the main

and synchronous rectifier or active clamp MOSFETs. The

delay is also used to optimize the turn−off transition of the

active clamp switch to achieve zero−volt switching of the

main switch in an active clamp topology. Figure 61 shows

the timing relationship between OUTA and OUTB.

Drive Outputs

The NCP1652 has out off phase output drivers with an

adjustable non−overlap delay (t ). The main output, OUTA,

t (lead)

delay

t (trail)

delay

D

drives the primary MOSFET. The secondary output, OUTB,

is designed to provide a logic signal used to control a

synchronous rectification switch in the secondary side, an

active clamp switch in the primary or both. The outputs are

OUTA

OUTB

biased directly from V and their high state voltage is

CC

approximately V

.

CC

OUTA has a source resistance of 13 W (typical) and a sink

resistance of 8.0 W (typical) OUTB has a source resistance

22 W (typical) and a sink resistance of 10 W (typical). OUTB

is a purposely sized smaller than OUTA because the gate

charge of an active switch or logic used with synchronous

rectification is usually less than that of the primary

MOSFET. If a higher drive capability is required, an external

discrete driver can be used.

Figure 61. Timing relationship between OUTA and

OUTB.

The dead time between OUTA and OUTB is adjusted by

connecting a resistor, R , from the R pin to ground. The

D

overlap delay is proportional to R . The delay time can be

D

set between 80 ns and 1.8 ms using the formula:

t_delay(in ns) + 8.0 R_delay(in kW) with

The drivers are enabled once V reaches V

and

CC

CC(on)

there are no faults present. They are disabled once V

R_delayvarying between 10 kW and 230 kW

CC

discharges to V . OUTB is always the last pulse

CC(off)

generated when the outputs are disabled due to a fault

(latch−off, V , overload, or brown−out). The last pulse

terminates at the end of the clock cycle. This ensures the

active clamp capacitor is reset.

The high current drive capability of OUTA and OUTB

may generate voltage spikes during switch transitions due to

parasitic board inductance. Shortening the connection

length between the drivers and their loads and using wider

connections will reduce inductance−induce spikes.

AC Error Amplifier and Buffer

CC(off)

The AC error amplifier (EA) shapes the input current into

a high quality sine wave by forcing the filtered input current

to follow the output of the reference generator. The output

of the reference generator is a full wave rectified ac signal

and it is applied to the non inverting input of the EA. The

filtered input current, I , is the current sense signal at the

in

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23

NCP1652, NCP1652A

ISpos pin multiplied by the current sense amplifier gain. It

is applied to the inverting input of the AC EA.

reference generator output. A pole-zero pair is created by

placing (R and capacitor (C series

a

)

COMP

The AC EA is a transconductance amplifier. A

transconductance amplifier generates an output current

proportional to its differential input voltage. This amplifier

has a nominal gain of 100 mS (or 0.0001 A/V). That is, an

input voltage difference of 10 mV causes the output current

to change by 1.0 mA. The AC EA has typical source and sink

currents of 70 mA.

combination at the output of the AC EA. The AC COMP pin

provides access to the AC EA output.

The output of the AC EA is inverted and converted into a

current using a second transconductance amplifier. The

output of the inverting transconductance amplifier is

V

Figure 62 shows the circuit schematic of the

ACEA(buffer).

AC EA buffer. The AC EA buffer output current, I

is given by Equation 1.

,

ACEA(out)

The filtered input current is a high frequency signal. A low

frequency pole forces the average input current to follow the

VDD

x 4

I

ACEA(out)

To PWM

+

comparator

−

2.8V

V

AC_REF

21.33kW

37.33kW

g

= 100mS

m

+

I

AVG

gm

+

−

AC error

amplifier

R

IAVG

AC COMP

R

AC_COMP

Figure 62. AC EA Buffer Amplifier

2.8 * V_ACEA

amplifier is a wide bandwidth amplifier with a differential

input. The current sense amplifier has two outputs, PWM

(eq. 1)

₊ǒ

Ǔ_@ 4

I_ACEA(out)

37.33k

Output and I

Output. The PWM Output is the

AVG

The voltage at the PWN non-inverting input is determined

by I , the instantaneous switch current along and the

ramp compensation current. OUTA is terminated once the

voltage at the PWM non-inverting input reaches 4 V.

instantaneous switch current which is filtered by the internal

leading edge blanking (LEB) circuitry prior to applying it to

the PWM Comparator non inverting input. The second

output is a filtered current signal resembling the average

value of the input current. Figure 63 shows the internal

architecture of the current sense amplifier.

ACEA(out)

Current Sense Amplifier

A voltage proportional to the main switch current is

applied to the current sense input, IS . The current sense

POS

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24

NCP1652, NCP1652A

I

p

I

spos

g

= 250mS

m

Inst. current A

blanking

To PWM

+

g

m

t

comparator

LEB

−

R

CS

Current sense

amplifier

Inst. current B

blanking

To PWM skip

comparator

t

LEB

I

AVG

V

IAVG

To AC error

amplifier

R

IAVG

Figure 63. Current Sense Amplifier

V_ISPOS

Caution should be exercised when designing a filter

between the current sense resistor and the IS input, due

I_CS+ I_IN

+

(eq. 3)

POS

4k

to the low impedance of this amplifier. Any series resistance

due to a filter creates a voltage offset (V ) due to its input

The PWM Output delivers current to the positive input of

the PWM input where it is added to the AC EA and ramp

compensation signal.

Output generates a voltage signal to a buffer

amplifier. This voltage signal is the product of I

OS

bias current, CA

. The input bias current is typically

Ibias

60 mA. The voltage offset is given by Equation 2.

The I

AVG

V

_OS+ CA_Ibias@ R_external

(eq. 2)

and an

AVG

external R

resistor filtered by the capacitor on the I

IAVG

AVG

The offset adds a positive offset to the current sense signal.

The ac error amplifier will then try to compensate for the

average output current which appears never to go to zero and

cause additional zero crossing distortion.

pin, C

. The pole frequency, f , set by C

should be

IAVG

P

IAVG

significantly below the switching frequency to remove the

high frequency content. But, high enough to not to cause

significant distortion to the input full wave rectified

sinewave waveform. A properly filtered average current

signal has twice the line frequency. Equation 4 shows the

A voltage proportional to the main switch current is

applied to the IS

pin. The IS

pin voltage is converted

POS

into a current, i , and internally mirrored. Two internal

1

relationship between C

(in nF) and f (in kHz).

IAVG

P

currents are generated, I and I

. I is a high frequency

AVG CS

CS

signal which is a replica of the instantaneous switch current.

is a low frequency signal. The relationship between

1

C_IAVG

+

(eq. 4)

I

AVG

2 @ p @ R_IAVG@ f_P

V

ISPOS

and I and I

is given by Equation 3.

CS

AVG

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25

NCP1652, NCP1652A

Oscillator

The gain of the low frequency current buffer is set by the

resistor at the I pin, R . R sets the scaling factor

between the primary peak and primary average currents.

The oscillator controls the switching frequency, f, the jitter

frequency and the gain of the multiplier. The oscillator ramp

is generated by charging the timing capacitor on the CT Pin,

AVG

IAVG IAVG

The gain of the current sense amplifier, A , is given by

CA

C , with a 200 mA current source. This current source is

T

Equation 5.

tightly controlled during manufacturing to achieve a

controlled and repeatable oscillator frequency. The current

RI_AVG

(eq. 5)

A_CA

+

4k

source turns off and C is immediately discharged with a

T

The current sense signal is prone to leading edge spikes

during the main switch turn on due to parasitic capacitance

and inductance. This spike may cause incorrect operation of

the PWM Comparator. Filtering the current sense signal will

inevitably change the shape of the current pulse. The

NCP1652 incorporates LEB circuitry to block the first

200 ns (typical) of each current pulse. This removes the

leading edge spikes without altering the current signal

waveform.

pull down transistor once the oscillator ramp reaches its peak

voltage, V , typically 4.0 V. The pull down transistor

CT(peak)

turns off and the charging current source turns on once the

oscillator ramp reaches its valley voltage, V

.

CT(valley)

Figure 64 shows the resulting oscillator ramp and control

circuitry.

VDD

x 1.2

To PWM

comparator

I

AVG

To PWM skip

comparator

R

IAVG

VDD

C

T

+

C

−

T

+

4.0 V / 0.1 V

Oscillator

Figure 64. Oscillator Ramp and Control Circuitry

The relationship between the oscillator frequency in kHz

and timing capacitor in pF is given by Equation 6.

A low frequency oscillator modulates the switching

frequency, reducing the controller EMI signature and

allowing the use of a smaller EMI filter. The frequency

modulation or jitter is typically 5% of the oscillator

frequency.

47000

C_T

+

(eq. 6)

f

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26

NCP1652, NCP1652A

Output Overload

The Feedback Voltage, V , is directly proportional to the

260 mV. A new Soft−Skip™ period starts once the voltage

on the AC−IN pin increases to 260 mV.

FB

output power of the converter. An internal 6.7 kW resistor

pulls−up the FB voltage to the internal 6.5 V reference. An

external optocoupler pulls down the FB voltage to regulate

the output voltage of the system. The optocoupler is off

during power up and output overload conditions allowing

the FB voltage to reach its maximum level.

The NCP1652 monitors the FB voltage to detect an

overload condition. A typical startup time of a single PFC

stage converter is around 100 ms. If the converter is out of

regulation (FB voltage exceeds 5.0 V) for more that 150 ms

(typical) the drivers are disabled and the controller enters the

double hiccup mode to reduce the average power

dissipation. A new startup sequence is initiated after the

double hiccup is complete. This protection feature is critical

to reduce power during an output short condition.

An increase in output load current terminates a

Soft−Skip™ event. A transient load detector terminates a

Soft−Skip™ period once V voltage exceeds V

by

FB

SSKIP

more than 550 mV. This ensures the required output power

is delivered during a load transient and the output voltage

does not fall out of regulation. Figure 66 shows the

relationship between Soft−Skip™ and the transient load

detector.

Soft−Skip™ Cycle Mode

The FB voltage reduces as the output power demand of the

V

SSKIP

converter reduces. Once V

drops below the skip

FB

V

FB

threshold, V , 1.30 V (typical) the drivers are disabled.

SSKIP

The skip comparator hysteresis is typically 180 mV.

The converter output voltage starts to decay because no

additional output power is delivered. As the output voltage

decreases the feedback voltage increases to maintain the

output voltage in regulation. This mode of operation is

known as skip mode. The skip mode frequency is dependent

of load loop gain and output capacitance and can create

audible noise due to mechanical resonance in the

Figure 66. Load transient during Soft−Skip]

transformer and snubber capacitor.

Soft−Skip™ mode reduces audible noise by slowly

increasing the primary peak current until it reaches its

maximum value. The minimum skip ramp period, t

2.5 ms. Figure 65 shows the relationship between V

A

proprietary

The output of the Soft−Skip™ Comparator is or−ed with

the PWM Comparator output to control the duty ratio. The

Soft−Skip™ Comparator controls the duty ratio in skip

mode and the PWM Comparator controls the duty cycle

during normal operation. In skip mode, the non−inverting

input of the Soft−Skip™ Comparator exceeds 4 V, disabling

the drivers. As the FB voltage increases, the voltage at the

non−inverting input is ramp down from 4 V to 0.2 V to

enable the drivers.

, is

SSKIP

,

FB

V

SSKIP

and the primary current.

Multiplier and Reference Generator

The NCP1652 uses a multiplier to regulate the average

output power of the converter. This controller uses a

proprietary concept for the multiplier used within the

reference generator. This innovative design allows greatly

improved accuracy compared to a conventional linear

analog multiplier. The multiplier uses a PWM switching

circuit to create a scalable output signal, with a very well

defined gain.

Figure 65. Soft−Skip] operation.

Skip mode operation is synchronous of the ac line voltage.

The output of the multiplier is the ac-reference signal. The

ac-reference signal is used to shape the input current. The

multiplier has three inputs, the error signal from an external

The NCP1652 disables Soft−Skip™ when the rectified ac

line voltage drops to its valley level. This ensures the

primary current always ramp up reducing audible noise. A

skip event occurring as the ac line voltage is decreasing,

causes the primary peak current to ramp down instead of

ramp up. Once the skip period is over the primary current is

only determined by the ac line voltage. A Soft−Skip™ event

terminates once the AC−IN pin voltage decreases below

error amplifier (V ), the full wave rectified ac input

FB

(AC_IN) and the feedforward input (V ).

FF

The FB signal from an external error amplifier circuit is

applied to the V pin via an optocoupler or other isolation

FB

circuit. The FB voltage is converted to a current with a V-I

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27

NCP1652, NCP1652A

converter. There is no error in the output signal due to the

series rectifier as shown in Figure 67.

factored by the AC_IN comparator output. The resulting

signal is filtered by the low pass R-C filter on the CM pin.

The low pass filter removes the high frequency content. The

gain of the multiplier is determined by the V-I converter, the

resistor on the CM pin, and the peak and valley voltages of

the oscillator sawtooth ramp.

The scaled version of the full wave rectified input ac wave

is applied to the AC_IN pin by means of a resistive voltage

divider. The multiplier ramp is generated by comparing the

scaled line voltage to the oscillator ramp with the AC_IN

Comparator. The current signal from the V-I converter is

FB

Multiplier

V−to−I

+

AC IN

CM

V

@ V

FB AC_IN

−

V

+ k @

AC_REF

2

V

FF

Oscillator

AC_REF

Divide

2

V

FF

V

FF

Square

Figure 67. Reference Generator

V

_FB@ V_{AC_IN}

The third input to the reference generator is the V signal.

FF

V_{AC_REF}

+

@ k

The V signal is a dc voltage proportional to the ac line

FF

(eq. 8)

2

V_FF

voltage. A resistive voltage divider attenuates the full wave

rectified line voltage between 0.7 and 5.0 V. The full wave

rectified line is then averaged with a capacitor. The ac

average voltage must be constant over each half cycle of the

line. Line voltage ripple (120 Hz or 100 Hz) ripple on the

The multiplier transfer function is given by Equation 8.

The output of the multiplier is the AC_REF. It connects to

the AC Error Amplifier.

where, k is the reference generator gain, typically 0.55. The

output of the reference generator is clamped at 4.5 V to limit

the maximum output power.

V

signal adds ripple to the output of the multiplier. This

FF

will distort the ac reference signal and reduce the power

factor and increase the line current distortion. Excessive

filtering delays the feedforward signal reducing the line

transient response. A good starting point is to set the filter

time constant to one cycle of the line voltage. The user can

then optimize the filter for line transient response versus

Feedforward maintains

a

constant input power

independent of the line voltage. That is, for a given FB

voltage, if the line voltage doubles (AC_IN), the

feedforward term quadruples and reduces the output of the

error amplifier in half to maintain the same input power.

power factor. The average voltage on the V pin is:

FF

AC Error Amplifier Compensation

A pole-zero pair is created by placing a series combination

2

p

Ǹ

V_FF

+

Vac 2a

(eq. 7)

of R

and C

at the output of the AC error amplifier

COMP

Where, a is the voltage divider ratio, normally 0.01.

(EA). The value of the compensation components is

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28

NCP1652, NCP1652A

dependent of the average input current and the instantaneous

switch current. The gain of the average input current or slow

loop is given by Equation 9.

where, V

is the low line ac input voltage, D is the duty

in(LL)

ratio, P is the output power, P is the input power, h is the

out

in

efficiency, L is the primary inductance and t is the on

P

on

time. Typical efficiency for this topology is around 88%.

The current sense resistor is selected to achieve maximum

signal resolution at the input of the ac reference amplifier.

The maximum voltage input of the ac reference amplifier to

prevent saturation is 4.5 V. This together with the

instantaneous peak current is used to calculate the current

R_IAVG

ǒ Ǔ_@ 2.286

@ gm @ R_{AC_COMP}

(

)

(eq. 9)

₊ǒ Ǔ

A_LF

4k

The low frequency gain is the product of the current sense

averaging circuit, the transconductance amplifier and the

gain of the AC error amplifier.

A current proportional to the instantaneous current is

generated using a 4 kW resistor in the current sense amplifier

input. This proportional current is applied to a 21.33 kW at

the PWM comparator input to generate a current sense

sense resistor, R , using Equation 16.

CS

_{4k @}ǒ_V

Ǔ

_in(LL)@ D

(eq. 16)

R

_CS+ 4.5

Ǹ

R

_IAVG@ P_in@ 2

voltage signal. The high frequency or fast loop gain, A , is

HF

calculated using Equation 10.

Ramp Compensation

21.33k

Subharmonic oscillations are observed in peak

current-mode controllers operating in continuous

conduction mode with a duty ratio greater than 50%.

Injecting a compensation ramp on the current sense signal

eliminates the subharmonic oscillations. The amount of

compensation is system dependent and it is determined by

the inductor falling di/dt.

A_HF

+

+ 5.333

(eq. 10)

4k

Equation 11 shows system stability requirements. That is,

the low frequency gain has to be less than one half of the high

frequency gain.

R_IAVG

5.333

ǒ

Ǔ_{@ (2.286) t}

(eq. 11)

ǒ Ǔ

@ gm @ R_{AC_COMP}

2

4k

The NCP1652 has built in ramp compensation to facilitate

system design. The amount of ramp compensation is set by

Equation 12 is obtained by re-arranging Equation 11 for

R

. This equation provides the maximum value for

the user with a resistor, R

, between the Ramp Comp

AC_COMP

RCOMP

.

pin and ground. The Ramp Comp pin buffers the oscillator

ramp generated on the C pin. The current across R

AC_COMP

T

RCOMP

4666

(eq. 12)

R

_{AC_COMP}t

is internally mirrored with a 1:1.2 ratio. The inverted ac error

amplifier and the instantaneous switch current signals are

added to the ramp compensation mirrored current. The

resulting current signal is applied to an internal 21.33 kW

between the PWM Comparator non inverting input and

ground as shown in Figure 64.

The maximum voltage contribution of the ramp

compensation signal to the error signal, V

Equation 17.

R

_IAVG@ gm

The control loop zero, f , is calculated using Equation 13.

Z

The control loop zero should be set at approximately at

1/10 of the oscillator frequency, f

capacitor is calculated using Equation 14.

th

. The compensation

OSC

1

(eq. 13)

(eq. 14)

f_z+

, is given by

RCOMP

2p @ C_{AC_COMP}@ R_{AC_COMP}

1

(eq. 17)

102.38k

C_{AC_COMP}

+

ǒ

Ǔ_@ 21.33k

(

)

(

)

1.2 @ V_CT(peak)

2p @ ^f^OSC@ R_{AC_COMP}

V_RCOMP

+

10

R_RCOMP

Current Sense Resistor

where, V

is the oscillator ramp peak voltage,

CT(peak)

The PFC stage has two control loops. The first loop

controls the average input current and the second loop

controls the instantaneous current across the main switch.

The current sense signal affects both loops. The current

sense signal is fed into the positive input of the error

amplifier to control the average input current. In addition,

the current sense information together with the ramp

compensation and error amplifier signal control the

instantaneous primary peak current.

typically 4.0 V.

For proper ramp compensation, the ramp signal should

match the falling di/dt (which has been converted to a dv/dt)

of the inductor at 50% duty cycle. Both the falling di/dt and

output voltage need to be reflected by the transformer turns

ratio to the primary side. Equations 18 through 23 assist in

the derivation of equations for R and R

.

CS

COMP

2

N_P

_@ǒ Ǔ

N_S

V_out

L_S

V_out

L_P

di

(eq. 18)

(eq. 19)

+

The primary peak current, I , is calculated using

PK

dt_secondary

Equation 15,

N_S

N

V_out

Ǹ

di

dt_primary

di

P

V_in(LL)@ t_on

2 @ P_out

+

@

+

(eq. 15)

I_PK

+

)

dt_secondaryN_P

L_PN_S

h @ V_in(LL)@ D 0.88 @ 2 @ L_P

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29

NCP1652, NCP1652A

di

latch is Set dominant which means that if both R and S are

high the S signal will dominate and Q will be high, which

will hold the power switch off.

(eq. 20)

V_RCOMP

+

@ T @ R_CS@ A_HF

dt_primary

N_S

L_P@ 102.38k

N_PT @ A_HF@ V_out@ R_RCOMP

The NCP1652 uses a pulse width modulation scheme

based on a fixed frequency oscillator. The oscillator

generates a voltage ramp as well as a pulse in sync with the

falling edge of the ramp. The pulse is an input to the PWM

Logic and Driver block. While the oscillator pulse is present,

the latch is reset, and the output drive is in its low state. On

the falling edge of the pulse, the OUTA goes high and the

power switch begins conduction.

The instantaneous inductor current is summed with a

current proportional to the ac error amplifier output voltage.

This complex waveform is compared to the 4 V reference

signal on the PWM comparator inverting input. When the

signal at the non-inverting input to the PWM comparator

exceeds 4 V, the output of the PWM comparator toggles to

a high state which drives the Set input of the latch and turns

the power switch off until the next clock cycle.

(eq. 21)

R_CS

+

@

At low line and full load, the output of the ac error

amplifier output is nearly saturated in a low state. While the

ac error amplifier output is saturated, I

not contribute to the voltage across the internal 21.33 kW

resistor on the PWM comparator non-inverting input. In this

operation mode, the voltage across the 21.33 kW resistor is

determined solely by the ramp compensation and the

instantaneous switch current as given by Equation 22.

is zero and does

ACEA

t_on

(eq. 22)

₊ǒ

Ǔ

V_ref(PWM)

V_RCOMP

@

) V_INST

T

The voltage reference of the PWM Comparator,

, is 4 V. For these calculations, 3.8 V is used to

provide some margin. The maximum instantaneous switch

V

REF(PWM)

current voltage contribution,

Equation 23.

V

,

is given by

INST

Brown−Out

The NCP1652 incorporates a brown−out detection circuit

to prevent the controller operate at low ac line voltages and

reduce stress in power components. A scaled version of the

rectified line voltage is applied to the VFF Pin by means of

a resistor divider. This voltage is used by the brown out

detector.

A brown−out condition exists if the feedforward voltage

is below the brown−out exit threshold, V

0.45 V. The brown−out detector has 180 mV hysteresis. The

controller is enabled once V is above 0.63 V and V

V

_INST+ I_PK@ R_CS@ A_HF

(eq. 23)

Substituting Equation 23 in Equation 22, setting

at 3.8 V (provides margin) and solving for

V

REF(PWM)

R

Equation 24 is obtained.

RCOMP,

⁺ǒ_{3.8 * 5.333 @ I}

Ǔ ^@^t^on

102.38k

R_RCOMP

(eq. 24)

(eq. 25)

T

_PK@ R_CS

, typically

BO(high)

Replacing Equation 24 in Equation 21 we obtain:

FF

CC

3.8

reaches V

. OUTB is the last drive pulse. Figure 68

R_CS

+

CC(on)

N

A

@V

@t

on

out

P

shows the relationship between the brown−out, V , OUTA

and OUTB signals.

P

S

HF

CC

ǒ

Ǔ

@

) 5.333 I_PK

L

PWM Logic

The PWM and logic circuits are comprised of a PWM

comparator, an RS flip-flop (latch) and an OR gate. The

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30

NCP1652, NCP1652A

V

CC

V

CC(on)

CC(off)

t

OUTA

OUTB

Last OUTB Pulase

t

V

FF

V

BO(low)

V

BO(high)

Brown−Out

t

Figure 68. Relationship Between the Brown−Out, V_CC, OUTA and OUTB

Vaux or VCC

VDD

OVP comparator

+

−

+

V

latch(high)

I

latch(clamp)

blanking

Latch−Off

t

latch(delay)

OTP comparator

S

R

−

Ilatch(shdn)

Q

Latch

+

V

NTC

latch(low)

V

latch(clamp)

Reset

Figure 69.

Latch Input

Once the controller is latched, OUTA is disabled and OUTB

generates a final pulse that ends with the oscillator period.

No more pulses are generated after OUTB is terminated.

Figure 70 shows the relationship between the Latch−Off,

The NCP1652 has a dedicated latch input to easily latch

the controller during overtemperature and overvoltage

faults (See Figure 69). The controller is latched if the

Latch−Off pin voltage is pulled below 1 V or above 6.5 V.

V , OUTA and OUTB signals.

CC

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31

NCP1652, NCP1652A

V

CC

V

CC(on)

CC(off)

t

OUTA

OUTB

t

Last OUTB Pulase

t

Latch−Off

V

latch(high)

V

latch(low)

t

Figure 70. Relationship Between the Latch−Off, V_CC, OUTA and OUTB

The Latch−Off pin is clamped at 3.5 V. A 50 mA (typical)

Latch−Off input features a 50 ms (typical) filter to prevent

pull−up current source is always on and a 100 mA (typical)

pull−down current source is enabled once the Latch−Off pin

voltage reaches 3.5 V (typical). This effectively clamps the

Latch−Off pin voltage at 3.5 V. A minimum pull−up or

pull−down current of 50 mA is required to overcome the

internal current sources and latch the controller. The

latching the controller due to noise or a line surge event.

The startup circuit continues to cycle V

between

CC

V

CC(on)

and V

while the controller is in latch mode.

CC(off)

The controller exits the latch mode once power to the system

is removed and V drops below V

.

CC(reset)

CC

APPLICATION INFORMATION

ON Semiconductor provides an electronic design tool,

facilitate design of the NCP1652 and reduce development

cycle time. The design tool can be downloaded at

www.onsemi.com.

The electronic design tool allows the user to easily

determine most of the system parameters of a single PFC

stage The tool evaluates the power stage as well as the

frequency response of the system.

ORDERING INFORMATION

†

Device

NCP1652DWR2G

Package

Shipping

SO−20 WB

(Pb−Free)

1000 / Tape & Reel

2500 / Tape & Reel

NCP1652DR2G

NCP1652ADR2G

SO−16

(Pb−Free)

SO−16

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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32

NCP1652, NCP1652A

PACKAGE DIMENSIONS

SO−20 WB

CASE 751D−05

ISSUE G

D

A

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

20

11

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

E

B

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

1

10

MILLIMETERS

DIM MIN

MAX

2.65

0.25

0.49

0.32

12.95

7.60

20X B

A

A1

B

C

D

E

2.35

0.10

0.35

0.23

12.65

7.40

M

S

B

T

0.25

A

e

1.27 BSC

H

h

10.05

0.25

0.50

0

10.55

0.75

0.90

7

SEATING

PLANE

L

^18Xe

q

_

A1

C

T

http://onsemi.com

33

NCP1652, NCP1652A

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16

9

8

−B−

P 8 PL

M

S

B

0.25 (0.010)

1

MILLIMETERS

INCHES

MIN

0.386

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00

G

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

F

R X 45

K

_

G

J

1.27 BSC

0.050 BSC

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

K

M

P

R

C

7

0

_

−T−

SEATING

PLANE

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

J

M

D

16 PL

M

S

A

0.25 (0.010)

T

B

SOLDERING FOOTPRINT

8X

6.40

16X

1.12

1

16

16X

0.58

1.27

PITCH

8

9

DIMENSIONS: MILLIMETERS

The products described herein (NCP1652), may be covered by one or more of the following U.S. patents; 6,373,734. There may be other patents pending.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP1652/D

http://onsemi.com

34


型号：	NCP1652DWR2G
厂家：	ONSEMI
描述：	Power Factor Controller (PFC), High Efficiency, Single Stage 开关控制器开关式稳压器开关式控制器功率因数校正光电二极管电源电路开关式稳压器或控制器
文件：	总34页 (文件大小：346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1652DWR2G [ONSEMI]

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