NCP1680ABD1R2G_技术文档

CrM Totem Pole PFC IC

Totem Pole CrM Power Factor Correction

Controller

NCP1680

The NCP1680 is a Critical Conduction Mode (CrM) Power Factor

Correction (PFC) controller IC designed to drive the bridgeless totem

pole PFC topology. The bridgeless totem pole PFC consists of two

totem pole legs: a fast switching leg driven at the PWM switching

frequency and a second leg that operates at the AC line frequency. This

topology eliminates the diode bridge present at the input

of a conventional PFC circuit, allowing significant improvement

in efficiency and power density.

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Features

SOIC−16

CASE 751B−05

• Totem Pole PFC Topology Eliminates Input Diode Bridge Enabling

Very High Efficiency & Compact Design

• AC Line Monitoring Circuit & AC Phase Detection

• Brownout Detection

MARKING DIAGRAM

• Critical Conduction Mode (CrM) Operation

• Discontinuous Conduction Mode (DCM) with Valley Turn On under

Light Load Conditions

NCP1680xx

AWLYWW

• Frequency Foldback in DCM with 25 kHz Minimum Frequency

• Digital Loop Compensation

• Simplified Valley Sensing

NCP1680

xx

A

WL

Y

WW

G

= Specific Device Code

= AA or AB

= Assembly Location

= Wafer Lot

= Year

= Work Week

• Novel Current Limit Scheme Eliminates the Needs for Hall Effect

Sensors

• Soft Skip Mode with a Skip Flag for Optimizing Light Load

Performance

• Near Unity Power Factor in All Operating Modes

• PFCOK Indicator

= Pb−Free Package

PIN CONNECTIONS

Safety Features

NCP1680

• Soft and Fast Overvoltage Protection

• 2−Level Latch Input for OVP & OTP

• Bulk Undervoltage Protection

• Internal Thermal Shutdown

• Cycle−by−Cycle Current Limit

FAULT

LVSNS2

LVSNS1

PFCOK

FB

SKIP

GND

AUX

VCC

PWMH

Applications

ZCD

SRH

SRL

PWML

• 5 G/Telecom Power Supplies

• Industrial Power Supplies

• Gaming Console Power Supplies

• Ultra High Density (UHD) Power Supplies

• Merchant Power

PGND

POLARITY

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 35 of this data sheet.

1

Publication Order Number:

June, 2021 − Rev. 0

NCP1680/D

NCP1680

Drawing / Pinout

NCP1680

FAULT

LVSNS2

LVSNS1

PFCOK

FB

SKIP

GND

AUX

VCC

PWMH

ZCD

SRH

SRL

PWML

PGND

POLARITY

Figure 1. NCP1680 Controller Pinout

Typical Application Schematic

Figure 2. Typical Application Schematic

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2

NCP1680

Functional Block Diagram

AC Line Monitor,

Polarity detection

Must be shorted

to PGND

Figure 3. Block Diagram

Pin Description

Table 1. PIN DESCRIPTIONS

Pin Number

Pin Name

FAULT

Function

1

2

Combined OVP/OTP fault pin.

PFCOK

The PFCOK pin is held low when the PFC output voltage is out of regulation and during fault conditions.

The pin becomes active when the PFC output achieves regulation in nominal operation, sourcing a

current proportional to the feedback voltage, V

.

FB

The PFCOK pin is bidirectional; it can be used to enable a downstream converter and can be used by

the downstream converter to force the NCP1680 into Soft Skip Mode operation.

3

4

FB

This pin senses the PFC output voltage for loop regulation.

Skip

The Skip pin is a 5 V signal that goes high when the device enables PWML/H pulses. When the device

enters Soft Skip Mode or is in Fault Mode, the pin will pull to GND.

The Skip pin is bidirectional; it can be used to enable/disable peripheral circuitry, reducing I

CC

consumption in Soft Skip Mode. The pin can also be used to force the NCP1680 into skip mode by

externally grounding the pin for at least 56 ꢀ s.

5

6

GND

ZCD

GND pin should be shorted to PGND.

The pin senses the inductor current downslope. It is used to detect demagnetization and turn−off the

(1−D) switch. Current limit is also based on the signal on this pin. Use of a low inductance current sensing

resistor is recommended.

7

SRH

Control signal for high side slow leg device.

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3

NCP1680

Table 1. PIN DESCRIPTIONS (continued)

8

SRL

POLARITY

PGND

PWML

PWMH

VCC

Control signal for low side slow leg device.

Output of the internal AC polarity detection circuit.

Power ground reference.

9

10

11

12

13

14

PWM logic level output for control of low side fast leg switch.

PWM logic level output for control of high side fast leg switch.

IC supply pin.

AUX

The pin is used to monitor the switch node resonance on the auxiliary winding and enable valley turn−on

during CrM and frequency foldback operation.

15

16

LVSNS1

LVSNS2

Low voltage input for AC line voltage monitoring. LVSNS1 resistor divider should be connected to AC

line side of the boost inductor.

Low voltage input for AC line voltage monitoring. LVSNS2 resistor divider should be connected to the

neutral of the AC line voltage.

Table 2. MAXIMUM RATINGS

Rating

Symbol

Value

Unit

V

Supply Input Voltage, V Pin

VCC

V

−0.3 to 30

−0.3 to 5.5

CC

CC(MAX)

PWML Pin Maximum Voltage

PWML Pin Maximum Current

PWML

V

PWML(MAX)

I

−100

+160

mA

PWML(SRC_MAX)

PWML(SNK_MAX)

PWMH Pin Maximum Voltage

PWMH Pin Maximum Current

PWMH

V

−0.3 to 5.5

V

PWMH(MAX)

I

−100

+160

mA

PWMH(SRC_MAX)

PWMH(SNK_MAX)

SRx, Polarity Pin Maximum Voltage

SRx, Polarity Pin Maximum Current

SRL, SRH,

Polarity

V

−0.3 to 14

V

SRx(MAX)

SRL, SRH,

Polarity

I

−100

+160

mA

SRx(SRC_MAX)

SRx(SNK_MAX)

AUX Pin Input Voltage

AUX

ZCD

V

−0.3 to 5.5 (Note 1)

−2 / +5

V

mA

V

AUX

AUX Pin Input Current

I

AUX

ZCD Pin Input Voltage Range

ZCD Pin Maximum Current

Maximum Input Voltage Other Pins

V

−0.3 to 5.5 (Note 1)

−2 / +5

ZCD

ZCD(MAX)

I

mA

V

LVSNS1,

LVSNS2,

Skip, FB,

FAULT

V

MAX

−0.3 to 5.5 (Note 1)

Maximum Current Other Pins

LVSNS1,

LVSNS2,

Skip, FB,

FAULT

I

−2 to +5

mA

MAX

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation at T = 70°C

Thermal Resistance Junction−to−Air

P

550

145

mW

°C/W

A

D

R

ꢁ

JA

(1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper Clad)

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

T

150

°C

J(MAX)

−40 to +125

−60 to +150

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4

NCP1680

Table 2. MAXIMUM RATINGS (continued)

ESD Capability, HBM Model (Note 2)

ESD Capability, CDM Model (Note 2)

3.5

kV

1.25

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages

can be applied if the pin current stays within the −2 mA / +5 mA range.

2. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,

Charged Device Model 1250 V per JEDEC Standard JESD22−C101E.

3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

Table 3. ELECTRICAL CHARACTERISTICS

(V = 12 V, V

= 1.2 V, V

= 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

J

= 0 V, C

= 100 nF,

CC

LVSNS1

= 100 pF, C

LVSNS2

= C

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH

J

otherwise noted)

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

START−UP & SUPPLY CIRCUITS

Supply Voltage

V

Startup Threshold

Minimum Operating Voltage

V

increasing

decreasing

V

9.75

8.2

1.2

2.5

10.5

8.8

1.7

4

11.25

9.4

–

CC

CC(on)

V

CC(off)

V

CC

Hysteresis (V

− V

)

V

CC(on)

CC(off)

CC(HYS)

CC(reset)

Internal Latch / Logic Reset Level

V

6

Supply Voltage

mA

Before Startup

Fault or Latch

Operational, Switching at 100 kHz

Operational, Skipping

V

= 9.5 V

I

−

1.8

3.3

2.2

4

CC

CC1

CC2

CC3

CC4

= 0 V

FLT

All DRVs Open

= 0 V

V

0.54

0.9

PFCOK

AC ZERO CROSSING MANAGEMENT

Recommended External Divider

Ratio

K

−

100

−

L_DIV

Main PWM Drive Control

PWM Zero Crossing Blanking

Thresholds

Threshold to Stop PWML/H Pulses

mV

V

= ⎪V

− V

⎜

ZCB_STOP

LVSNS1

LVSNS2

V

Decreasing, V

LVSNS2

Increasing, V

LVSNS2

= 0 V

= 4 V

V

LVSNS1

ZCB_STOP1(LL)

V

LVSNS1

ZCB_STOP2(LL)

Threshold to Start PWML/H Pulses

V

= ⎪V

− V

⎜

ZCB_START

LVSNS1

LVSNS2

V

Increasing, V

Decreasing, V

= 0 V

= 4 V

LVSNS2

V

+

LVSNS1

LVSNS2

ZCB_START1(LL)

ZCB_STOPx(LL)

V

20

LVSNS1

ZCB_START2(LL)

−

Zero Crossing Blanking Filter

Polarity Detection Control

Polarity Detection Filter

t

20

25

ꢀ

s

FILT(ZCB)

t

−

200

ꢀ

s

POL_FILTER

Polarity Detection Threshold

V

= V

− V

LVSNS2

mV

POL_DETx

LVSNS1

V

Decreasing, V

Increasing, V

= 0 V

= 4 V

V

−55

−20

−15

15

20

55

LVSNS1

LVSNS2

POL_DET1

LVSNS1

POL_DET2

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5

NCP1680

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 1.2 V, V = 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

J

= 0 V, C

= 100 nF,

CC

LVSNS1

LVSNS2

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, C

= C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH

J

otherwise noted)

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

AC ZERO CROSSING MANAGEMENT

Slow Leg (SR) Drive Control

Slow Leg Zero Crossing Blanking

Thresholds

mV

Threshold to Stop SRx Pulses

V

= ⎪V

− V

⎜

SR_STOP

LVSNS1

LVSNS2

V

Decreasing, V

LVSNS2

Increasing, V

LVSNS2

= 0 V

= 4 V

V

180

LVSNS1

SR_STOP1(LL)

LVSNS1

SR_STOP2(LL)

Threshold to Start SRx Pulses

V

= ⎪V

− V

⎜

SR_START

LVSNS1

LVSNS2

V

Increasing, V

Decreasing, V

= 0 V

= 4 V

V

+

LVSNS1

LVSNS2

SR_START1(LL)

SR_STOPx(LL)

20

LVSNS2

SR_START2(LL)

Synchronous (1 – d) Drive

Control

Sync Zero Crossing Blanking

Thresholds

mV

Threshold to Stop Sync Pulses

V

= ⎪V

− V

⎜

SYNC_STOP

LVSNS1

LVSNS2

V

Decreasing, V

LVSNS2

Increasing, V

LVSNS2

= 0 V

= 4 V

V

200

LVSNS1

SYNC_STOP1(LL)

LVSNS1

SYNC_STOP2(LL)

Threshold to Start Sync Pulses

V

= ⎪V

− V

⎜

SYNC_START

LVSNS1

LVSNS2

V

Increasing, V

Decreasing, V

= 0 V

= 4 V

V

+

LVSNS1

LVSNS2

SYNC_START1(LL)

SYNC_STOPx(LL)

V

SR_START2(LL)

20

LVSNS1

LVSNS2

BROWN−OUT, LINE SAG AND LINE RANGE DETECTION

Line Sag and Brown−Out Detection

⎪V

− V

⎜ Increasing

V

BO(START)

1.02

0.92

1.10

1.00

1.18

1.08

V

LVSNS1

LVSNS2

Upper Threshold

Line Sag and Brown−Out Detection

Lower Threshold

⎪V

− V

⎜ Decreasing

V

BO(STOP)

LVSNS1

LVSNS2

Brown−Out Detection Hysteresis

− V

⎜ Increasing

V

60

20

100

25

mV

ms

LVSNS1

LVSNS2

BO(HYS)

Line Sag Detection Blanking Timer

⎪V

LVSNS1

− V

⎜ < V

t

30

LVSNS2

BO(STOP),

SAG(blank)

Delay to Soft Stop Enable

Brown−Out Detection Blanking

⎪V

− V ⎜ Decreasing,

t

520

2.20

2.07

650

2.36

2.22

780

2.52

2.37

ms

V

LVSNS1

LVSNS2

BO(blank)

Timer

Delay to Polarity Disable

High−Line Level Detection

Threshold

⎪V

− V

⎜ Increasing

V

HL

LVSNS1

LVSNS2

Low−Line Level Detection

Threshold

⎪V

− V

⎜ Decreasing

V

LL

V

LVSNS1

LVSNS2

Line Range Select Hysteresis

− V

⎜ Increasing

V

100

20

140

25

mV

ms

LVSNS1

LVSNS2

LR(HYS)

High to Low Line Mode Selector

Timer

⎪V

− V

⎜ < V

t

30

LVSNS1

LVSNS2

LL

blank(LL)

Low to High Line Mode Selector

Timer Filter

⎪V

− V

⎜ > V

t

200

400

300

500

400

600

ꢀ s

LVSNS1

LVSNS2

HL

filter(HV)

Lockout Timer for Low to High Line

Mode Transition

Low Line Mode,

− V ⎜ > V

t

ms

line(lockout)

⎪V

LVSNS1

LVSNS2

HL

AC LINE FREQUENCY MONITORING

Line Frequency Upper Threshold

Line Frequency Lower Threshold

Device Enable Counter

t

66

37

72

41

4

78

45

Hz

LINE(65)

LINE(45)

N

DRV_EN

Slow Leg Disable Counter

N

1

SR_DIS

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6

NCP1680

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 1.2 V, V = 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

= 0 V, C

= 100 nF,

CC

LVSNS1

LVSNS2

= C

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH J J

otherwise noted)

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

ms

AC LINE FREQUENCY MONITORING

Line Frequency2 Timer

Delay to PWM Disable

t

60

100

165

LINEFREO(DLY)

VALLEY DETECTION CIRCUIT

Valley Detection Thresholds in

Positive Half Line Cycle

V

= 1.2 V, V

= 0 V,

mV

LVSNS1

LVSNS2

V

Rising (Arm)

V

150

50

200

100

250

150

AUX

VD1_TH(rising)

V

Falling (Trigger)

V

AUX

VD1_TH(falling)

Valley Detection Hysteresis in

Positive Half Line Cycle

V

50

100

mV

ns

VD1(HYS)

Propagation Delay of Valley

Detection in Positive Half Line

Cycle

Step V

Time to PWML = 2.5 V

1.5 V to −0.2 V,

T

VD1

50

80

AUX

Valley Detection Thresholds in

Negative Half Line Cycle

V

= 0 V, V = 1.2 V,

mV

LVSNS1

LVSNS2

V

Falling (Arm)

V

50

150

100

200

150

250

AUX

VD2_TH(falling)

Rising (Trigger)

AUX

VD2_TH(rising)

Valley Detection Hysteresis in

Negative Half Line Cycle

V

50

100

mV

ns

VD2(HYS)

Propagation Delay of Valley

Detection in Negative Half Line

Cycle

Step V

Time to PWMH = 2.5 V

0 V to 1.5 V,

T

VD2

45

75

AUX

Minimum AUX Pulse Width

AUX Pin Bias Current,

T

95

1

155

2

ns

SYNC

I

0.5

ꢀ

A

AUX(bias1)

V

= V

AUX

VD1_TH(rising)

AUX Pin Bias Current,

= V

1

2

ꢀ

A

AUX(bias2)

V

AUX

VD1_TH(falling)

FAST LEG DRIVE SIGNALS (PWML & PWMH)

PWMx Rise Time,

x = L, H

V

= 10% to 90% of 5 V,

PWMx

T

95

30

ns

PWMx

PWMx(rise)

C

= 1 nF

PWMx Fall Time

V

PWMx

= 90% to 10% of 5 V,

T

PWMx(fall)

C

= 1 nF

PWMx

Source Resistance

Sink Resistance

ROH

ROL

−

15

5

25

10

ꢂ

Peak Source Current

V

= 0 V

= 5 V

I

100

mA

PWMx

PWMx(SRC)

(Guaranteed by Design)

Peak Sink Current

(Guaranteed by Design)

V

PWMx

I

160

mA

PWMx(SNK)

PWMx Clamp Voltage

R

= 10 kꢂ

V

4.5

90

5

5.5

V

PWMx

PWMx(high)

Non−overlap Time between Falling

Edge of PWMd & Rising Edge of

PWM(1−d)

V

= 0.5 V

T

DT1

130

170

ns

ZCD

SLOW LEG DRIVE SIGNALS (SRL & SRH)

SRx Rise Time

x = L, H

V

= 10% to 90% of 12 V

PWMSRx

T

185

125

ns

PWMSRx

PWMSRx(rise)

C

= 1 nF

SRx Fall Time

V

= 90% to 10% of 12 V

T

PWMSRx(fall)

PWMSRx

C

= 1 nF

PWMSRx

Source Resistance

Sink Resistance

ROH2

ROL2

−

45

30

85

60

ꢂ

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NCP1680

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 1.2 V, V = 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

= 0 V, C

= 100 nF,

CC

LVSNS1

LVSNS2

= C

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH J J

otherwise noted)

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

SLOW LEG DRIVE SIGNALS (SRL & SRH)

SRx Peak Source Current

(Guaranteed by Design)

V

= 0 V

I

100

160

mA

PWMSRx

PWMSRx(SRC)

SRx Peak Sink Current

(Guaranteed by Design)

V

= 12 V

I

PWMSRx(SNK)

PWMSRx

SRx Clamp Voltage

R

= 10 kꢂ ꢃ V = 30 V

V

10

12

9

14

V

PWMSRx

CC

PWMSRx(high)

SRx Minimum Drive Voltage

R

= 10 kꢂ,

7.8

PWMSRx

= V

PWMSRx(MIN)

V

+ 100 mV

CC

CC(off)

POLARITY OUTPUT

POLARITY Rise Time

V

= 10% to 90% of 12 V,

POLARITY

T

185

125

ns

POLARITY

POLARITY(rise)

C

= 1 nF

POLARITY Fall Time

= 10% to 90% of 12 V,

T

POLARITY(fall)

POLARITY

C

= 1 nF

POLARITY

Source Resistance

Sink Resistance

ROH3

ROL3

−

45

30

85

60

ꢂ

POLARITY Peak Source Current

(Guaranteed by Design)

V

= 0 V

I

100

mA

POLARITY

POLARITY(SRC)

POLARITY Peak Sink Current

(Guaranteed by Design)

V

= 12 V

I

160

12

9

mA

V

POLARITY

POLARITY(SNK)

POLARITY Clamp Voltage

R

= 10 kꢂ

= 30 V

V

10

14

POLARITY

POLARITY(high)

V

CC

POLARITY Minimum Drive Voltage

R

CC

= 10 kꢂ

+ 100 mV

V

7.8

V

POLARITY

= V

POLARITY(MIN)

V

CC(off)

ON TIME MODULATION CIRCUIT

Maximum On Time in CrM

NCP1680AA

NCP1680AB

V

< V

T

on, max, CrM

ꢀ s

kHz

ꢀ s

FB

REF,

V

= 1.20 V, V

= 0 V

15.5

9

17.2

10.2

18.9

11.4

LVSNS1

LVSNS2

Maximum Frequency Clamp

NCP1680AA

NCP1680AB

F

clamp1

130

275

On−Time Below Which Frequency

Foldback is Engaged

(t

)

ON_FF LL

(t

)

ON_FF HL

NCP1680AA

Low Line

High Line

3.84

1.92

NCP1680AB

Low Line

High Line

1.82

0.91

Minimum Frequency Clamp

F

25

30.5

260

36

kHz

ns

MIN

Minimum On−Time

V

FB

> V

C

= Open

T

200

320

REF, PWMx

on, min

on, max, DCM

Maximum On Time in DCM

NCP1680AA

T

ꢀ

s

20

NCP1680AB

12.7

REGULATION BLOCK

Feedback Voltage Reference:

@ 25°C

Over the Temperature Range

V

REF

V

2.475

2.44

2.50

2.525

2.56

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NCP1680

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 1.2 V, V = 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

= 0 V, C

= 100 nF,

CC

LVSNS1

LVSNS2

= C

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH J J

otherwise noted)

Characteristics

REGULATION BLOCK

Ratio (V Low Detect Lower

Conditions

Symbol

Min

Typ

Max

Unit

V

Decreasing

Increasing

V

L / V

REF

95.0

95.5

96.0

%

OUT

FB

DRE

Threshold / V

)

REF

(Guaranteed by Design)

Ratio (V Low Detect Higher

V

FB

V

H / V

97.5

2

98.0

2.5

98.5

%

OUT

DRE

REF

Threshold / V

REF

(Guaranteed by Design)

Ratio (V Low Detect

V

FB

H

/ V

REF

−

OUT

DRE

Hysteresis / V

)

REF

(Guaranteed by Design)

STATIC OVP

Duty Ratio

V

FB

= 3 V

D

−

0

%

MIN

SOFT SKIP CIRCUIT

SKIP Voltage in CrM/DCM

SKIP Current Capability

V

4.5

450

1.2

5

5.5

−

V

ꢀ A

V

SKIP

I

700

1.5

SKIP

SKIP Threshold Voltage to Enter

Skip Mode

V

1.8

SKIP(th)

SKIP Minimum Pulse Duration for

SKIP Detection

V

SKIP

< V

T

SKIP1

56

ꢀ s

SKIP(th)

PFCOK SKIP Threshold

V

0.4

10

0.5

30

0.6

50

V

SKIP2

Minimum PFCOK Negative Pulse

Duration for SKIP Detection

T

SKIP2

ꢀ s

V

Lower Value at the End of a

(R

)

92.5

94

95.5

%

FB

FB recover

Soft Skip Cycle Burst Defined as a

V

REF

Percentage

V

Restart Level in Skip Cycle

V

2.35

500

V

FB

RESTART

Blanking Time for Operation

Recovery

T

400

600

ms

recover

SKIP Confirmation Window

T

400

ꢀ

s

WINDOW

ZCD PIN

ZCD Arming Threshold

NCP1680AA

NCP1680AB

V

Increasing

Decreasing

V

mV

ZCD

ZCD(ARM)

300

100

ZCD Trigger Threshold

V

ZCD

V

50

mV

ZCD(TRG)

Threshold for Inrush Current

Protection

V

ZCD(INRUSH)

Propagation Delay to (1−D) Drive

Step V

ZCD(ARM)

Time to PWMx = 2.5 V

0 V to

T

−

45

75

ns

V

ZCD

ZCD(ARM)

Pulse

V

+ 250 mV

Propagation Delay (1−D) Drive

Termination

Step V

1 V to

− 250 mV;

T

ZCD(TRG)

ZCD

V

ZCD(TRIG)

Time to PWMx = 2.5 V

Low−Line Range ZCD Protection

Threshold

V

ZCDLIM1(LL)

NCP1680AA

NCP1680AB

1.33

0.56

1.4

0.6

1.47

0.64

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9

NCP1680

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 1.2 V, V = 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

= 0 V, C

= 100 nF,

CC

LVSNS1

LVSNS2

= C

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH J J

otherwise noted)

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

ZCD PIN

High−Line Range ZCD Protection

Threshold

V

ZCDLIM1(HL)

NCP1680AA

NCP1680AB

0.80

0.325

0.84

0.36

0.88

0.395

On−Time in CrM Current Limit

V

FB

= 2.0, V

pulse 0–2 V

ꢀ s

ZCD

LVSNS1 = 1.626, Pulse for 16 ꢀ s

LVSNS1 = 3.253, Pulse for 14 ꢀ s

T

1.9

1.3

ON_ZCDLIM(LL)

ON_ZCDLIM(HL)

ZCD Pullup Current Source

V

= 0 V

= 2.7 V

I

0.7

1

1.3

ꢀ A

ZCD

V

ZCD

ZCD Minimum Current Threshold

for THD Enhancer Enable

NCP1680AA

NCP1680AB

V

Increasing

V

mV

ZCD

ZCD(MIN)

45

5

70

30

95

55

ZCD Minimum Current Ratio

K

= V

/V

K

5

%

ZCD(MIN)

ZCD(MIN) ZCDLIM1(LL)

UNDERVOLTAGE & OVERVOLTAGE PROTECTION

UVP Threshold

V

Decreasing

V

R

−

0.3

−

FB

UVP

Ratio (UVP Threshold) over V

UVP REF

V

Decreasing

Increasing

8

12

50

16

mV

V

REF

FB

UVP

(V

/V

)

UVP Hysteresis

V

−

100

FB

UVP(HYST)

Soft OVP Threshold

V

Increasing

V

R

−

2.625

105

−

%

FB

softOVP

Ratio (soft OVP Threshold) over

(V /V

V

FB

104

106

softOVP

V

REF

)

softOVP REF

Ratio (soft OVP Hysteresis) over

REF

V

Decreasing

Increasing

R

1.5

2

2.5

V

FB

softOVP(H)

V

Fast OVP Threshold

V

R

−

2.7

−

%

FB

fastOVP

Ratio (Fast OVP Threshold) over

(soft OVP Upper Threshold)

fastOVP softOVP

V

Increasing

R

102.4

106.5

103

103.4

109.5

%

FB

fastOVP1

fastOVP2

(V

/V

)

Ratio (Fast OVP Threshold) over

(V /V

V

FB

Increasing

Decreasing

108

%

V

REF

)

fastOVP REF

FB Threshold for Recovery from a

Soft or Fast OVP

V

FB

V

2.575

OVPrecover

FB Bias Current @ V = V

(I )

B FB

50

250

450

nA

FB

softOVP

and V = V

FB

UVP

PFCOK & BUV PROTECTION

PFCOK Voltage in OFF Mode

PFCOK Current

PFCOK Pin Sink Current = 1 mA

= 2.5 V, V = 1 V

V

−

100

27

mV

ꢀ A

V

PFCOK(low)

V

FB

I

PFCOK

23

25

PFCOK

BUV Threshold

V

FB

Decreasing

V

BUV

T

BUV

1.95

400

2.0

500

2.05

600

BUV Delay During Which Operation

Is Disabled

ms

FAULT PROTECTION

OTP Fault Threshold

V

Decreasing

V

0.38

43

0.40

46

0.42

49

V

Fault

FLT(OTP)

OTP Fault Source Current

V

= V

+ 200 mV

I

FLT

ꢀ

A

Fault

FLT(OTP)

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10

NCP1680

Table 3. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 1.2 V, V = 0 V, V = 2.4 V, V

= open, C

= 100 pF, V

= 0 V, V

= 0 V, C

= 100 nF,

CC

LVSNS1

LVSNS2

= C

FB

FAULT

POLARITY

AUX

ZCD

VCC

C

= C

= 100 pF, C

= 100 pF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless

SRL

SRH

PWML

PWMH J J

otherwise noted)

Characteristics

FAULT PROTECTION

Conditions

Symbol

Min

Typ

Max

Unit

OTP Detection Filter Delay

OTP Blanking During Startup

OTP Fault Recovery Threshold

OVP Fault Threshold

V

Decreasing

t

22.5

4

30

5

37.5

6

ꢀ s

ms

V

Fault

OTP(DLY)

t

OTP(BLANK)

V

Increasing

V

0.874

2.88

0.92

3

0.966

3.12

Fault

FLT(REC)

V

Fault

FLT(OVP)

OVP Detection Filter Delay

Fault Clamp Voltage

V

Increasing

t

22.5

1.15

1.32

30

1.7

37.5

2.25

1.78

ꢀ s

V

Fault

OVP(DLY)

V

= Open

V

R

Fault

FLT(CLAMP)

Fault Clamp Resistance

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

1.55

kꢂ

Temperature Increasing

Temperature Decreasing

T

SHDN

−

150

50

−

°C

T

SHDN(HYS)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Totem Pole Theory of Operation

Figure 4. Block Diagram

The Totem Pole PFC (TPFC) circuit is shown in Figure 4.

The topology consists of two half−bridge configurations;

one half bridge, commonly referred to as the “Fast Leg”

switches at the PWM frequency and the other, commonly

referred to as the “Slow Leg” switches at the AC line

frequency. The fast leg switches perform the role of the

switch and the diode in a classical boost PFC, that is these

switches function to regulate the output voltage and shape

the input current to provide high power factor and low

harmonic distortion. The slow leg switches perform the role

of the diode bridge in a classical boost PFC. Active switches

with low ON resistance are utilized instead of diodes

resulting in improved efficiency. Also, as will be described

in the discussion below, the TPFC operates with only one

slow leg and one fast leg device in the conduction path

whereas the conventional boost PFC operates with two

bridge diodes and one active switch or boost diode in the

conduction path. Fewer devices in the conduction path and

active switches replacing bridge diodes allow the TPFC

topology to achieve higher system efficiency and power

density than the classical boost PFC.

The fast leg switches are represented as MOSFETs in this

particular figure, but the type of switch used for these

devices is adaptable and either silicon FETs or Wide

Bandgap (WBG) transistors can be used. Silicon FETs

specified as fast recovery and/or low reverse recovery

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11

NCP1680

charge (Q ) are suitable for this topology. WBG devices,

whether Silicon Carbide (SiC) or Gallium Nitride (GaN),

The TPFC operates with bidirectional current flow in the

inductor and the command of the fast and slow leg switches

changes depending on the polarity of the AC line cycle.

Operation of the TPFC during the positive and negative half

line cycles is illustrated in Figure 5 and Figure 6,

respectively.

rr

offer excellent Q *R

figure of merit and virtually no

g

ds(on)

Q , making them optimal devices for the TPFC fast leg. The

rr

NCP1680 is designed for Critical Conduction Mode (CrM)

and the PWM drive signals are logic level signals so there is

no restriction on using either Si or WBG devices with the

selection of an appropriate external half bridge driver.

Positive Half Cycle Operation

Figure 5. Positive Half Cycle Operation

During the positive AC line cycle the PWML signal is

responsible for performing pulse width modulation or duty

cycle control of the converter. PWML toggles high turning

on the low side fast leg device, allowing current to charge

and store energy in the inductor, as shown by the solid blue

line in Figure 5. When the PWML signal toggles low the

inductor current diverts through the high side fast leg switch,

transferring energy from the inductor to the load, as shown

by the dashed blue line. In this half line cycle the high side

fast leg device does not need to conduct for proper PFC

operation, however the PWMH signal can toggle high to

turn on the high side device, providing enhanced system

efficiency at medium to high load levels. Throughout the

positive half line cycle current is flowing left to right through

the inductor and always returning to the source through the

low side slow leg device, hence the SRL signal can toggle

high to turn on the respective slow leg device for optimum

converter efficiency.

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NCP1680

Negative Half Cycle Operation

Figure 6. Negative Half Cycle Operation

During the negative AC line cycle the PWMH signal is

responsible for performing pulse width modulation or duty

cycle control of the converter. PWMH toggles high

commanding the high side fast leg device to conduct,

allowing current to charge and store energy in the inductor,

as shown by the solid red line in Figure 6. When the PWMH

signal toggles low the inductor current diverts through the

low side fast leg switch, transferring energy from the

inductor to the load, as shown with the dashed red line. In

this half line cycle the low side fast leg device does not need

to conduct for proper PFC operation, however the PWML

signal can toggle high to turn on the low side device,

providing enhanced system efficiency at medium to high

load levels. Throughout the negative half line cycle current

is flowing right to left through the inductor and always

returning to the source through the high side slow leg device,

hence the SRH signal can toggle high to turn on the

respective slow leg device for optimum converter

efficiency.

from a downstream converter. Additionally, the controller

must have sufficient input voltage (BONOK cleared) and

validation that the ac line frequency is within the expected

operating range (N

> 4), then the control can power

DRV_EN

up on the next rising polarity edge, synchronizing the startup

to a positive half line cycle. The startup requirements are

summarized:

• Brown−out protection, BONOK, is cleared

• V > V

CC

CC(ON)

• N

> 4

DRV_EN

• Polarity rising edge

If the supply voltage is in the hysteresis band, i.e. if

V

< V < V

then the controller will not start

CC(OFF)

CC

CC(ON)

up. This is done to ensure that the minimum specified

hysteresis between V and V of 1.2 V, is

CC(ON)

CC(OFF)

available for the device so that the increased current

consumption at startup doesn’t pull V below V

,

CC(OFF)

CC

typically 8.8 V. Once the device has been enabled then the

voltage can fall to as low as V without disabling

V

CC

CC(OFF)

V_CCManagement and Startup Sequence

The NCP1680 controller requires a supply bias of at least

but for startup the V voltage has to exceed and remain

CC

above V

.

CC(ON)

V , typically 10.5 V, to enable and begin normal

CC(ON)

operation. Since the controller does not include an internal

high voltage startup, the bias supply will have to come from

an external source such as a dedicated auxiliary supply or

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13

NCP1680

Line Voltage Sensing

node of the main boost inductor, L , and the LVSNS2

BOOST

Figure 7 shows the recommended application

configuration for the line voltage sensing scheme. External

resistor dividers are required to divide down two high

voltage nodes to perform differential line sensing. The

recommended divide down factor for universal input

pin is intended to interface with the bridge voltage of the

slow leg power switches. The internal Line Detector circuit

is designed with substantially high input impedance

allowing for large external resistors to minimize the power

dissipation in the dividers, enabling the application to

achieve low no load power consumption. Typical values for

consumer applications is K

, typically 100; i.e.

L_DIV

R_LOWERx

R

can be in the range of 5 Mꢂ to 10 Mꢂ while

can be 50 kꢂ to 100 kꢂ. In practice the upper

1

UPPERx

+

such that the low voltage

K_{L_DIV}

(R_LOWERx) R_UPPERx

)

LOWERx

signals which interface to the NCP1680 are approximately

1% of the high voltage signals that are being monitored. The

LVSNS1 pin is intended to interface with the low frequency

portion of the resistor divider should consist of at least two

1206 components connected in series to withstand the

voltage drop.

Figure 7. Line Sensing Configuration

In the Totem Pole topology the AC line voltage floats with

respect to the controller ground. This necessitates a

differential measurement technique to determine the AC

line voltage magnitude. The NCP1680 employs differential

voltage detection and rectification to reconstruct a

sensing will additionally be responsible for determining the

polarity (i.e. positive or negative half−line cycle) of the AC

voltage and for measuring the frequency of the AC line

voltage. In total, the line sense will be utilized for the

following functions:

waveform equal to |V

– V

|. For simplicity

a. Polarity detection

LVSNS1

LVSNS2

|V

LVSNS1

– V

| will be referred to as V . The key

b. AC Line Frequency Monitoring

LVSNS2

LINE

waveforms are shown in Figure 8. The reconstructed

waveform is utilized to perform functions such as

brown−out and line level detection where it is necessary to

measure the amplitude of the line voltage. The line voltage

c. Brownout protection feature

d. Line level detection

e. AC zero crossing drive management

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NCP1680

Figure 8. Line Sense Waveforms

Polarity Detection

capacitance may be added to improve noise immunity of the

polarity detection circuitry; the recommend time constant of

the RC filter is about 50 ꢀ s to 200 ꢀ s, enough to provide

noise immunity from the switching frequency of the power

supply but not such a large time constant so as to introduce

significant lag in the line sense signals.

Figure 9 shows a simplified diagram of the polarity

detection circuitry. The two line sense signals are compared

directly against each other to determine when they intersect.

The intersection or crossover of the two signals indicates

that the AC line voltage has changed polarity. External filter

Figure 9. Polarity Detection Diagram

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15

NCP1680

Additionally, the output of the polarity sense comparison

from high to low (or vice versa) but does not remain in that

state for a time greater than T , then the output

will remain in its previous logic state and the timer will

effectively reset. In Figure 10, time durations t1, t2, t3 and

circuit is passed through a digital glitch filter which will

provide additional immunity if the comparison circuit is

toggling repeatedly. The glitch filter has a timer,

POL_FILTER

T

, of 200 ꢀ s. The behavior of the filter is shown

POL_FILTER

t5, t6, t7 are all less than T

and hence the output

POL_FILTER

below in Figure 10. The input to the filter must remain at a

logic state (high or low) for greater than the filter’s timer for

the output to transition to that state. If the input transitions

of the filter remains unchanged. Time durations t4 and t8 are

greater than T , causing the output to transition to

POL_FILTER

the new state.

Figure 10. Polarity Glitch Filter Operation

AC Line Frequency Monitoring

The NCP1680 controller comes with an optional line

frequency monitoring circuit. The NCP1680 utilizes timers

Should the polarity toggles continue to measure outside of

the mains frequency specification and the timer expires then

the controller will disable fast leg drive pulses and enter fault

& counters to monitor the AC line frequency (T

)

LINEFREQ

to ensure that the polarity comparator output toggles at a rate

consistent with the mains frequency specification of

45 Hz to 65 Hz. A timing diagram of the AC line frequency

monitor operation is shown in Figure 11. Practically the

controller measures the time between every edge transition

of the filtered polarity signal. If one timing interval, such as

mode as shown after t . Note that throughout timing interval

5

t the slow leg pulses are disabled. While in fault mode the

5

polarity signal and the line frequency monitor will remain

active, performing continuous time interval measurements

of the polarity signal. The device will auto−recover from the

fault mode once the device detects 4 consecutive polarity

edges that are within the line frequency specification, same

as a new startup. The thresholds for the AC line frequency

t , measures outside of the expected frequency range then

1

the controller will disable the slow leg drive signals, SRL

and SRH, and start a 100 ms timer, t

. If a

monitor are given by t , nominally 72 Hz, and

LINE(65)

LINEFREQ(DLY)

timing interval within the specification is measured prior to

expiring, then t is reset and

t

, nominally 42 Hz. These thresholds are designed to

LINE(45)

t

provide some margin so that under worst case tolerance the

AC line frequency can always operate from 45 Hz to 65 Hz.

LINEFREQ(DLY)

slow leg drive pulses are again enabled. This is shown with

timing interval t and t .

2

3

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16

NCP1680

Figure 11. Line Frequency Faults Timing Diagram

th

As previously mentioned, startup of the NCP1680

controller is synchronized to the rising edge of the filtered

polarity signal and requires at least 4 consecutive half−line

high on the rising edge of the 4 consecutive polarity toggle

with valid time duration. The rising edge of the polarity

signal indicates that the AC line is entering a positive half

line cycle which is the preferred conduction angle for

starting up the application because the low−side fast leg

device will be the duty cycle controlled device.

cycles (polarity toggles) to be within the valid T

LINEFREQ

duration. The controller enable counter is denoted as

in the electrical table. Line Frequency operation

N

DRV_EN

is shown in Figure 12 where the Line Freq OK flag is set

Figure 12. Polarity Startup Timing Diagram

Brown−Out and Line Sag Protection

disabling drive pulses when the line voltage falls below the

The NCP1680 feature set includes line voltage

Brown−out (BO) and Line sag (SAG) detection. These

detection circuits function collaboratively as a line voltage

UVLO, enabling drive pulses when the peak line voltage

V

threshold, typically 1 V, for a given timer duration.

BO(stop)

Considering that the LVSNSx inputs are recommended to be

1% of the AC line voltage, this translates to a nominal enable

threshold of ~ 110 V, or ~ 78 V , and a nominal disable

AC

exceeds the V

threshold, typically 1.1 V, and

threshold of ~ 100 V, or ~ 71 V

.

BO(start)

AC

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17

NCP1680

V

BO(start)

+

BO_H_cmp

CMP

Vline

Bi−dir Timer

360 ꢀ s up

BO

−

650 ms down

Bi−dir Timer

360 ꢀ s up

25 ms down

V

BO(stop)

SAG

+

BO_L_cmp

CMP

−

Figure 13. BO/SAG Detection Circuit

Figure 13 is a representative schematic of the NCP1680

BO/SAG detection circuitry. The circuitry monitors the line

are the same, with the difference between the two features

being the timing after which the respective output is set high,

and the action taken by the controller after each of the

respective outputs. Figure 14 illustrates the controller

response during a line sag and brownout.

voltage, V , generated by the NCP1680’s internal

LINE

differential line sensing. V

is compared against the two

LINE

V

BO

thresholds. Both the BO and SAG voltage thresholds

Figure 14. Line Sag and Brownout Timing Diagram

The 25 ms SAG timer, t

, allows the application

gradually narrowed, reducing the power delivery of the

application. After the soft stop period the polarity signal

remains active and the controller will be ready for

immediate restart should the line voltage exceed the

SAG(blank)

to sustain a line voltage dropout for a single AC line cycle

while the NCP1680 continues to deliver drive pulses. If the

SAG timer expires, the controller will enter a soft stop

period where the internal control voltage is slowly

discharged to 0 V and the pulse width of the PWM is

V

threshold. If the 650 ms brown−out timer expires,

BO(start)

the NCP1680 will disable the polarity detection circuit and

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18

NCP1680

reset the device, including any latching faults. When the

application restarts from a BO the controller functions as it

would for an initial power up.

mV to act as another protection against the device oscillating

back and forth between low and high line.

The purpose of line range detection is that the controller

modifies the gain of the internal digital compensator in order

to optimize performance and operation of the PFC for

universal, wide−input mains applications. Specifically, the

loop gain of the digital compensator is reduced by a factor

of 4 when the device detects that it is in the high line range.

Line Range Detection

The NCP1680 features input voltage range detection,

which distinguishes between high line (nominally 230 V

)

AC

and low line (nominally 115 V ) input voltages. The input

AC

voltage range is detected based on the peak voltage

measured with the reconstructed V

signal. By default

AC Zero Crossing Management

LINE

the controller will power up into low line mode. If V

AC zero crossing management is the feature in the

NCP1680 that determines when to enable and disable the

various drive signals at the beginning and end of each of the

half line cycles. This feature is critical to the robustness and

performance of the Totem pole topology. The NCP1680

features 6 drive signals that can be divided into three classes:

1. The primary or duty−cycle controlled PWM drive

signal.

LINE

exceeds the high line threshold, V , typically 2.36 V, for a

HL

duration longer than t , typically 300 ꢀ s, the

filter(HV)

controller transitions to high line mode. Once in high line

mode the peak line voltage must fall below V , typically

LL

2.22 V, for a duration longer than t

, typically 25 ms,

blank(LL)

to enter back into the low line mode. The blanking duration,

, is set long enough to allow the controller to remain

t

blank(LL)

in high line mode in the event of a single line cycle dropout.

Should the controller transition from high line to low line

2. The synchronous (sync) PWM drive signal that

occurs during the (1 − d) portion of the switching

period.

mode, a lockout timer t , typically 500 ms, is

line(lockout)

enabled. The lockout timer blocks the controller from

transitioning back to high line immediately after a low line

transition for the duration of the timer, preventing the

controller from oscillating between low line and high line

mode. The transition thresholds of 2.36 V and 2.22 V

3. The slow leg “rectifier” or SR drive signal that

switches once per half line cycle.

Each drive signal has a respective stop and start threshold,

which is a function of the line voltage amplitude, V

,

LINE

where V

= |V

– V

| as previously

LINE

LVSNS1

LVSNS2

typically translate to line voltages of 167 and 157 V

,

AC

mentioned.

respectively, which are intermediate voltages that do not

correspond to any national standard for AC mains, leaving

little likelihood that the input voltage to the application will

operate near the transition thresholds. Further, the transition

Figure 15 illustrates the zero crossing management

thresholds for the primary PWM drive, denoted as PWMd.

The same stop and start principle applies to the Synchronous

PWM and SR drives, although with different thresholds.

thresholds have a minimum hysteresis, V

, of 100

LR(HYS)

Figure 15. AC Zero Crossing Management Thresholds

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19

NCP1680

Open Loop Drive Pulses

Figure 15 shows a full AC line cycle beginning with a

positive half−line cycle, i.e. conduction angle between 0° to

180°. In the positive half−line cycle the voltage at the

LVSNS2 pin is pulled to 0 V and the voltage at LVSNS1 is

increasing proportional to the AC line amplitude. When the

Another critical feature of the NCP1680 is the open loop

drive pulses that are issued immediately following a polarity

transition. After the AC line zero crossing, the slow leg

bridge maintains a residual voltage charge from the previous

half line cycle and must be transitioned from V

to 0 V

AC line amplitude exceeds the threshold V

,

BULK

ZCB_START1(xL)

(or vice versa) during the upcoming half line cycle.

Considering that PWM−controlled drive pulses near an AC

line zero crossing would typically operate with a high duty

cycle, using these pulses to transition the slow bridge

voltage can result in excessively high current spikes in the

inductor; hence it is beneficial use shorter drive pulses drive

pulses with a smaller, fixed duty cycle to initiate the slow leg

bridge node transition. The ON time of the main

duty−controlled FET is gradually increased during this

phase to assist the slow leg bridge node voltage in

transitioning between the bulk voltage and ground. The OFF

time of the main duty−controlled FET is also gradually

increased during this phase to maintain the same duty ratio.

During the open loop drive pulses the slow leg drive and

(1−d) drives are held at 0. The duration and period of the

open loop drive pulses is capture in Table 4.

typically 120 mV, the controller begins issuing drive signals

to the duty−controlled device, PWML in this case. As the

conduction angle approaches 180°, V

will eventually

threshold, typically 100 mV,

LINE

fall below the V

ZCB_STOP1(xL)

and the controller will blank drive pulses to the

duty−controlled device.

In the negative half line cycle the zero crossing

management works largely the same as positive half line

cycle with the controller processing the different LVSNS

signals that are unique to negative half line cycle operation.

In this half line cycle LVSNS2 is pulled up to a voltage

proportional to about 1% of the PFC bulk voltage, and the

LVSNS1 decreases in amplitude relative to the controller

GND pin, but increases in amplitude relative to the LVSNS2

signal. The controller’s differential line sensing reconstructs

V

LINE

= |V

– V

| so that V

is symmetrical

LVSNS1

LVSNS2

LINE

in positive and negative half line cycle and the zero crossing

management can use the same comparison thresholds for

Table 4. OPEN LOOP DRIVE PULSES

both half line cycles. The V

threshold is

ZCB_START2(xL)

Ton (ms)

Toff (ms)

Period (ms)

120 mV, and the V

threshold is 100 mV, same

ZCB_STOP2(xL)

st

1

Pulse

1

2

3

4

8

5

as the start and stop thresholds in positive half line cycle,

ensuring that the zero crossing management is symmetric

across a full AC line cycle.

Zero crossing management of the synchronous PWM and

SR drives follows the same principle as that used to manage

the primary PWM drive, however the thresholds are higher

as the primary PWM switches for a greater portion of the

nd

2

10

15

20

50

rd

3

4

12

16

th

total

half line cycle. For the slow leg SR drive, V

SR_START1(xL)

Figure 16 provides an annotated timing diagram of a zero

crossing transition including the open loop drive pulses. For

simplicity, the sync PWM (1−D) drive signals are not shown

in this figure.

is typically 200 mV and V

is typically 180 mV

SR_STOP1(xL)

and because operation is symmetric the start and stop

thresholds in negative half line cycle are the same. For the

sync drive, the start threshold, V

, is

SYNC_START1(xL)

typically 220 mV and the stop threshold is typically 200 mV.

All of the thresholds in the AC zero crossing management

block include hysteresis to ensure stable operation without

repeated enabling and disabling should noise corrupt the

LVSNS signals. Also, all of the drive signals are disabled

before the AC line voltage reaches its true zero crossing.

While this can lead to a small amount of increased zero

crossing distortion, the benefit of disabling all drives is to

create a quite environment to ensure the precision and

robustness of the polarity signal which is critical to

guarantee that the PWM and SR drive signals are directed to

the proper device during the respective half line cycle.

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20

NCP1680

PWMH

SRH

PWML

Event (A)

Event (A) – When the sensed line voltage falls below

, the “D” drive signal is disabled.

V

ZCB_STOP2(xL)

Fast leg

DRV signals

Event (B) – When the sensed line voltage falls below

, the slow leg drive signal is disabled.

Event (H)

V

SR_STOP2(xL)

Note that Event (B) occurs before Event (A).

Event (B)

Slow leg

DRV signals

SRL

Event (C) – The two sense nodes cross over, repre-

senting the actual AC phase reversal instant.

Event (I)

Event (D) – The polarity edge after the filter.

Polarity

Event (C)

Event (E) – Open Loop Drive pulses issued on the low

side (PWML) drive during the negative to positive half

line cycle transition or on the high side (PWMH) drive

during the positive to negative half line cycle transi-

tion.

Event (D)

Polarity

post filter

T

Event (F) – The open loop drive pulses assist the slow

leg switch node transition from 400 V to 0 V or from

0 V to 400 V.

POL_FILTER

Open loop

Event (E)

Event (G)

DRV pulses on

Event (G) – Settling of the slow leg switch node

voltage.

PWML

T

VBR2 SETTLE

Event (H) – Fast leg drive (PWML) is enabled if the

line voltage exceeds V

ZCB_START1(xL)

400 V

Event (I) – Low side slow leg (SRL) is enabled if the

line voltage exceeds V

Slow leg

switch node

.

SR_START(xL)

Event (F)

0 V

Figure 16. AC Zero Crossing Timing Diagram

Operating Modes

The NCP1680 achieves power factor correction by

operating in a Frequency Clamped Critical Conduction

Mode (FCCrM). An illustration of FCCrM operation is

shown in Figure 17. In FCCrM the controller operates in

critical conduction mode (CrM) at higher load levels where

the peak inductor current is high, and the switching

frequency is slower. As the load level decreases the peak

inductor current decreases which naturally forces the

application to operate at higher switching frequencies. The

switching frequency will continue to increase until a

mitigates against hard switching operation by continuously

tracking the resonant valleys and always beginning a new

switching cycle during a valley as shown in Figure 17. As

the load decreases towards 0, the controller clamps the

switching frequency to a minimum, F

~ 30 kHz, to mitigate audible noise.

, typically

MIN

Note that frequency−clamped operation is controlled by

novel circuitry which modulates the on−time and switching

period on a cycle−by−cycle basis to prevent any

discontinuity in operation and ensure proper current

shaping. Within any AC half−line cycle of operation, the

circuit can readily transition between CrM and DCM, often

operating in DCM near the AC line zero crossings and in

CrM at the peak of the AC line as the inductor currents are

larger, forcing lower switching frequencies. These

transitions between CrM and DCM should occur

seamlessly, causing no discontinuity or oscillation in the

operation.

maximum frequency clamp, F , is reached, after

CLAMP

which the controller transitions into a discontinuous

conduction mode (DCM) of operation. F is 130 kHz

CLAMP

for the NCP1680AA and 275 kHz for the NCP1680AB.

Once in DCM the switching frequency will decrease,

gradually, as the load decreases. The frequency reduction in

DCM is achieved by a novel ramp modulation circuit that

forces longer switching periods, and more resonant valleys

as the load is decreasing. While in DCM the controller

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21

NCP1680

Figure 17. FCCrM Operating Modes

On Time Modulation Block

The NCP1680 operates with a constant on−time control

algorithm. The on−time of the main PWM switch is

controlled by the compensation voltage and a modulating

ramp as shown in Figure 18.

Figure 18. On Time Modulation

The circuitry for the on time modulator is internal to the

NCP1680; the compensation voltage is generated by the

internal digital compensator and translated into the analog

domain, and the timing components for the modulator ramp

are also internal. In CrM the slope of the modulating ramp

As long as the application remains in CrM operation the

average input current to the PFC is approximately equal to

I

half of the peak inductor current, i.e. I_in

+

^L,PK, and a

2

modulating ramp with a fixed slope will continue to achieve

good power factor. However, when the application

transitions to DCM operation the inductor current remains

at zero for some portion of the switching cycle and the input

current will begin to distort unless that portion of the

switching cycle is compensated out. Figure 19 shows a

sample inductor current in DCM operation and the

associated dead time that occurs prior to the next drive pulse.

is fixed and the maximum on time, T , occurs when

on,max,CrM

the compensation voltage has railed to V

of 4.2 V.

C(MAX)

The different available NCP1680 devices have different on

time capabilities and are tuned to operate with different

inductance values. Equation 1 can be used to approximate

the maximum allowable inductor value for the respective

devices given the estimated system efficiency (ꢄ), minimum

AC line voltage, and the maximum output power

requirements of the application.

ꢄ @ V_ac²@ T_{on, max, CrM}

(eq. 1)

L t

2 @ P_o

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22

NCP1680

Figure 19. DCM Operation and Dead Time Compensation

T_ON) T

In DCM the average input current is now a function of the

factor equal to ^k_DT

+

^OFF. Multiplying the slope of

T_SW

I_L,ꢀPK

T_ON) T

dead time, specifically ^I_in

+

@

^OFF, and the

the modulating ramp by a factor of k

increases the

DT

2

T_SW

on−time inversely proportionally to k compensating out

DT

input current will begin to distort if the on−time generator

continues using a modulating ramp with a fixed slope. The

NCP1680 dead time compensation mitigates input current

distortion, retaining good power factor across all operating

modes, by adjusting the slope of the modulating ramp by a

the effects of the inductor current dead time and allowing the

application to maintain good power factor performance

across CrM and DCM operation.

V

out

PWM latch

Fast OVP

Detection

SoftOVP

Soft OVP

Detection

R

FB1

Soft−Stop

HL

FB

Regulation

Signal

Generation

V

REGUL

Digital Error Amplifier

And Compensator

CONTROL

S/H

staticOVP

I

B(FB)

STBY

R

FB2

Dynamic

Response

Enhancer

DRE

OFF

Bulk Under−

Voltage

BUV

Detection

UVP

Detection

Skip

Exit

SKIPout

Detection

Figure 20. FB and Regulation Architecture

The general structure of the feedback and regulation

architecture is shown in Figure 20. The bulk voltage is

divided down via a resistor divider and input to a sample and

hold circuit which passes the sensed voltage to the input of

the error amplifier where it is compared against a 2.5

reference voltage.

circuit. The “Digital Error Amplifier and Compensator”

block performs the compensation generating the error

voltage, V^CONTROL, and the “Regulation Signal Generation”

block performs additional processing of the error voltage,

including the ripple voltage cancellation, to generate the

V^REGULsignal. Practically, in FFCrM operation the VREGUL

signal is the digital domain version of VC signal from

Figure 18 which dictates the on−time of the application.

The NCP1680 is internally compensated with a digital

error amplifier and a control voltage ripple cancellation

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23

NCP1680

The compensation in NCP1680 is equivalent to a Type−II

analog compensator as shown in Figure 21 with the

following component values: G = 200 ꢀ S, R = 24 kꢂ,

This compensator provides greater than 50° of phase

boost at 2 Hz, over 70° of phase boost between 5 to 10 Hz,

and the mid−band gain measures at 13.4 dB. For most PFC

applications, having a mid−band gain between 10 to 15 dB

will ensure a loop crossover frequency in the range of 5 Hz

to 10 Hz, hence the NCP1680 compensator is designed to

satisfy a 5 Hz to 10 Hz loop bandwidth with > 60° of phase

margin.

OTA

Z

C = 4.62 ꢀ F, C = 97.24 nF. Based on these values the key

Z

P

characteristics of the compensator are the following:

• Mid−band gain = 20*log10(RZ*GOTA) = ~ 13.6 dB

• Compensation zero location =

= 1/(2*ꢅ*R *C ) = ~1.44 Hz

Z

Additionally, the V

voltage is passed through an

CONTROL

• High frequency pole location =

= 1/(2*ꢅ*R^Z*CP) = ~ 68.2 Hz

optional line frequency ripple cancellation circuit which is

designed to eliminate the AC ripple present on the

V

voltage. High amplitude AC ripple on the

CONTROL

control voltage can increase harmonic distortion of the AC

line current, hence the desire to eliminate this ripple

component. However, a side effect of the ripple cancellation

circuit is that it behaves as another filter in the control loop,

degrading the phase boost provided by the compensator.

Figure 22 provides a Bode plot of the transfer function from

FB to V

including the effects of sampling,

REGUL

compensation, and ripple cancellation. The overall

compensation loop is optimized for a crossover point

of ~ 5 Hz where 60° phase margin can be achieved and

bandwidths up to ~ 14 Hz can be designed with an acceptable

45° phase margin.

Figure 21. Equivalent Analog Compensator

Figure 22. Bode Plots with Ripple Cancellation Filter

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24

NCP1680

Output Voltage Protection Features

scale down factor of the feedback resistors

The NCP1680 features multiple protection and

enhancement features for improved performance and

robustness of the application. The soft OVP, UVP and DRE

comparators monitor the sampled FB pin voltage. Based on

R_FB2

ǒ_k

Ǔ_.

+

FB

R_FB1) R_FB2

V

is the internal threshold for the bulk under−voltage

BUV

protection (BUV). Its typical value is 2 V. The BUV

protection thus typically trips when the output voltage drops

to 80% of its nominal level.

the typical value of their parameters and if (V

) is the

out,nom

output voltage nominal value (e.g., 395 V), we can deduce

the following levels:

ǒ

Ǔ

ǒ

Ǔ

V_{out,ꢀsoftSKIP}and V_{out,ꢀsoftSKIP}are the levels between

V_REF

H

L

• Output Regulation Level: V_out,ꢀnom

+

which the output voltage swings when in soft−SKIP mode

(see the “Soft−SKIP Mode” section).

The soft−OVP trips when the feedback voltage exceeds

k_FB

• Output soft OVP Level: V_out,ꢀSOVP+ 105% @ V_out,ꢀnom

• Output Fast OVP Level: V_out,ꢀFOVP+ 108% @ V_out,ꢀnom

• Output UVP Level: V_out,ꢀUVP+ 12% @ V_out,ꢀnom

105% of V

and remains in this mode until V drops

REF

FB

below 103% of V . When the soft−OVP trips, it reduces

• Output DRE Level: V_out,ꢀDRE+ 95.5% @ V_out,ꢀnom

the power delivery down to zero in 4 steps as shown in

Figure 23.

• Step 1: VREGUL drops to 75% of the VCONTROL value for

100 ꢀ s

V

• Output BUV Level: V_out,ꢀBUV

+

^BUV@ V_out,ꢀnom

V_REF

• Output Upper Soft−SKIP Level:

ǒ

Ǔ

• Step 2: VREGUL drops to 50% of the VCONTROL value for

V_{out,ꢀsoftSKIP}+ V_out,ꢀnom

H

100 ꢀ s

• Output Lower Soft−SKIP Level:

• Step 3: VREGUL drops to 25% of the VCONTROL value for

100 ꢀ s

• Step 4: VREGUL drops to 0 until the soft−OVP fault is over,

that is, when the output voltage drops below 103% of its

regulation level

ǒ

Ǔ

V_{out,ꢀsoftSKIP}+ 94% @ V_out,ꢀnom

L

VREF is the regulation reference (2.5 V typically) and RFB1

and RFB2 are the feedback resistors per Figure 20; kFB is the

105% − V

OUT, NOM

V

OUT

V

103% V

OUT, NOM

time

Soft−OVP

V

CONTROL

(V

)

CONTROL

0

The regulation loop decreases V

(quantization steps are not shown)

CONTROL

(V

)

1

CONTROL

time

75% − V

CONTROL

V

REGUL

50% − V

CONTROL

V

= (V

)

CONTROL

0

REGUL

25% − V

CONTROL

100 ꢀs

V

= (V

)

CONTROL

1

REGUL

0% − V

CONTROL

100 ꢀs

time

Figure 23. Soft−OVP Timing Diagram

The fast OVP comparator is analog and directly monitors

the feedback pin voltage for immediate blanking of the drive

pulses. The Fast OVP comparator trips when the feedback

The dynamic response enhancer circuit functions to

firmly contain undershoot of the output by increasing the

gain of the control loop in response to the bulk voltage

falling below a percentage of the desired regulation voltage.

Practically when the FB pin voltage falls below 95.5% of

voltage exceeds 108% of V

and does not allow drive

REF

pulses until the feedback voltage falls below 103% of V

.

REF

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25

NCP1680

V , the DRE speeds up the charge of the compensation

REF

differently in the positive and negative AC line cycles. The

network until the FB pin voltage exceeds 98% of V

.

PWM−controlled switch changes from the low side switch

REF

st

The FB pin also features a small 250 nA sink current for

protection against an open FB pin, in which case V will be

to the high side switch, the inductor current changes from 1

rd

to 3 quadrant operation, and the “valley” of the switch

FB

pulled below the V

tripping the UVP protection. The UVP feature further works

as a protection in the case of a FB pin that is shorted to GND.

(300 mV typically) threshold

node does not always occur when the auxiliary winding

voltage approaches zero. Specifically, in negative half line

cycle, the “valley” is really a peak and the desired turn−on

of the PWM switch occurs when the switch node voltage is

approaching the bulk voltage. This is illustrated in Figure 24

where the switch node voltage is depicted in both positive

and negative half line cycles.

UVP

Auxiliary Winding and Valley Detection Block

The TPFC topology presents a unique challenge to the use

of an auxiliary winding for valley detection. Unlike the

classical bridged CrM boost PFC, the TPFC operates

Figure 24. Switch Node Voltage in Positive (Left) and Negative (Right) Half Line Cycles

To adapt to the changing operation of the TPFC, while

maintaining the use of a single low−cost auxiliary winding,

the NCP1680 implements a novel “valley” sensing scheme

combining edge detection with threshold detection. The

NCP1680 accomplishes this by changing the “Arming” and

“Triggering” thresholds depending on the polarity of the AC

line. During positive half line cycle, the valley detection

arms when the aux voltage goes above 200 mV, and triggers

when the aux voltage falls below 100 mV. During negative

half line cycle the opposite occurs, namely the valley

detection arms when the aux voltage goes below 100 mV

and triggers when the aux voltage comes back above

200 mV. By reusing the same comparators and thresholds,

and only changing the function of the thresholds, the

NCP1680 effectively combines edge and threshold

detection to achieve a robust, low−cost solution that

overcomes the bidirectional operation of the TPFC.

Figure 25. Valley Detection in DCM. Positive Line Cycle on Left, Negative on Right

Figure 25 shows waveforms demonstrating the valley

detection implementation of the NCP1680 in DCM

operation. The waveforms show the switch node voltage

(Ch.4) and the auxiliary winding voltage (Ch.3) as its image

traversing through 5 valleys before the respective PWM

signal sets high. In both positive and negative half line cycle

the turn on occurs on the correct edge of the auxiliary

winding voltage.

Figure 26 is an example of valley detection in CrM

operation. The switch node voltage is again shown on

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26

NCP1680

channel 4 and although there is no image of the auxiliary

coordinated to the “valley” of the switch node enabling very

winding voltage, it can be seen that the turn−on of the

low turn−on voltage for optimized efficiency.

PWML (Ch.2) on the left, and PWMH (Ch.3) on the right are

Figure 26. Valley Detection in CrM. Positive Half Line Cycle on Left, Negative on Right

The recommended auxiliary winding connection is shown

in Figure 27. To optimize the symmetry of the valley

detection between positive and negative half line cycles, a

swings high, reducing the current into the ESD protection of

the valley detect circuit. A Schottky diode, D , is

recommended to protect the AUX pin voltage from going

too far below ground when the auxiliary winding voltage

AUX

resistance, R

, with no series blocking diode is

AUX1

recommended between the auxiliary winding and the AUX

pin. A pulldown resistance at the pin, R , helps divert

current to ground when the auxiliary winding voltage

goes negative. Finally, a capacitor to ground, C

used to tune the valley detection for optimizing valley

switching and efficiency in the fast leg.

, can be

AUX

AUX2

Figure 27. Recommended Auxiliary Winding Circuit

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27

NCP1680

Zero Current Detection Block

Figure 28. Zero Current Detection in Positive and Negative Half Line Cycle

The zero current detection feature utilizes a series sensing

element to detect the inductor discharge current that flows

to the load during the 1−D period of the switching cycle. This

is shown in Figure 28. During the PWM on−time the current

follows a different path through a different switch when in

positive half line cycle as compared to negative half line

cycle, however the inductor discharge current is consistently

observable, regardless of the AC line conduction angle, in

the return path from the bulk capacitor to the half bridge

switching cell. A series element such as a current sense

resistor or current transformer placed in this return path

allows the controller to sense a portion of the inductor

current and take action to control the (1−D) transistor, enable

some form of peak current limiting in the application, and

also enhancing THD performance.

Synchronous PWM Drive Control

The synchronous PWM or (1−D) device in the TPFC

topology enables higher efficiency performance but proper

gating of the device is necessary for optimizing efficiency

and ensuring robustness in the application. A diagram of the

sync control methodology is shown in Figure 29. First, the

NCP1680 employs a dead time, T^DT1, typically 130 ns,

following the falling edge of the PWM duty−controlled

drive to prevent cross conduction. After the dead time has

expired the controller looks for the ZCD voltage to exceed

the V^ZCD(ARM)threshold to enable the sync drive. In lighter

loads, the ZCD voltage may never exceed this V^ZCD(ARM)

threshold and the sync device will never enable. This is done

to prevent switching of the sync device at light loads where

the associated switching losses could negatively impact the

overall efficiency of the application.

Figure 29. Synchronous PWM Drive Control

At increasing loads the ZCD voltage will exceed the

arming threshold and the sync drive will remain enabled

until the ZCD falls below the V

threshold of

ZCD(TRIG)

50 mV. The trigger threshold has been set close to 0 to keep

the sync conduction period as long as possible but without

letting the inductor current reverse polarity. Should the sync

device remain on for too long the inductor current would

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28

NCP1680

reverse polarity and begin cycling energy from the bulk

capacitance. This would lead to increased RMS currents in

the system and diminish overall efficiency.

• V

voltage crossing 220 mV which is 22 V on the

LINE

AC line with a 100:1 divider – This avoids premature

enabling of the sync pulses and enhances efficiency

• PFCOK sets high – To avoid reverse currents during

startup

The V

) threshold also gates the turn−on of the

ZCD(TRIG

subsequent PWM(d) pulse, regardless of whether the sync

pulse was ever enabled. If the ZCD voltage is held above this

threshold, the device blanks PWM pulses indefinitely. This

feature is intended to reduce the stress of hard switching

events at power up of the application when the peak of the

AC line voltage and the bulk voltage are approximately

equal. It is also beneficial in the case of differential line surge

events where the AC mains can peak charge the bulk

capacitor. In the event of a surge, if there is current flowing

to the bulk capacitor this will be detected by the NCP1680

through the ZCD resistor, and the controller will disable

PWM(d) pulses until the surge event subsides.

Overload and Peak Current Limit Protection

Overload and peak current limiting are necessary features

in any application to protect the system from destructive

damage due to either overcurrent or excessive thermal

stress. The NCP1680 features a novel protection algorithm

which utilizes the inductor discharge current detected

through the ZCD sensing element. A circuit representation

of the algorithm is shown in Figure 30. The ZCD voltage at

the beginning of the (1−D) period is representative of the

peak inductor current. The NCP1680 measures the time

duration, ꢆT , that the ZCD voltage exceeds the

OS

Summarizing, the sync (1−D) pulses are gated by the

following criteria:

V

threshold and integrates the time duration into a

OS

ZCDLIM1

voltage, ꢆV . This voltage is then subtracted from a 5 V

• A delay, t , of 125 ns (typical) after the PWM(d)

DT1

rail and the difference becomes the threshold for the ZCD

current limit comparator. Higher peak currents result in

longer time durations and hence lower thresholds for the

ZCD current limit comparator.

turn−off – This prevents cross conduction

• ZCD voltage crosses the V

threshold – This

ensures sync pulses are enabled only at higher loads for

efficiency improvement across all load conditions

ZCD(ARM)

Figure 30. ZCD Current Limit Schematic

The noninverting input of the current limit comparator is

fed a ramp voltage, different than the modulating ramp used

for the PWM on−time control. The ramp in the current limit

circuit has a slope proportional to the instantaneous line

voltage, hence as the AC line voltage increases the current

limit ramp becomes faster allowing the current limit circuit

to produce shorter on times at higher line voltages. The ramp

characteristics and maximum allowable on times is shown

in Table 5. This novel current limit scheme eliminates the

need for Hall effect sensors and current sense transformers,

thereby significantly reducing the system BOM cost.

Table 5. CURRENT LIMIT CHARACTERISTICS

Ramp Slope

T

ON,MAX

[V/ms]

[ms]

V

ac

V

ac, PK

V

LINE, PK

85

120.2

162.6

325.3

374.8

1.20

0.246

0.333

0.909

1.048

20.34

15.04

5.50

115

230

265

1.63

3.25

3.75

4.77

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NCP1680

ZCD Resistor Calculation

THD Enhancer

To calculate the ZCD resistor value one must first

calculate the maximum peak inductor current in the

application using Equation 2. The maximum inductor

current is determined by maximum output power, minimum

AC input voltage, and an estimate of the application

efficiency, ꢄ. Once the maximum peak current is

determined, Equation 3 is used to find an upper limit on the

ZCD resistor based on the ZCD current limit threshold,

Another feature of the NCP1680 that is derived from the

ZCD voltage is the THD enhancer, which produces a small

on−time extension proportional to the time duration that the

ZCD voltage is less than the V

threshold. This is

ZCD(MIN)

shown in Figure 31 where the orange square represents the

time duration that the THD enhancer integrates to produce

an on−time extension. Typically, at lighter loads and near the

AC zero crossings the amplitude of the inductor current

reduces and the ZCD voltage will spend longer durations

below this minimum threshold resulting in larger on−time

extensions. Note that the THD enhancer does not

compensate for the dead time period shown in Figure 31 as

this is handled by the dead time compensation circuit. The

THD enhancer working in conjunction with the dead time

compensation circuit allows the NCP1680 to achieve THD

<10% at medium to heavy loads across the universal input

range.

V ). Typically this calculation is only needed at the

ZCDLIM(xL

minimum AC voltage, usually 90 V , however the

AC

calculation should also be repeated at the minimum high line

voltage in the application because the NCP1680 has an

optional 60% reduction of the ZCD current limit at high line

to provide power limiting at high line.

Ǹ

2 2 @ P_O

ꢄ @ V_ac

I_{L, PK}

+

t

(eq. 2)

(eq. 3)

V_ZCDLIM(xL)

I_{L, PK}

R_ZCD

Figure 31. ZCD THD Enhancer Diagram

Soft Skip Mode

The NCP1680 features a Soft Skip mode which enables

the application to achieve very good no load and light load

performance. The device must be externally commanded to

enter the Skip mode by pulsing of either the PFCOK or SKIP

pins. When the device enters the Skip mode, it sheds much

of its functionality except for FB and V^CCmonitoring, and

the internal consumption of the device is reduced to I^CC4,

typically 540 ꢀ A. While in Skip mode the output voltage

decays to 94% of the regulation voltage allowing for a long

period, sometimes up to 1 minute, of inactivity. When the

output voltage reaches 94% of its nominal value, the device

exists Skip mode for a brief burst period during which drives

are enabled and the output voltage is pushed back up to the

nominal regulation value. Provided that the NCP1680

continues to receive Skip command pulses from an external

source, the device will continue to operate in this

Skip−burst−skip mode indefinitely. A timing diagram of the

Skip operation is shown in Figure 32.

www.onsemi.com

30

NCP1680

Figure 32. Skip Operation Timing Diagram

Skip Command Pulses

pin voltage is filtered by a minimum 56 ꢀ s filter preventing

false skip commands in the event of a noisy environment.

One the device enters the skip mode the Skip output buffer

is turned off to minimize current consumption in the

controller. The NCP1680 also starts a recovery timer,

typically 500 ms, and enables the Skip output buffer for a

400 ꢀ s window every 500 ms to check whether the external

pulldown signal is still commanding the device into skip

mode. If the device detects that the external pulldown has

been disabled within the 400 ꢀ s window then the device will

exit the skip mode and resume normal operation.

The command pulses needed to force the NCP1680 into

skip can be delivered to either the Skip or the PFCOK pin.

A schematic and timing diagram for Skip is shown in

Figure 33. To command the NCP1680 into the skip mode an

external pulldown signal must be applied to the pin. The

signal can be applied directly or through a diode if the

pulldown signal exceeds the 5 V absolute maximum rating

of the pin. The pulldown must overcome the current

sourcing capability of the pin, I

order to pull the pin below the V

, typically 700 ꢀ A, in

SKIP

voltage of 1.5 V. The

SKIP(th)

Figure 33. Skip Schematic and Timing Diagram

www.onsemi.com

31

NCP1680

The Skip pin can also be utilized, along with some

external circuitry, to further optimize the no load

performance of the application. Many external gate driver

circuits such as the NCP51820 have an Enable/Disable input

that can be toggled to bring the respective device into a low

consumption state. The Skip pin, which is a 0 to 5 V signal

can be used to control the external driver by directly

connecting the pin to the Enable pin of the driver. A small

RC resistor at the enable pin is recommended for

decoupling.

For gate driver circuits that do not have an Enable/Disable

pin, such as the NCP51530 or the NCP5183, which can be

Figure 34. V_CCPass−Through Circuit

used to drive the slow leg transistors, a V pass−through

CC

The PFCOK pin is typically utilized for communication

to a downstream converter, acting as an enable or UVLO. In

this case it may be necessary for the PFCOK pin to remain

high during the skip mode so that the downstream converter

does not shutdown. For that reason, the command pulse

logic for the PFCOK pin is optimized for a pulse train, rather

than for a pulldown to ground like the Skip pin. For the

NCP1680 to enter skip mode the PFCOK pin must be pulled

circuit can be used to disable the drivers when the NCP1680

is in the Skip mode. An example pass−through circuit is

shown in Figure 34 where the Skip pin directly drives a

smaller signal NMOS transistor. When the NMOS is

conducting, current is pulled from the base of the PNP

transistor allowing it to conduct so that V

= V . In skip

CC1

CC

mode the Skip pin will pull low shutting off both NMOS and

the PNP pass transistor.

below the V

), typically 0.5 V, for a duration greater

SKIP2(th

than T

, typically 30 ꢀ s. The frequency of the PFCOK

SKIP2

pulse train needs to be faster than the burst frequency of the

PFC. Figure 35 shows a sample schematic and timing

diagram for the interface between the downstream converter

and the PFCOK pin of the NCP1680.

Figure 35. PFCOK Schematic and Timing Diagram

PFCOK Operation

The PFCOK pin is intended to control operation of a

downstream DC−DC converter by acting as an enable or

UVLO signal. The pin output is high when the application

is in nominal operation and low when the application is in

startup or when the device detects a fault condition. The

output of the pin is a current source proportional to the FB

pin voltage with a gain of 10 ꢀ A/V. A resistor to ground

placed at the pin will give the downstream converter an

image of the bulk voltage for use as a UVLO or as a logic

enable.

www.onsemi.com

32

NCP1680

V_BUV

Figure 36. PFCOK Schematic

Fault Pin and Fault Matrix

A logic diagram detailing the PFCOK pin operation is

shown in Figure 36. Worth noting is that at startup of the

application the PFCOK pin remains pulled to ground until

Fault Pin

The NCP1680 includes a dedicated fault input accessible

via the Fault pin. The controller can be latched off by pulling

the pin up above the upper fault threshold, V

the V voltage reaches 98% of V . Once the FB voltage

FB

REF

exceeds 98% of V

the internal PFCOK flag goes high

REF

,

FLT(OVP)

which enables the sync PWM and slow leg SR drive pulses.

Sync PWM and slow leg SR pulses are also gated by other

criteria but prior to achieving regulation, they are

completely disabled. The PFCOK flag also gates skip mode

operation and the bulk undervoltage (BUV) fault so that the

device is unable to enter skip mode or declare a BUV fault

until having first achieved regulation.

typically 3.0 V. The controller is disabled if the Fault pin

voltage, V , is pulled below the lower fault threshold,

Fault

V

, typically 0.4 V. The lower threshold is normally

FLT(OTP)

used for detecting an overtemperature fault. The controller

operates normally while the Fault pin voltage is maintained

within the upper and lower fault thresholds. Figure 37 shows

the architecture of the Fault input.

Figure 37. Fault Pin Schematic

The lower fault threshold is intended to be used to detect

an overtemperature fault using an NTC thermistor. A pull up

will enable switching once the fault pin voltage exceeds the

V

threshold, typically 0.92 V. The OTP fault also

FLT(REC)

current source I , (typically 46 ꢀ A) generates a voltage

includes a 5 ms blanking circuit, t , which

OTP(BLANK)

FLT

drop across the thermistor. The resistance of the NTC

thermistor decreases at higher temperatures resulting in a

lower voltage across the thermistor. The controller detects a

prevents the OTP fault from being asserted when the device

first powers up. The blanking period is needed to allow any

external pin capacitance to be charged up above the OTP

threshold.

fault once the thermistor voltage drops below V

.

FLT(OTP)

The OTP fault is an auto−recoverable fault so the NCP1680

www.onsemi.com

33

NCP1680

A clamp circuit prevents the Fault pin voltage from

reaching the upper latch threshold if the pin is left open. To

reach the upper threshold, the external pull−up current must

be higher than the pull−down capability of the clamp (set by

t

and t

are both typically 30 ꢀ s. A fault is

OVP(DLY)

OTP(DLY)

detected if the fault condition is asserted for a period longer

than the blanking delay. Some external capacitance is also

recommended at the FAULT pin to provide additional noise

immunity.

R

at V

. The upper fault threshold can

FLT(CLAMP)

be used for V over−voltage protection in the application,

particularly for protecting external gate drivers. The

CC

Fault Matrix

The NCP1680 has an extensive suite of fault handling

capabilities designed to enable a robust application design

utilizing the Totem Pole PFC topology. Although much of

the fault handling has been described in some detail

throughout the datasheet, Table 6 is provided as a Fault

Handling Matrix summarizing all of the key protection

features including the conditions needed to set the fault,

reset the fault, and the specific action taken by the controller

for the given fault.

NCP1680 V

pin is rated for 30 V, however external

CC

devices used to drive either the fast of slow leg transistors

often have V pins rated only up to 20 V so a simple Zener

CC

diode connected between V

and the FAULT pin can

CC

protect those external devices. The controller is latched once

exceeds V . Both of the Fault signals include

V

Fault

FLT(OVP)

internal filtering to prevent noise from triggering the fault

detectors. Upper and lower fault detector blanking delays,

Table 6. NCP1680 FAULT HANDLING MATRIX

Fault

Set

Reset

Controller Action

− Begin soft stop sequence

Line SAG

(V

t

< V

SAG(blank)

) +

V

LINE

V

LINE

> V

LINE

BO(STOP

BO(START)

expires

− PWM and SR drives disabled after soft stop

− PFCOK pulled low if StaticOVP or BUV

(OFF Mode)

−Cancels T

BUV

BO Fault

(V

LINE

t

< V

BO(blank)

) +

> V

− Resets Controller

− Polarity signal disabled

− PFCOK pulled low if StaticOVP (OFF Mode)

BO(STOP

expires

Line Frequency 1

Line Frequency 2

t

< t

or > t

t

< t

< t )

LINE(65

− SR drives disabled

LINE

LINE(45)

LINE(65)

LINE(45)

LINE

− Starts t

timer

LINEFREQ(DLY)

T

timer expires

N

= 4 : t <

− PWM Drive disables

− Polarity signal remains active

consecutive polarity toggles − PFCOK pulled low (OFFF Mode)

LINEFREQ(DLY)

DRV_EN

LINE(45)

for 4

t

< t

LINE

LINE(65)

UVP

V

FB

< V

V

FB

> V

+ V

UVP(HYS)

− PWM and SR drives disabled

− Polarity signal remains active

− PFCOK pulled low (OFF Mode)

UVP

Bulk Under − Voltage PFCOK high & (V < V

)

T

BUV

expires

− PWM and SR drives disabled

− Polarity signal remains active

− PFCOK pulled low (OFF Mode)

FB

BUV

(BUV)

− Automatic restart after T

BUV

Soft OVP

Hard OVP

V

> V

V

< V

− Begin soft OVP sequence

− PWM Drive disables after soft OVP sequence

− Polarity & SR remains active

FB

softOVP

FB

OVPrecover

V

FB

> V

< V

V

FB

− PWM Drive disables immediately

− Polarity & SR remains active

hardOVP

OVPrecover

V

CC

UVLO

V

CC

V

> V

− PWM and SR drives disabled

− Polarity signal disabled

− PFCOK pulled low (OFF Mode)

CC(OFF)

CC

CC(ON)

Fault OTP

Fault OVP

TSD

t

expires + V

<

V

> V

− PWM and SR drives disabled

− Polarity signal remains active

− PFCOK pulled low (OFF Mode)

OTP(BLANK)

FLT

)

FLT

FLT(REC)

(V

+ t

FLT(OTP)

OTP(DLY)

V

> V

+ t

OVP(DLY)

Master Reset

− PWM and SR drives disabled

− Polarity signal remains active

− PFCOK pulled low (OFF Mode)

FLT

FLT(OVP)

T > T

T < (T

− T )

SHDN(HYS)

− PWM and SR drives disabled

− Polarity signal remains active

− PFCOK pulled low (OFF Mode)

J

SHDN

J

SHDN

www.onsemi.com

34

NCP1680

Table 7. ORDERING INFORMATION TABLE

†

OPN

T

[ms]

F

[kHz]

V

[V]

V

[mV]

Package

Shipping

ONMAX, CRM

CLAMP

ZCDILIM

ZCD(ARM)

NCP1680AA

NCP1680AB

17.2

130

275

1.4

300

SOIC16

(Pb−Free)

2500 /

Tape & Reel

10.2

0.6

100

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

35

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

DATE 29 DEC 2006

SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16

9

8

−B−

P 8 PL

M

S

B

0.25 (0.010)

1

MILLIMETERS

INCHES

MIN

0.386

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00

G

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

F

R X 45

K

_

G

J

1.27 BSC

0.050 BSC

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

K

M

P

R

C

7

0

_

−T−

SEATING

PLANE

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

J

M

D

16 PL

M

S

A

0.25 (0.010)

T B

STYLE 1:

STYLE 2:

STYLE 3:

STYLE 4:

PIN 1. COLLECTOR

2. BASE

3. EMITTER

4. NO CONNECTION

5. EMITTER

6. BASE

7. COLLECTOR

8. COLLECTOR

9. BASE

10. EMITTER

11. NO CONNECTION

12. EMITTER

13. BASE

PIN 1. CATHODE

2. ANODE

3. NO CONNECTION

4. CATHODE

5. CATHODE

6. NO CONNECTION

7. ANODE

8. CATHODE

9. CATHODE

10. ANODE

11. NO CONNECTION

12. CATHODE

13. CATHODE

14. NO CONNECTION

15. ANODE

PIN 1. COLLECTOR, DYE #1

2. BASE, #1

3. EMITTER, #1

4. COLLECTOR, #1

5. COLLECTOR, #2

6. BASE, #2

PIN 1. COLLECTOR, DYE #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. COLLECTOR, #3

6. COLLECTOR, #3

7. COLLECTOR, #4

8. COLLECTOR, #4

9. BASE, #4

10. EMITTER, #4

11. BASE, #3

12. EMITTER, #3

13. BASE, #2

7. EMITTER, #2

8. COLLECTOR, #2

9. COLLECTOR, #3

10. BASE, #3

11. EMITTER, #3

12. COLLECTOR, #3

13. COLLECTOR, #4

14. BASE, #4

SOLDERING FOOTPRINT

14. COLLECTOR

15. EMITTER

16. COLLECTOR

14. EMITTER, #2

15. BASE, #1

16. EMITTER, #1

15. EMITTER, #4

16. COLLECTOR, #4

8X

6.40

16. CATHODE

16X

1.12

STYLE 5:

STYLE 6:

STYLE 7:

PIN 1. SOURCE N‐CH

PIN 1. DRAIN, DYE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. DRAIN, #3

6. DRAIN, #3

7. DRAIN, #4

8. DRAIN, #4

9. GATE, #4

PIN 1. CATHODE

2. CATHODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

7. CATHODE

8. CATHODE

9. ANODE

2. COMMON DRAIN (OUTPUT)

3. COMMON DRAIN (OUTPUT)

4. GATE P‐CH

5. COMMON DRAIN (OUTPUT)

6. COMMON DRAIN (OUTPUT)

7. COMMON DRAIN (OUTPUT)

8. SOURCE P‐CH

1

16

16X

0.58

9. SOURCE P‐CH

10. SOURCE, #4

11. GATE, #3

12. SOURCE, #3

13. GATE, #2

14. SOURCE, #2

15. GATE, #1

16. SOURCE, #1

10. ANODE

11. ANODE

12. ANODE

13. ANODE

14. ANODE

15. ANODE

16. ANODE

10. COMMON DRAIN (OUTPUT)

11. COMMON DRAIN (OUTPUT)

12. COMMON DRAIN (OUTPUT)

13. GATE N‐CH

14. COMMON DRAIN (OUTPUT)

15. COMMON DRAIN (OUTPUT)

16. SOURCE N‐CH

1.27

PITCH

8

9

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42566B

SOIC−16

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

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


型号：	NCP1680ABD1R2G
厂家：	ONSEMI
描述：	图腾柱临界导通模式（CrM）功率因素校正控制器控制器
文件：	总37页 (文件大小：2834K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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