NCP1910B100DWR2G_技术文档

NCP1910

High Performance Combo

Controller for ATX Power

Supplies

Housed in a SO−24WB package, the NCP1910 combines a

state−of−the−art circuitry aimed to powering next generation of ATX

or flat TVs converters. With a 65 kHz Continuous Conduction Mode

Power Factor Controller and a LLC controller hosting a high−voltage

driver, the NCP1910 is ready to power 85+ types of offline power

supplies. To satisfy stringent efficiency considerations, the PFC circuit

implements an adjustable frequency fold back to reduce switching

losses as the load is going light. To cope with all the signal sequencing

required by the ATX and flat TVs specifications, the controller

includes several dedicated pins enabling handshake between the

secondary and the primary sides. These signals include a power−good

line but also a control pin which turns the controller on and off via an

opto coupler. Safety−wise, a second OVP input offers the necessary

redundancy in case the main feedback network would drift away.

Finally, a fast fault input immediately reacts in presence of an over

current condition by triggering an auto−recovery soft−start sequence.

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SO−24WB Less Pin 21

DW SUFFIX

CASE 752AB

MARKING DIAGRAM

NCP1910XXX

AWLYYWWG

1

XXXXX = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

Features

• Fixed−Frequency 65 kHz CCM Power Factor Controller

• Average Current−Mode Control for Low Line Distortion

• Dynamic Response Enhancer Reduces Bulk Undershoot

• Independent Over Voltage Protection Sensing Pin with Latch−off

Capability

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 36 of this data sheet.

• Adjustable Frequency Fold Back Improves Light Load Efficiency

• Adjustable Line Brown−out Protection with 50 ms

Delay to Help Meeting Hold−up Time Specifications

• Programmable Over current Threshold Leads to an

Optimized Sensing Resistor

• on/off Control Pin for Secondary−Based Remote

Control

• On−Board 5 V Reference Voltage for Precise

Thresholds/Hysteresis Adjustments

• Power Good Output Management Signal

•

1 A peak Current Drive Capability

• LLC Controller Operates from 25 kHz to 500 kHz

• On Board 600 V High−Voltage Drivers

• 1 A/0.5 A Sink/Source Capability

• A Version with Dual Ground Pinout (No Skip),

B Version with Single Ground and Skip Operation for

the LLC Controller

• 20 V Operation

• These are Pb−Free Devices

• Minimum Frequency Precision Down to 3% Over

Temperature Range

• Internally Fixed Dead−Time Value of 300 ns

Typical Applications

• Adjustable Soft−Start Sequence

• Multi Output ATX Power Supplies (A version)

• Flat TVs Power Supplies (B version)

• Fast Fault Input with Soft−Start Trigger for Immediate

Auto−Recovery Protection

1

Publication Order Number:

December, 2012 − Rev. 1

NCP1910/D

NCP1910

1

24

SS

Rt

Vboot

MU

PG out

ON/OFF

Bridge

ML

CC

BO adj.

Vref

V

PG adj.

OVP2

FB

VCTRL

VM

DRV

GND/PGND

Skip/AGND

CS/FF

CS

LBO

Fold

Figure 1. Pin Connections

PIN DESCRIPTION

Pin N5

Pin Name

Function

Pin Description

1

SS

Rt

Soft−start

A capacitor to ground sets the LLC soft−start duration

2

The LLC feedback pin

A resistive arrangement sets the maximum and minimum

switching frequencies with opto coupler−based feedback

capabilities.

3

4

PG out

on/off

The open−collector power good signal

This pin is low when V

is ok, opens when V

passes

bulk

below a level adjusted by PGadj pin.

Remote control

When pulled low, the circuit operates: the PFC starts first and

once FB is in regulation, the LLC is authorized to work. When

left open, the controller is in idle mode.

5

BO adj.

Brown−out adjustment

This pin sets the on and off levels for the PFC powering the

LLC converter

6

7

Vref

The 5 V reference pin

This pin delivers a stable voltage for threshold adjustments

PG adj.

The power good trip level

From the Vref pin, a dc level sets the trip point for the PFC

bulk voltage at which the PG out signal is down.

8

9

OVP2

FB

Redundant OVP

PFC feedback

A fully latched OVP monitoring the PFC bulk independently

from FB pin.

Monitors the boost bulk voltage and regulates it. It also serves

as a quick auto−recovery OVP

10

11

12

13

V

PFC Error amplifier output

PFC current amplifier output

PFC line input voltage sensing

PFC fold back

PFC error amplifier compensation pin

CTRL

V

M

A resistor to ground sets the maximum power level

Line feed forward and PFC brown−out

LBO

Fold

This pin selects the power level at which the frequency starts

to reduce gradually.

14

15

16

17

CS

PFC current sense

Fast−fault input

This pin senses the inductor current and also programs the

maximum sense voltage excursion

CS/FF

When pulled above 1 V, the LLC stops and re−starts via a full

soft−start sequence.

Skip/AGND

GND/PGND

DRV

Skip (B)/AGND (A)

GND (B)/PGND (A)

This pin is either used as the analog GND for the signal circuit

(A) or for skip operation (B).

The controller ground for the driving loop (A) or the lump

ground pin for all circuits (B)

18

19

20

22

23

24

PFC drive signal

The controller supply

Lower−side MOSFET

Half−bridge

The driving signal to the PFC power MOSFET

The power supply pin for the controller, 20 V max.

Drive signal for the lower side half−bridge MOSFET

This pin connects to the LLC half−bridge

V

CC

ML

Bridge

MU

Upper−side MOSFET

Bootstrapped Vcc

Drive signal for the upper side half−bridge MOSFET

V

boot

The bootstrapped V for the floating driver

CC

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2

NCP1910

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3

NCP1910

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4

NCP1910

Grand Reset

PFC_BO

PFC_abnormal

latched

R

S

20 us filter

OVP2

+

Q

“1” OVP2, “0” = ok

Latched adjustable OVP2

PFC_OVP2

latched

107% Vpref

VOVP2

−

Vctrl(max)

“1” OVP, “0” = ok

−

1 sec

delay

+

PFCflag

105% Vpref

PFC_OVP

Auto−recovery internal OVP

+

−

+

VOVP

VUVP

−

Vctrl

“1” = UVP, “0” ok

RFB

+

pull down

+

PFC_UVP

VDD

8% Vpref

Grand

Reset

−

FB

PFC_BO

Vctrl(min) − 0.1 V

Latch

PFC_BO

Grand Reset

If PFC issues an abnormal

situation, then latch off

IVLD

PFC_OPL

PFC_OK

R

S

Dynamic

PFC_OK

Q

PFC_SKIP

Response

Enhancer

(0.6 V clamp

voltage is

activated.)

−

“1” = below 5% reg

“0” ok

+

VLD

95% Vpref

Vctrl

−

Grand Reset

PFC_BO

Closed

The “PFC_OK” toggles high when:

− VLD is low

OTA

+

if “1”

PFC drive signal

− PFC issues a driving pulse

The “PFC_OK” toggles low when:

Vpref

−

“1” = FB > Vpref

− Vctrl stays out of window [Vctrl,min to

+

Vctrl,max] > 1 sec

− at this point, the latch is reset and the

Vfold

“PFC_OK” output goes low.

“1” open

“0” close

Vfold(max)

Ict(fold)

Grand Reset

PFC_BO

VCTRL

LBO

“1” BO NOTOK,

“0” BOK

Vctrl(min)

S

R

VLBOT

Q

S

PFC_BO

+

Q

VLBO

BO delay

−

ILBO

R

PFC_OK

Latch

A

B

VLBO^2

Onoff

UVLO

TSD

Multiplier

VDD

PFC_SKIP

PFC_OL

PFC_OVP

PFC_BO

−

+

VLBO^2

ICS

Vpref

Vdd

Vctrl−Vctrl(min)

2

ICt

CS

ICS VLBO

ICt(min)

ICS

(

))

B

A

4 Vctrl * Vctrl min

A / B

ICS x VLBO^2

ICS x VLBO > 275 uA

“0” / “1”

Vpref / 10%Vpref

“1” = OPL

+

PFC_OPL

PFC_OL

Oscillator section

−

ICS > 200 uA

+

“1” = OCP

PFC_OCP

−

VM

Vcc

DRV

Figure 4. Internal PFC Block Diagram

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5

NCP1910

Vrt

Vboot

Q

S

CLK

Mupper

S

B

R

QN

D

Q

+

-

Clk

A

Rt

R

UVLO

Hi side

Level

shifter

Latch

Vref

Bridge

Vcc

Vref

Pulse

Trigger

Latch

Grand

Reset

Dead time

UVLO

B

Grand

Reset

Vdd

Vcc

management

A

Mlower

delay

BO adj

"1" BONOT OK

+

-

LLC_BO

tBOK

Prop. delay

matching

tBONOTOK

PFC_FB

GND_LLC

PFC_OK

"1" is ok

"0" notok

"1" PGNOT OK

-

"1" enables LLC

"0" LLC is locked

+

Skip: B version only

-

PG adj

Skip/GND_PFC

LLC_BO

+

LLC_PG

20 ms delay

tdel1

Grand

Reset

Vskip

R

LLC_BO

PG out

5 ms delay

tdel2

GND

SS

Grand Reset

Grand

Reset

"1" after reset

"0" when PG out

drops after 5 ms

PFC_OVP2

+

-

S

Q

Latch

Q

S

VCS2

R

Q

R

Q

Grand Reset

PFC_BO

R

CS/FF

+

LLC_PG

-

Grand Reset

VCS1

-

+

SS_RST

Vdd

UVLO

PFC_UVP

on/off

"1" controller is off

"0" controller is on

Grand Reset

Rpull up

on_off

on/off

Onoff

Thermal

Shut Down

TSD

"1" TSD is on

"0" TSD is off

Figure 5. Internal LLC Block Diagram

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6

NCP1910

MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

V

Bridge

Continuous High Voltage bridge pin, pin 22

−1 to 600

−0.3 to 20

V

–V

Floating supply voltage, pin 24−22

V

BOOT Bridge

V

MU

, V

DRV

High side output voltage, pin 23

V − 0.3 to

BRIDGE

V

+ 0.3

BOOT

V

Low side output voltage, pin 18, 20

−0.3 to V + 0.3

V

V/ns

V

ML

CC

dV

/dt

Allowable output slew rate on the Bridge pin, pin 22

Power Supply voltage, pin 19

50

20

Bridge

V

CC

Pin voltage, all pins (except pin 2, 6, 18 − 24, GND)

−0.3 to 10

V

R

Thermal Resistance Junction−to−Air

°C/W

θ

JA

2

50 mm , 1 oz

80

65

2

650 mm , 1 oz

Storage Temperature Range

−60 to + 150

°C

kV

V

ESD Capability, Human Body Model (All pins except V and HV)

2

200

CC

ESD Capability, Machine Model

Power Supply voltage, pin 19

Pin voltage, all pins (except pin 2, 6, 18 ~ 24, GND)

Rt pin voltage

V

CC

20

V

−0.3 to 10

−0.3 to 5

−0.3 to 7

0.5

V

Rt

V

ref_out

V

ref

pin voltage

V

I

Pin current on pin 10, 12, and 13

Pin current on pin 3

mA

MAX

I

5

PGout

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model 200 V per JEDEC Standard JESD22−A115−A

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,

J

V

CC

= 12 V unless otherwise noted)

Symbol

Rating

Min

Typ

Max

Unit

COMMON TO BOTH CONTROLLERS

SUPPLY SECTION

V

Turn−on threshold level, V going up

19

9.4

8

10.4

9

11.4

10

V

CC(on)

CC

V

Minimum operating voltage after turn−on

CC(min)

CC(Hys)

Boot(on)

V

Hysteresis between V

and V

19

1.2

7.8

7

−

V

CC(on)

CC(min)

Startup voltage on the floating section

Cutoff voltage on the floating section

24,22

19

8.8

8

9.8

9

V

Boot(min)

I

Startup current, V < V

CC(on)

−

100

6.4

mA

startup

CC

I

PFC consumption alone, DRV pin unloaded, on/off pin grounded,

LLC off (PFC is 65 kHz)

19

−

5.1

CC1

I

PFC consumption, DRV pin loaded by 1 nF, on/off pin grounded, LLC

off (PFC is 65 kHz)

19

−

5.9

7.4

mA

CC2

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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NCP1910

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,

J

V

CC

= 12 V unless otherwise noted)

Symbol

Rating

Min

Typ

Max

Unit

COMMON TO BOTH CONTROLLERS

SUPPLY SECTION

I

IC consumption, both PFC and LLC loaded in no load conditions

19

−

5.9

6.9

64

−

7.2

8.6

mA

CC4

CC5

CC6

CC7

(PFC is 65 kHz and R = 70 kW (LLC is 25 kHz))

t

IC consumption, both PFC and LLC loaded 1 nF load conditions

(PFC is 65 kHz and R = 70 kW (LLC is 25 kHz))

t

IC consumption in fault mode from V

boot(min)

(drivers disabled, V

>

300

950

boot

V

)

IC consumption in OFF mode from V (on/off pin is open)

mA

CC

REFERENCE VOLTAGE

V

Reference voltage for external threshold setting @ I = 5 mA

6

4.75

4.9

5

5.25

5.1

V

ref−out

out

V

Reference voltage for external threshold setting @ I = 5 mA – T =

out

J

25°C

V

Vcc rejection capability, I = 5 mA − DV = 1 V – T = 25°C

6

−

0.01

1.6

5

7

mV

refLineReg

out

CC

J

V

Reference variation with load changes, 1 mA < I < 5 mA – T =

ref J

25°C

refLoadReg

I

Maximum output current capability

6

5

−

mA

ref−out

NOTE: Maximum capacitance directly connected to V

DELAY

pin must be under 100 nF.

REF

t

Turn−on LLC delay after PFC OK signal is asserted

Turn−off LLC after power good pin goes low (Note 3)

−

10

2

20

5

30

8

ms

DEL1

DEL2

PROTECTIONS

R

on/off pin pull−up resistor

4

3

7

−

5

−

1

kW

ms

V

Pull−up

t

Propagation delay from on to off (ML & MU are off) (Note 4)

Low level input voltage on on/off pin (NCP1910 is enabled)

High level input voltage on on/off pin (NCP1910 is disabled)

Open voltage on on/off pin

on/off

V

on

−

1

V

off

3

−

V

op

−

7

−

V

I

Maximum Power good pin sink current capability

5

−

mA

mV

nA

mV

°C

PG

V

PG

Power good saturation voltage for I = 5 mA

−

350

−

PG

I

Input bias current, PGadj pin

PG comparator hysteresis

−

10

100

−

PGadj

V

−

PGadjH

TSD

Temperature shutdown (Note 4)

Temperature Hysteresis Shutdown

140

−

TSDhyste

30

−

POWER FACTOR CORRECTION

GATE DRIVE SECTION

R

Source Resistance @ I

= −100 mA

DRV

18

−

9

20

18

−

W

POH

R

Sink Resistance @ I

= 100 mA

DRV

6.6

60

40

POL

t

Gate Drive Voltage Rise Time from 1.5 V to 10.5 V (C = 1 nF)

ns

Pr

L

t

Pf

Gate Drive Voltage Fall Time from 10.5 V to 1.5 V (C = 1 nF)

−

L

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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NCP1910

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,

J

V

CC

= 12 V unless otherwise noted)

Symbol

Rating

Min

Typ

Max

Unit

POWER FACTOR CORRECTION

REGULATION BLOCK

V

PFC Voltage reference

−

10

−

2.425

−

2.5

$30

200

−

2.575

−

V

PREF

I

EA

Error Amplifier Current Capability

Error Amplifier Gain

mA

mS

mA

V

G

I

100

0

300

0.3

EA

Bias Current @ V = V

9

B

FB

PREF

V

CTRL

CTRL(max)

V

Maximum Control Voltage @ V = 2 V

10

−

2.7

3.6

0.6

3

−

3.3

FB

Minimum Control Voltage @ V = 3 V

CTRL(min)

DV

= V

−V

CTRL

CTRL(max) CTRL(min)

V

H

L / V

Ratio (V

Low Detect Threshold / V ) (Note 4)

PREF

−

94

−

95

0.5

230

96

−

%

OUT

PREF

OUT

L / V

Low Detect Hysteresis / V

)

OUT

PREF

EA

PREF

I

+ I

Source Current when (V

Low Detect) is activated

10

190

260

mA

VLD

OUT

CURRENT SENSE

V

Current Sense Pin Offset Voltage, (I = 100 mA)

14

−

10

−

mV

S

CS

I

Over−Current Protection Threshold

185

200

215

mA

CS(OCP)

POWER LIMIT

x V

I

Over Power Limitation Threshold

−

215

275

335

mVA

mA

CS

LBO

I

Over−Power Current Threshold (V

= 1.8 V, V = 0 V)

119

56

153

75

187

99

CS(OPL1)

CS(OPL2)

LBO

M

= 3.6 V, V = 0 V)

M

PULSE WIDTH MODULATION

F

PFC Switching Frequency

18

58

34

65

39

72

43

kHz

PSW

PSW(fold)

F

Minimum Switching Frequency (V

0.1 V)

= 1.5 V, V

= V

+

fold

CTRL

CTRL(min)

DC

Maximum PFC Duty Cycle

Minimum PFC Duty Cycle

18

10

−

97

−

0

%

V

Pmax

DC

Pmin

CTRL(fold)

V

CTRL

pin voltage to start frequency foldback (V

= 1.5 V)

1.8

1.4

2

2.2

1.8

fold

V

pin voltage as frequency foldback reducing to the minimum

= F , V = 1.5 V)

1.6

V

CTRL(foldend)

CTRL

PSW

(F

PSW(fold) fold

V

Maximum internal fold voltage (Note 4)

−

1.97

2

2.03

V

fold(max)

LINE BROWN−OUT DETECTION

V

Line Brown−Out Voltage Threshold

12

−

0.96

6

1.00

7

1.04

8

V

LBOT

I

Line Brown−Out Hysteresis Current Source

Line Brown−Out Blanking Time

mA

ms

mV

LBOH

t

25

−

50

75

−

LBO(blank)

t

Line Brown−Out Monitoring Window (Note 4)

−

50

LBO(window)

V

LBO Pin clamped voltage if V < V

during t (I =

LBO(BLANK) LBO

12

980

LBO(clamp)

BO

LBOT

100 mA)

V

Hysteresis (V

– V ) (Note 4)

LBO(clamp)

12

10

100

0.4

35

−

60

−

mV

mA

V

LBOH

LBOT

I

Current Capability of LBO

LBO(clamp)

V

LBO pin voltage when clamped by the PNP Transistor (I

100 mA)

=

0.7

0.9

LBO(PNP)

LBO

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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9

NCP1910

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,

J

V

CC

= 12 V unless otherwise noted)

Symbol

Rating

Min

Typ

Max

Unit

POWER FACTOR CORRECTION

LINE BROWN−OUT DETECTION

V

Pull Down V

Threshold

12

−

1.8

4.5

2.5

55

2

5

2.2

6.1

7.5

90

V

LBO(PD)

LBO

t

Time Limitation

ms

LBO(Pdlimit)

t

Time Delay to Confirm that V

is the maximum to Pull down V

LBO

−

5

PFCflag

LBO(Pdblank)

CTRL

t

Pull Down V

Blanking Time

−

77

LBO

CURRENT MODULATION

I

Multiplier Output Current (V

CS

=V

– 0.2 V , V

= 3.6 V,

= 1.2 V,

11

46

15

58

19

72

mA

M1

M2

CTRL

CTRL(max)

LBO

I

= 50 mA)

I

Multiplier Output Current (V

= 150 mA)

24.5

CTRL

CTRL(max)

LBO

I

CS

OVER−VOLTAGE PROTECTION

Internal Auto Recovery Over Voltage Threshold

V

OVP1

9

2.536

2.615

44

2.694

60

V

Hysteresis of Internal Auto Recovery Over Voltage Threshold

(Note 4)

−

mV

OVP1H

t

Propagation Delay (V = 108% V ) to Drive Low

PREF

9, 18

−

2.595

−

500

2.675

2

−

2.755

−

ns

V

OVP1

FB

V

External Latched Over Voltage Threshold

The difference between V and V

8

OVP2

K

over V

((V

−

%

OVPH

OVP2

OVP1

PREF

OVP2

V

)/V

)

OVP1

PREF

t

External Latched OVP Integrating Filter Time Constant

Input bias current, OVP2

−

20

10

−

ms

DELOVP2

I

8

nA

b,OVP2

UNDER−VOLTAGE PROTECTION

V

/V

UVP Activate Threshold Ratio

UVP Deactivate Threshold Ratio

UVP Lockout Hysteresis

9

4

6

−

8

12

4

12

18

−

%

ms

UVP(on) PREF

/V

9

UVP(off) PREF

V

UVP(H)

t

Propagation Delay (V < 8 % V ) to Drive Low

PREF

9 − 18

7

−

UVP

FB

PFC ABNORMAL

PFC Abnormal Delay Time (V

t

= V

or V

=

−

1

1.5

2.1

sec

PFCabnormal

CTRL

CTRL(max)

CTRL

V

– 0.1 V)

CTRL(min)

LLC CONTROL SECTION

OSCILLATOR

F

Minimum switching frequency, Rt = 70 kW on R pin

2

24.25

208

424

48

25

245

500

50

25.75

282

575

52

kHz

%

Lsw,min

t

F

Lsw

switching frequency, DT = 300 ns, Rt = 7 kW on R pin

2

L

t

F

Maximum switching frequency, DT = 300 ns, Rt = 3.5 kW on R pin

2

23, 20

2

Lsw,max

L

t

DC

Operating Duty−Cycle symmetry

L

V

Reference voltage for oscillator charging current generation

Discharge switch resistance

3.33

−

3.5

70

3.67

−

V

refRt

R

1

W

SS

Soft−start reset voltage

1

−

200

400

50

−

mV

RST

Skip

V

Skip cycle threshold, B version only

16

350

−

450

−

V

Hysteresis level on skip cycle comparator, B version only

skip,hyste

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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10

NCP1910

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,

J

V

CC

= 12 V unless otherwise noted)

Symbol

Rating

Min

Typ

Max

Unit

LLC CONTROL SECTION

DRIVE OUTPUT

T

Output voltage rise−time @ C = 1 nF, 10−90% of output signal

23, 20

−

40

20

12

5

−

ns

W

Lr

Lf

L

Output voltage fall−time @ C = 1 nF, 10−90% of output signal

L

R

Source resistance

23, 20

−

26

11

386

5

LOH

R

Sink resistance

23, 20

−

W

LOL

DT

Dead time, measured between 50% of the rise and fall edge

Leakage current on high voltage pins to GND (600 Vdc)

23, 20

268

−

327

−

ns

mA

L

I

22, 23, 24

HV,leak

PROTECTIONS

I

Input bias current, BOadj pin

5

−

15

100

150

20

1

−

nA

mV

ms

V

BOadj

V

BO comparator hysteresis

BOadjH

t

BO comparator Integrating Filter Time Constant from High to Low

BO comparator Integrating Filter Time Constant from Low to High

Current−sense pin level that resets the soft−start capacitor

Current−sense pin level that permanently latches off the circuit

Propagation delay from VCS1/2 activation to respective action

5

−

BOK

BONOTOK

t

5

−

V

t

15

0.95

1.42

−

1.05

1.58

500

CS1

CS2

CS

1.5

−

V

ns

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,

when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge

slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage

is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

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11

NCP1910

TYPICAL CHARACTERISTICS

11

10.5

10

9.5

9

V

CC(on)

V

boot(on)

9.5

9

8.5

8

V

boot(min)

V

CC(min)

8.5

7.5

8

−50

7

−50

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 6. V_CC(on)and V_CC(min)vs. Temperature

Figure 7. V_boot(on)and V_boot(min)vs.

Temperature

100

75

50

25

0

950

850

750

650

550

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 8. I_startupvs. Temperature

Figure 9. I_CC7vs. Temperature

5.25

5.15

5.05

4.95

4.85

4.75

4.99

4.989

4.988

4.987

−50

−25

0

25

50

75

100

125

0

1

2

3

4

5

6

TEMPERATURE (°C)

Figure 10. V_ref-outvs. Temperature

Figure 11. V_ref-out@ 255C vs. I_ref-out

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NCP1910

TYPICAL CHARACTERISTICS

10

8

3

2.5

2

V

off

R

POL

R

POH

6

V

on

4

1.5

1

2

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 12. V_onand V_offvs. Temperature

Figure 13. R_POHand R_POLvs. Temperature

2.8

2.7

2.6

2.5

2.4

−20

−25

−30

−35

−40

V

OVP2

OVP1

V

PREF

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 14. V_PREF, V_OVP1, and V_OVP2vs.

Temperature

Figure 15. I_EA(source)vs. Temperature

40

35

30

25

20

300

250

200

150

100

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 16. I_EA(sink)vs. Temperature

Figure 17. G_EAvs. Temperature

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NCP1910

TYPICAL CHARACTERISTICS

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3

2.9

2.8

2.7

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 18. V_CTRL(max)vs. Temperature

Figure 19. DV_CTRLvs. Temperature

215

260

250

240

230

220

210

200

190

210

205

200

195

190

185

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 21. I_CS(OCP)vs. Temperature

Figure 20. I_VLD+I_EAvs. Temperature

190

180

170

160

150

140

130

120

95

85

75

65

55

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 22. I_CS(OPL1)vs. Temperature

Figure 23. I_CS(OPL2)vs. Temperature

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14

NCP1910

TYPICAL CHARACTERISTICS

72

70

68

66

64

62

60

58

44

42

40

38

36

34

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 24. F_PSWvs. Temperature

Figure 25. F_PSW(fold)vs. Temperature

1.04

1.02

1

8

7.5

7

0.98

6.5

0.96

6

−50

−25

0

25

50

75

100

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 26. V_LBOTvs. Temperature

Figure 27. I_LBOHvs. Temperature

18

16

14

12

10

8

26

25.5

25

V

/ V

PREF

UVP(off)

V

/ V

PREF

UVP(on)

24.5

24

6

4

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 28. V_UVP(on)/V_PREFand V_UVP(off)/V_PREF

vs. Temperature

Figure 29. F_Lsw,minvs. Temperature

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NCP1910

TYPICAL CHARACTERISTICS

280

270

260

250

240

230

220

210

525

500

475

450

425

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 30. F_Lswvs. Temperature

Figure 31. F_Lsw,maxvs. Temperature

3.7

3.6

3.5

3.4

3.3

300

250

200

150

100

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 33. SS_RSTvs. Temperature

Figure 32. V_refRtvs. Temperature

24

22

20

18

16

14

12

10

8

450

425

400

375

350

R

LOH,ML

R

LOL,ML

6

4

2

−50

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 34. V_skipvs. Temperature

Figure 35. R_LOH,MLand R_LOL,MLvs.

Temperature

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NCP1910

TYPICAL CHARACTERISTICS

340

330

320

310

300

24

22

20

18

16

14

12

10

8

R

LOH,MU

R

LOL,MU

6

4

2

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 36. R_LOH,MUand R_LOL,MUvs.

Temperature

Figure 37. DT_Lvs. Temperature

1.05

1.025

1

1.6

1.55

1.5

0.975

0.95

1.45

1.4

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 38. V_CS1vs. Temperature

Figure 39. V_CS2vs. Temperature

140

120

100

80

60

40

20

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 40. t_CSvs. Temperature

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17

NCP1910

APPLICATION INFORMATION

The NCP1910 represents a new generation of control

abrupt load or input voltage variations (e.g. at start up).

If the bulk voltage is too far from the regulation level:

♦ Over−Voltage Protection: NCP1910 turns off the

circuit, associating two individual cores performing the

functions of Continuous Conduction Mode (CCM) Power

Factor Correction (PFC) and LLC resonant control. These

cores interact together and implement handshake functions

in normal operating conditions but also when a fault appears.

Based on the ON Semiconductor proprietary high−voltage

technology, the LLC section can drive the high−side

MOSFET of the LLC half−bridge without the need of a

gate−drive transformer.

power switch as soon as V

exceeds the OVP

bulk

threshold (105% of the regulation level). This is an

auto−recovery function.

♦ Dynamic Response Enhancer: NCP1910

drastically speeds up the regulation loop by its

internal 200 mA current source, activated when the

bulk voltage drops below 95% of its regulation level.

• Line Brown−Out Detection: the circuit detects low ac

line conditions and disables the PFC stage in this case.

This protection mainly protects the power switch from

the excessive stress that could damage it in such

conditions.

• Over−Power Limitation: the NCP1910 computes the

maximum permissible current in dependence of the

average input voltage measured by the brown−out

block. It is the second OCP with a threshold that is line

dependent. When the circuit detects an excessive power

transfer, it resets the driver output immediately.

• Redundant Over−Voltage Protection: As a redundant

safety feature, the NCP1910 offers a second latched

OVP whose input is available on OVP2 pin. If the

voltage on this pin is above the maximum allowable

voltage, the PFC and the LCC are latched off.

• PFC Abnormal Protection: When PFC faces an

abnormal situation so that the bulk voltage is under

regulation longer than the allowable timing, the PFC

and LLC are latched off.

Power Factor Correction

• Compactness and Flexibility: the NCP1910 requires a

minimum of external components to perform a CCM

PFC operation. In particular, the circuit scheme

simplifies the PFC stage design. In addition, the circuit

offers some functions like the line brown−out detection

or true power limiting capability that enable the

optimization of the PFC design.

• Low Consumption and Shutdown Capability: the

NCP1910 is optimized to consume a small current in all

operation modes. The consumed current is particularly

reduced during the start−up phase and in shutdown

mode so that the power losses are minimized when the

circuit is disabled. This feature helps meet stringent

stand−by low power specifications. Grounding the

Feed−back pin can force the circuit to enter standby but

the on/off pin can also serve this purpose.

• Maximum Current Limit: the circuit permanently

senses the inductor current and immediately turns off

the power switch if it is higher than the set current

limit. The NCP1910 also prevents any turn on of the

power switch as long as the inductor current is not

below its maximum permissible level. This feature

protects the MOSFET from possible excessive stress

that could result from the switching of a current higher

than the one the power switch is dimensioned for. In

particular, this scheme effectively protects the PFC

stage during the start−up phase when large in−rush

currents charge the bulk capacitor.

• Frequency Foldback: in light output loading

conditions, the user has the ability to program a point

on the V

pin where the oscillator frequency is

CTRL

gradually reduced. This helps to maintain an adequate

efficiency on the PFC power stage alone.

• Soft−Start: to offer a clean start−up sequence and limit

both the stress on the power MOSFET and the bulk

voltage overshoot, a 30 mA current source charges the

compensation network installed on V

pin and

CTRL

makes V

raise gradually.

• Under−Voltage Protection for Open Loop

Protection: the circuit detects when the feed−back

voltage goes below than about 8% of the regulation

level. In this case, the circuit turns off and its

CTRL

• Output Stage Totem Pole: the NCP1910 incorporates

a 1.0 A gate driver to efficiently drive TO220 or

TO247 power MOSFETs.

consumption drops to a very low value. This feature

protects the PFC stage from starting operation in case

of low ac line conditions or in case of a failure in the

feed−back network (i.e. bad connection). In case the

UVP circuitry is activated, the Power Good signal is

disabled and the LLC circuit stops immediately.

LLC Controller

• Wide frequency operation: the part can operate to a

frequency up to 500 kHz by connecting a resistive

network from R pin to ground. One resistor sets the

maximum switching frequency whereas a second

resistor set the minimum frequency.

t

• Fast Transient Response: given the low bandwidth of

the regulation block, the output voltage of PFC stages

may exhibit excessive over or under−shoots because of

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18

NCP1910

is asserted. This delay is always reset when the combo

is started from a Vcc ULVO, line brown−out condition

or via the on/off pin.

• On board dead time: to eliminate the shoot−through

on the half−bridge leg, a dead time is included in the

controller (see DT parameter).

L

• Power good signal: the power good signal (PG) is

intended to instruct the downstream circuitry installed

on the isolated secondary side that the combo is

working. Once the PFC has started, an internal

• Soft−start: a dedicated pin discharges a capacitor to

ground upon start−up to offer a smooth output voltage

ramp up. The start−up frequency is the maximum set by

the resistor connected between R pin and SS pin. The

t

“PFC_OK” signal is asserted. 20 ms later, the PG pin is

brought low. This signal can now disappear in two

cases: the bulk voltage decreases to an abnormal level,

capacitor connected from R pin to ground fixes the soft

t

start duration. In fault mode, when the voltage on

CS/FF pin exceeds a typical value of 1 V, the soft−start

pin is immediately discharged and a re−start at high

frequency occurs.

programmed by a reference voltage imposed on PG

adj

pin. This level is usually above the LLC turn−off

voltage, programmed by BO pin. Therefore, in a

adj

• Skip cycle operation: to avoid any frequency runaway

in light conditions but also to improve the standby

power consumption, the NCP1910B welcomes a skip

input (Skip pin) which permanently observes the

opto−coupler collector. If this pin senses a low voltage,

it cuts the LLC output pulses until the collector goes up

again. The NCP1910A does not offer the skip

capability and routes the analog ground on pin 16

instead.

normal turn−off sequence, PG first drops and signals

the secondary side that it must be prepared for

shutdown. The second event that can drop the PG

signal is when the PFC experiences a fault: broken

feedback path, severe overload. In this case, the PG

signal is immediately asserted high and a 5 ms timer

starts. Once this timer is elapsed, the LLC converter can

be safely halted.

• Latched event: in the event of a severe operating

condition, the PFC can be latched (OVP2 pin) and/or

the LLC controller also (CS/FF pin). In either case, the

whole combo controller is locked and can only be reset

• High−voltage drivers: capitalizing on

ON Semiconductor technology, the LLC controller

includes a high−voltage section allowing a direct

connection to the high−voltage rail. The MOSFET leg

can therefore be directly driven without using a

gate−drive transformer.

via a V UVLO, line brown−out or a level transition

CC

on pin on/off.

• Thermal Shutdown: an internal thermal circuitry

disables the circuit gate drive and then keeps the power

switch off when the junction temperature exceeds

140°C typically. The circuit resumes operation once the

temperature drops below about 110°C (30°C

hysteresis).

• Fault protection: as explained in the above lines, the

CS/FF pin combines a two−level protection circuit. If

the level crosses the first level (1 V), the LLC converter

immediately increases its switching frequency to the

maximum set by the external resistive divider

connected on R pin. This is an auto−recovery

t

protection mode. In case the fault is more severe, the

signal on the CS/FF pin crosses the second threshold

(1.5 V) and latches off the whole combo controller.

Principle of NCP1910 Scheme

PFC Section

A CCM PFC boost converter is shown in Figure 41. The

input voltage is a rectified 50 Hz or 60 Hz sinusoidal signal.

The MOSFET is switching at a high frequency (typically

65 kHz in NCP1910) so that the inductor current I basically

consists of high and low−frequency components.

Reset occurs via an UVLO detection on V , a reset on

CC

the on/off pin or a brown−out detection on the PFC

stage. This latter confirms that the user has unplugged

and re−plugged the power supply.

L

Combo Management

Filter capacitor C is an essential and very small value

in

• Start−up delay: the PFC start−up sequence often

generates an output overshoot followed by damped

oscillations. To make sure the PFC output voltage is

fully stabilized before starting the LLC converter, a

20 ms delay is inserted after the internal PFC_ok signal

capacitor in order to eliminate the high−frequency

component of the inductor I . This filter capacitor cannot be

L

too bulky because it can pollute the power factor by

distorting the rectified sinusoidal input voltage.

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19

NCP1910

I

Bulk voltage (V

)

bulk

L

in

L

V

in

C

bulk

C

R

in

SENSE

Figure 41. CCM PFC Boost Converter

PFC Methodology

♦ V is the rectified input voltage,

in

The NCP1910 uses a proprietary PFC methodology

particularly designed for CCM operation. The PFC

methodology is described in this section.

♦ T is the switching period,

♦ t is the MOSFET on time, and

1

♦ t is the MOSFET off time.

2

The input filter capacitor C and the front−ended EMI

in

filter absorbs the high−frequency component of inductor

current I . It makes the input current I a low−frequency

L

in

signal only of the inductor current.

I_in+ I_L−50

(eq. 2)

Where:

♦ I is the input AC current.

in

♦ I is the inductor current.

L

Figure 42. Inductor Current in CCM

♦ I

supposes a 50 Hz operation. The suffix 50

L−50

means it is with a 50 Hz bandwidth of the original

I .

As shown in Figure 42, the inductor current I in a

L

switching period T includes a charging phase for duration t

1

From Equations 1 and 2, the input impedance Z is

in

and a discharging phase for duration t . The voltage

2

formulated.

conversion ratio is obtained in Equation 1.

V_in

I_in

V_bulk

T * t₁

V_bulk

V_in

t₁) t₂

T

(eq. 3)

Z_in

+

T

I_L*50

t₂

T * t₁

(eq. 1)

where: Z is input impedance.

in

T * t₁

Power factor is corrected when the input impedance Z in

V_in

V_bulk

in

T

Equation 3 is constant or varies slowly in the 50 or 60 Hz

bandwidth.

Where:

♦ V

is the output voltage of PFC stage,

bulk

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20

NCP1910

V

PREF

V

PREF

Figure 43. PFC Duty Modulation and Timing Diagram

The PFC modulation and timing diagram is shown in

Figure 43. The MOSFET on time t is generated by the

V_MV_bulk

(eq. 7)

Z_in

+

1

V_PREFI_L−50

intersection of reference voltage V

and ramp voltage

PREF

Because V

and V

are roughly constant versus

PREF

bulk

V

ramp

. A relationship in Equation 4 is obtained.

time, the multiplier voltage V is designed to be

M

I_cht₁

proportional to the I

in order to have a constant Z for

PFC purpose. It is illustrated in Figure 44.

L−50

in

(eq. 4)

V_ramp+ V_M

)

+ V_PREF

C_ramp

Where:

♦ V

is the internal ramp voltage, the positive input

ramp

of the PFC modulation comparator,

♦ V is the multiplier voltage appearing on V pin,

M

♦ I is the internal charging current,

ch

♦ C

♦ V

is the internal ramp capacitor, and

ramp

is the internal reference voltage, the negative

PREF

input of the PFC modulation comparator.

I , C , and V also act as the ramp signal of

ch

ramp

PREF

switching frequency. Hence the charging current I is

ch

specially designed as in Equation 5. The multiplier voltage

V

M

is therefore expressed in terms of t in Equation 6.

1

Figure 44. Multiplier Voltage Timing Diagram

C

_rampV_PREF

T

C_ramp

(eq. 5)

I_ch

+

It can be seen in the timing diagram in Figure 43 that V

M

originally consists of a switching frequency ripple coming

V

t₁

C_ramp

T * t₁

^PREF+ V_PREF

from the inductor current I . The duty ratio can be

inaccurately generated due to this ripple. This modulation is

L

V_M+ V_PREF

*

T

(eq. 6)

the so−called “peak current mode”. Hence, an external

From Equation 3 and Equation 6, the input impedance Z

is re−formulated in Equation 7.

in

capacitor C connected to the multiplier voltage V pin is

M

essential to bypass the high−frequency component of V .

M

The modulation becomes the so−called “average current

mode” with a better accuracy for PFC.

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21

NCP1910

2

_{M CS}ǒ_V_LBOǓ

R I

V

M

I

M

V

+

M

11

₄ǒ_V

_ǓǓ

* V

ǒ

CTRL

CTRL min

C

M

R

M

PFC Duty

Modulation

Figure 45. The Multiplier Voltage Pin Configuration

The multiplier voltage V is generated according to

♦ V

is the control voltage signal, the output

M

CTRL

Equation 8.

voltage of Operational Trans−conductance Amplifier

(OTA), as described in Equation 17.

2

ǒ

Ǔ

R_MI_CSV_LBO

♦ V

is not only the minimum operating

CTRL(min)

V_M

+

(eq. 8)

voltage of V

but also the offset voltage for the

₄ǒ_V

Ǔ

CTRL

_CTRL* V_CTRL(min)

PFC current modulation.

Where:

♦ R is the external multiplier resistor connected to

R

directly limits the maximum input power capability.

M

2

Also, due to the V feed−forward feature, where the V

is squared, the transfer function and the power delivery is

independent from the ac line level. The relationship between

M

in

LBO

V

M

pin, which is constant.

♦ V

is the input voltage signal appearing on the

LBO

LBO pin, which is proportional to the rms input

voltage,

V

CTRL

and power delivery will be depicted later on.

♦ I is the sense current proportional to the inductor

CS

current I as described in Equation 13.

L

Line Brown−Out Protection

V

in

Ac line

EMI

LBO comp.

R

LBOU

C

in

V

Filter

LBOcomp

V

LBOT

PFC_BO

LBO

C

LBO

R

SENSE

R

LBOL

S

t

Q

t

LBO(window)

LBO(blank)

L

BO

R

Vdd

reset

V

LBO(clamp)

reset

I

LBOH

Figure 46. The Line Brown−Out Configuration

As shown in Figure 46, the Line Brown−Out pin

(represented LBO pin) as receives a portion of the input

LBO pin voltage when a brown−out condition is detected.

This is for hysteresis purpose as required by this function.

In nominal operation, the voltage applied to LBO pin must

voltage (V ). As V is a rectified sinusoid, a capacitor must

in

integrate the ac line ripple so that a voltage proportional to

be above the internal reference voltage, V

(1 V

LBOT

the average value of V is applied to the brown−out pin.

The main function of the LBO block is to detect too low

typically). In this case, the output of the LBO comparator

V is low.

LBOcomp

in

input voltage conditions. A 7 mA current source lowers the

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22

NCP1910

Conversely, if V

and a 980 mV voltage source, V

goes below 1 V, V

turns high

, is connected to

R_LBOL

LBO

LBOcomp

Ǹ

V_LBO+ 2 V_ac,rms

* I_LBOH

LBO(clamp)

R_LBOU) R_LBOL

R_LBOU@ R_LBOL

the LBO pin to maintain the pin level near 1 V. Then a 50 ms

blanking delay, t , is activated during which no

LBO(blank)

@

R_LBOU) R_LBOL

fault is detected. The main goal of the 50 ms lag is to help

meet the hold−up requirements. In case of a short mains

interruption, no fault is detected and hence, both PFC and

LLC keep operating. In addition, LBO pin being kept at

980 mV, there is almost no extra delay between the line

recovery and the occurrence of a proper voltage applied to

LBO pin, that otherwise would exist because of the large

capacitor typically placed between LBO pin and ground to

filter the input voltage ripple. As a result, the NCP1910

effectively “blanks” any mains interruption that is shorter

than 25 ms (minimum guaranteed value of the 50 ms timer).

If R

<< R

,

LBOL

LBOU

(eq. 9)

R_LBOL

R_LBOU) R_LBOL

Ǹ

V_LBO] 2 V_ac,rms

* I_LBOHR_LBOL

• After the PFC stage has started operation, the input

voltage becomes a rectified sinusoid and the average

voltage becomes <V > = (2/p) √2 V

, which

in

ac,rms

decays 2/π of the peak value of rms input voltage.

Hence, the average voltage applied to LBO pin is:

At the end of this blanking delay (t

timer is activated that sets a 50 ms window during which a

), another

<V

> = (2/p) √2 V

R

/(R

+ R ).

LBOL

LBO(blank)

LBO

ac,rms LBOL

LBOU

And because of the ripple on the LBO pin, the

fault can be detected. This is the role of the t

Figure 46:

in

minimum value of V

is around:

LBO(window)

LBO

R_LBOL

2

Ǹ

V_LBO

+

2 V_ac,rms

• If V

is high during the second 50 ms delay

), a line brown−out condition is confirmed

LBOcomp

p

R_LBOU) R_LBOL

(t

LBO(window)

(eq. 10)

and PFC_BO signal is asserted high.

f_LBO

ǒ_{1 *}Ǔ

• If V

remains low for the duration of the

, no fault is detected.

LBOcomp

3f_line

t

LBO(window)

Where:

When the PFC_BO signal is high:

♦ f

is the sensing network pole frequency.

LBO

• The PFC driver is disabled, and the V

pin is

CTRL

R_LBOU) R_LBOL

grounded to recover operation with a soft−start when

f_LBO

+

the fault has gone.

2pR_LBOUR_LBOLC_LBO

• The V

voltage source is removed from LBO

LBO(clamp)

♦ f

is the line frequency.

line

pin.

♦ R

is low side resistor of the dividing resistors

between LBO pin and ground.

is upper side resistor of the dividing resistors

LBOL

• The I

current source (7 mA typically) is enabled

that lowers the LBO pin voltage for hysteresis purpose.

At startup, a pnp transistor ensures that the LBO pin

LBOH

♦ R

LBOU

between V and LBO pin.

in

voltage remains below when: V < UVLO or ON/OFF pin

CC

f_LBO

The term

of Equation 10 enables to take into

1 *

is released open or UVP or Thermal Shutdown. This is to

guarantee that the circuit starts operation in the right state,

which is “PFC_BO” high. When the NCP1910 is ready to

work, the pnp transistor turns off and the circuit enables the

3f_line

account the LBO pin voltage ripple (first approximation).

If as a rule of the thumb, we will assume that

f_line

.

f_LBO

+

10

I

.

LBOH

Re−arranging the Equation 9 and 10, the network connected

Also, I

is enabled whenever the part is in off mode,

LBOH

to LBO pin can be calculated with the following equations:

but at startup, I

is disabled until V reaches V

.

LBOH

CC

CC(on)

ȡ

ȣ

@

Line Brown−Out Network Calculation

V_LBOT

V_ac,on

V_ac,off

1

p

R_LBOL

+

@

* 1

If the line brown−out network is connected to the voltage

after bridge diode, the monitored voltage can be very

different depending on the phase:

ȧ

1 * ^f

2

I_LBOH

LBO

Ȣ

Ȥ

3f

(eq. 11)

line

• Before operation, the PFC stage is off and the input

bridge acts as a peak detector. As a consequence, the

input voltage is approximately flat and nearly equates

V_LBOT

V_ac,on

V_ac,off

1

p

^

ǒ

@

* 1 @

Ǔ

0.967

2

I_LBOH

the ac line amplitude: <V > = √2 V

, where V

in

ac,rms

Ǹ

2 @ V_ac,on

(eq. 12)

is the rms voltage of the line. As depicted in previous

section, the I turns on before PFC operates for the

R_LBOU

+

ǒ

* 1 R_LBOL

Ǔ

I_LBOHR_LBOL) V_LBOT

LBOH

purpose of adjustable line brown−out hysteresis; hence,

the average voltage applied to LBO pin is:

Where:

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23

NCP1910

PFC Over−Power Limitation (OPL)

♦ V

is the rms ac voltage to starts PFC operating.

ac,on

This is a second OCP with a threshold that is line

♦ V

the rms ac voltage for line brown−out

ac,off

dependent. Sense current I represents the inductor current

detection.

CS

I

and hence represents the input current approximately.

L

PFC Current Sense

Input voltage signal V

represents the rms input voltage.

LBO

The product (I x V

) represents an approximated input

CS

LBO

power (I x V ). It is illustrated in Figure 48.

L

ac

I

L

I

R

CS CS

CS

I

V

in

NCP1910

L

+

GND

V

CS

−

R

SENSE

I

L

R

SENSE

Figure 47. PFC Current Sensing Configuration

R

CS

The device senses the inductor current I by the current

sense scheme in Figure 47. The device maintains the voltage

L

CS

I

Current

mirror

CS

at CS pin to be zero voltage, i.e. V = 0 V, so that

CS

R

LBOU

R_SENSE

OPL

LBO

(eq. 13)

I_CS

+

I_L

> 275 mVA?

R_CS

C

LBO

R

LBOL

Where:

♦ R

is the sense resistor to sense I .

L

SENSE

♦ R is the offset resistor between CS pin and

CS

R

.

SENSE

Figure 48. PFC Over−Power Limitation Configuration

This scheme has the advantage of the minimum number

of components for current sensing. The sense current I

represents the inductor current I and will be used in the PFC

duty modulation to generate the multiplier voltage V ,

Over−Power Limitation (OPL), and Over−Current

Protection. Equation 13 would insist in the fact that it

provides the flexibility in the R

allows to detect in−rush currents.

CS

When the product (I

x V

) is greater than a

LBO

CS

L

permissible level 275 mVA, the device turns off the PFC

driver so that the input power is limited. The OPL is

M

automatically deactivated when the product (I x V

) is

CS

LBO

lower than the 275 mVA level. This 275 mVA level

choice and that it

SENSE

corresponds to the approximated input power (I x Vac) to

L

be smaller than the particular expression in Equation 15.

PFC Over−Current Protection (OCP)

I_CSV_LBOt 275 mVA

PFC Over−Current Protection is reached when I is

CS

(eq. 15)

Ǹ

R_SENSE

2 2K_LBO

larger than I

(200 mA typical). The offset voltage of

S(OCP)

ǒ Ǔ

I_L

@ V

t 275 mVA

ǒ Ǔ

ac

the CS pin is typical 10 mV and it is neglected in the

calculation. Hence, the maximum OCP inductor current

p

R_CS

threshold I

is obtained in Equation 14.

L(OCP)

R_CS@ p

I_L@ V_ac

t

@ 97 mVA

R_CSI_{S OCP}

ǒ

Ǔ

R_CS

R_SENSE@ K_LBO

(eq. 14)

I_{L OCP}

+

200 mA

ǒ

Ǔ

R_SENSE

Where

When over−current protection threshold is reached, the

PFC drive goes low. The device automatically resumes

operation when the inductor current goes below the

threshold.

R_LBOL

K_LBO

+

R_LBOU) R_LBOL

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24

NCP1910

PFC Reference Section

The internal reference voltage (V

V_CTRL

R_FBL@ G_EAR_Z

R_FBL) R_FBU

1 ) sR_ZC_Z

+

@

(eq. 17)

) is trimmed to be

PREF

V_bulk

ǒ

Ǔ

sR_ZC_Z1 ) sR_ZC_P

2% accurate over the temperature range (the typical value

is 2.5 V). V is the reference used for the regulation of

PREF

PFC Power Analysis and V_in²Feed−Forward

From Equation 7 through 13, the input impedance Z is

PFC section.

in

re−formulated in Equation 18.

PFC Feedback and Compensation

2R_MR_SENSE@ K_LBO²@ V_ac²@ V_{bulk L}

I

Z_in

+

V

bulk

V

in

2

ǒ

Ǔ

p R_CS@ V_CTRL* V_{CTRL min}@ V_{PREF L−50}

I

ǒ

Ǔ

(eq. 18)

When I is equal to I

, Equation 18 is re−formulated in

L

L−50

Equation 19.

2R_MR_SENSE@ K_LBO²@ V_ac²@ V_bulk

R

FBU

Z_in

+

(eq. 19)

FB

2

ǒ

Ǔ

p R_CS@ V_CTRL* V_{CTRL min}@ V_PREF

ǒ

Ǔ

OTA

V

The multiplier capacitor C is the one to filter the

CTRL(min)

V

PREF

M

V

CTRL

high−frequency component of the multiplier voltage V .

M

R

FBL

The high−frequency component is basically coming from

the inductor current I . On the other hand, the input filter

L

R

Z

capacitor C similarly removes the high−frequency

To Multiplier of V pin

in

M

C

component of inductor current I . If the capacitors C and

P

L M

C match with each other in terms of filtering capability, I

in

L

C

Z

becomes I

. Input impedance Z is roughly constant over

L−50

in

the bandwidth of 50 or 60 Hz and power factor is corrected.

Input and output power (P and P ) are derived in

Figure 49. V_CTRLType−2 Compensation

in

out

Equations 20 and 21 when the circuit efficiency η is

The output voltage V

FB pin via the resistor divider (R

of the PFC circuits is sensed at

obtained or assumed. The variable V stands for the rms

bulk

ac

and R

) as shown in

input voltage.

FBL

FBU

Figure 49. V

is regulated as described in Equation 16.

bulk

R_FBU) R_FBL

2

_@ǒ_V

_ǓǓ_@ V

p

@ R

* V

(eq. 16)

V_bulk+ V_PREF

ǒ

CS

CTRL

PREF

2

CTRL min

V

ac

R_FBL

P

+

T

+

in

2

Z

2R R

K

@ V

in

The feedback signal V represents the output voltage

M

SENSE LBO

bulk

FB

V

bulk

and will be used in the output voltage regulation,

Over−voltage protection (OVP), fast transient response, and

under−voltage protection (UVP)

(eq. 20)

ǒ_V

_ǓǓ

* V

ǒ

CTRL

CTRL min

V

The Operational Trans−conductance Amplifier (OTA)

bulk

constructs a control voltage, V

, depending on the

CTRL

2

_@ǒ_V

_ǓǓ_@ V

p @ R

* V

CTRL

ǒ

output power and hence V . The operating range of

PREF

CS

CTRL min

bulk

P

+ hP + h

V

CTRL

is from V

to V

. The signal used

CTRL(min)

CTRL(max)

in

2

2R R

K

@ V

M

SENSE LBO

bulk

for PFC duty modulation is after decreasing a offset voltage,

, i.e. V −V

V

.

CTRL(min)

CTRL

(eq. 21)

ǒ_V

_ǓǓ

* V

This control voltage V

is a roughly constant voltage

ǒ

CTRL

CTRL min

CTRL

T

that comes from the PFC output voltage V

varying signal. The bandwidth of V

that is a slowly

bulk

V

bulk

can be additionally

CTRL

2

Because of the V feed−forward, the power delivery is

in

limited by inserting the external type−2 compensation

components (that are R , C , and C as shown in Figure 49).

independent from input voltage. Hence the transfer function

of power stage is independent from input voltage, which

easies the compensation loop design.

Z

P

It is recommended to limit cross over frequency of open loop

system below 20 Hz typically if the input ac voltage is 50 Hz

to achieve power factor correction purpose.

The transformer of V

to V

is as described in

bulk

CTRL

Equation 16 if C >> C . G is the error amplifier gain.

Z

P

EA

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25

NCP1910

PFC Frequency Foldback

NCP1910 implements frequency foldback feature on PFC

is hence done by comparing (V

− V

) with

CTRL

CTRL(min)

V

fold

, the voltage on Fold pin.

section to improve the efficiency at light load. Thanks to

The simplified block diagram of PFC frequency foldback

feature is depicted in Figure 50.

2

V

in

feed−forward feature, the output power is proportional

to the (V

− V

). The PFC frequency foldback

CTRL

CTRL(min)

PFCOSC

Vref

Vdd

Ict(min)

Ict

Vfold

Vfold(max)

Ict(fold)

“0” / ”1”

V

/ 10%V

PREF

Oscillator section

Vctrl

Grand Reset

PFC BO

Vctrl(min)

S

R

Q

PFC OK

Figure 50. The PFC Frequency Foldback Block

Where:

♦ The transient slope of frequency foldback vs. V

CTRL

♦ I

limits the minimum operating frequency.

is fixed inside.

Ct(min)

♦ I and I

provide the charging current for

♦ V

is to limit the maximum power level of

Ct

Ct(min)

fold(max)

oscillator and hence control the nominal operating

frequency.

frequency foldback, which is around 2 V typically.

The frequency foldback is disabled at startup, i.e. before

the PFCok signal in Figure 50 is asserted high.

♦ V

determines the power level at which the

fold

frequency foldback starts.

steals the I and hence reduces the

The user can adjust the power level at which the frequency

foldback starts by adjust the resistor divider between V

♦ I

REF

Ct(fold)

Ct

pin and fold pin. Also, the frequency foldback can be

disabled by grounding fold pin.

operating frequency according to the error

information between V

and (V

−

fold

CTRL

The relationship between operating frequency and V

V

).

CTRL

CTRL(min)

is depicted in Figure 51.

F

sw

The slope is fixed internally.

The power level at which fre-

quency starts reducing is ad-

F

sw(fold)

justable by modifying V

.

fold

V

CTRL

−V

T Power

CTRL(min)

V

fold

– 0.4

V

fold

Figure 51. The Relationship between Frequency and V_CTRL

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26

NCP1910

PFC Power Boost

As depicted in previous section, thanks to the V

2

too soon, which is about 77 ms typically. The PFC power

in

feed-forward, the power delivery is independent from input

voltage. It brings benefit of good power factor and a direct

control on the frequency foldback. However, in some special

case such as when the ac input voltage drops sharply from

high line to low line, the power will be limited because the

filter on LBO pin slows down the reaction speed to follow

up the change on input voltage. In the end, the bulk voltage

might drop too low and stop the LLC converter.

boost function is inhibited at start-up until bulk voltage is

above 95% of nominal output.

PFC Skip Mode

In order to ensure a proper regulation in no load

conditions, the circuit skips cycles when V

is at its

CTRL

minimum level. V

is maintained between about 0.6 V

CTRL

and 3.6 V due to the internal active clamps. A skip sequence

occurs as long as the 0.6 V clamp circuitry is triggered and

switching operations is recovered when the clamp is

inactive.

Hence, NCP1910 builds a so-called PFC power boost

function inside. The idea is to pull down LBO pin to 2 V

typically, V

, when

LBO(PD)

• V

is above 2 V, V

line, and

, i.e. the input is at high

LBO

LBO(PD)

Fast Transient Response

Given the low bandwidth of the regulation block, the

output voltage of PFC stages may exhibit excessive over or

under−shoots because of abrupt load or input voltage

variations (such as start−up duration). As shown in

Figure 52, if the output voltage is out of regulation,

NCP1910 has 2 functions to maintain the output voltage

regulation.

• V

is at maximum for more than timer defined by

, and,

is under 95% of nominal output, i.e. VLD is

CTRL

t

PFCflag

• V

bulk

triggered.

The maximum pulling-down duration is defined by

t

, which is 5 ms typically. A blanking timer,

, is to avoid this power boost function reacting

LBO(PDlimit)

LBO(PDblank)

V

bulk

Vdd

PFC_OK

PFC_OPL

I

VLD

200 mA

PFC_OVP

+

R

FBU

−

105% V

PREF

FB

VLD

95% V

PREF

R

FBL

C

FB

$30 mA

OTA

V

PREF

V

CTRL

Figure 52. PFC OVP and VLD

voltage is 105% of 390 V = 410 V. Hence a cost and

size effective bulk capacitor of lower voltage rating is

suitable for this application,

• Over−Voltage Protection (OVP): When V is higher

FB

than 105% of V

(i.e. V

> 105% of nominal

PREF

bulk

bulk voltage), the PFC driver output goes low for

• Voltage−Low Detection (VLD): NCP1910 drastically

speeds up the regulation loop by its internal 200 mA

enhanced current source when the bulk voltage is below

95% of its regulation level. Under normal condition, the

protection. The circuit automatically resumes operation

when V becomes lower than 103.2% of V

, i.e.

PREF

FB

around 44 mV hysteresis in the OVP comparator. If the

nominal V is set at 390 V, then the maximum bulk

bulk

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27

NCP1910

maximum sink and source of output current capability

of OTA is around 30 mA. Due to the “V Low Detect”

response performance. The relationship between

current flowing in/out V

in Figure 53.

pin and V is as shown

out

CTRL

FB

block (VLD), when the V is below 95% V

, an

PREF

FB

It is recommended to add a typical 100 pF capacitor C

extra 200 mA current source (I

in Figure 52) will

FB

VLD

decoupling capacitor next to feedback pin to prevent from

noise impact.

raise V

rapidly. Hence prevent the PFC output

CTRL

from dropping too low and improve the transient

50

0

−50

−100

−150

−200

−250

2

2.2

2.4

2.6

2.8

3

No DRV when V is

above 105% V

FB

PREF

230 mA raises V

rapidly

CTRL

V_FB

when V is below 95%

FB

V

PREF

Figure 53. V_FBvs. Current Flowing in/out From V_CTRLPin

PFCok Signal

Refer to Figure 54. “PFCok” signal is low when

• the PFC stage start−up, or

The PFC provides a “PFCok” signal to:

• enable the dynamic response enhancer (I

below 95%, finish of the PFC soft−start,

• enable the PFC frequency foldback,

• enable the timer (t

converter,

) if V

is

• any latch off signal arrives, or

• line brown−out activates.

VLD

bulk

“PFCok” signal is high when

• DRV starts operating and the PFC stage is above 95%

of target, i.e. the VLD comparator output is high, or

), which is to start the LLC−HB

DEL1

• enable the timer (t

), which is to stop LLC−HB

DEL2

• the PFC stage is above 100% target, i.e. PFC

REG

converter once “PFCok” is asserted low or V

is

bulk

comparator output is high.

lower than PG level after LLC−HB has started.

This “PFCok” signal is high when the PFC stage is in

normal operation, i.e. its output is above 95% of normal

output, and low otherwise.

PFC_BO

Latch

Grand Reset

R

S

PFC_OK

Q

DRV

95% V

+

PREF

−

VLD

FB

+

−

V

PREF

PFC

REG

Figure 54. PFCok Signal Block Diagram

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28

NCP1910

PFC Soft−Start

Refer to Figure 52 and 54. The device provides no PFC

driver output when the V

As shown in Figure 55, when V is less than 8% of

FB

V

, the device is shut down. The device automatically

PREF

is lower than V

.

starts operation when the output voltage goes above 12% of

. In normal situation of boost converter configuration,

CTRL

CTRL(min)

V

is pulled low by:

V

•^CV^TRLUnder−Voltage Lockout, or

PREF

the bulk voltage V

is always greater than the input

bulk

CC

voltage V and the feedback signal V has to be always

in

FB

• Off signal from on/off pin, or

• Thermal Shut−down (TSD), or

• Line Brown−out, or

greater than 8% and 12% of V

to enable NCP1910 to

PREF

operate.

The main purpose of this Under−Voltage Protection

function is to protect the power stage from damage at

• PFC Under−Voltage Protection

At one of these situations, NCP1910 grounds the V

CTRL

feedback loop abnormal, such as V is grounded or the

FB

pin and turns off the 200 mA current source in regulation

block.

feedback resistor R

is open.

FBU

Redundant Over−Voltage Protection (OVP2 pin)

Except the Over−Voltage Protection in FB pin, NCP1910

also reserve one dedicated pin, OVP2 pin, for the redundant

over voltage protection on bulk voltage. The purpose of this

feature is to protect the power components from damage in

case of any drift on the feedback resistor. As shown in

Figure 56, the OVP2 has 3 differences compared to the OVP

in FB pin:

• The protection mode provided by OVP2 pin is

latch−off. When OVP2 is triggered, the NCP1910 stays

at latch off mode, i.e. both PFC and LLC stop.

• A 20 ms filter is built−in after the OVP2 comparator for

better noise immunity.

When the IC turns on again:

• V

will be pulled low and PFC DRV output keeps

CTRL

off until V

is below V

to make PFC

CTRL

CTRL(min)

starts with lowest duty cycle.

• The 200 mA current source block keeps off. Only the

Operating Transconductance Amplifier (OTA) raises

the V

slowly.

CTRL

This is to obtain a slow increasing duty cycle and hence

reduce the voltage and current stress on the MOSFET. A

soft−start operation is obtained.

PFC Under−Voltage Protection (UVP) for Open Loop

Protection

• The reference voltage for this OVP2 comparator is

107% of V

PREF.

The resistance value of R

and R

could be the

OVPU

OVPL

I

CC2

same as R

and R

depending on the requirement of

FBU

FBL

Operating

Shutdown

PREF

OVP2 level. In this case, the level of the OVP in FB pin

would be 105% of normal bulk voltage and OVP2 will be

107% of normal bulk voltage. Or if one would need a higher

level for the OVP2, then it is flexible to change the value.

If someone doesn’t need this OVP2 feature, then OVP2

function could be disable by grounding the OVP2 pin.

I

CC7

V

FB

8% V

12% V

PREF

Figure 55. PFC Under−Voltage Protection

V

bulk

R

OVPU

OVP2

20 ms filter

PFC_OVP2

to SR-latch

107% V

PREF

R

OVPL

C

OVP

Figure 56. PFC 2^ndOver−Voltage Protection

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29

NCP1910

PFC Abnormal

The PFC abnormal is detected by sensing V

However, as a D−flip−flop that creates division−by−two

level.

internally provides two outputs (A and B in Figure 57), the

final effective signal on LLC driver outputs (ML and MU)

switches between 25 kHz and 500 kHz. The CCO is

configured in such a way that if the current that flows out

CTRL

, or lower than V

When V

stays at V

CTRL

CTRL(max) CTRL(min)

– 0.1 V, for more than t

, PFC turns off first. After

PFCabnormal

t

, LLC shuts down. It is latches off protection.

DEL2

The main purpose of this feature is to avoid LLC from

operating without correct operation of PFC stage.

from the R pin increases, the switching frequency also goes

t

up.

LLC Section

Current Controlled Oscillator (CCO)

The current controlled oscillator features a high−speed

circuitry allowing operation from 50 kHz up to 1 MHz.

VDD

S

B

for MU

for ML

D

Q

+

-

V

Rt

Clk

R

t

A

I

DT

R

C

R

t

R

max

SS

min

V

Ctmax

SS

LLCenable

Feedback

opto-coupler

Grand Reset

Latch

C

SS

Grand Reset

LLC_BO

elapsed

CS/FF > V

CS1

t

DEL2

S

R

Grand Reset

Q

Disable LLC ML and MU

R

Grand Reset

-

LLC_PG

+

V

SS_RST

Figure 57. The Current Controlled Oscillator Architecture and Configuration

The internal timing capacitor C is charged by current

which is proportional to the current flowing out from the

For the resonant applications, it is necessary to adjust

minimum operating frequency with high accuracy. The

designer also needs to limit maximum operating and startup

frequency. All these parameters can be adjusted by using

t

R pin. The discharging current i is applied when voltage

t

DT

on this capacitor reaches V

. The output drivers are

Ctmax

disabled during discharge period so the dead time length is

given by the discharge current sink capability. Discharge

sink is disabled when voltage on the timing capacitor

external components connected to the R pin as shown in

Figure 57.

The following approximate relationships hold for the

minimum, maximum and startup frequency respectively:

t

reaches zero and charging cycle starts again. C is grounded

t

to disable the oscillator when either of “turn−off LLC”

signals arrives.

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30

NCP1910

The definition of start−up, shut−off and these 2 delay

timers (t and t ) will be depicted later in “combo

management section”.

There are the other 2 delay timers are built−in after the

brown−out comparator:

• The minimum switching frequency is given by the R

min

DEL1

DEL2

resistor value. This frequency is reached if there is no

feedback action and soft start period has already

elapsed.

• t

is the delay timer after V

BO level.

is rising above the

BOK

bulk

490 10⁶V_Rt

(eq. 22)

R_min

+

F_min

• t

is the delay timer after V

is falling down

BONOTOK

the BO level.

bulk

• The maximum switching frequency excursion is limited

by the R selection. Note that the maximum

NCP1910 gets the information of V

from the PFC FB

max

bulk

pin, which minimizes the losses of the high voltage sensing

circuit. As depicted in Figure 22, 3 resistors (R , R , and R )

frequency is influenced by the opto−coupler saturation

voltage value.

1

2

3

among V , PG , BO pin, and ground determine the

REF

adj

490 10⁶V_Rt

levels of PG signal and LLC brown−out as the following

(eq. 23)

R_max

+

out

F_max* F_min

formulas:

• Resistor R together with capacitor C prepares the

R₂) R₃

SS

V_PG

+

@ V_REF

soft start period for the resonant converter.

R₁) R₂) R₃

490 10⁶V_Rt

(eq. 25)

(eq. 24)

R_SS

+

R_FBL

V_PREF

F_SS* F_min

+ V_bulk,PG

@

+ V_bulk,PG

@

R_FBU) R_FBL

V_bulk,nom

Where:

♦ V = 3.5 V

R₃

R₁) R₂) R₃

Rt

V_BO

+

@ V_REF

♦ F

is the minimal frequency

is the maximal frequency

min

max

(eq. 26)

V_PREF

♦ F is the maximal soft start switching frequency

SS

R_FBL

+ V_bulk,BO

@

+ V_bulk,BO

R_FBU) R_FBL

V_bulk,nom

LLC Power Good Signal and Brown−out (PG_adj, PG_out

and BO_adjPin)

As shown in Figure 22, the NCP1910 provides the

Brown−Out circuitry (BO) that offer a way to protect the

Where:

♦ V is the voltage on PG pin

PG

adj

♦ V is the voltage on BO pin

BO

adj

resonant converter from operating at too low V . In the

bulk

♦ V

is the reference voltage (5 V typically).

is the internal reference voltage for PFC

feedback OTA (2.5 V typically)

REF

mean time, NCP1910 provides a Power Good signal (PG

to inform the isolated secondary side that the NCP1910 is in

order of match.

)

out

PREF

♦ V

is the bulk voltage when PG pin is

bulk,PG

out

Once the PFC has started and raises V

above 95% of

bulk

released open.

its regulated voltage, an internal “PFC_OK” signal is

asserted. 20 ms later (t ), the PG pin is brought low.

♦ V

is the bulk voltage when brown−out

function of LLC activates.

is the normal bulk voltage, e.g. 390 V.

Divide Equation 25 by 26, we can get the relationship

bulk,BO

DEL1

out

The PG signal can now disappear, which will release

out

♦ V

bulk,nom

PG pin open, in two cases:

out

• V

decreases to the level, programmed by a reference

bulk

between R and R in Equation 27:

2

3

voltage imposed on PG pin. This level is usually

adj

V_bulk,PG

R₂

R₃

above the LLC turn−off voltage, programmed by BO

adj

(eq. 27)

+

* 1

pin. Therefore, in a normal turn−off sequence, PG first

drops and informs the secondary side that it must be

prepared for shutdown.

V_bulk,BO

Hence, by given V

and V

, and choose the

bulk,PG

bulk,BO

st

value R as the 1 step, we can get the R by Equation 27 and

3

2

• The second event that can drop the PG signal is when

the PFC experiences a fault: broken feedback path

(PFC UVP), PFC abnormal, or input line brown−out. In

either case, the internal PFCok signal will drop and

R by Equation 26.

For example, V

1

is 390 V, V

is 340 V, and

bulk,nom

bulk,PG

V

is 330 V. Choose 10 kW resistor as R . Then R2 is

303 W. Choose 300 W as it is the closet standard resistor.

Then we can get the R is 13.3 kW.

bulk,BO

3

then assert the PG signal high, and starts a 5 ms timer

out

1

(t

). Once this timer is elapsed, the LLC converter

DEL2

can be safely halted.

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31

NCP1910

V

REF

R

3

BOadj

+

”1” BONOTOK

LLC_BO

t

BOK

−

BONOTOK

R

1

2

PFC_FB

LLCenable

PFC_OK

”1” is ok

”0” notok

”1” PGNOTOK

”1” enables LLC

”0” LLC is locked

−

PGadj

+

LLC_BO

LLC_PG

V

CC

SS is reset

Grand

Reset

t

DEL1

R

V

SB

20 ms

t

DEL2

PGout

5 ms

To close switch

at SS pin

”1” after reset

”0” when PG out

drops after 5 ms

PGI for

supervisory

Figure 58. The PG and BO Block Diagram for LLC

LLC Fast Fault Input (CS/FF Pin)

(ML and MU) is shifted up to keep the primary current under

acceptable level.

In case of heavy overload, like transformer short circuit,

the primary current grows very fast and thus could reach

danger level. The NCP1910 therefore features additional

As shown in Figure 59, the NCP1910 offers a dedicated

input (CS/FF pin) to detect the primary over−current

conditions and protect the power stage from damage.

Once the voltage on the CS/FF pin exceeds the threshold

of V

(1 V typically), the internal switch at SS pin will be

comparator V

(1.5 V typically) at the CS/FF pin to

CS1

CS2

closed to discharge C until V is below V

permanently latch the device (both PFC and LLC) and

protect against destruction.

SS

SS_RST

(150 mV typically). Hence the switching frequency of LLC

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32

NCP1910

PFC_OVP2

CS/FF

+

−

S

R

Latch

Q

”1” to disable LLC and PFC driver,

and pull down PFCok

V

CS2

PFC_BO

+

Grand Reset

”1” to set the SR−latch to

pull low SS pin

−

V

CS1

Figure 59. The Fast Fault Input at CS/FF pin

LLC Soft−Start (SS Pin)

Once the LLC part starts operation, the internal switch at

In resonant converter, a soft−start is needed to avoid

suddenly applying the full current into the resonating circuit.

NCP1910 reserves SS pin to fully discharge soft−start

capacitor before re−start and in case of fault conditions:

SS pin is released open and the empty soft−start capacitor

withdraws current from R pin through soft−start resistor,

t

R . This current charges up and soft−start capacitor and

SS

increases the operating frequency of LLC. As the soft−start

capacitor is charged, the LLC driver output frequency

• LLC brown−out actives,

smoothly decreases down to F . Of course, practically, the

min

• t

is elapsed, where t

timer could be activated

DEL2

feedback loop is supposed to take over the CCO lead as soon

as the output voltage has reached the target.

by line brown−out or power good comparator,

• CS/FF pin is above V , the fast fault input for LLC,

CS1

• V UVLO,

LLC Skip (Skip Pin, B Version Only)

CC

To avoid any frequency runaway in light conditions but

also to improve the standby power consumption, the

NCP1910B welcomes a skip mode operation (Skip pin)

which permanently observes the opto−coupler collector as

depicted in Figure 60. If skip pin senses a low voltage, it cuts

the LLC output pulses (ML and MU pins) until the collector

goes up again.

• PFC UVP,

• Off signal from on/off pin, or

• Thermal Shut−Down (TSD)

When the switch inside SS pin is activated to discharge the

soft−start capacitor, it keeps close until V is below

SS

V

SS_RST

(150 mV typically). It ensures the full discharge of

soft−start capacitor before re−start, and hence the fresh

soft−start is confirmed.

R

t

R

max

R

SS

R

min

SS

C

SS

Feedback

opto−coupler

Skip

−

Disable ML and

MU

+

V

Skip

Figure 60. The LLC Skip Mode Configuration

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33

NCP1910

LLC High−Voltage Driver

another timer (t

) starts. Once the t

is elapsed, LLC

DEL2

The NCP1910 includes a high−voltage driver allowing a

direct connection to the upper side MOSFET of LLC

converter. This device also incorporates an upper UVLO

circuitry that makes sure enough gate voltage is available for

the upper side MOSFET. The bias of the floating driver

stops its drivers (ML and MU pins).

Figure 61 depicts the start−up and stop delay of LLC and

PG

.

out

Once the PFC is ready (PFCok is asserted high), t

DEL1

(20 ms typically) is started. Once this delay is elapsed:

section is provided by C

capacitor between V

pin and

boot

• PG pin is asserted low

out

HB pin that is refilled by external booststrap diode. The

floating portion can go up to 600 Vdc and makes the IC

perfectly suitable for offline applications featuring a 400 V

PFC front−end stage.

• LLC drivers (ML and MU pins) can start to operate.

As shutdown by unplug ac input, V

decreases:

bulk

• When it reaches the PG signal, which is adjusted by

PG pin, PG pin is released open.

adj

out

Combo Management Section

• If V

reaches the LLC stop level (BO level adjusted

bulk

by BO pin), the LLC stops; or if V

drops slowly,

Start−up and Stop Delay of LLC and Pgout signal

adj

bulk

(t_DEL1and t_DEL2

To ensure the proper operation of LLC, LLC cannot start

if the PFC is not ready.

As depicted in the “PFCok signal” section, the internal

PFCok signal is asserted high when V

)

e.g. light load, LLC drivers (ML and MU pins) will

stop 5 ms after PG pin is released (t ).

out

DEL2

As shutdown by line brown−out situation, PFCok signal will

be pulled down:

is above 95% of

bulk

• PG pin is released open once this internal PFCok

out

normal bulk voltage. After PFCok signal is high, a timer

(t ) starts to ensure PFC stage is fully stable before LLC

signal is low.

DEL1

• LLC drivers (ML and MU pins) will stop 5 ms after

starts. When t

is elapsed, PG pin is grounded and

DEL1

out

PG pin is released open (t

).

out

DEL2

LLC starts its driver outputs (ML and MU pins).

In case of shutdown by unplugging ac input or line brown

out situation, PG

signal is released open. And then

out

V

bulk

95%

PG level

BO level

t

DEL1

20 ms

PG

out

t

DEL2

LLC works

off

5 ms

off

time

Figure 61. The Timing for t_DEL1and t_DEL2

Remote on/off (on/off pin)

NCP1910 reserves one dedicated pin for remote control

feature at on/off pin:

• When the on/off pin is above 3 V, the device stops both

PFC and LLC immediately and keeps low

consumption. Figure 62 depicts the relationship

between the operation mode and on/off pin.

• When the on/off pin is pulled below 1 V, the PFC starts

operation. 20 ms after V

level, LLC starts.

is above 95% of target

bulk

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34

NCP1910

State

ON

OFF

On/off pin

TBD

I

CC

< 600 mA

V

on

V

off

On/off pin

Figure 62. Remote on/off (on/off Pin)

V_CCUnder−Voltage LockOut (UVLO)

The device incorporates an Under−Voltage Lockout block

to prevent the circuit from operating when V is too low in

order to ensure a proper operation. An UVLO comparator

some hysteresis (V

) to prevent erratic operation as

CC(Hys)

the V crosses the threshold. When V goes below the

CC

UVLO comparator lower threshold (V

turns off. It is illustrated in Figure 63. After startup, the

operating range is between 9 V and 20 V.

), the circuit

CC(min)

CC

monitors V pin voltage to allow the NCP1910 to operate

CC

when V exceeds V

. The comparator incorporates

CC

CC(on)

State

ON

OFF

V

CC

TBD

I

CC

< 100mA

V

CC(on)

CC(min)

CC

Figure 63. V_CCUnder−Voltage LockOut (UVLO)

Bias the Controller

It is recommended to add a typical 1 nF to 100 nF

decoupling capacitor next to the V

operation. The hysteresis between V

temperature exceeds TSD level. The output stage is then

enabled once the temperature drops below typically 110°C

pin for proper

(i.e. TSD − TSD

). The thermal shutdown is provided to

CC

hyste

and V

is

prevent possible device failures that could result from an

CC(on)

CC(min)

small because the NCP1910 is supposed to be biased by

external power source. Therefore it is recommended to

make a low−voltage source to bias NCP1910, e.g. the

standby power supply.

accidental over−heating.

5 V Reference

The V

pin provides an accurate ( 2% typically) 5 V

REF

reference voltage. The Power−Good and Brown−Out of

LLC converter, and the frequency foldback level (fold pin)

of PFC can hence can get an accurate reference voltage by

resistor dividers.

Thermal Shutdown

An internal thermal circuitry disables the circuit gate drive

and then keeps the power switch off when the junction

http://onsemi.com

35

NCP1910

Latched Protections and Reset

As depicated in the above sections, there are 3 fault modes

that latch off both PFC and LLC:

• Recycle V so that V is below V

and back

CC

again.

CC(min)

to above V

CC(on)

• Recycle the remote on/off function, which toggles

on/off pin high and low again.

• Recycle the line brown−out function, which could be

done by unplug and re−plug the ac input.

• PFC abnormal

• PFC OVP2

• LLC CS/FF pin is above V

CS2

To release from the latch−off mode, NCP1910 offers 3

ways:

ORDERING INFORMATION

†

Device

Version

Marking

Package

Shipping

NCP1910A65DWR2G

65 kHz − A

NCP1910A65

SOIC 24WB Less Pin 21

1000 / Tape & Reel

(Pb−Free)

NCP1910B65DWR2G

65 kHz − B

NCP1910B65

SOIC 24WB Less Pin 21

1000 / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

http://onsemi.com

36

NCP1910

PACKAGE DIMENSIONS

SOIC−24 WB LESS PIN 21

CASE 752AB−01

ISSUE O

2X

NOTES:

0.20 C A-B

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL

BE 0.10 mm TOTAL IN EXCESS OF ’b’ AT MAXIM-

UM MATERIAL CONDITION.

4. DIMENSIONS b AND c APPLY TO THE FLAT SEC-

TION OF THE LEAD AND ARE MEASURED

BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.

5. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH, PROTRUSIONS OR GATE BURRS SHALL

NOT EXCEED 0.15 mm PER SIDE. INTERLEAD

FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 PER SIDE. DIMENSIONS D AND E1 ARE

DETERMINED AT DATUM H.

D

E

A

NOTE 7

H

C

24

1

13

12

NOTES 5 & 6

E1

2X

L2

L

0.33 C

0.10 C

D

DETAIL A

2X

B

NOTE 7

PIN 1

INDICATOR

24X

b

6. DIMENSIONS D AND E1 ARE DETERMINED AT

THE OUTERMOST EXTREMES OF THE PLASTIC

BODY EXCLUSIVE OF MOLD FLASH,

M

0.25

C A-B D

PROTRUSIONS, TIE BAR BURRS, OR GATE

BURRS BUT INCLUSIVE OF ANY MOLD

MISMATCH BETWEEN THE TOP AND BOTTOM OF

THE PLASTIC BODY.

7. DIMENSIONS A AND B ARE TO BE DETERMINED

AT DATUM H.

8. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

NOTES 3 & 4

TOP VIEW

h ^{NOTE 9}

_

x 45

0.10 C

M

0.10 C

9. THIS CHAMFER IS OPTIONAL. IF IT IS NOT

PRESENT, THEN A PIN 1 IDENTIFIER MUST BE

LOCATED IN THE INDICATED AREA.

c

A

e

SEATING

PLANE

A1

DETAIL A

C

NOTE 8

END VIEW

SIDE VIEW

MILLIMETERS

DIM MIN

MAX

2.65

0.29

0.51

0.33

A

A1

b

2.35

0.10

0.31

0.20

RECOMMENDED

SOLDERING FOOTPRINT*

J

D

E

E1

e

15.40 BSC

10.30 BSC

7.50 BSC

1.27 BSC

23X

1.62

23X

0.52

h

L

L2

M

0.25

0.40

0.25 BSC

0.75

1.27

8

0

_

11.00

1

1.27

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP1910/D

http://onsemi.com

37


型号：	NCP1910B100DWR2G
厂家：	ONSEMI
描述：	高性能组合控制器，用于 ATX 电源控制器
文件：	总37页 (文件大小：396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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