NCP302155AMNTWG [ONSEMI]
Integrated Driver and MOSFETs, 55 A;
| 型号： | NCP302155AMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | Integrated Driver and MOSFETs, 55 A |
| 文件： | 总19页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Driver and
MOSFET
NCP302155A
The NCP302155A integrates a MOSFET driver, high−side
MOSFET and low−side MOSFET into a single package.
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP302155A
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
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Features
• Capable of Average Currents up to 55 A
• Capable of Switching at Frequencies up to 2 MHz
• Compatible with 3.3 V or 5 V PWM Input
• Responds Properly to 3−level PWM Inputs
• Option for Zero Cross Detection with 3−level PWM
• Internal Bootstrap Diode
PQFN31 5X5, 0.5P
CASE 483BR
MARKING DIAGRAM
Pin1
• Undervoltage Lockout
NCP
302155A
AWLYYWW
• Supports Intel® Power State 4
• Thermal Warning output
• Thermal Shutdown
A
= Assembly Location
WL = Wafer Lot
YY = Year
Applications
• Notebook, Tablet PC and Ultrabook
WW = Work Week
• Servers and Workstations, V−Core and Non−V−Core DC−DC
Converters
PINOUT DIAGRAM
• Desktop and All−in−One Computers, V−Core and Non−V−Core
DC−DC Converters
8
7
6
5
4
3
2
1
• High−Current DC−DC Point−of−Load Converters
• Small Form−Factor Voltage Regulator Modules
VIN
VIN
VIN
THWN
DISB#
VCCD
32
AGND
5V
PGND
GL
33
GL
PGND
PGND
PGND
PGND
VCCD VCC
VIN
THWN
BOOT
SW
Zero Current
Detect Enable
ZCD_EN
DISB#
SW
DRVON from controller
PWM from controller
SMOD from controller
SW
PWM
VOUT
SMOD#
16
17
18
19
20
21
22
23
VSW
CGND
PGND
ORDERING INFORMATION
Figure 1. Application Schematic
†
Device
Package
Shipping
NCP302155AMNTWG
5 x 5
PQFN
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
August, 2021 − Rev. 1
NCP302155A/D
NCP302155A
VCCD 29
5 BOOT
VIN
8−11
VCC
3
LEVEL
SHIFT
UVLO
VSW
16−26
VCC
7 PHASE
DEAD
TIME
CONTROL
SMOD#
PWM
2
1
SHUTDOWN
WARNING
TEMP
SENSE
DISB#
30
LEVEL
SHIF
PGND
PGND
28
THWN
31
12−15
GL
GL
27
33
ZCD
CONTROL
AGND
CGND
32
4
Figure 2. Block Diagram
Table 1. PIN LIST AND DESCRIPTION
Pin No.
Symbol
PWM
Description
1
2
PWM Control Input and Zero Current Detection Enable
SMOD#
Skip Mode pin. 3−state input (see Table 6):
SMOD# = High ³ State of PWM determine whether the NCP302155A performs ZCD or not.
SMOD# = Mid ³ Connects PWM to internal resistor divider placing a bias voltage on PWM pin.
Otherwise, logic is equivalent to SMOD# in the high state.
SMOD# = Low ³ Placing PWM into mid−state pulls GH and GL low without delay.
There is an internal pull−up resistor to VCC on this pin.
3
4, 32
5
VCC
CGND, AGND
BOOT
nc
Control Power Supply Input
Signal Ground (pin 4 and pad 32 are internally connected)
Bootstrap Voltage
6
Open pin (not used)
7
PHASE
VIN
Bootstrap Capacitor Return
8−11
12−15, 28
16−26
27, 33
29
Conversion Supply Power Input
Power Ground
PGND
VSW
Switch Node Output
GL
Low Side FET Gate Access (pin 27 and pad 33 are internally connected)
Driver Power Supply Input
VCCD
DISB#
30
Output disable pin. When this pin is pulled to a logic high level, the driver is enabled. There is an
internal pull−down resistor on this pin.
31
THWN
Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
reaches TTHWN, this pin is pulled low.
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2
NCP302155A
Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise)
Pin Name / Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−5
Max
6.5
30
Unit
V
VCC, VCCD
VIN
V
BOOT (DC)
35
V
BOOT (< 20 ns)
BOOT to PHASE (DC)
VSW, PHASE (DC)
VSW, PHASE (< 20 ns)
PHASE (< 5 ns)
All Other Pins
40
V
6.5
30
V
V
35
V
−15
−0.3
35
V
V
+ 0.3
V
VCC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL INFORMATION
Rating
Symbol
Value
12.4
Unit
_C/W
_C/W
_C
q
JA
Thermal Resistance (under On Semi SPS Thermal Board)
q
1.8
J−PCB
Operating Junction Temperature Range (Note 1)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Maximum Power Dissipation
T
J
−40 to +150
−40 to +125
−55 to +150
10.5
T
A
_C
T
STG
_C
W
Moisture Sensitivity Level
MSL
1
1. The maximum package power dissipation must be observed.
2. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
3. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
Pin Name
VCC, VCCD
VIN
Conditions
Min
4.5
4.5
Typ
5.0
19
Max
5.5
24
Unit
V
Supply Voltage Range
Conversion Voltage
V
Continuous Output Current
55
A
F
F
= 1 MHz, V = 12 V, V
= 1.0 V, T = 25_C
SW
IN
OUT
A
= 300 kHz, V = 12 V, V
= 1.0 V, T = 25_C
60
A
SW
IN
OUT
A
Peak Output Current
85
A
Duration = 5 ms, Period = 10 ms
= 500 kHz, V = 12 V, V = 1.0 V,
OUT
F
SW
80
A
IN
Duration = 10 ms, Period = 1 s, T = 25_C
A
Junction Temperature
−40
125
_C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
NCP302155A
Table 5. ELECTRICAL CHARACTERISTICS
(V
VCC
= V
= 5.0 V, V
= 12 V, V
= 2.0 V, C
= C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the
VCCD
VIN
DISB#
VCCD
VCC
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
VCC SUPPLY CURRENT
Operating
Symbol
Conditions
Min.
Typ.
Max.
Unit
DISB# = 5 V, PWM = 400 kHz
DISB# = 5 V, PWM = 0 V
DISB# = 0 V, SMOD# = VCC
DISB# = 0 V, SMOD# = GND
VCC rising
−
−
−
1
−
2
2
mA
mA
mA
mA
V
No switching
Disabled
0.4
6
1
15
3.37
−
UVLO Start Threshold
UVLO Hysteresis
V
2.89
150
−
UVLO
−
mV
VCCD SUPPLY CURRENT
Enabled, No switching
DISB# = 5 V, PWM = 0 V,
PHASED
−
175
300
mA
V
= 0 V
Disabled
DISB# = 0 V
−
−
0.4
1
mA
Operating
DISB# = 5 V, PWM = 400 kHz
−
26
mA
DISB# INPUT
Input Resistance
Upper Threshold
Lower Threshold
Hysteresis
To Ground
−
−
467
−
−
2.0
−
kW
V
V
V
UPPER
0.8
200
−
−
V
LOWER
V
− V
−
−
mV
ms
UPPER
LOWER
Enable Delay Time
Time from DISB# transitioning HI
to when VSW responds to PWM.
−
40
Disable Delay Time
Time from DISB# transitioning
LOW to when both output FETs
are off.
−
21
50
ns
SMOD# INPUT
SMOD# Input Voltage High
SMOD# Input Voltage Mid−state
SMOD# Input Voltage Low
SMOD# Input Resistance
SMOD# Propagation Delay, Falling
V
V
V
2.65
1.4
−
−
−
−
2.0
0.7
−
V
V
SMOD_HI
SMOD#_MID
SMOD_LO
−
V
R
Pull−up resistance to VCC
−
455
34
kW
ns
SMOD#_UP
T
SMOD# = Low to GL = 90%,
PWM = MID
−
42
SMOD#_PD_F
SMOD# Propagation Delay, Rising
T
SMOD# = High to GL = 10%,
PWM = MID
−
22
30
ns
SMOD#_PD_R
PWM INPUT
Input Voltage High
Input Mid−state Voltage
Input Low Voltage
Input Resistance
V
V
V
2.65
1.4
−
−
−
−
−
−
2.1
0.7
−
V
V
PWM_HI
PWM_MID
PWM_LO
V
R
SMOD# = V
SMOD#_LO
or
10
MW
PWM_HIZ
SMOD#_HI
V
Input Resistance
R
SMOD# = V
SMOD# = V
−
−
−
68
1.7
13
−
−
−
kW
V
PWM_BIAS
PWM_BIAS
NOL_L
SMOD#_MID
PWM Input Bias Voltage
Non−overlap Delay, Leading Edge
V
SMOD#_MID
T
T
T
GL Falling = 1 V to GH−VSW Ris-
ing = 1 V
ns
Non−overlap Delay, Trailing Edge
GH−VSW Falling = 1 V to
GL Rising = 1 V
−
−
12
13
−
ns
ns
NOL_T
PWM Propagation Delay, Rising
PWM = High to GL = 90%
35
PWM,PD_R
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4
NCP302155A
Table 5. ELECTRICAL CHARACTERISTICS
(V
VCC
= V
= 5.0 V, V
= 12 V, V
= 2.0 V, C
= C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the
VCCD
VIN
DISB#
VCCD
VCC
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
Symbol
Conditions
Min.
−
Typ.
47
Max.
52
Unit
ns
PWM Propagation Delay, Falling
T
T
PWM = Low to SW = 90%
PWM = Mid−to−Low to GL = 10%
PWM,PD_F
Exiting PWM Mid−state Propagation
Delay, Mid−to−Low
−
14
25
ns
PWM_EXIT_L
Exiting PWM Mid−state Propagation
Delay, Mid−to−High
T
PWM = Mid−to−High to SW = 10%
−
13
25
ns
PWM_EXIT_H
ZD FUNCTION
Zero Cross Detect Threshold
ZCD Blanking + Debounce Time
THERMAL WARNING & SHUTDOWN
Thermal Warning Temperature
Thermal Warning Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
THWM Open Drain Current
BOOST STRAP DIODE
Forward Voltage
V
−
−
−6
−
−
mV
ns
ZCD
t
330
BLNK
T
T
T
T
Temperature at Driver Die
Temperature at Driver Die
−
−
−
−
−
150
15
−
−
−
−
5
_C
_C
_C
_C
mA
THWN
THWN_HYS
THDN
180
25
THDN_HYS
THWN
I
−
Forward Bias Current = 2.0 mA
Source Current = 100 mA
Source Current = 100 mA
−
380
−
mV
HIGH−SIDE DRIVER
Output Impedance, Sourcing
Output Sourcing Peak Current
Output Impedance, Sinking
Output Sinking Peak Current
LOW−SIDE DRIVER
R
−
−
−
−
0.9
2
−
−
−
−
W
A
W
A
SOURCE_GH
I
SOURCE_GH
R
0.7
2.5
SINK_GH
SINK_GH
I
Output Impedance, Sourcing
Output Sourcing Peak Current
Output Impedance, Sinking
Output Sinking Peak Current
GL Rise Time
R
Source Current = 100 mA
GL = 2.5 V
−
−
−
−
−
−
0.9
2
−
−
−
−
−
−
W
A
SOURCE_GL
I
SOURCE_GL
R
Sink Current = 100 mA
GL = 2.5 V
0.4
4.5
12
6
W
A
SINK_GH
SINK_GL
I
T
T
GL = 10% to 90%, C
GL = 90% to 10%, C
= 3.0 nF
= 3.0 nF
ns
ns
R_GL
LOAD
LOAD
GL Fall Time
F_GL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NCP302155A
Table 6. LOGIC TABLE
INPUT TRUTH TABLE
DISB#
PWM
SMOD# (Note 4)
GH (not a pin)
GL
L
X
X
L
H
L
L
L
L
H
H
H
H
H
X
L
L
X
H or MID
L
H
MID
MID
ZCD (Note 5)
L (Note 6)
4. PWM input is driven to mid−state with internal divider resistors when SMOD# is driven to mid−state and PWM input is undriven externally.
5. GL goes low following 80 ns de−bounce time, 250 ns blanking time and then SW exceeding ZCD threshold.
6. There is no delay before GL goes low.
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6
NCP302155A
TYPICAL PERFORMANCE CHARACTERISTICS
Test Conditions: V = 12 V, V = V
= 5 V, V
= 1 V, L
= 250 nH, T = 25 °C and natural convection cooling, unless
IN
CC
CCD
OUT
OUT A
otherwise noted.
Figure 3. Efficiency − 19 V Input, 1.0 V Output
Figure 4. Efficiency − 19 V Input, 1.8 V Output
Figure 5. Efficiency − 12 V Input, 1.0 V Output
Figure 6. Efficiency − 12 V Input, 1.8 V Output
Figure 7. Power Iosses vs. Output Current, 12 Vin
Figure 8. Power Iosses vs. Output Current, 19 Vin
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NCP302155A
TYPICAL PERFORMANCE CHARACTERISTICS
Test Conditions: V = 12 V, V = PV = 5 V, V
= 1 V, L
= 250 nH, T = 25 °C and natural convection cooling, unless
IN
CC
CC
OUT
OUT A
otherwise noted.
Figure 9. Power Loss vs. Switching Frequency
Figure 10. Power Loss vs. Input Voltage
Figure 11. Power Loss vs. Driver Supply Voltage
Figure 12. Power Loss vs. Output Voltage
Figure 13. Driver Supply Current vs. Switching
Frequency
Figure 14. Driver Supply Current vs. Driver Supply
Voltage
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8
NCP302155A
Theory of Operation
Safety Timer and Overlap Protection Circuit
The NCP302155A is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. The NCP302155A supports numerous application
control definitions including ZCD (Zero Current Detect)
and alternately PWM Tristate control. A PWM input signal
is required to control the drive signals to the high−side and
low−side integrated MOSFETs.
It is important to avoid cross−conduction of the two
MOSFETS which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP302155A prevents cross−conduction by
monitoring the status of the MOSFETs and applying the
appropriate amount of non−overlap (NOL) time (the time
between the turn−off of one MOSFET and the turn−on of the
other MOSFET). When the PWM input pin is driven high,
the gate of the low−side MOSFET (LSGATE) goes low after
a propagation delay (tpdlGL). The time it takes for the
low−side MOSFET to turn off is dependent on the total
charge on the low−side MOSFET gate.
The NCP302155A monitors the gate voltage of both
MOSFETs and the switch node voltage to determine the
conduction status of the MOSFETs. Once the low−side
MOSFET is turned off an internal timer delays (tpdhGH) the
turn−on of the high−side MOSFET. When the PWM input
pin goes low, the gate of the high−side MOSFET (HSGATE)
goes low after the propagation delay (tpdlGH). The time to
turn off the high−side MOSFET (tfGH) is dependent on the
total gate charge of the high−side MOSFET. A timer is
triggered once the high−side MOSFET stops conducting, to
delay (tpdhGL) the turn−on of the low−side MOSFET.
Low−Side Driver
The
low−side
driver
drives
an
internal,
ground−referenced low−RDS(on) N−Channel MOSFET.
The voltage supply for the low−side driver is internally
connected to the VCCD and PGND pins.
High−Side Driver
The high−side driver drives an internal, floating
low−RDS(on) N−channel MOSFET. The gate voltage for the
high side driver is developed by a bootstrap circuit
referenced to Switch Node (VSW and PHASE) pins.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor and resistor. When the
NCP302155A is starting up, the VSW pin is at ground,
allowing the bootstrap capacitor to charge up to VCCD
through the bootstrap diode (See Figure 1). When the PWM
input is driven high, the high−side driver turns on the
high−side MOSFET using the stored charge of the bootstrap
capacitor. As the high−side MOSFET turns on, the voltage
at the VSW and PHASE pins rises. When the high−side
MOSFET is fully turned on, the switch node settles to VIN
and the BST pin settles to VIN + VCCD (excluding parasitic
ringing).
Zero Current Detect
The Zero Current Detect PWM (ZCD_PWM) mode is
enabled when SMOD# is high (see tables 6 and 8).
With PWM set to > VPWM_HI, GL goes low and GH
goes high after the non−overlap delay. When PWM is driven
to < VPWM_HI and to > VPWM_LO, GL goes high after
the non−overlap delay, and stays high for the duration of the
ZCD blanking timer (TZCD_BLANK) and an 80 ns de−bounce
timer. Once this timer expires, VSW is monitored for zero
current detection, and GL is pulled low once zero current is
detected. The threshold on VSW to determine zero current
undergoes an auto−calibration cycle every time DISB# is
brought from low to high. This auto−calibration cycle
typically takes 25 ms to complete.
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (CBST) and an integrated diode to provide current
to the HS Driver. A multi−layer ceramic capacitor (MLCC)
with a value greater than 100 nF should be used as the
bootstrap capacitor. An optional 1 to 4 W resistor in series
with the bootstrap capacitor decreases the VSW overshoot.
PWM Input
Power Supply Decoupling
The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. It also determines the state of
the LS MOSFET. See Table 6 for logic operation. The PWM
in some cases must operate with frequency programming
resistances to ground. These resistances can range from
10 kW to 300 kW depending on the application. When
SMOD# is set to > VSMOD#_HI or to < VSMOD#_LO, the
input impedance to the PWM input is very high in order to
avoid interferences with controllers that must use
programming resistances on the PWM pin.
The NCP302155A sources relatively large currents into
the MOSFET gates. In order to maintain a constant and
stable supply voltage (VCCD) a low−ESR capacitor should
be placed near the power and ground pins. A multi−layer
ceramic capacitor (MLCC) between 1 mF and 4.7 mF is
typically used.
A separate supply pin (VCC) is used to power the analog
and digital circuits within the driver. A 1 mF ceramic
capacitor should be placed on this pin in close proximity to
the NCP302155A. It is good practice to separate the VCC
and VCCD decoupling capacitors with a resistor (10 W
typical) to avoid coupling driver noise to the analog and
digital circuits that control the driver function (See Figure
1).
If SMOD# is set to < VSMOD#_HI and > VSMOD#_LO
(Mid−State), the PWM pin undriven default voltage is set to
Mid−State with internal divider resistances.
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NCP302155A
Disable Input (DISB#)
VCC Undervoltage Lockout
The DISB# pin is used to disable the GH to the High−Side
FET to prevent power transfer. The pin has a pull−down
resistance to force a disabled state when it is left
unconnected. DISB# can be driven from the output of a logic
device or set high with a pull−up resistance to VCC.
The VCC pin is monitored by an Undervoltage Lockout
Circuit (UVLO). VCC voltage above the rising threshold
enables the NCP302155A.
Table 7. Table 2. UVLO/DISB# LOGIC TABLE
UVLO
DISB#
Driver State
L
H
H
H
X
L
Disabled (GH = GL = 0)
Disabled (GH = GL = 0)
Enabled (See Table 1)
Disabled (GH = GL = 0)
H
Open
Thermal Warning/Thermal Shutdown Output
enables the low side synchronous MOSFET to operate
independently of the internal ZCD function. When the
SMOD# pin is set low during the PWM cycle it disables the
low side MOSFET to allow discontinuous mode operation.
The NCP302155A has the capability of internally
connecting a resistor divider to the PWM pin. To engage this
mode, SMOD# needs to be placed into mid−state. While in
SMOD# mid−state, the IC logic is equivalent to SMOD#
being in the high state.
The THWN pin is an open drain output. When the
temperature of the driver exceeds TTHWN, the THWN pin is
pulled low indicating a thermal warning. At this point, the
part continues to function normally. When the temperature
drops TTHWN_HYS below TTHWN, the THWN pin goes high. If
the driver temperature exceeds TTHDN, the part enters
thermal shutdown and turns off both MOSFETs. Once the
temperature falls TTHDN_HYS below TTHDN, the part resumes
normal operation.
Skip Mode Input (SMOD#)
The SMOD# tri−state input pin has an internal pull−up
resistance to VCC. When driven high, the SMOD# pin
NOTE: If the Zero Current Detect circuit detects zero current after the ZCD Wait timer period, the GL is driven low by
the Zero Current Detect signal.
If the Zero Current Detect circuit detects zero current before the ZCD Wait timer period expires, the Zero Current
detect signal is ignored and the GL is driven low at the end of the ZCD Wait timer period.
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge
triggers the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
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NCP302155A
Inductor
Current
PWM
GH
SMOD#
triggered
GL
SMOD#
Figure 15. SMOD# Timing Diagram
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge
triggers the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
For Use with Controllers with 3−State PWM and No
Zero Current Detection Capability:
Table 8. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH NO ZCD
PWM
SMOD#
GH (not a pin)
GL
OFF
ZCD
ON
H
M
L
H
H
H
ON
OFF
OFF
This section describes operation with controllers that are
capable of 3 states in their PWM output and relies on the
NCP302155A to conduct zero current detection during
discontinuous conduction mode (DCM).
The SMOD# pin needs to either be set to 5 V or left
disconnected. The NCP302155A has an internal pull−up
resistor that connects to VCC that sets SMOD# to the logic
high state if this pin is disconnected.
and low states. To enter into DCM, PWM needs to be
switched to the mid−state.
Whenever PWM transitions to mid−state, GH turns off
and GL turns on. GL stays on for the duration of the
de−bounce timer and ZCD blanking timers. Once these
timers expire, the NCP302155A monitors the SW voltage
and turns GL off when SW exceeds the ZCD threshold
voltage. By turning off the LS FET, the body diode of the LS
FET allows any positive current to go to zero but prevents
negative current from conducting.
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
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11
NCP302155A
Figure 16. Timing Diagram − 3−state PWM Controller, No ZCD
FOR USE WITH CONTROLLERS WITH 3−STATE
PWM CONTROLLERS DETECTION CAPABILITY:
Table 9. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH ZCD
PWM
SMOD#
GH (not a pin)
GL
OFF
OFF
ON
H
M
L
L
L
L
ON
OFF
OFF
This section describes operation with controllers that are
capable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
The SMOD# pin needs to be pulled low (below
and low states. During DCM, the controller is responsible
for detecting when zero current has occurred, and then
notifying the NCP302155A to turn off the LS FET. When the
controller detects zero current, it needs to set PWM to
mid−state, which causes the NCP302155A to pull both GH
and GL to their off states without delay.
V
).
SMOD#_LO
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
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12
NCP302155A
SMOD# = Low
SMOD# 0 V
IL 0 A
PWM
Controller detects zero current →
Sets
PWM to mid−state.
PWM in mid−state pulls GL
low.
GH
GL
Figure 17. Timing Diagram − 3−state PWM Controller, with ZCD
Figure 18. Top Copper Layer
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13
NCP302155A
Figure 19. Bottom Copper Layer
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14
NCP302155A
RECOMMENDED PCB FOOTPRINT
(Option 1)
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15
NCP302155A
RECOMMENDED PCB FOOTPRINT
(Option 2)
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN31 5X5, 0.5P
CASE 483BR
ISSUE D
DATE 13 FEB 2023
SCALE 2.5:1
MILLIMETERS
DIM
MIN.
0.70
0.00
0.15
0.20
0.13
4.90
3.70
0.75
1.88
1.22
0.45
NOM.
0.75
MAX.
0.80
0.05
0.25
0.30
0.30
5.10
3.90
0.95
2.08
1.42
0.65
A
A1
A3
b
−
0.20
0.25
b1
D
0.18
5.00
D2
D3
D4
D5
D6
D7
E
3.80
0.85
1.98
1.32
0.55
0.38 REF
5.00
4.90
1.82
0.93
0.93
0.93
0.20
5.10
2.02
1.13
1.13
1.13
0.40
E2
E3
E4
E5
E6
E7
e
1.92
1.03
1.03
1.03
0.30
0.22 REF
0.50 BSC
0.25 BSC
0.25 BSC
0.75 BSC
0.25 BSC
0.40 REF
0.45 REF
0.40 REF
0.30 REF
0.55 REF
0.50 REF
0.40 REF
0.40
e/2
e/3
e/4
e/5
k1
k2
k3
k4
k5
k6
k7
L
C.L.
C.L.
16 17 181920
2122
23
16 17 181920
2122
23
15
14
13
12
24
25
26
27
28
29
30
31
15
14
13
24
25
26
27
28
29
30
31
12
33
33
C.L.
C.L.
11
10
9
11
10
9
32
32
0.30
0.30
0.15
0.50
0.50
0.35
L1
L2
m
0.40
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0.25
0.15 REF
0.80 REF
2.28 REF
2.38 REF
0.80 REF
0.625 REF
n
p
q
r
z
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13680G
PQFN31 5X5, 0.5P
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN31 5X5, 0.5P
CASE 483BR
ISSUE D
DATE 13 FEB 2023
8
1
31
9
11
12
32
33
27
26
15
24
16
23
8
1
9
11
12
31
32
33
33
27
26
15
24
16
23
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
A
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
G
= Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13680G
PQFN31 5X5, 0.5P
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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