NCP302155RMNTWG [ONSEMI]
Integrated Driver and MOSFET;
| 型号： | NCP302155RMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | Integrated Driver and MOSFET |
| 文件： | 总16页 (文件大小：940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Integrated Driver and
MOSFET
NCP302155R
The NCP302155R integrates a MOSFET driver, high−side
MOSFET and low−side MOSFET into a single package.
PQFN31 5X5, 0.5P
CASE 483BR
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP302155R
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
MARKING DIAGRAM
Pin1
NCP
Features
302155R
AWLYYWW
• Capable of Average Currents up to 55 A
• Capable of Peak Currents up to 80 A
• Capable of Switching at Frequencies up to 2 MHz
• Compatible with 3.3 V or 5 V PWM Input
• Responds Properly to 3−level PWM Inputs
• Internal Bootstrap Diode
• Undervoltage Lockout
• Supports Intel® Power State 4
• Thermal Warning output
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PINOUT DIAGRAM
8
7
6
5
4
3
2
1
Applications
VIN
VIN
VIN
nc
• Desktop and All−in−One Computers, V−Core and Non−V−Core
DC−DC Converters
• High−Current DC−DC Point−of−Load Converters
• Small Form−Factor Voltage Regulator Modules
THWN
32
AGND
VCCD
PGND
GL
33
GL
PGND
PGND
PGND
PGND
VSW
VSW
VSW
16
17
18
19
20
21
22
23
ORDERING INFORMATION
†
Device
Package
Shipping
NCP302155RMNTWG PQFN31
3000 / Tape &
Reel
(Pb−Free)
Figure 1. Application Schematic
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
May, 2023 − Rev. 0
NCP302155R/D
NCP302155R
3.1 V
Figure 2. Block Diagram
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2
NCP302155R
Table 1. PIN LIST AND DESCRIPTION
Pin No.
Symbol
PWM
Description
1
2
PWM Control Input
Output disable pin.
DISB#
High = Enabled with normal PWM operation without ZCD. Connects PWM to internal resistor
divider placing a bias voltage on PWM pin.
Low = Driver is disabled and in a low power state.
There is an internal pull−down resistor to GND on this pin.
3
4, 32
5
VCC
CGND, AGND
BOOT
NC
Control Power Supply Input
Signal Ground (pin 4 and pad 32 are internally connected)
Bootstrap Voltage
6
Open pin (not used)
7
PHASE
VIN
Bootstrap Capacitor Return
8−11
12−15, 28
16−26
27, 33
29
Conversion Supply Power Input
Power Ground
PGND
VSW
Switch Node Output
GL
Low Side FET Gate Access (pin 27 and pad 33 are internally connected)
Driver Power Supply Input
VCCD
THWN
30
Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
reaches TTHWN, this pin is pulled low.
31
NC
Open pin (not used)
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3
NCP302155R
Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise)
Pin Name / Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−5
Max
6.5
30
Unit
V
VCC, VCCD
VIN
V
BOOT (DC)
30
V
BOOT (< 20 ns)
BOOT to PHASE (DC)
VSW, PHASE (DC)
VSW, PHASE (< 20 ns)
All Other Pins
35
V
6.5
30
V
V
36
V
−0.3
V
VCC
+ 0.3
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL INFORMATION
Rating
Symbol
Value
12.4
Unit
_C/W
_C/W
_C
q
JA
Thermal Resistance (under On Semi SPS Thermal Board)
q
1.8
J−PCB
Operating Junction Temperature Range (Note 1)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
T
J
−40 to +150
−40 to +125
−55 to +150
1
T
A
_C
T
STG
_C
MSL
1. The maximum package power dissipation must be observed.
2. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
3. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage Range
Conversion Voltage
Junction Temperature
Pin Name
VCC, VCCD
VIN
Conditions
Min
4.5
Typ
5.0
−
Max
5.5
20
Unit
V
4.5
V
−40
125
_C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCP302155R
Table 5. ELECTRICAL CHARACTERISTICS
(V
= V
= 5.0 V, V
= 12 V, V
= 2.0 V, C
= C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the
VCC
VCCD
VIN
DISB#
VCCD
VCC
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
VCC SUPPLY CURRENT
Operating
Symbol
Conditions
Min.
Typ.
Max.
Unit
DISB# = 5 V, PWM = 400 kHz
DISB# = 5 V, PWM = 0 V
DISB# = 0 V
−
−
1
−
2
2
mA
mA
mA
V
No switching
Disabled
−
0.4
−
1
UVLO Start Threshold
UVLO Hysteresis
V
VCC rising
3.65
400
4.1
−
UVLO
500
mV
VCCD SUPPLY CURRENT
Enabled, No switching
DISB# = 5 V, PWM = 0 V,
PHASED
−
175
300
mA
V
= 0 V
Disabled
DISB# = 0 V
−
−
0.4
1
mA
Operating
DISB# = 5 V, PWM = 400 kHz
−
30
mA
DISB# INPUT
Input Resistance
Upper Threshold
Lower Threshold
Hysteresis
To Ground
−
−
467
−
−
2.0
−
kW
V
V
V
UPPER
0.8
200
−
−
V
LOWER
V
− V
−
−
mV
ms
UPPER
LOWER
Enable Delay Time
Time from DISB# transitioning HI
to when VSW responds to PWM.
28
52
Disable Delay Time
Time from DISB# transitioning
LOW to when both output FETs
are off.
−
21
50
ns
PWM INPUT
Input Voltage High
V
V
V
2.95
1.25
−
−
−
−
V
V
PWM_HI
PWM_MID
PWM_LO
Input Mid−state Voltage
Input Low Voltage
2.3
0.7
20
2.3
−
−
V
Input Resistance
R
DISB# = 5 V
DISB# = 5 V
9.2
1.2
−
14.6
1.7
13
kW
V
PWM_BIAS
PWM_BIAS
NOL_L
PWM Input Bias Voltage
Non−overlap Delay, Leading Edge
V
T
T
GL Falling = 1 V to GH−VSW Ris-
ing = 1 V
ns
Non−overlap Delay, Trailing Edge
GH−VSW Falling = 1 V to
GL Rising = 1 V
−
12
−
ns
NOL_T
PWM Propagation Delay, Rising
PWM Propagation Delay, Falling
T
T
T
PWM = High to GL = 90%
PWM = Low to SW = 90%
PWM = Mid−to−Low to GL = 10%
−
−
−
13
50
14
35
65
25
ns
ns
ns
PWM,PD_R
PWM,PD_F
PWM_EXIT_L
Exiting PWM Mid−state Propagation
Delay, Mid−to−Low
THERMAL WARNING
Thermal Warning Temperature
Thermal Warning Hysteresis
THWM Open Drain Current
BOOT STRAP DIODE
Forward Voltage
T
T
Temperature at Driver Die
−
−
−
150
15
−
−
−
5
_C
_C
THWN
THWN_HYS
THWN
I
mA
Forward Bias Current = 2.0 mA
Source Current = 100 mA
−
−
380
0.9
−
−
mV
LOW−SIDE DRIVER
Output Impedance, Sourcing
R
W
SOURCE_GL
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NCP302155R
Table 5. ELECTRICAL CHARACTERISTICS
(V
= V
= 5.0 V, V
= 12 V, V
= 2.0 V, C
= C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the
VCC
VCCD
VIN
DISB#
VCCD
VCC
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
LOW−SIDE DRIVER
Symbol
Conditions
Min.
Typ.
Max.
Unit
Output Impedance, Sinking
GL Rise Time
R
Sink Current = 100 mA
GL = 10% to 90%
GL = 90% to 10%
−
−
−
0.4
12
6
−
−
−
W
ns
ns
SINK_GL
T
T
R_GL
GL Fall Time
F_GL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 6. LOGIC TABLE
DISB#
PWM
X
GH (not a pin)
GL
L
L
H
H
H
L
H
L
H
L
L
H
L
MID
L
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NCP302155R
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V =12 V, V =PV =5 V, V
=1 V, L
=250 nH, T =25°C and natural convection cooling, unless otherwise noted)
IN
CC
CC
OUT
OUT
A
Figure 3. Safe Operating Area with 12 VIN
Figure 4. Safe Operating Area with 16 VIN
Figure 5. Power Loss vs. Output Current with 12
VIN
Figure 6. Power Loss vs. Output Current with 19
VIN
Figure 7. Power Loss vs. Switching Frequency
Figure 8. Power Loss vs. Input Voltage
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NCP302155R
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V =12 V, V =PV =5 V, V
=1 V, L
=250 nH, T =25°C and natural convection cooling, unless otherwise noted)
IN
CC
CC
OUT
OUT
A
Figure 9. Power Loss vs. Driver Supply Voltage
Figure 10. Power Loss vs. Output Voltage
Figure 11. Power Loss vs. Output Inductor
Figure 12. Driver Supply Current vs. Switching
Frequency
Figure 13. Driver Supply Current vs. Driver Supply
Voltage
Figure 14. Driver Supply Current vs. Output
Current
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NCP302155R
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V =12 V, V =PV =5 V, V
=1 V, L
=250 nH, T =25°C and natural convection cooling, unless otherwise noted)
IN
CC
CC
OUT
OUT
A
Figure 15. UVLO Threshold vs. Temperature
Figure 16. PWM Threshold vs. Driver Supply
Voltage
Figure 17. PWM Threshold vs. Temperature
Figure 18. Body Diode Forward Voltage vs.
Temperature
Figure 19. Driver Shutdown vs. Temperature
Figure 20. Driver Quiescent Current vs. Temperature
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NCP302155R
Theory of Operation
Safety Timer and Overlap Protection Circuit
The NCP302155R is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. The NCP302155R supports PWM Tristate
control. A PWM input signal is required to control the drive
signals to the high−side and low−side integrated MOSFETs.
It is important to avoid cross−conduction of the two
MOSFETS which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP302155R prevents cross−conduction by
monitoring the status of the MOSFETs and applying the
appropriate amount of non−overlap (NOL) time (the time
between the turn−off of one MOSFET and the turn−on of the
other MOSFET). When the PWM input pin is driven high,
the gate of the low−side MOSFET (LSGATE) goes low after
a propagation delay (tpdlGL). The time it takes for the
low−side MOSFET to turn off is dependent on the total
charge on the low−side MOSFET gate.
Low−Side Driver
The
low−side
driver
drives
an
internal,
ground−referenced low−RDS(on) N−Channel MOSFET.
The voltage supply for the low−side driver is internally
connected to the VCCD and PGND pins.
High−Side Driver
The NCP302155R monitors the gate voltage of both
MOSFETs and the switch node voltage to determine the
conduction status of the MOSFETs. Once the low−side
MOSFET is turned off an internal timer delays (tpdhGH) the
turn−on of the high−side MOSFET. When the PWM input
pin goes low, the gate of the high−side MOSFET (HSGATE)
goes low after the propagation delay (tpdlGH). The time to
turn off the high−side MOSFET (tfGH) is dependent on the
total gate charge of the high−side MOSFET. A timer is
triggered once the high−side MOSFET stops conducting, to
delay (tpdhGL) the turn−on of the low−side MOSFET.
The high−side driver drives an internal, floating
low−RDS(on) N−channel MOSFET. The gate voltage for the
high side driver is developed by a bootstrap circuit
referenced to Switch Node (VSW and PHASE) pins.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor and resistor. When the
NCP302155R is starting up, the VSW pin is at ground,
allowing the bootstrap capacitor to charge up to VCCD
through the bootstrap diode (See Figure 1). When the PWM
input is driven high, the high−side driver turns on the
high−side MOSFET using the stored charge of the bootstrap
capacitor. As the high−side MOSFET turns on, the voltage
at the VSW and PHASE pins rises. When the high−side
MOSFET is fully turned on, the switch node settles to VIN
and the BST pin settles to VIN + VCCD (excluding parasitic
ringing).
PWM Input
The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. It also determines the state of
the LS MOSFET. See Table 6 for logic operation.
When DISB# is high the PWM pin undriven default
voltage is set to Mid−State with internal divider resistances.
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (CBST) and an integrated diode to provide current
to the HS Driver. A multi−layer ceramic capacitor (MLCC)
with a value greater than 100 nF should be used as the
bootstrap capacitor. An optional 1 to 4 W resistor in series
with the bootstrap capacitor decreases the VSW overshoot.
The boot resistor is strongly recommended when VIN is
higher than 15 V.
Disable Input (DISB#)
The DISB# pin is used to disable the GH to the High−Side
FET to prevent power transfer when set to low. The pin has
a pull−down resistance to force a disabled state when it is left
unconnected. When DISB# is set to high it enables normal
PWM operation without ZCD. DISB# can be driven from
the output of a logic device or set high with a pull−up
resistance to VCC.
Power Supply Decoupling
VCC Undervoltage Lockout
The NCP302155R sources relatively large currents into
the MOSFET gates. In order to maintain a constant and
stable supply voltage (VCCD) a low−ESR capacitor should
be placed near the power and ground pins. A multi−layer
ceramic capacitor (MLCC) between 1 mF and 4.7 mF is
typically used.
A separate supply pin (VCC) is used to power the analog
and digital circuits within the driver. A 1 mF ceramic
capacitor should be placed on this pin in close proximity to
the NCP302155R. It is good practice to separate the VCC
and VCCD decoupling capacitors with a resistor (10 W
typical) to avoid coupling driver noise to the analog and
digital circuits that control the driver function (See
Figure 1).
The VCC pin is monitored by an Undervoltage Lockout
Circuit (UVLO). VCC voltage above the rising threshold
enables the NCP302155R.
Table 7. UVLO/DISB# LOGIC TABLE
UVLO
DISB#
Driver State
L
H
H
H
X
L
Disabled (GH = GL = 0)
Disabled (GH = GL = 0)
Enabled (See Table 1)
Disabled (GH = GL = 0)
H
Open
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NCP302155R
Thermal Warning
The THWN pin is an open drain output. When the
temperature of the driver exceeds TTHWN, the THWN pin is
pulled low indicating a thermal warning. At this point, the
part continues to function normally. When the temperature
drops TTHWN_HYS below TTHWN, the THWN pin goes high.
FOR USE WITH CONTROLLERS WITH 3−STATE
PWM CONTROLLERS DETECTION CAPABILITY:
Table 8. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH ZCD
PWM
DISB#
GH (not a pin)
GL
OFF
OFF
ON
H
M
L
H
H
H
ON
OFF
OFF
This section describes operation with controllers that are
capable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
and low states. During DCM, the controller is responsible
for detecting when zero current has occurred, and then
notifying the NCP302155R to turn off the LS FET. When the
controller detects zero current, it needs to set PWM to
mid−state, which causes the NCP302155R to pull both GH
and GL to their off states without delay.
IL 0 A
PWM
Controller detects zero current →
Sets
PWM to mid−state.
PWM in mid−state pulls GL
low.
GH
GL
Figure 21. Timing Diagram − 3−state PWM Controller, with ZCD
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NCP302155R
Figure 22. Top Copper Layer
Figure 23. Bottom Copper Layer
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12
NCP302155R
RECOMMENDED PCB FOOTPRINT
(Option 1)
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13
NCP302155R
RECOMMENDED PCB FOOTPRINT
(Option 2)
Intel is a registered trademark of Intel Corporation in the U.S. And/or other countries.
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14
NCP302155R
PACKAGE DIMENSIONS
PQFN31 5X5, 0.5P
CASE 483BR
ISSUE C
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15
NCP302155R
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
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Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
onsemi Website: www.onsemi.com
◊
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