NCP3063BDR2G [ONSEMI]
1.5 A, Step−Up/Down/Inverting Switching Regulators; 1.5 A ，步上/下/反相开关稳压器
| 型号： | NCP3063BDR2G |
| 厂家： | 
ONSEMI |
| 描述： | 1.5 A, Step−Up/Down/Inverting Switching Regulators |
| 文件： | 总16页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP3063, NCP3063B,
NCV3063
1.5 A, Step−Up/Down/
Inverting Switching
Regulators
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MARKING
The NCP3063 Series is a higher frequency upgrade to the popular
MC34063A and MC33063A monolithic DC−DC converters. These
devices consist of an internal temperature compensated reference,
comparator, a controlled duty cycle oscillator with an active current
limit circuit, a driver and a high current output switch. This series was
specifically designed to be incorporated in Step−Down, Step−Up and
Voltage−Inverting applications with a minimum number of external
components.
DIAGRAMS
3063x
ALYW
G
8
1
1
Features
SOIC−8
D SUFFIX
CASE 751
• Operation to 40 V Input
V3063
ALYW
G
• Low Standby Current
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation of 150 kHz
• Precision 1.5% Reference
1
NCP3063x
AWL
• New Features: Internal Thermal Shutdown with Hysteresis
New Features: Cycle−by−Cycle Current Limiting
• Pb−Free Packages are Available
YYWWG
1
8
1
Applications
NCV3063
AWL
YYWWG
PDIP−8
P, P1 SUFFIX
CASE 626
• Step−Down, Step−Up and Inverting supply applications
• High Power LED Lighting
• Battery Chargers
1
8
8
1
NCP3063
SET dominant
TSD
1
R
S
3063y
ALYW G
DFN−8
SUFFIX
CASE 488
Q
7
COMPARATOR
−
+
S
2
3
SET dominant
Q
Rs
NCP3063x = Specific Device Code
x = B
R
0.15 W
D
OSCILLATOR
CT
0.2 V
A
=
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
Pb−Free Package
6
V
in
L, WL
Y, YY
W, WW
G
L
47 mH
12 V
+
CT
2.2 nF
COMPARATOR
C
1.25 V
REFERENCE
REGULATOR
in
+
−
220 mF
V
5
out
3.3 V /
4
(Note: Microdot may be in either location)
800 mA
3.9 kW
R2
+
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
R1
2.4 kW
470 mF
C
out
Figure 1. Typical Buck Application Circuit
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 1
NCP3063/D
NCP3063, NCP3063B, NCV3063
PIN CONNECTIONS
1
Switch Collector
Switch Emitter
8
7
N.C.
Sense
I
2
3
4
pk
Timing Capacitor
GND
6
5
V
CC
Comparator
Inverting
Input
(Top View)
NCP3063
8
1
TSD
N.C.
Switch Collector
SET dominant
R
Q
S
COMPARATOR
7
−
+
2
3
I
Sense
pk
S
Q
R
Switch Emitter
SET dominant
0.2 V
OSCILLATOR
CT
6
5
Timing Capacitor
+V
CC
COMPARATOR
1.25 V
REFERENCE
REGULATOR
+
−
4
GND
Comparator Inverting Input
Figure 2. Block Diagram
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2
NCP3063, NCP3063B, NCV3063
PIN DESCRIPTION
Pin No.
Pin Name
Description
Internal Darlington switch collector
1
2
3
4
5
Switch Collector
Switch Emitter
Timing Capacitor
GND
Internal Darlington switch emitter
Timing Capacitor to control the switching frequency
Ground pin for all internal circuits
Comparator
Inverting input pin of internal comparator
Inverting Input
6
7
V
Voltage supply
CC
I
Sense
Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak
current through the circuit
pk
8
N.C.
Pin not connected
MAXIMUM RATINGS (measured vs. pin 4, unless otherwise noted)
Rating
Symbol
Value
Unit
V
pin 6
V
0 to +40
V
V
CC
CC
Comparator Inverting Input pin 5
V
− 0.2 to + V
CII
CC
CC
Darlington Switch Collector pin 1
V
SWC
V
SWE
0 to +40
− 0.6 to + V
0 to +40
1.5
V
V
V
A
V
Darlington Switch Emitter pin 2 (transistor OFF)
Darlington Switch Collector to Emitter pin 1−2
Darlington Switch Current
V
SWCE
I
SW
I
Sense pin 7
V
− 0.2 to V + 0.2
pk
IPK
CC
Power Dissipation and Thermal Characteristics
PDIP−8
°C/W
°C/W
Thermal Resistance Junction−to−Air
R
100
q
q
JA
SOIC−8
Thermal Resistance Junction−to−Air
R
T
180
−65 to +150
+150
JA
Storage Temperature Range
°C
°C
°C
STG
Maximum Junction Temperature
T
J MAX
Operating Junction Temperature Range (Note 3)
NCP3063
T
J
0 to +70
NCP3063B, NCV3063
−40 to +125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115
Machine Model Method 200 V
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is T = T + R
4. The pins which are not defined may not be loaded by external signals
P
D
q •
J
A
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NCP3063, NCP3063B, NCV3063
ELECTRICAL CHARACTERISTICS (V = 5.0 V, T = T to T [Note 5], unless otherwise specified)
high
CC
J
low
Symbol
Characteristic
Conditions
Min
Typ
Max
Unit
OSCILLATOR
f
Frequency
(VPin 5 = 0 V, CT = 2.2 nF,
110
5.5
150
6.0
190
6.5
kHz
−
OSC
T = 25°C)
J
I
/
Discharge to Charge Current Ratio
(Pin 7 to V , T = 25°C)
DISCHG
CC
J
I
CHG
V
Current Limit Sense Voltage
(TJ = 25°C) (Note 6)
165
200
235
mV
IPK(Sense)
OUTPUT SWITCH (Note 7)
V
Darlington Switch Collector to
Emitter Voltage Drop
(I
= 1.0 A, Pin 2 to GND,
SW
T = 25°C) (Note 7)
J
1.0
1.3
V
SWCE(DROP)
I
Collector Off−State Current
(V = 40 V)
CE
0.01
100
mA
C(OFF)
COMPARATOR
V
Threshold Voltage
T = 25°C
1.250
V
%
TH
J
NCP3063
−1.5
−2
+1.5
+2
NCP3063B, NCV3063
%
REG
Threshold Voltage Line Regulation
Input Bias Current
(V = 5.0 V to 40 V)
−6.0
−1000
2.0
6.0
mV
nA
LiNE
CC
I
(V = V )
−100
1000
CII in
in
th
TOTAL DEVICE
I
Supply Current
(V = 5.0 V to 40 V,
7.0
mA
CC
CC
CT = 2.2 nF, Pin 7 = V
,
CC
VPin 5 > V , Pin 2 = GND,
th
remaining pins open)
Thermal Shutdown Threshold
Hysteresis
160
10
°C
°C
5. NCP3063: T
= 0°C, T
= +70°C;
high
low
low
NCP3063B, NCV3063: T = −40°C, T
= +125°C
high
6. TheVIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn−off value depends
on comparator response time and di/dt current slope. See the Operating Description section for details.
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
8. NCV prefix is for automotive and other applications requiring site and change control.
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NCP3063, NCP3063B, NCV3063
200
180
160
140
190
180
170
160
150
140
130
C
= 2.2 nF
T
T = 25°C
J
120
100
80
60
40
20
0
120
110
0 1 2 3 4 5 6 7 8 9 1011 12 1314 15 16 1718 19 20
Ct, CAPACITANCE (nF)
3
7
12
16
21
25
29
34
38 40
V
, SUPPLY VOLTAGE (V)
CC
Figure 3. Oscillator Frequency vs. Oscillator
Timing Capacitor
Figure 4. Oscillator Frequency vs. Supply
Voltage
2.4
2.2
2.0
1.8
1.25
1.20
1.15
1.10
V
= 5.0 V
= 1 A
CC
V
= 5.0 V
= 1 A
CC
I
E
I
C
1.6
1.4
1.05
1.0
1.2
1.0
−50
0
50
100
150
−50
0
50
100
150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Emitter Follower Configuration Output
Darlington Switch Voltage Drop vs. Temperature
Figure 6. Common Emitter Configuration Output
Darlington Switch Voltage Drop vs. Temperature
2.0
1.9
1.5
1.4
V
= 5.0 V
V
= 5.0 V
CC
CC
T = 25°C
J
T = 25°C
J
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.6
0.5
0
0.5
1.0
1.5
0
0.5
1.0
1.5
I , EMITTER CURRENT (A)
E
I , COLLECTOR CURRENT (A)
C
Figure 7. Emitter Follower Configuration Output
Darlington Switch Voltage Drop vs. Emitter Current
Figure 8. Common Emitter Configuration
Output Darlington Switch Voltage Drop vs.
Collector Current
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NCP3063, NCP3063B, NCV3063
1.30
1.28
1.26
1.24
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
1.22
1.20
0.12
0.10
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Comparator Threshold Voltage vs.
Temperature
Figure 10. Current Limit Sense Voltage vs.
Temperature
6.0
5.5
5.0
4.5
4.0
3.5
3.0
C
T
= 2.2 nF
Pin 5, 7 = V
CC
2.5
2.0
Pin 2 = GND
33 38
3.0 8.0
13
V
18
23
28
43
, SUPPLY VOLTAGE (V)
CC
Figure 11. Standby Supply Current vs. Supply Voltage
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NCP3063, NCP3063B, NCV3063
INTRODUCTION
The NCP3063 is a monolithic power switching regulator
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the output switch next cycle turning on is inhibited. The
feedback comparator will enable the switching immediately
when the load current causes the output voltage to fall below
nominal. Under these conditions, output switch conduction
can be enabled for a partial oscillator cycle, a partial cycle
plus a complete cycle, multiple cycles, or a partial cycle plus
multiple cycles. (See AN920/D for more information).
optimized for dc to dc converter applications. The
combination of its features enables the system designer to
directly implement step−up, step−down, and voltage−
inverting converters with a minimum number of external
components. Potential applications include cost sensitive
consumer products as well as equipment for industrial
markets. A representative block diagram is shown in
Figure 2.
Operating Description
Oscillator
The NCP3063 is a hysteric, dc−dc converter that uses a
gated oscillator to regulate output voltage. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 12. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
The oscillator frequency and off−time of the output switch
are programmed by the value selected for timing capacitor
C . Capacitor C is charged and discharged by a 1 to 6 ratio
T
T
internal current source and sink, generating a positive going
sawtooth waveform at Pin 3. The oscillator peak and valley
voltage difference is 500 mV typically. To calculate the C
T
capacitor value for required oscillator frequency, use the
equations found in Figure 13. An Excel based design tool
can be found at www.onsemi.com on the NCP3063 product
page.
1
Feedback Comparator Output
0
1
I
Comparator Output
PK
0
Timing Capacitor, C
T
On
Off
Output Switch
Nominal Output Voltage Level
Output Voltage
Startup
Operation
Figure 12. Typical Operating Waveforms
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NCP3063, NCP3063B, NCV3063
Peak Current Sense Comparator
With a voltage ripple gated converter operating under
normal conditions, output switch conduction is initiated by
the Voltage Feedback comparator and terminated by the
oscillator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
Real V
on Rsc resistor
turn−off
V
+ V ) Rs @ (t_delay @ dińdt)
ipk(sense)
turn_off
Typical I comparator response time t_delay is 350 ns.
pk
The di/dt current slope is growing with voltage difference on
the inductor pins and with decreasing inductor value.
It is recommended to check the real max peak current in
the application at worst conditions to be sure that the max
peak current will never get over the 1.5 A Darlington Switch
Current max rating.
sensing is lost. Under these conditions, the I Current Sense
pk
comparator will protect the Darlington output Switch. The
switch current is converted to a voltage by inserting a
fractional ohm resistor, R , in series with V and the
SC
CC
Darlington output switch. The voltage drop across R is
SC
monitored by the Current Sense comparator. If the voltage
Thermal Shutdown
drop exceeds 200 mV with respect to V , the comparator
CC
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 160°C, the Output
Switch is disabled. The temperature sensing circuit is
designed with 10°C hysteresis. The Switch is enabled again
when the chip temperature decreases to at least 150°C
threshold. This feature is provided to prevent
catastrophic failures from accidental device
overheating. It is not intended to be used as a
replacement for proper heatsinking.
will set the latch and terminate output switch conduction on
a
cycle−by−cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on−time during a given oscillator cycle.
Real
on
I1
V
turn−off
Rs Resistor
I through the
Darlington
Switch
di/dt slope
Io
V
Output Switch
ipk(sense)
t_delay
The output switch is designed in a Darlington
configuration. This allows the application designer to
operate at all conditions at high switching speed and low
voltage drop. The Darlington Output Switch is designed to
switch a maximum of 40 V collector to emitter voltage and
current up to 1.5 A.
The V
Current Limit Sense Voltage threshold is
IPK(Sense)
specified at static conditions. In dynamic operation the
sensed current turn−off value depends on comparator
response time and di/dt current slope.
APPLICATIONS
Figures 14 through 22 show the simplicity and flexibility
of the NCP3063. Three main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams.
Figure 13 gives the relevant design equations for the key
parameters. Additionally, a complete application design aid
for the NCP3063 can be found at www.onsemi.com.
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NCP3063, NCP3063B, NCV3063
(See Notes 9, 10, 11)
Step−Down
Step−Up
Voltage−Inverting
|V | ) V
t
V
out
) V
V
out
) V * V
in
out
F
on
F
F
t
V
in
* V
* V
V
* V
V
in
* V
off
SWCE
out
in
SWCE
SWCE
t
t
t
t
t
t
on
off
on
off
on
off
ton
t
t
t
on
t
on
on
f ǒ ) 1Ǔ
f ǒ ) 1Ǔ
f ǒ ) 1Ǔ
off
t
t
off
off
381.6 @ 10*6
CT
C
T
+
* 343 @ 10*12
f
osc
IL(avg)
t
t
I
on
on
out
out ǒ ) 1Ǔ
out ǒ ) 1Ǔ
I
I
t
t
off
off
Ipk (Switch)
RSC
DI
2
DI
2
DI
2
L
L
L
I
)
I
)
I
)
L(avg)
L(avg)
L(avg)
0.20
pk (Switch)
0.20
0.20
I
I
I
pk (Switch)
pk (Switch)
L
V
in
* V
DI
V
in
* V
DI
V
in
* V
* V
out
SWCE
L
SWCE
L
SWCE
ǒ
Ǔt
ǒ
Ǔt
ǒ
Ǔt
on
on
on
DI
L
Vripple(pp)
2
t
I
t
I
on out
on out
C
1
8 f C
) (ESR)2
L
[
) DI @ ESR
[
) DI @ ESR
L
DI Ǹǒ Ǔ
L
C
O
O
O
Vout
R
2
R
2
R
2
THǒ ) 1Ǔ
THǒ ) 1Ǔ
THǒ ) 1Ǔ
V
R
1
V
V
R
1
R
1
The Following Converter Characteristics Must Be Chosen:
V − Nominal operating input voltage.
in
V
− Desired output voltage.
− Desired output current.
out
I
out
DI − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DI be chosen to be
L
L
less than 10% of the average inductor current I
. This will help prevent I
from reaching the current limit threshold
L(avg)
pk (Switch)
set by R . If the design goal is to use a minimum inductance value, let DI = 2(I ). This will proportionally reduce
SC
L
L(avg)
converter output current capability.
f − Maximum output switch frequency.
V
− Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low
ripple(pp)
value since it will directly affect line and load regulation. Capacitor C should be a low equivalent series resistance (ESR)
O
electrolytic designed for switching regulator applications.
9. V
− Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 5, 6, 7 and 8.
SWCE
10.V − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
F
11. The calculated t /t must not exceed the minimum guaranteed oscillator charge to discharge ratio.
on off
Figure 13. Design Equations
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NCP3063, NCP3063B, NCV3063
U201
N.C. SWC
R201
0R15
8
7
6
5
1
2
3
4
+V
= +3.3 V / 800 mA
OUT
L201 47 mH
+V = +12 V
SWE
I
1
IN
PK
TCAP
1
V
J203
CC
C206
0.1 mF
D201
+
C203
COMP GND
NCP3063
J201
C205
470 mF / 25 V
+
2.2 nF
1N5819
J204
1
C201
0.1 mF
C202
220 mF / 50 V
GND
J202
1
R203
3K9 1%
GND
R202
2K4 1%
Figure 14. Typical Buck Application Schematic
Value of Components
Name
L201
D201
C202
C205
C203
Value
Name
R201
R202
R203
C201
C202
Value
47 mH, I > 1.5 A
150 mW, 0.5 W
sat
1 A, 40 V Schottky Rectifier
220 mF, 50 V, Low ESR
470 mF, 25 V, Low ESR
2.2 nF Ceramic Capacitor
2.40 kW
3.90 kW
100 nF Ceramic Capacitor
100 nF Ceramic Capacitor
Test Results
Test
Condition
= 9 V to 12 V, I = 800 mA
Results
Line Regulation
Load Regulation
Output Ripple
V
in
V
in
V
in
V
in
V
in
8 mV
9 mV
o
= 12 V, I = 80 mA to 800 mA
o
= 12 V, I = 40 mA to 800 mA
≤ 85 mV
o
pp
Efficiency
= 12 V, I = 400 mA to 800 mA
> 73%
1.25 A
o
Short Circuit Current
= 12 V, R
= 0.15 W
load
76
74
72
70
68
66
64
0.1 0.2 0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (Adc)
0.8 0.9
1.0
Figure 16. Efficiency vs. Output Current for the Buck
Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C
Figure 15. Buck Demoboard Layout
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NCP3063, NCP3063B, NCV3063
L101
100 mH
U101
N.C. SWC
+V
= +24 V / 350 mA
OUT
R101
0R15
D101
1N5819
8
7
6
5
1
2
3
4
1
+V = +12 V
SWE
I
J103
IN
PK
+
TCAP
1
V
CC
C106
0.1 mF
C105
330 mF / 50 V
C103
2.2 nF
COMP GND
NCP3063
J101
+
J104
1
C101
0.1 mF
C102
470 mF / 25 V
GND
J102
1
R103
18K0 1%
GND
R102
1K0 1%
Figure 17. Typical Boost Application Schematic
Value of Components
Name
L101
D101
C102
C105
C103
Value
Name
R101
R102
R103
C101
C106
Value
100 mH, I > 1.5 A
150 mW, 0.5 W
sat
1 A, 40 V Schottky Rectifier
470 mF, 25 V, Low ESR
330 mF, 50 V, Low ESR
2.2 nF Ceramic Capacitor
1.00 kW
18.00 kW
100 nF Ceramic Capacitor
100 nF Ceramic Capacitor
Test Results
Test
Condition
= 9 V to 15 V, I = 250 mA
Results
Line Regulation
Load Regulation
Output Ripple
Efficiency
V
in
V
in
V
in
V
in
2 mV
5 mV
o
= 12 V, I = 30 mA to 350 mA
o
= 12 V, I = 10 mA to 350 mA
≤ 350 mV
o
pp
= 12 V, I = 50 mA to 350 mA
> 85.5%
o
90
89
88
87
86
85
84
83
82
81
80
0
0.05
0.1
0.15
0.2
0.25 0.3
0.35 0.4
OUTPUT LOAD (Adc)
Figure 19. Efficiency vs. Output Current for the Boost
Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C
Figure 18. Boost Demoboard Layout
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NCP3063, NCP3063B, NCV3063
U501
N.C. SWC
R501
0R15
8
7
6
5
1
2
3
4
+V = +5 V
SWE
I
IN
PK
TCAP
1
V
CC
L501
C503
COMP GND
NCP3063
J501
D501
1N5819
+
22 mH
2.2 nF
C501
0.1 mF
C502
330 mF / 25 V
V
= −12 V / 100 mA
OUT
J502
1
R503
1
J503
C506
1K96 1%
GND
C505
R502
16K9 1%
+
470 mF / 35 V
0.1 mF
J504
1
GND
Figure 20. Typical Voltage Inverting Application Schematic
Value of Components
Name
L501
D501
C502
C505
C503
Value
Name
R501
R502
R503
C501
C506
Value
22 mH, I > 1.5 A
150 mW, 0.5 W
16.9 kW
sat
1 A, 40 V Schottky Rectifier
330 mF, 25 V, Low ESR
470 mF, 35 V, Low ESR
2.2 nF Ceramic Capacitor
1.96 kW
100 nF Ceramic Capacitor
100 nF Ceramic Capacitor
Test Results
Test
Condition
= 4.5 V to 6 V, I = 50 mA
Results
Line Regulation
Load Regulation
Output Ripple
V
in
V
in
V
in
V
in
V
in
1.5 mV
1.6 mV
o
= 5 V, I = 10 mA to 100 mA
o
= 5 V, I = 0 mA to 100 mA
≤ 300 mV
o
pp
Efficiency
= 5 V, I = 100 mA
49.8%
o
Short Circuit Current
= 5 V, R
= 0.15 W
0.885 A
load
52
50
48
46
44
42
40
38
36
0
20
40
60
80
100
OUTPUT LOAD (mA
)
dc
Figure 22. Efficiency vs. Output Current for the
Voltage Inverting Demo Board at Vin = +5 V,
Vout = −12 V, TA = 255C
Figure 21. Voltage Inverting Demoboard Layout
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12
NCP3063, NCP3063B, NCV3063
ORDERING INFORMATION
Device
†
Package
Shipping
NCP3063PG
PDIP−8
(Pb−Free)
50 Units / Rail
50 Units / Rail
NCP3063BPG
NCP3063DR2G
NCP3063BDR2G
NCP3063
PDIP−8
(Pb−Free)
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
TBD
SOIC−8
(Pb−Free)
DFN−8
(Pb−Free)
NCV3063PG
PDIP−8
(Pb−Free)
50 Units / Rail
NCV3063DR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV prefix is for automotive and other applications requiring site and change control.
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13
NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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14
NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
8
5
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
MILLIMETERS
DIM MIN MAX
INCHES
MIN
1
4
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
10.16 0.370
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27 0.030
0.30 0.008
0.050
0.012
0.135
K
L
3.43
0.115
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
−−−
1.01 0.030
10
0.040
_
_
J
−T−
SEATING
PLANE
STYLE 1:
N
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
M
D
K
G
H
5. GROUND
6. OUTPUT
7. AUXILIARY
M
M
M
B
0.13 (0.005)
T A
8. V
CC
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15
NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
8 PIN DFN, 4x4
CASE 488AF−01
ISSUE B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
D
8X L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
8X K
PIN ONE
IDENTIFICATION
1
8
D2
E
MILLIMETERS
4
5
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
2X
0.15
C
A
b 8X NOTE 3
E2
e
A3
b
0.20 REF
0.25
0.10
0.05
C
A B
TOP VIEW
0.35
2X
0.15
C
D
4.00 BSC
C
BOTTOM VIEW
D2 1.91
2.21
E
4.00 BSC
E2 2.09
2.39
e
K
L
0.80 BSC
0.20
0.30
−−−
0.50
0.10
0.08
C
C
A
8X
(A3)
A1
SEATING
PLANE
C
SIDE VIEW
SOLDERING FOOTPRINT*
4.30
8X
2.21
2.39
0.63
1
0.40
0.80
PITCH
8X
0.35
DIMENSIONS: MILLIMETERS
2.75
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
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NCP3063/D
相关型号：
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