NCP3136MNTXG [ONSEMI]
集成式同步 DC-DC 步降转换器，2.9 V - 5.5 V，5 A;
| 型号： | NCP3136MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | 集成式同步 DC-DC 步降转换器，2.9 V - 5.5 V，5 A 开关 转换器 |
| 文件： | 总11页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP3136
Integrated Synchronous
Buck Converter
6 A
NCP3136 is a fully integrated synchronous buck converter for 3.3 V
and 5 V step−down applications. It can provide up to 6.5 A
instantaneous current. NCP3136 supports high efficiency, fast
transient response and provides power good indicator. The control
scheme includes two operation modes: FCCM and automatic
CCM/DCM. In automatic CCM/DCM mode, the controller can
smoothly switch between CCM and DCM, where converter runs at
reduced switching frequency with much higher efficiency. NCP3136
is available in 3 mm x 3 mm QFN16 pin package.
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MARKING
DIAGRAM
1
3136
ALYWG
G
QFN16
CASE 485DA
Features
3136
A
L
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
• High Efficiency in Both CCM and DCM
• Operation Frequency: 1.1 MHz
Y
W
G
• Support MLCC Output Capacitor
• Small Footprint, 3 mm x 3 mm, 16−pin QFN Package
• 2.9 V to 5.5 V Wide Conversion Voltage Range
= Pb−Free Package
(Note: Microdot may be in either location)
• Output Voltage Range from 0.6 V to 0.84 X V
IN
PINOUT DIAGRAM
• Automatic Power−Saving Mode
• Voltage Mode Control
• Support Pre−bias Start−up Functionality
• Output Discharge Operation
16
15
14
13
EN
NC
VDD
AGND
FB
1
2
3
4
12
11
10
9
• Over−Temperature Protection
• Built−in Over−Voltage, Under−Voltage and Over−Current Protection
• Power Good Indicator
NCP3136
PGD
VBST
• This Device is Pb−Free and is RoHS Compliant
COMP
Applications
5
6
7
8
• 5 V Step Down Rail
• 3.3 V Step Down Rail
ORDERING INFORMATION
†
Device
NCP3136MNTXG
Package
Shipping
QFN16
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2019 − Rev. 3
NCP3136/D
NCP3136
VIN
BST
UVLO
NC
OSC
Ramp
Control Logic
DRVH
DRVL
&
Mode
PS
EN
PWM Logic
Selection
SS
SWN
COMP
VREF
+
+ E/A
Power Good
−
FB
PGND
VDD
UVP, OVP, UVLO,
Overtemperature
and Vout discharge
OCP
PGD
AGND
Figure 1. Block Diagram
PIN DESCRIPTION
Pin No.
Symbol
EN
Description
1
Logic control to enabling the switcher. Internally pulled up to VDD with a 1.35 MW resistor.
Not connected.
2
3
NC
PGD
BST
SWN
PS
Open drain power good output.
4
Gate drive voltage for high side FET. Connect capacitor from this pin to SWN.
Switch node between high−side MOSFET and low−side MOSFET.
5,6,7
8
Mode configuration pin:
Connecting to ground: Forced CCM
Pulled high or floating (internal pulled high): Forced CCM
Connect with 24.3 kW to GND: Automatic CCM/DCM
Connect with 57.6 kW to GND: Automatic CCM/DCM
Connect with 105 kW to GND: Automatic CCM/DCM
Connect with 174 kW to GND: Automatic CCM/DCM
9
10
COMP
FB
Output of the error amplifier.
Feedback pin. Connect to resistor divider to set up the desired output voltage.
Analog ground
11
AGND
VDD
VIN
12
Power supply input for control circuitry.
Power input for power conversion and gate driver supply.
Power ground
13,14
15,16
PGND
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2
NCP3136
L1
Vin=2.9V~5.5V
C5
C6
C4
C7
C9
13
VIN
14
5
6
7
Vin
VIN SW SW SW
12 VDD
R7
C8
R5
VBST 4
11 AGND
NCP3136
2
1
8
NC
EN
PS
PGD
FB 10
COMP
3
PGD
R3
C1
R1
EN
Vout
C2
R4
9
PGND
15
PGND
16
R2
C3
Figure 2. Application Circuit
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3
NCP3136
ABSOLUTE MAXIMUM RATINGS
Value
Min
−0.3
−0.3
−0.3
−0.3
−1
Max
6.5
17
Parameter
Condition
Unit
Input Voltage Range
VIN, PS
VBST
V
VBST (with respect to SW)
EN, FB
6.5
VDD + 0.3
6.5
Output Voltage Range
SW
DC
Pulse < 20 ns, E = 5 mJ
PGD
V
−3
10
−0.3
−0.3
−0.3
−40
−55
−40
6.5
COMP
VDD + 0.3
0.3
PGND
Operation ambient temperature
Storage temperature
T
A
125
°C
T
S
150
Junction temperature
T
J
150
Thermal Characteristics
Electrostatic Discharge
R
45.4
2000
2000
300
°C/W
q
JA
Human Body Model (HBM)
V
Charged Device Model (CDM)
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATION RATINGS
Value
Typ
Min
2.9
Max
5.5
Parameter
Input Voltage Range
Condition
Unit
VIN
V
VBST
−0.1
−0.1
−0.1
2.9
13.5
6.0
VBST (with respect to SW)
EN, PS, FB
VDD
VDD
5.5
Output Voltage Range
V
SW
−1
6.5
PGD
−0.1
−0.1
−0.1
−40
6.0
COMP
PGND
VDD
0.1
Junction temperature range, T
125
°C
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCP3136
ELECTRICAL CHARACTERISTICS
(V = V = 3.3 V, T = T = −40°C to +125°C. Typical values are at T = 25°C, PGND = GND unless otherwise noted)
DD
IN
A
J
A
Parameter
SYMBOL
Test Conditions
Min
Typ
Max
Unit
POWER SUPPLY
VIN operation voltage
VIN UVLO threshold
VIN UVLO hysteresis
VOLTAGE MONITOR
Power good low voltage
VIN
Nominal input voltage range
Ramp up; EN = ‘HI’
2.9
5.5
V
V
2.8
110
mV
Pull−down voltage with 4 mA sink current
60
0
200
2.0
86
mV
mA
Power good high leakage current
Power good threshold
−2.0
80
Feedback lower voltage limit
Feedback higher voltage limit
83
%Vref
%Vref
ms
Power good threshold
114
117
400
117
120
Power good high delay
t
PGDELAY
Output over-voltage protection
threshold at FB
114
1.0
80
120
2.5
86
%Vref
Over-voltage blanking time
T
Time from FB higher than 20% of Vref
to OVP fault
1.5
83
11
ms
%Vref
ms
OVPDLY
Output under−voltage protection
threshold at FB
Under-voltage blanking time
T
Time from FB lower than
20% of Vref to UVP fault
UVPDLY
SUPPLY CURRENT (T = +25°C)
J
VIN quiescent current
IVIN
EN = ‘HI’, no switching
EN = ‘LO’
1.5
3.5
15
mA
VIN shutdown supply current
IVIN_SD
mA
FEEDBACK VOLTAGE & ERROR AMPLIFIER
Reference voltage at FB
Unity gain bandwidth (Note 1)
Open loop gain (Note 1)
FB pin leakage current
VREF
594
14
600
606
100
mV
MHz
dB
80
nA
Output sourcing and sinking
current (Note 1)
C
= 20 pF
5
5
mA
comp
Slew rate (Note 1)
V/ms
OVER CURRENT PROTECTION & ZERO CROSSING
Over−current limit on high−side FET
When I exceeds this threshold
7.6
8.2
8.8
A
out
for 4 consecutive cycles,
V
= 3.3 V, V
= 1.5 V with 1 mH
IN
OUT
inductor, F = 1.1 MHz, T = 25°C
sw
A
Hiccup time duration
t
F
sw
= 1.1 MHz
14.5
ms
hiccup
Zero crossing comparator internal
offset (Note 1)
PGND−SWN, Automatic CCM/DCM mode
−4.5
−3.0
−1.5
mV
LOGIC PINS:I/O VOLTAGE AND CURRENT
EN high threshold voltage
EN hysteresis
1.1
1.18
0.18
1.2
1.30
0.24
V
V
EN input pull up resistor
MW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design, not production tested.
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5
NCP3136
ELECTRICAL CHARACTERISTICS
(V = V = 3.3 V, T = T = −40°C to +125°C. Typical values are at T = 25°C, PGND = GND unless otherwise noted)
DD
IN
A
J
A
Parameter
SYMBOL
Test Conditions
Min
Typ
Max
Unit
V
LOGIC PINS:I/O VOLTAGE AND CURRENT
PS mode threshold voltage
PS
Level 1 to Level 2
Level 2 to Level 3
0.05
1.3
7
THS
PS source current
I
PS
7 mA pull-up current when enabled
mA
mA
W
INTERNAL BST DIODE
Reverse−bias leakage current
SOFT STOP
VBST = 6.6 V, V = 3.3 V, TA = 25°C
1
IN
Output discharge on−resistance
TIMERS: SOFT−START
Soft−Start ramp−up time
Delay after EN asserting
Switching Frequency Control
EN = 0, V = 3.3 V, V
= 0.5 V
36
IN
OUT
TSS
Rising from V = 0 V to V = 0.6 V
1.5
0.5
ms
ms
SS
SS
EN = ‘HI’
FCCM mode
Frequency setting = 1.1 MHz
0.99
1.10
1.21
140
MHz
PWM
Minimum OFF time
FCCM mode or
Automatic CCM/DCM mode
100
ns
V
PWM ramp amplitude (Note 1)
2.9 V< V < 6.0 V
V /4
IN
IN
Maximum duty cycle, FCCM mode
or Automatic CCM/DCM mode
F
SW
= 1.1 MHz
84%
130
89%
THERMAL SHUTDOWN
Thermal shutdown threshold
(Note 1)
140
40
150
°C
°C
Thermal shutdown hysteresis
(Note 1)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design, not production tested.
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6
NCP3136
TYPICAL CHARACTERISTICS
98
96
94
92
90
88
86
84
96
3.3 V
2.5 V
94
3.3 V
92
2.5 V
1.8 V
1.5 V
90
1.8 V
88
1.5 V
1.2 V
86
1.2 V
84
V
= 1.0 V
OUT
V
= 1.0 V
OUT
82
80
82
80
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 3. Efficiency at Vin = 5.0 V FCCM
Operation Mode
Figure 4. Efficiency at Vin = 5.0 V Auto
CCM/DCM Operation Mode
98
96
94
92
90
88
86
84
98
96
94
92
90
88
86
84
2.5 V
2.5 V
1.8 V
1.5 V
1.8 V
1.5 V
1.2 V
1.2 V
82
80
V
= 1.0 V
82
80
V
= 1.0 V
OUT
OUT
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 5. Efficiency at Vin = 3.3 V FCCM
Operation Mode
Figure 6. Efficiency at Vin = 3.3 V Auto
CCM/DCM Operation Mode
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7
NCP3136
DETAILED DESCRIPTION
VDD Voltage
Overview
NCP3136 is a low input voltage high performance
synchronous buck converter with two integrated
N−MOSFETs. NCP3136’s output voltage range is from
0.6 V to 0.84 x Vin and it has wide input voltage range from
2.9 V to 5.5 V. The features of NCP3136 include supporting
pre−bias start−up to protect sensitive loads, cycle−by−cycle
over−current limiting and short circuit protection, power
good monitor, over voltage and under voltage protection,
built in output discharge and thermal shutdown.
NCP3136 provides two operation modes to fit various
application requirements. The automatic CCM/DCM mode
operation provides reduced power loss and increases the
efficiency at light load. The adaptive power control
architecture enables smooth transition between light load
and heavy load while maintaining fast response to load
transients.
The VDD voltage is supplied from VIN via an intrenal
resistor. Meanwhile, it is also ok to short the VDD pin and
VIN pins externally.
Reference Voltage
The NCP3136 incorporates 600 mV reference voltage
with 1.0% tolerance.
Internal Soft−Start
To limit the start−up inrush current, an internal soft start
circuit is used to ramp up the reference voltage from 0 V to
its final value linearly. The internal soft start time is 2.0 ms
typically.
Soft Stop
Soft−Stop or discharge mode is always on during faults or
disable. In this mode, disable (EN) causes the output to be
discharged through an internal 40 W transistor inside of SW
terminal. The time constant of soft−stop is a function of
output capacitance and the resistance of the discharge
transistor.
Operation Mode
In forced continuous conduction mode (FCCM), the
high−side FET is ON during the on−time and the low−side
FET is ON during the off−time. The switching is
synchronized to an internal clock thus the switching
frequency is fixed.
Automatic Power Saving Mode
In Automatic CCM/DCM mode when the load current
decreases, the converter will enter power saving mode
operation. During power saving mode, the low−side
MOSFET will turn off when the inductor current reaches
zero. So the converter skips switching and operates with
reduced frequency, which minimizes the quiescent current
and maintains high efficiency.
In Automatic CCM/DCM mode, the high−side FET is ON
during the on−time and low−side FET is ON during the
off−time until the inductor current reaches zero. An internal
zero−crossing comparator detects the zero crossing of the
inductor current from positive to negative. When the
inductor current reaches zero, the comparator sends a signal
to the logic circuitry and turns off the low−side FET.
When the load is increased, the inductor current is always
positive and the zero−crossing comparator does not send any
zero−crossing signal. The converter enters into continuous
conduction mode (CCM) when no zero−crossing is detected
for two consecutive PWM pulses. In CCM mode, the
switching synchronizes to the internal clock and the
switching frequency is fixed.
Forced Continuous Conduction Mode
When PS pin is floating or pulled high, NCP3136 is
operating in forced continuous conduction mode in both
light load and heavy load conditions. In this mode, the
switching frequency remains constant over the entire load
range, making it suitable for applications that need tight
regulation of switching frequency at a cost of lower
efficiency at light load.
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8
NCP3136
PROTECTIONS
Under Voltage Lockout (UVLO)
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP3136 supports pre−bias
start up by holding low−side FETs off until soft start ramp
reaches the FB pin voltage.
There is under-voltage lock out protection (UVLO) for
VIN in NCP3136, which has a typical trip threshold voltage
2.8 V and trip hysteresis 130 mV for VIN. If UVLO is
triggered, the device resets and waits for the voltage to rise
up over the threshold voltage and restart the part. Please note
this protection function DOES NOT trigger the fault counter
to latch off the part.
Thermal Shutdown
The NCP3136 protects itself from over heating with an
internal thermal monitoring circuit. When the die
temperature goes beyond a threshold value 135°C, both the
high−side and the low−side FETs turn off until the
temperature falls 40°C below of the threshold value. Then
the converter restarts.
Over Voltage Protection (OVP)
When feedback voltage is above 17% (typical) of nominal
voltage for over 1.7 ms blanking time, an OV fault is set. In
this case, the converter de−asserts the PGD signal and
performs the over−voltage protection function. The top gate
drive is turned off and the bottom gate drive is turned on to
discharge the output. The bottom gate drive will be turned
off until VFB drops below the UVP threshold. The device
enters a high−impedance state. This protection is latched.
Application Note
For higher output voltage application cases (Vout =
3.3 V), choose the inductor value not to be lower than 1 mH
to avoid over-current protection being triggered by inductor
current ripple; For Vin = 5 V and Vout = 3.3 V case, add a
voltage divider between Vin and EN to ensure that the part
can start up without triggering UVP. Use Figure 7 as design
reference for schematics. For other lower output voltage
cases, it is not necessary to add this divider.
Under Voltage Protection (UVP)
Output under−voltage protection works in conjunction
with the current protection described in the Over−current
Protection sections. An UVP circuit monitors the feedback
voltage to detect under−voltage event. The under−voltage
limit is 17% (typical) below of nominal voltage at FB pin.
If the feedback voltage is below this threshold over 11 ms, an
UV fault is set and both the high−side and the low−side FETs
turn off. After a hiccup delay, the part tries to restart. This
protection behavior is hiccup.
V
IN
= 5 V
10 kW
EN
Power Good Monitor (PGD)
NCP3136 provides window comparator to monitor the
output voltage at FB pin. When the output voltage is within
17% of regulation voltage, the power good pin outputs a
high signal. Otherwise, PGD stays low. The PGD pin is open
drain 5 mA pull down output. During startup, PGD stays low
until the feedback voltage is within the specified range for
about 0.4 ms. If feedback voltage falls outside the tolerance
band, the PG pin goes low after 10 ms delay.
3.6 kW
PGND
Figure 7. Voltage divider between VIN and EN for
start−up in VIN = 5 V and VOUT = 3.3 V case
Layout Guidelines
The PGD pin de−asserts as soon as the EN pin is pulled
low or an under−voltage event on VDD is detected.
When laying out a power PCB for the NCP3136 there are
several key points to consider.
Use four vias to connect the thermal pad to power ground.
Separate the power ground and analog ground planes;
connect them together at a single point.
Increase the thickness of PCB copper, it can help to lower
the die temperature and improve the overall efficiency but
meanwhile increase the cost of the board fabrication.
Use wide traces for the nodes conducting high current
such as VIN, VOUT, PGND and SW.
Over Current Protection (OCP)
NCP3136 provides high−side MOSFET current limiting.
When the current through the high−side FET exceeds 7.5 A,
the high−side FET turns off and the low−side FET turns on
until next PWM cycle. An over−current counter is triggered
and starts to increment each occurrence of an over−current
event. Both the high−side and the low−side FETs turn off
when the OC counter reaches four. The OC counter resets if
the detected current is less than 7.5 A after an OC event.
Place feedback and compensation network components
close to the IC.
Keep FB, COMP away from noisy signals such as SW,
BST.
Place VIN and VDD decoupling capacitors as close to the
IC as possible.
Pre−Bias Startup
In some applications the controller will be required to start
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485DA
ISSUE A
1
SCALE 2:1
DATE 22 SEP 2015
NOTES:
A
B
E
L
L
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN ONE
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
2X
0.10 C
A3
A3
MOLD CMPD
EXPOSED Cu
2X
0.10
C
0.20
0.30
1.75
TOP VIEW
D
D2
E
3.00 BSC
1.55
3.00 BSC
A
DETAIL B
0.05
C
E2
e
K
L
L1
L2
1.55
0.50 BSC
0.275 REF
0.30
0.00
0.09 REF
1.75
A1
A3
DETAIL B
0.50
0.15
ALTERNATE
CONSTRUCTIONS
0.05
C
SEATING
PLANE
A1
NOTE 4
C
SIDE VIEW
GENERIC
0.10 C
A
B
MARKING DIAGRAM*
D2
DETAIL A
16X L
XXXXX
XXXXX
ALYWG
G
5
8X
L2
0.10 C
A
B
9
E2
XXXXX = Specific Device Code
16X
b
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
0.10 C
A
B
0.05 C
NOTE 3
K
16
e
e/2
(Note: Microdot may be in either location)
BOTTOM VIEW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
3.30
16X
0.61
PACKAGE
OUTLINE
1.78
1
1.78 3.30
16X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON87551E
QFN16, 3X3, 0.5P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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