NCP3163MNR2G [ONSEMI]
3.4 A, Step−Up/Down/Inverting 50−300 kHz Switching Regulator; 3.4 A，步上/下/负输出50〜300 kHz的开关稳压器
| 型号： | NCP3163MNR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.4 A, Step−Up/Down/Inverting 50−300 kHz Switching Regulator |
| 文件： | 总20页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP3163
3.4 A, Step−Up/Down/
Inverting 50−300 kHz
Switching Regulator
The NCP3163 Series is a performance enhancement to the popular
MC33163 and MC34163 monolithic DC−DC converters. These
devices consist of an internal temperature compensated reference,
comparator, controlled duty cycle oscillator with an active current
limit circuit, driver and high current output switch. This controller was
specifically designed to be incorporated in step−down, step−up, or
voltage−inverting applications with a minimum number of external
components. The NCP3163 comes in an exposed pad package which
can greatly increase the power dissipation of the built in power switch.
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MARKING
DIAGRAMS
16
16
1
NCP3163xPW
AWLYYWWG
SOIC−16W
EXPOSED PAD
PW SUFFIX
CASE 751AG
Features
• Output Switch Current in Excess of 3.0 A
1
1
• 3.4 A Peak Switch Current
• Frequency is Adjustable from 50 kHz to 300 kHz
• Operation from 2.5 V to 40 V Input
• Externally Adjustable Operating Frequency
• Precision 2% Reference for Accurate Output Voltage Control
• Driver with Bootstrap Capability for Increased Efficiency
• Cycle−by−Cycle Current Limiting
18
18
NCP3163x
AWLYYWW G
G
18−LEAD DFN
MN SUFFIX
CASE 505
1
• Internal Thermal Shutdown Protection
• Low Voltage Indicator Output for Direct Microprocessor Interface
• Exposed Pad Power Package
NCP3163x = Specific Device Code
= Assembly Location
A
• Low Standby Current
WL = Wafer Lot
YY = Year
WW = Work Week
• This is a Pb−Free Device
G
G
= Pb−Free Package
= Pb−Free Package
Current
Limit
8
7
6
5
9
−
+
(Note: Microdot may be in either location)
V
in
10
11
12
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
+
V
CC
C
in
Oscillator
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
R
S
Q
Thermal
4
3
13
14
V
CC
+
+
−
2
1
15
16
+
+
−
LVI
V
CC
V
+
out
(Bottom View)
Figure 1. Typical Buck Application Circuit
C
O
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
May, 2006 − Rev. 1
NCP3163/D
NCP3163
Current
Limit
0.25 V
I
8
7
6
5
9
−
+
PKsense
Driver Collector
Switch Collector
R
SC
10
11
12
V
CC
V
CC
Timing Capacitor
Q1
Oscillator
C
T
Q2
60
Shutdown
R
S
R
DT
Q
Thermal
4
3
13
14
Gnd
Latch
CC
V
Voltage Feedback 1
Voltage Feedback 2
LVI Output
Switch Emitter
45 k
2.0 mA
+
+
−
2
1
15
16
Feedback
Comparator
1.25 V
15 k
+
+
−
7.0 V
Bootstrap Input
1.125 V
(Bottom View)
LVI
V
CC
+
= Sink Only
Positive True Logic
−
Figure 2. Representative Block Diagram
PIN FUNCTION DESCRIPTION
SOIC16
DFN18
15
PIN NAME
LVI Output
DESCRIPTION
1
2
This pin will sink current when FB1 and FB2 are less than the LVI threshold (V ).
th
16
Voltage Feedback 2
Connecting this pin to a resistor divider off of the output will regulate the application
according to the V design equation in Figure 22.
out
3
4
6
17
18
1
Voltage Feedback 1
GND
Connecting this pin directly to the output will regulate the device to 5.05 V.
Ground pin for all internal circuits and power switch.
Timing Capacitor
Connect a capacitor to this pin to set the frequency. The addition of a parallel resis-
tor will decrease the maximum duty cycle and increase the frequency.
7
8
3
4
V
Power pin for the IC.
CC
I
Sense
When (V −V
) > 250 mV the circuit resets the output driver on a pulse by
pk
CC
IPKsense
pulse basis.
9
5
6,7,8,9
10,11,12,13
14
Drive Collector
Switch Collector
Switch Emitter
Bootstrap Input
Voltage driver collector
10,11
14,15
16
Internal switch transistor collector
Internal switch transistor emitter
Connect this pin to V for operation at low V levels. For some topologies, a
CC
CC
series resistor and capacitor can be utilized to improve the converter efficiency.
5,12,13
2
No Connect
These pins have no connection.
Exposed
Pad
Exposed
Pad
Exposed Pad
The exposed pad beneath the package must be connected to GND (pin 4). Addi-
tionally, using proper layout techniques, the exposed pad can greatly enhance the
power dissipation capabilities of the NCP3163.
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2
NCP3163
MAXIMUM RATINGS (Note 1)
Rating
Symbol
Value
0 to +40
−1.0 to +40
−2.0 to +40
+40
Unit
V
Power Supply Voltage
V
CC
Switch Collector Voltage Range
Switch Emitter Voltage Range
Switch Collector to Emitter Voltage
Switch Current
V
CSW
V
ESW
V
V
V
V
CESW
I
3.4
A
SW
Driver Collector Voltage (Pin 8)
Driver Collector Current (Pin 8)
Bootstrap Input Current Range
V
−1.0 to +40
150
V
CC
CC
I
mA
mA
V
I
−100 to +100
BST
Current Sense Input Voltage Range
V
(V − 7.0) to (V + 1.0)
CC CC
IPKSNS
Feedback and Timing Capacitor Input Voltage Range
Low Voltage Indicator Output Voltage Range
Low Voltage Indicator Output Sink Current
V
−1.0 to +7.0
V
in
V
CLVI
CLVI
−1.0 to +40
10
V
I
mA
Power Dissipation and Thermal Characteristics
Thermal Characteristics
°C/W
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Air
R
R
15
56
q
JC
JA
q
Storage Temperature Range
T
−65 to +150
+150
°C
°C
°C
stg
Maximum Junction Temperature
T
Jmax
Operating Ambient Temperature (Note 3)
NCP3163PW
T
A
0 to +70
NCP3163BPW
−40 to +85
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 1500 V per MIL−STD−883, Method 3015.
Machine Model Method 150 V.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded.
4. The pins which are not defined may not be loaded by external signals.
PIN CONNECTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Bootstrap Input
LVI Output
Voltage Feedback 2
Voltage Feedback 1
18
17
16
15
14
13
12
11
10
Timing Capacitor
N/C
GND
1
2
3
4
5
6
7
GND
Voltage Feedback 1
Voltage Feedback 2
LVI Output
Switch
Emitter
V
CC
I
pk
Sense
GND
N/C
Bootstrap Input
Switch Emitter
Switch Emitter
Switch Emitter
Switch Emitter
Driver Collector
Switch Collector
Switch Collector
Switch Collector
Switch Collector
N/C
Timing Capacitor
Switch Collector
Driver Collector
EP Flag
8
9
V
CC
I
pk
Sense
(Top View)
Note: Pin 18 must be tied to EP Flag on PCB
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3
NCP3163
ELECTRICAL CHARACTERISTICS (V = 15 V, Pin 16 = V , C = 270 pF, R = 15 kW, for typical values T = 25°C, for min/max
CC
CC
T
T
A
values T is the operating ambient temperature range that applies (Note 5), unless otherwise noted.)
A
Characteristic
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency
f
kHz
OSC
T = 25°C, V = 15 V
225
212
250
250
275
288
A
CC
Total Variation over V = 2.5 V to 40 V and Temperature (Note 5)
CC
Charge Current
I
−
−
225
25
−
−
mA
mA
−
chg
Discharge Current
I
dischg
Charge to Discharge Current Ratio
Sawtooth Peak Voltage
Sawtooth Valley Voltage
I
/I
8.0
−
9.0
10
−
chg dischg
V
V
1.25
0.55
V
OSC(P)
OSC(V)
−
−
V
FEEDBACK COMPARATOR 1
Threshold Voltage
V
V
th(FB1)
T = 25°C
4.9
4.85
5.05
−
5.2
5.25
A
Total Variation over V = 2.5 V to 40 V and Temperature (Note 5)
CC
Threshold Voltage
REGline
%/V
(FB1)
Line Regulation (V = 2.5 V to 40 V, T = 25°C)
−
−
0.008
100
0.03
200
CC
A
Input Bias Current (V
= 5.05 V)
I
mA
FB1
IB(FB1)
FEEDBACK COMPARATOR 2
Threshold Voltage
V
V
th(FB2)
T = 25°C, V = 15 V
1.225
1.213
1.25
−
1.275
1.287
A
CC
Total Variation over V = 2.5 V to 40 V and Temperature (Note 5)
CC
Threshold Voltage
REGline
%/V
(FB1)
Line Regulation (V = 2.5 V to 40 V, T = 25°C)
−
0.008
−
0.03
0.4
CC
A
Input Bias Current (V
= 1.25 V)
I
− 0.4
mA
FB2
IB(FB2)
CURRENT LIMIT COMPARATOR
Threshold Voltage
V
mV
th(Sense)
IB(Sense)
T = 25°C
−
230
250
−
−
270
A
Total Variation over V = 2.5 V to 40 V, and Temperature (Note 5)
CC
Input Bias Current (V
= 15 V)
I
−
1.0
20
mA
Ipk (Sense)
DRIVER AND OUTPUT SWITCH (Note 6)
Saturation Voltage (I = 2.5 A, Pins 14, 15 grounded)
V
V
SW
CE(sat)
Non−Darlington Connection (R
Darlington Connection (Pins 9, 10, 11 connected) (Note 7)
= 110 W to V , I /I
≈ 20)
−
−
0.6
1.0
1.0
1.4
Pin 9
CC SW DRV
Collector Off−State Leakage Current (V = 40 V)
I
−
0.02
2.0
100
4.0
mA
mA
V
CE
C(off)
Bootstrap Input Current Source (V = V + 5.0 V)
I
0.5
BS
CC
source(DRV)
Bootstrap Input Zener Clamp Voltage (I = 25 mA)
V
V
+ 6.0
V
+ 7.0
V
+ 9.0
CC
Z
Z
CC
CC
LOW VOLTAGE INDICATOR
Input Threshold (V
Increasing)
Decreasing)
V
1.07
1.125
15
1.18
V
mV
V
FB2
th
Input Hysteresis (V
V
−
−
−
−
FB2
H
Output Sink Saturation Voltage (I
= 2.0 mA)
V
0.15
0.01
0.4
5.0
sink
OL(LVI)
Output Off−State Leakage Current (V
= 15 V)
I
mA
OH
OH
TOTAL DEVICE
Standby Supply Current (V = 2.5 V to 40 V, Pin 8 = V
,
I
CC
−
6.0
10
mA
CC
CC
Pins 6, 14, 15 = GND, remaining pins open)
5. Maximum package power dissipation limits must be observed.
6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
7. T
= 0°C for NCP3163
= − 40°C for NCP3163B
T
= + 70°C for NCP3163
= + 85°C for NCP3163B
low
high
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4
NCP3163
300
250
200
150
V
= 15 V
CC
T = 25°C
A
R = 15 kW
t
R = open
t
100
50
0
100
200
300
400
500
600
700
C , TIMER CAPACITANCE (pF)
T
Figure 3. Oscillator Frequency vs. Timer
Capacitance (CT)
2.0
0
4.0
V
= 15 V
C = 230 pF
V
= 15 V
C = 620 pF
CC
CC
2.0
0
T
R = 20 kW
T
T
−ꢀ2.0
−ꢀ4.0
−ꢀ6.0
−ꢀ2.0
−ꢀ4.0
−ꢀ6.0
−ꢀ8.0
−ꢀ10
−ꢀ55
−ꢀ25
0
25
50
75
100
125
−ꢀ50
−ꢀ25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
TEMPERATURE (°C)
Figure 4. Oscillator Frequency Change vs.
Temperature when only CT is connected to Pin 6
Figure 5. Oscillator Frequency Change vs.
Temperature when CT and RT are connected to Pin 6
140
120
1300
V
V
= 15 V
= 5.05 V
CC
V
= 15 V
V
Max = 1275 mV
FB1
CC
th
1280
1260
1240
1220
1200
V
V
Typ = 1250 mV
Min = 1225 mV
th
th
100
80
60
−ꢀ55
−ꢀ25
0
25
50
75
100
125
−ꢀ55
−ꢀ25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 6. Feedback Comparator 1 Input Bias
Current vs. Temperature
Figure 7. Feedback Comparator 2 Threshold
Voltage vs. Temperature
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5
NCP3163
7.6
2.8
2.4
V
= 15 V
Pin 16 = V + 5.0 V
CC
I = 25 mA
Z
CC
7.4
7.2
7.0
6.8
2.0
1.6
1.2
−ꢀ55
−ꢀ25
0
25
50
75
100
125
−ꢀ55
−ꢀ25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 8. Bootstrap Input Current
Source vs. Temperature
Figure 9. Bootstrap Input Zener Clamp
Voltage vs. Temperature
1.2
1.0
0.8
0.6
0.4
0.2
0
0
Darlington Configuration
V
CC
Emitter Sourcing Current to GND
Pins 7, 8, 10, 11 = V
Pins 4, 5, 12, 13 = GND
Darlington, Pins 9, 10, 11 Connected
Grounded Emitter Configuration
Collector Sinking Current From V
Pins 7, 8 = V = 15 V
CC
Pins 4, 5, 12, 13, 14, 15 = GND
T = 25°C, (Note 2)
A
−ꢀ0.4
CC
T = 25°C, (Note 2)
A
−ꢀ0.8
−1.2
−1.6
−ꢀ2.0
CC
Bootstrapped, Pin 16 = V + 5.0 V
CC
Saturated Switch, R
= 110 W to V
CC
Pin9
Non−Bootstrapped, Pin 16 = V
CC
GND
1.6
0
0.8
1.6
I , EMITTER CURRENT (A)
2.4
3.2
0
0.8
2.4
3.2
I , COLLECTOR CURRENT (A)
C
E
Figure 10. Output Switch Source Saturation
vs. Emitter Current
Figure 11. Output Switch Sink Saturation
vs. Collector Current
0
0.5
0.4
V
ꢁ=ꢁ5 V
CC
GND
T ꢁ=ꢁ25°C
A
I = 10 mA
C
−ꢀ0.4
−ꢀ0.8
−ꢀ1.2
−ꢀ1.6
−ꢀ2.0
0.3
0.2
0.1
0
I = 10 mA
C
V
= 15 V
CC
Pins 7, 8, 9, 10, 16 = V
CC
Pins 4, 6 = GND
Pin 14 Driven Negative
−ꢀ55
−ꢀ25
0
25
50 75 100
125
0
2.0
4.0
6.0
8.0
T , AMBIENT TEMPERATURE (°C)
A
I , OUTPUT SINK CURRENT (mA)
sink
Figure 12. Output Switch Negative Emitter
Voltage vs. Temperature
Figure 13. Low Voltage Indicator Output Sink
Saturation Voltage vs. Sink Current
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6
NCP3163
254
252
250
248
246
1.6
V
= 15 V
CC
V
V
= 15 V
CC
= 15 V
Ipk (Sense)
1.4
1.2
1.0
0.8
0.6
−ꢀ55
−ꢀ25
0
25
50
75
100
125
−ꢀ55
−ꢀ25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 14. Current Limit Comparator Threshold
Voltage vs. Temperature
Figure 15. Current Limit Comparator Input Bias
Current vs. Temperature
8.0
6.0
4.0
7.2
6.4
V
= 15 V
Pins 7, 8, 16 = V
CC
CC
Pins 4, 6, 14 = GND
Remaining Pins Open
5.6
4.8
4.0
Pins 7, 8, 16 = V
CC
Pins 4, 6, 14 = GND
Remaining Pins Open
T = 25°C
A
2.0
0
0
10
20
, SUPPLY VOLTAGE (V)
30
40
−ꢀ55
−ꢀ25
0
25
50
75
100
125
V
T , AMBIENT TEMPERATURE (°C)
CC
A
Figure 16. Standby Supply Current
vs. Supply Voltage
Figure 17. Standby Supply Current
vs. Temperature
3.0
2.6
C = 620 pF
T
Pins 7,8 = V
CC
Pins 4, 14 = GND
Pin 9 = 1.0 kW to 15 V
Pin 10 = 100 W to 15 V
Pin 16 Open
2.2
1.8
Pin 16 = V
CC
1.4
1.0
−ꢀ55
−ꢀ25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
Figure 18. Minimum Operating Supply
Voltage vs. Temperature
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7
NCP3163
INTRODUCTION
The NCP3163 is a monolithic power switching regulator
oscillator cycle, a partial cycle plus a complete cycle,
multiple cycles, or a partial cycle plus multiple cycles.
optimized for DC−to−DC converter applications. The
combination of its features enables the system designer to
directly implement step−up, step−down, and voltage−
inverting converters with a minimum number of external
components. Potential applications include cost sensitive
consumer products as well as equipment for the automotive,
computer, and industrial markets. A representative block
diagram is shown in Figure 2.
Oscillator
The oscillator frequency and on−time of the output switch
are programmed by the value selected for timing capacitor
C . Capacitor C is charged and discharged by a 9 to 1 ratio
T
T
internal current source and sink, generating a negative going
sawtooth waveform at Pin 6. As C charges, an internal
T
pulse is generated at the oscillator output. This pulse is
connected to the NOR gate center input, preventing output
switch conduction, and to the AND gate upper input,
allowing the latch to be reset if the comparator output is low.
Thus, the output switch is always disabled during ramp−up
and can be enabled by the comparator output only at the start
of ramp−down. The oscillator peak and valley thresholds are
1.25 V and 0.55 V, respectively, with a charge current of
225 mA and a discharge current of 25 mA, yielding a
maximum on−time duty cycle of 90%. A reduction of the
maximum duty cycle may be required for specific converter
configurations. This can be accomplished with the addition
OPERATING DESCRIPTION
The NCP3163 operates as a fixed on−time, variable
off−time voltage mode ripple regulator. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 19. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the feedback comparator sets the latch, immediately
terminating switch conduction. The feedback comparator
will inhibit the switch until the load current causes the output
voltage to fall below nominal. Under these conditions,
output switch conduction can be inhibited for a partial
of an external deadtime resistor (R ) placed across C . The
DT
T
resistor increases the discharge current which reduces the
on−time of the output switch. The converter output can be
inhibited by clamping C to ground with an external NPN
T
small−signal transistor. To calculate the frequency when
only C is connected to Pin 6, use the equations found in
T
Figure 22. When R is also used, the frequency and
T
maximum duty cycle can be calculated with the NCP3163
design tool found at www.onsemi.com.
1
Comparator Output
0
1.25 V
Timing Capacitor C
T
0.55 V
t
9t
1
Oscillator Output
0
On
Output Switch
Off
Nominal Output
Voltage Level
Output Voltage
Startup
Quiescent Operation
Figure 19. Typical Operating Waveforms
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8
NCP3163
Feedback and Low Voltage Indicator Comparators
output state is controlled by the highest voltage applied to
either of the two noninverting inputs.
Output voltage control is established by the Feedback
comparator. The inverting input is internally biased at 1.25 V
and is not pinned out. The converter output voltage is
typically divided down with two external resistors and
monitored by the high impedance noninverting input at Pin 2.
The maximum input bias current is 0.4 mA, which can cause
an output voltage error that is equal to the product of the input
bias current and the upper divider resistance value. For
applications that require 5.0 V, the converter output can be
directly connected to the noninverting input at Pin 3. The high
impedance input, Pin 2, must be grounded to prevent noise
pickup. The internal resistor divider is set for a nominal
voltage of 5.05 V. The additional 50 mV compensates for a
1.0% voltage drop in the cable and connector from the
converter output to the load. The Feedback comparator’s
The Low Voltage Indicator (LVI) comparator is designed
for use as a reset controller in microprocessor−based
systems. The inverting input is internally biased at 1.125 V,
which sets the noninverting input thresholds to 90% of
nominal. The LVI comparator has 15 mV of hysteresis to
prevent erratic reset operation. The Open Collector output is
capable of sinking in excess of 6.0 mA (see Figure 13). An
external resistor (R ) and capacitor (C
) can be used to
DLY
LVI
program a reset delay time (t ) by the formula shown
DLY
below, where V
is the microprocessor reset input
th(MPU)
threshold. Refer to Figure 20.
1
V
ǒ Ǔ
th(MPU)
tDLY = RLVI ⋅ CDLY ⋅ In
1 −
Vout
3
14
+
+
−
Feedback
Comparator
2
15
16
R
LVI
1.25 V
+
+
−
Low Voltage
Indicator Output
1
C
LVI
1.125 V
DLY
L
V
out
C
O
(Bottom View)
Figure 20. Partial Application Schematic Showing
Implementation of LVI Delay with RLVI and CDLY
Current Limit Comparator, Latch and Thermal
Shutdown
200 ns. The parasitic inductance associated with R and the
SC
circuit layout should be minimized. This will prevent
unwanted voltage spikes that may falsely trip the Current
Limit comparator.
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 170°C, the Latch
is forced into the “Set” state, disabling the Output Switch.
This feature is provided to prevent catastrophic failures from
accidental device overheating. It is not intended to be used
as a replacement for proper heatsinking.
With a voltage mode ripple converter operating under
normal conditions, output switch conduction is initiated by
the oscillator and terminated by the Voltage Feedback
comparator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the Current Limit
comparator will protect the Output Switch.
The switch current is converted to a voltage by inserting
a fractional ohm resistor, R , in series with V and output
SC
CC
switch transistor Q . The voltage drop across R
is
2
SC
Driver and Output Switch
monitored by the Current Sense comparator. If the voltage
To aid in system design flexibility and conversion
efficiency, the driver current source and collector, and
output switch collector and emitter are pinned out
separately. This allows the designer the option of driving the
output switch into saturation with a selected force gain or
driving it near saturation when connected as a Darlington.
The output switch has a typical current gain of 70 at 2.5 A
and is designed to switch a maximum of 40 V collector to
emitter, with up to 3.4 A peak collector current. The
drop exceeds 250 mV with respect to V , the comparator
will set the latch and terminate output switch conduction on
CC
a
cycle−by−cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on−time during a given oscillator cycle. The
calculation for a value of R is:
SC
0.25 V
(Switch)
R
SC
+
I
pk
Figures14 and 15 show that the Current Sense comparator
threshold is tightly controlled over temperature and has a
typical input bias current of 1.0 mA. The propagation delay
from the comparator input to the Output Switch is typically
minimum value for R is:
SC
0.25 V
3.4 A
R
+
+ 0.0735 W
SC(min)
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9
NCP3163
When configured for step−down or voltage−inverting
low ESR capacitors. The equation below is used to calculate
a minimum value bootstrap capacitor based on a minimum
zener voltage and an upper limit current source.
applications (see application notes at the end of this
document) the inductor will forward bias the output rectifier
when the switch turns off. Rectifiers with a high forward
voltage drop or long turn−on delay time should not be used.
If the emitter is allowed to go sufficiently negative, collector
current will flow, causing additional device heating and
reduced conversion efficiency.
t
Dt
DV
on
C
+ I
+ 4.0 mA
+ 0.001 t
on
B(min)
4.0 V
Parametric operation of the NCP3163 is guaranteed over
a supply voltage range of 2.5 V to 40 V. When operating
below 3.0 V, the Bootstrap Input should be connected to
Figure 12 shows that by clamping the emitter to 0.5 V, the
collector current will be in the range 10 mA over
temperature. A 1N5822 or equivalent Schottky barrier
rectifier is recommended to fulfill these requirements.
A bootstrap input is provided to reduce the output switch
saturation voltage in step−down and voltage−inverting
converter applications. This input is connected through a
series resistor and capacitor to the switch emitter and is used
V
. Figure 18 shows that functional operation down to
CC
1.7 V at room temperature is possible.
Package
The NCP3163 is contained in a heatsinkable 16−lead
plastic package in which the die is mounted on a special heat
tab copper alloy pad. This pad is designed to be soldered
directly to a GND connection on the printed circuit board to
improve thermal conduction. Since this pad directly
contacts the substrate of the die, it is important that this pad
be always soldered to GND, even if surface mount heat
sinking is not being used. Figure 21 shows recommended
layout techniques for this package.
to raise the internal 2.0 mA bias current source above V
.
CC
An internal zener limits the bootstrap input voltage to V
CC
+7.0 V. The capacitor’s equivalent series resistance must
limit the zener current to less than 100 mA. An additional
series resistor may be required when using tantalum or other
Vias to 2nd Layer Metal
for Maximum Heat Sinking
Exposed Pad
0.175
0.188
Minimum
Recommended
Exposed Copper
0.145
Flare Metal for Maximum Heat Sinking
Figure 21. Layout Guidelines to Obtain Maximum
Package Power Dissipation
APPLICATIONS
Figures 23 through 30 show the simplicity and flexibility
equations for the key parameters. Additionally, a complete
application design aid for the NCP3163 can be found at
www.onsemi.com.
of the NCP3163. Three main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams. Figure 22 gives the relevant design
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10
NCP3163
Calculation
Step−Down
) V
Step−Up
Voltage−Inverting
(See Notes 1,2,3)
|V | ) V
V
V
) V – V
t
t
on
off
out
F
out
out
F
F
in
V
* V
V
* V
* V
V
– V
sat
in
sat
out
sat
in
in
t
t
t
t
t
t
on
off
on
off
on
off
t
on
t
t
t
on
on
on
ƒ ǒ Ǔ
ƒ ǒ Ǔ
ƒ ǒ Ǔ
) 1
) 1
) 1
t
t
t
off
off
off
*6
*6
*6
32.143 · 10
32.143 · 10
32.143 · 10
*12
*12
*12
C
* 20 @ 10
* 20 @ 10
* 20 @ 10
T
f
f
f
t
t
t
t
on
on
I
I
out ǒ ) 1
Ǔ
I
out ǒ ) 1
Ǔ
I
L(avg)
out
off
off
DI
DI
DI
L
L
L
I
pk (Switch)
I
)
I
)
I
)
L(avg)
L(avg)
L(avg)
2
2
2
0.25
pk (Switch)
0.25
pk (Switch)
0.25
pk (Switch)
R
SC
I
I
I
V
in
* V
* V
V
* V
V
* V
sat
DI
out
sat
sat
in
in
ǒ
Ǔ on
t
ǒ Ǔ on
t
ǒ Ǔ on
t
L
DI
DI
L
L
L
t
I
t
I
on
on
C
1
out
out
2
V
ǒ
Ǔ2
DI
) (ESR)
[
[
ripple(pp)
L
8 ƒ C
C
O
O
O
R
R
R
2
1
2
1
2
1
V
ǒ
) 1
Ǔ
V
ǒ
) 1
Ǔ
V
ǒ
) 1
Ǔ
V
out
ref
ref
ref
R
R
R
The following Converter Characteristics must be chosen:
V
− Nominal operating input voltage.
− Desired output voltage.
in
V
out
I
− Desired output current.
out
DI − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DI be chosen to be less
L
L
than 10% of the average inductor current I
. This will help prevent I
L(avg)
from reaching the current limit
pk (Switch)
threshold set by R . If the design goal is to use a minimum inductance value, let DI = 2(I ). This will
L(avg)
SC
L
proportionally reduce converter output current capability.
p − Maximum output switch frequency.
− Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value
V
ripple(pp)
since it will directly affect line and load regulation. Capacitor C should be a low equivalent series resistance (ESR)
O
electrolytic designed for switching regulator applications.
NOTES: 1. V − Saturation voltage of the output switch, refer to Figures 10 and 11.
sat
NOTES: 2. V − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V.
F
NOTES: 3. The calculated t /t must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum
on off
NOTES: 3. operating input voltage.
Figure 22. Design Equations
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11
NCP3163
Current
Limit
0.25 V
8
7
6
5
9
−
+
R
SC
10
11
12
V
in
C
in
V
CC
Oscillator
Q
1
C
R
T
T
Q
2
R
Q
60
S
Thermal
Latch
4
3
13
14
V
CC
45 k
R
+
+
−
1
Feedback
Comparator
2
1
15
16
D
2.0 mA
7.0 V
1.25 V 15 k
1.125 V
+
+
−
R
2
C
R
B
LVI
V
B
CC
L
V
out
C
O
(Bottom View)
Figure 23. Typical Buck Application Schematic
Value of Components
Name
Value
47 mH
Name
Value
15 kW
L
R
R
R
C
R
1
D
C
C
C
R
2 A, 40 V Schottky Rectifier
47 mF, 35 V
24.9 kW
80 mW, 1 W
4.7 nF
2
in
sc
b
100 mF, 10 V
out
270 pF 10%
15 kW
200 W
t
t
b
Test Results for Vout = 3.3 V
Test
Condition
= 8.0 V to 24 V, I = 2.5 A
Results
13 mV
25 mV
100 mVpp
70.3%
Line Regulation
Load Regulation
Output Ripple
V
in
in
in
in
in
out
V
V
V
V
= 12 V, I = 0 to 2.5 A
out
= 12 V, I = 0 to 2.5 A
out
Efficiency
= 12 V, I = 2.5 A
out
Short Circuit Current
= 12 V, R = 0.1 W
3.1 A
L
Test Results for Vout = 5.05 V
Test
Condition
Results
54 mV
28 mV
150 mVpp
75.5%
Line Regulation
Load Regulation
Output Ripple
V
in
V
in
V
in
V
in
V
in
= 10.2 V to 24 V, I = 2.5 A
out
= 12 V, I = 0 to 2.5 A
out
= 12 V, I = 0 to 2.5 A
out
Efficiency
= 12 V, I = 2.5 A
out
Short Circuit Current
= 12 V, R = 0.1 W
3.1 A
L
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12
NCP3163
Figure 24. Buck Layout
APPLICATION SPECIFIC CHARACTERISTICS
85
3.3 V Eff
5.0 V Eff
80
75
70
65
60
55
50
0
0.5
1.0
1.5
2.0
2.5
I
(A)
out
Figure 25. Efficiency vs. Output Current for the
Buck Demo Board at Vin = 12 V, TA = 255C
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13
NCP3163
Current
Limit
L
0.25 V
8
7
9
−
+
R
SC
10
11
12
V
in
+
C
in
V
CC
6
Oscillator
Q
1
R
T
C
T
Q
2
R
Q
5
S
60
Thermal
Latch
4
3
13
14
V
CC
D
45 k
+
+
−
Feedback
Comparator
2
1
15
16
2.0 mA
7.0 V
1.25 V
15 k
+
+
−
1.125 V
LVI
V
CC
V
out
+
R
C
O
R
(Bottom View)
1
2
Figure 26. Typical Boost Application Schematic
Value of Components for Vout = 24 V
Name
Value
33 mH
Name
Value
42.2 kW
2.32 kW
L
R
R
C
R
1
D
C
C
R
2 A, 40 V Schottky Rectifier
330 mF, 35 V
270 pF 10%
15 kW
2
330 mF, 25 V
80 mW, 1 W
in
t
out
sc
t
Test Results for Vout = 24 V
Test
Condition
= 10 V to 20 V, I = 700 mA
Results
90 mV
80 mV
300 mVpp
83%
Line Regulation
Load Regulation
Output Ripple
V
in
in
in
in
in
out
V
V
V
V
= 12 V, I = 0 to 700 mA
out
= 12 V, I = 0 to 700 mA
out
Efficiency
= 12 V, I = 700 mA
out
Short Circuit Current
= 12 V, R = 0.1 W
3.1 A
L
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14
NCP3163
Figure 27. Boost Demo Board Layout
86
84
82
80
78
76
74
0.1
0.2
0.3
0.4
(A)
0.5
0.6
0.7
I
out
Figure 28. Efficiency vs. Output Current for the
Boost Demo Board at Vin = 12 V, TA = 255C
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15
NCP3163
Current
Limit
0.25 V
8
7
6
5
9
−
+
R
SC
10
11
12
V
in
+
C
in
V
CC
Oscillator
Q
1
C
R
T
T
Q
2
R
Q
S
60
Thermal
Latch
4
3
13
14
V
CC
L
45 k
+
+
−
Feedback
Comparator
2
1
15
16
R
C
B
2.0 mA
7.0 V
1.25 V 15 k
+
+
−
B
LVI
1.125 V
D
V
CC
V
out
R
C
1
(Bottom View)
R
O
2
+
Figure 29. Typical Voltage Inverting Application Schematic
Value of Components for Vout = −15 V
Name
Value
47 mH
Name
Value
L
R
R
R
C
R
1.07 kW
11.8 kW
1
D
C
C
C
2 A, 40 V Schottky Rectifier
270 mF, 16 V
2
80 mW, 1 W
4.7 nF
in
sc
b
2 X 270 mF, 16 V
150 pF 10%
out
t
200 mW
b
Test Results for Vout = −15 V
Test
Condition
= 7.0 V to 16 V, I = 500 mA
Results
35 mV
20 mV
100 mVpp
68%
Line Regulation
Load Regulation
Output Ripple
V
in
in
in
in
in
out
V
V
V
V
= 12 V, I = 0 to 500 mA
out
= 12 V, I = 0 to 500 mA
out
Efficiency
= 12 V, I = 500 mA
out
Short Circuit Current
= 12 V, R = 0.1 W
3.1 A
L
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16
NCP3163
Figure 30. Voltage Inverting Demo Board Layout
70
66
62
58
54
50
0.1 0.15
0.2 0.25
0.3 0.35
(A)
0.4
0.45 0.5
I
out
Figure 31. Efficiency vs. Output Current for the
Voltage Inverting Demo Board at Vin = 12 V, TA = 255C
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17
NCP3163
ORDERING INFORMATION
†
Device
Package
Shipping
NCP3163PWG
SOIC−16 W Exposed Pad
(Pb−Free)
47 Units / Rail
1000 / Tape & Reel
47 Units / Rail
NCP3163PWR2G
NCP3163BPWG
NCP3163BPWR2G
NCP3163MNR2G
NCP3163BMNR2G
SOIC−16 W Exposed Pad
(Pb−Free)
SOIC−16 W Exposed Pad
(Pb−Free)
SOIC−16 W Exposed Pad
(Pb−Free)
1000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
DFN18
(Pb−Free)
DFN18
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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18
NCP3163
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY, EXPOSED PAD
PW SUFFIX
CASE 751AG−01
ISSUE O
−U−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
M
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
16
1
9
P
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R−01 OBSOLETE, NEW STANDARD 751R−02.
B
M
M
W
0.25 (0.010)
R x 45
_
8
−W−
MILLIMETERS
INCHES
MIN
G
14 PL
PIN 1 I.D.
DIM MIN
MAX
10.45
7.60
2.65
0.49
0.90
MAX
0.411
0.299
0.104
0.019
0.035
DETAIL E
A
B
C
D
F
10.15
7.40
2.35
0.35
0.50
0.400
0.292
0.093
0.014
0.020
TOP SIDE
C
G
H
J
1.27 BSC
0.050 BSC
F
3.31
0.25
0.00
4.58
0
3.51
0.32
0.10
4.78
7
0.130
0.010
0.000
0.180
0
0.138
0.012
0.004
0.188
7
−T−
0.10 (0.004)
T
SEATING
K
D16 PL
0.25 (0.010)
H
K
L
PLANE
M
P
R
_
_
_
_
M
S
S
T
U
W
J
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
DETAIL E
1
8
9
SOLDERING FOOTPRINT*
EXPOSED PAD
L
0.350
Exposed
Pad
0.175
0.050
16
BACK SIDE
C
L
0.188
0.200
0.376
C
L
0.074
0.024
0.145
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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19
NCP3163
PACKAGE DIMENSIONS
18−LEAD DFN, 5 x 6 mm
MN SUFFIX
CASE 505−01
ISSUE B
NOTES:
A
E
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
B
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1 LOCATION
2X
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.15
C
A
A1
A3
b
0.80
0.00
0.20 REF
2X
0.15
C
0.18
0.30
TOP VIEW
D
6.00 BSC
D2
E
3.98
5.00 BSC
4.28
E2
e
K
2.98
0.50 BSC
0.20
0.45
3.28
(A3)
0.10
0.08
C
C
−−−
0.65
A
18X
L
A1
C
SIDE VIEW
SEATING
PLANE
D2
e
18X L
1
9
E2
18X K
18
10
18X b
0.10 C A
0.05
B
C
NOTE 3
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP3163/D
相关型号：
NCP3218GMNR2G
SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, QCC48, 6 X 6 MM, 0.40 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, QFN-48
ONSEMI
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