NCP3237MNTXG [ONSEMI]
8 A Integrated Synchronous Buck Regulator;
| 型号： | NCP3237MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | 8 A Integrated Synchronous Buck Regulator |
| 文件： | 总15页 (文件大小：958K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MARKING
DIAGRAM
8 A Integrated Synchronous
Buck Converter
1
3237
ALYWG
G
NCP3237
QFN18 3.5x3.5, 0.5P
CASE 485FR
The NCP3237 is a single−phase synchronous buck converter that
integrates power MOSFETs to provide a high−efficiency and
compact−footprint power management solution. This device is able to
deliver up to 8 A output current over a wide output voltage range from
0.6 V to 12 V (up to 80% of V ). The NCP3237 offers a fixed
frequency regulator ideally suited for noise sensitive systems.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
IN
= Pb−Free Package
(Note: Microdot may be in either location)
Features
• V = 4.5 V ~ 16 V
IN
PINOUT DIAGRAM
• V
= 0.6 V ~ 0.80*V and up to 12 V
IN
OUT
• Integrated Power MOSFETs
• Up to 8 A Output Current
• Integrated 5 V LDO
• Programmable Switching Frequency from 300 kHz to 1.2 MHz
• Forced CCM
• Both High−side and Low−side OCP Operation
• Hiccup Over−Current Protection
• Hiccup Over−Voltage and Under−Voltage Protection
• Recoverable Thermal Shutdown Protection
• 3.5 mm x 3.5 mm, QFN18 Package
• Safe Startup into Pre−biased Output Voltage
• This is a Pb−Free Device
(Top View)
Typical Application
• Base Station Radio Units
• Point of Load
• Telecom and Networking
• Server and Storage System
ORDERING INFORMATION
†
Device
Package
Shipping
NCP3237MNTXG
QFN18
3000 /
(Pb−Free)
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
November, 2022 − Rev. 4
NCP3237/D
NCP3237
VIN
BST
VIN
PGND
VOUT
FSET
SW
NCP3237
VCC
AGND
PGOOD
PGOOD
EN
FB
ENABLE
COMP
Figure 1. Typical Application Circuit
BST
VIN
SW
LDO
Gate Drive
PGN
D
VCC
EN
UVLO
&
Protections
&
Power Good
PWM
FB
PGO
OD
PWM
Control
Programming Detection
Vref
COM
P
&
Soft Start
AGN
D
FSET
Figure 2. Functional Block Diagram
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2
NCP3237
PIN DESCRIPTION
Pin
Name
Type
Description
1
BST
Power
Bidirectional
Bootstrap. Provides bootstrap voltage for the high−side gate driver. A 0.1 mF ~ 1 mF ceramic
capacitor is required from this pin to SW.
2, 11
VIN
Power Input
Power Supply Input. Power supply input pin of the device, which is connected to drain of
internal high−side power MOSFET. Ceramic capacitors must bypass this input to power
ground. The capacitors should be placed as close as possible to this pin.
3, 4, 5, 8,
9, 10
PGND
SW
Power Ground
Power Output
Power Ground. These pins are the power supply ground pins of the device, which are con-
nected to source of internal low−side power MOSFET.
6, 7
Switching Node. Pins to be connected to an external inductor. These pins are intercon-
nection between internal high−side MOSFET and low−side MOSFET.
12
13
14
15
16
AGND
FSET
FB
Analog Ground Analog Ground. Signal reference ground for the IC. Must be connected to the power ground.
Analog Input
Analog Input
Analog Output
Analog Power
Frequency Option. A resistor from this pin to AGND programs switching frequency.
Feedback. Inverting input to error amplifier.
COMP
VCC
Compensation. Output pin of error amplifier.
Voltage Supply of Controller. Power supply input pin of control circuits. A 4.7 mF or larger
ceramic capacitor bypasses this input to AGND. This capacitor should be placed as close as
possible to this pin.
17
18
EN
Logic Input
Enable. Logic high enables the device and logic low shuts down the device.
PGOOD
Logic Output
Power Good. Open−drain output. Provides a logic high valid power good output signal, indi-
cating the regulator’s output is in regulation window.
MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
V
Power Supply Voltage to PGND
Switch Node to PGND
V
IN
−0.3
17
V
SW
−0.3
−3 (<10ns)
17
V
22 (<10ns)
Analog Supply Voltage to GND
BST to PGND
V
−0.3
−0.3
6.0
V
V
CC
BST_PGND
22
28 (<10ns)
BST to SW
BST_SW
FB
−0.3
−0.3
−0.3
−0.3
−0.3
−40
6.0
6.0
0.3
0.3
V
V
FB to AGND
AGND to PGND
V
Exposed Pad to PGND
Other Pins
V
V
+0.3
V
CC
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
T
J
150
°C
°C
°C
_C/W
T
A
−40
150
150
T
STG
−55
Thermal Characterization Parameter, Junction to Top Case
(Note 1)
R
2
Ψ
JC
Thermal Resistance Junction to Bottom Case/Leads (Note 1)
Thermal Resistance Junction to Ambient (Note 1)
R
R
3.3
31
4
_C/W
_C/W
W
θ
JC
JA
D
θ
Power Dissipation at T = 25°C (Note 2)
P
A
ESD Capability, Human Body Model per JESD22−A114
ESD Capability, Charged Device Model per JESD22−C101
ESD
ESD
2
kV
HBM
CDM
1
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and
2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors etc.)
2. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on T
= 150°C and R
= 31°C/W.
θ
JMAX
JA
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NCP3237
RECOMMENDED OPERATING RANGE
Rating
Symbol
Min
4.5
0.6
0
Max
16
Unit
V
Input Voltage
V
IN
Output Voltage
V
12
V
OUT
OUT
Output Current, Continuous
Junction Temperature (Note 3)
I
8
A
T
J
−40
130
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Device specifications tested and characterized for 150°C operation with the Tsd function disabled.
ELECTRICAL CHARACTERISTICS
(V = 12V, typical values are referenced to T = 25°C, Min and Max values are referenced to T = −40°C to 150°C. unless otherwise noted.)
IN
J
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Units
SUPPLY VOLTAGE MONITOR
VCC Under−Voltage (UVLO)
VCC falling
VCC rising
V
V
3.7
3.88
V
CCUV
Threshold
VCC OK Threshold
VCC UVLO Hysteresis
SUPPLY CURRENT
4.15
269
4.3
V
CCOK
V
mV
CCHYS
V
Quiescent Supply Cur-
EN high, V = 600 mV, Non−switching
I
QIN
6.1
65
9.5
mA
IN
FB
rent
V
IN
Shutdown Current
EN low
I
115
mA
SD_IN
VCC
Output Voltage
6V < VIN < 16V, IVCC = 20mA, EN High
(Note 4)
V
4.85
5.0
5.15
3.0
V
CC
Load Regulation
6V < VIN < 16V, IVCC = 5mA to 50mA, EN
High (Note 4)
V
V
−3.0
%
CC_LOR
Dropout Voltage
VIN = 5V, IVCC = 50mA, EN High (Note 4)
FSW < 600 kHz
260
mV
nF
DC_VCC
LDO_EFF
680
840
Effective Capacitance of
VCC Bypass Capacitor
C
FSW ≥ 600 kHz
ENABLE
EN High Threshold
EN Low Threshold
EN Input Impedance
SOFT START
Normal Operation
V
1.6
V
V
H_EN
Shutdown
V
1.2
L_EN
Resistance from EN pin to AGND
R
1.5
MW
EN
System Reset Time
BST Refresh Time
Soft Start Slew Rate
From EN High to BST Refresh (Note 5)
T
0.8
10
ms
ms
RST
T
BST
Refer to Internal VREF
From Beginning of SS until PGOOD Asserts
SR
0.55
0.6
0.68
mV/ms
SS
PGOOD
PGOOD Startup Delay
Measured from end of Soft Start to PGOOD
Assertion (Note 5)
T
100
1
ms
d_PGOOD
PGOOD Shutdown Delay
PGOOD Low Voltage
Measured from EN to PGOOD de−assertion
ms
V
I
= −4 mA
V
0.3
1.0
PGOOD
I_PGOOD
PGOOD Leakage Current
SWITCHING FREQUENCY
Switching Frequency in CCM
VOLTAGE REGULATION
Regulated Feedback Voltage
PGOOD = 5 V
I
mA
lkg_PGOOD
1% 40.2 kW Resistor from FSET Pin to AGND
F
SW
495
550
605
kHz
mV
EN = High
0°C to 85°C
−40°C to 150°C
V
FB
595
594
600
600
605
606
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NCP3237
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, typical values are referenced to T = 25°C, Min and Max values are referenced to T = −40°C to 150°C. unless otherwise noted.)
IN
J
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Units
PWM MODULATION
PWM Ramp Amplitude
Minimum On Time
(Note 5)
(Note 5)
V
V
/8
V
RAMP
IN
T
50
68
ns
ns
on_min
Minimum Off Time, absolute
VOLTAGE ERROR AMPLIFIER
Open−Loop DC Gain
Unity Gain Bandwidth
Slew Rate
(Note 5) (Note 6)
T
160
200
off_min
(Note 5)
(Note 5)
(Note 5)
GAIN
94
11
9
100
14
dB
MHz
V/ms
V
EA
GBW
EA
SR
15
COMP
I
I
(source) = 2 mA
V
2.6
3
COMP Voltage Swing
COMP
COMP
maxCOMP
(sink) = 2 mA
= 0.6 V
V
0.75
0.89
100
minCOMP
FB Bias Current
V
V
V
I
FB
−100
18
nA
mA
mA
FB
FB
FB
COMP Max Sourcing
COMP Max Sinking
HIGH−SIDE MOSFET
= 0.5 V
I
COMP(source)
COMP(sinking)
= 0.7 V
I
10
Drain−to−Source
BST − SW = 5 V, T = T = 25°C
R
ON_H
10.5
5.2
mW
mW
A
A
J
ON Resistance
LOW−SIDE MOSFET
Drain−to−Source
ON Resistance
V
CC
= 5 V, T = T = 25°C
R
ON_L
A
J
PROTECTIONS
High−side Current Limit
Low−side Current Limit
I
_
11
10
13
12
−6
16
15
Over Current Threshold
LMT HS
I
_
LMT LS
Negative Over Current
Threshold
Low−side negative current limit
I
_
_
−10
A
LMT LS NEG
Under Voltage Protection
(UVP) Threshold
Voltage from FB to GND
V
350
20
mV
mV
ms
UVTH
Under Voltage Protection
(UVP) Hysteresis
V
UVHYS
Under Voltage Protection
(UVP) Debounce Time
t
2
D_UVTH
Over Voltage Protection
(OVP) Threshold
Voltage from FB to GND
V
750
30
mV
mV
ms
OVTH
OVHYS
D_OVTH
Over Voltage Protection
(OVP) Hysteresis
V
Over Voltage Protection
(OVP) Debounce Time
t
1
Thermal Shutdown (TSD)
Threshold
(Note 5)
(Note 5)
T
133
116
°C
sd
Recovery Temperature
Threshold
T
rec
°C
BOOTSTRAP
On Resistance of Rectifier
Switch
V
VCC
= 5 V, Id = 2 mA, T = T = 25°C
R
BST
40
W
A
J
Rectifier Switch Leakage
Current
I
1.1
mA
lkgBST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Not for external usage
5. Guaranteed by Design and/or Characterization. Not Production Tested
6. For most applications, the observed off−time will be over−ridden by the 80% duty cycle limit.
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NCP3237
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= 12 V, V
= 1.8 V, Fsw = 550 kHz, L = 1 mH (TDK, SPM6550T−1R0M100A),
OUT
C
= 4x 47 mF + 0.1 mF, T = 25°C, unless otherwise indicated.
A
OUT
Figure 3. Efficiency vs. Load Current and
Output Voltage
Figure 4. Efficiency vs. Load Current and Input
Voltage
Figure 5. Load Regulation
Figure 6. Thermal Safe Operating Area, No
Airflow, PCB: 2 oz. Cu
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NCP3237
TYPICAL PERFORMANCE CHARACTERISTICS
V
IN
= 12 V, V
= 1.8 V, Fsw = 550 kHz, L = 1 mH (TDK, SPM6550T−1R0M100A),
OUT
C
= 4x 47 mF + 0.1 mF, T = 25°C, unless otherwise indicated.
A
OUT
Figure 7. Start−up, No Load
Figure 8. Start−up With 50% Pre−bias
Figure 9. Load Transient, 2 A <−> 6 A, Slew
Rate = 1 A/ms
Figure 10. Over Current Protection, Hiccup
Mode
Figure 11. Thermal Image, No Airflow, IOUT = 8 A,
PCB: 2 oz. Cu
Figure 12. ICC vs. Switching Frequency and
Ambient Temperature
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NCP3237
DETAILED DESCRIPTION
General
Reference Voltage
NCP3237 is a single−phase synchronous buck converter
The NCP3237 incorporates an internal reference that
allows output voltage to be as low as 0.6 V. The tolerance of
the internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
with two integrated N−type power MOSFETs to provide a
high−efficiency and compact−footprint power management
solution. The device is able to deliver up to 8A output current
over a wide output voltage range from 0.6 V to 0.8 × VIN.
It has a wide input voltage range from 4.5 V to 16 V.
The NCP3237 features include resistor adjustable
frequency input to optimize the output filter size, an enable
and power good indicator for sequencing and an internal
soft−start function during the initial power up. These
devices offer safe start up into a pre−biased output condition
and offer multiple protection features including
cycle−by−cycle high side and low side over−current
limiting, output over−voltage protection (OVP), under
voltage protection (UVP) and thermal shutdown protection
(TSD). During over−current, over−voltage and
under−voltage conditions, these devices enter hiccup
protection.
Oscillator Ramp
The ramp waveform is a saw tooth formed at the PWM
frequency with a peak−to−peak amplitude of VIN/8, offset
from AGND by typically 1.0 V. The PWM duty cycle is
limited to a typical 80%, allowing the bootstrap capacitor to
charge during each cycle.
Soft Start
The NCP3237 incorporates a soft start function. The
output starts to ramp up following a system reset period
(T ) after the device is enabled. Please see Figure 13 for
RST
the timing of the soft start. The device is able to start up
smoothly with an output pre−biased voltage up to the target
VOUT level.
Operation
NCP3237 operates in forced CCM. In forced CCM, the
high−side FET is ON during the on−time and the low−side
FET is ON during the entire off−time. The switching is
synchronized to an internal clock thus the switching
frequency is fixed.
Under−Voltage Lockout (UVLO)
UVLO engages when V falls below V
and the
CC
CCUV
device shuts down. Once V
rises above V
, a
CC
CCOK
soft−start is initiated following BST refresh cycles (T ).
BST
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8
NCP3237
EN
PGOOD
Td_PGOOD
TRST
TBST
Vout
GL
SRSS
200ns
2.0us
TBST = 10us
Figure 13. Timing Diagram of Soft Start
High−side MOSFET Over−Current Protection (HSOCP)
The NCP3237 protects the converter from high−side
MOSFET over currents by employing a cycle−by−cycle
peak current limit. The high−side MOSFET current is
monitored by differential voltage sensing between VIN pin
and SW pin, and compared with the internal OCP limit value
down, the high side switch is held off, while the low side
switch remains on until a ZCD is detected. This is to prevent
the switching node going very negative which can cause
malfunction. PGOOD is pulled low upon ZCD detection.
The device implements a 6 soft−start cycle hiccup
time−out after PGOOD goes low. After the time−out, it
implements BST refresh cycles before a normal soft−start
attempt. Please see Figure 14 for the timing diagram.
The device may enter into under voltage protection before
OCP hiccup happens if the output voltage drops down very
fast.
I
. If it reaches the I
level on any given clock
LMT_HS
LMT_HS
cycle, the cycle terminates to prevent the current from
increasing any further.
If HSOCP occurs for more than 3 consecutive switching
cycles, the device shuts down and enters hiccup mode. To
prevent nuisance trips, the internal HSOCP counter adds 2
for a HSOCP event, and subtracts 1 for every normal
switching cycle (not LSOCP cycles). The counter resets
when it counts up to 6 and the device shuts down. Upon shut
HSOCP detection starts from the beginning of soft−start,
and ends in shutdown and idle time of hiccup mode.
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NCP3237
PGOOD
T
BST
HSOCP trip level
LSOCP trip level
T
SS
T
= 6T
SS
hiccup_HSOCP
Inductor
Current
HSOCP Asserted
1 cycle
GH
GL
GH = L
GL−>L @ZCD
Extended
cycle
+2
+2
OCP Detection
+2
+2
−1
−1
Reset
HSOCP
Counter
Time−out
SS
Figure 14. Timing Diagram of High−Side Over Current Protection
Low−side MOSFET Over−Current Protection (LSOCP)
The NCP3237 protects the converter from low−side
MOSFET over current utilizing a cycle−by−cycle current
limit. The low−side MOSFET current is monitored by
voltage sensing between SW pin and PGND pin, and
when it counts up to 8 and the device shuts down. Upon shut
down, the high side switch keeps off all the time, while the
low side switch keeps on until a ZCD is detected. This is to
prevent the switching node going very negative which can
cause malfunction. PGOOD is pulled low upon ZCD
detection.
compared with the internal OCP limit value I . If it is
LMT_LS
higher than I
level on any given clock cycle, the
LMT_LS
high−side MOSFET will not be turned on and the low−side
MOSFET stays on for the next switching cycle. The
high−side MOSFET is turned on again only when the
low−side current is below the OCP limit value during the
previous switching cycle.
If LSOCP occurs for more than 4 consecutive switching
cycles, the device shuts down and enters hiccup mode. To
prevent nuisance trips, the internal LSOCP counter adds 2
for a LSOCP event, and subtracts 1 for every normal
switching cycle (not extended cycles). The counter resets
The device implements a 4 soft−start cycle time−out after
PGOOD goes low. After the time−out, it implements BST
refresh cycles before a normal soft−start attempt. Please see
Figure 15 for the timing diagram.
The device may enter into under voltage protection before
OCP hiccup happens if the output voltage drops down very
fast.
LSOCP detection starts from the beginning of the soft
start time, and ends in shutdown and idle time of hiccup
mode.
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NCP3237
PGOOD
T
BST
HSOCP trip level
LSOCP trip level
T
= 4T
SS
hiccup_OCP
T
SS
Inductor
Current
1 cycle
LSOCP Asserted
Skipped
HS on
GH
GL
GH = L
GL−>L @ZCD
Extended
cycle
LSOCP
Counter
+2
+2
−1
−1
+2
+2
+2
Reset
Time out
OCP Detection
SS
Figure 15. Timing Diagram of Low−Side Over Current Protection
Under Voltage Protection (UVP)
NCP3237 monitors the FB voltage to detect a UVP event.
from when PGOOD goes low. After the time−out, it
implements BST refresh cycles before a normal soft−start
attempt. Please see Figure 16 for the timing diagram.
A UVP is asserted once FB voltage drops below V
for
UVTH
more than UVP debounce time (t
). When UVP is
D_UVTH
asserted, it turns off the high side FET, and keep the low−side
FET on until a ZCD is detected. PGOOD is pulled low upon
ZCD detection. It implements a 5 soft−start cycle time−out
UVP detection starts when PGOOD delay T
expired right after a soft start, and ends in shutdown and idle
time of hiccup mode.
is
d_PGOOD
FB
UVP
threshold
GH = L
GL->L @ZCD
< UVP
debounce
time
UVP
debounce
time
T
BST
T
hiccup
T
SS
GND
PGOOD
Delay
PGOOD = L
ZCD
PGOOD
Figure 16. Timing Diagram of Non−latched Under Voltage Protection
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NCP3237
Over Voltage Protection (OVP)
During normal operation the output voltage is monitored
at the FB pin. If FB voltage exceeds the OVP threshold
negative over current protection trips, the low−side
MOSFET turns off and stays off for at least 640 ns. If the
OVP is still not cleared, the low−side MOSFET will turn on
again. The OVP threshold is set to a fixed value of Vovth.
After the OVP gets asserted, NCP3237 implements an 8
normal soft−start cycle time−out. Then it is followed by BST
refresh cycles before a normal soft−start attempt. Please see
Figure 17 for the timing diagram.
(V
)for more than t
, OVP is triggered and
OVTH
D_OVTH
PGOOD is pulled low. In the meanwhile, the high−side
MOSFET is latched off and the low−side MOSFET is turned
on. After the OVP trips, the DAC immediately goes down
to zero. The low−side MOSFET current would become
negative during OVP. If the low−side negative current limit
is exceeded, the low−side MOSFET is turned off
immediately. In this scenario, both MOSFETs are off. After
OVP detection starts from the beginning of the soft start
and ends in shutdown and idle time of hiccup mode.
OVP threshold
FB
PGOOD=L
GH=L
GL->L @NOCP
OVP
debounce
time
DAC
< OVP
debounce
time
DAC
ramp
Thiccup_OVP=8Tss
TBST
down
OVP
triggered
TSS
Tss
GND
Figure 17. Function of Non Latch−Off Over Voltage Protection
Thermal Shutdown (TSD)
Switching Frequency
The NCP3237 has an internal thermal shutdown
protection to protect the device from overheating in an
extreme case that the die temperature exceeds Tsd. TSD
detection starts from the beginning of soft−start. Once the
thermal protection is triggered, the whole chip shuts down.
If the temperature drops below Trec, the system
automatically recovers and a normal soft−start sequence
follows.
The NCP3237 provides programmable switching
frequency in the range of 300 kHz to 1.2 MHz. The
switching frequency can be programmed through the
resistor from the FSET pin to AGND. The switching
frequency is calculated by:
40 kW
RFSET
+ ǒ Ǔ@ 550 kHz
FSW
The default switching frequency is set at 550 kHz typical
with a 40.2 kW resistor. 1% resistors are recommended to be
used.
Power Good Monitor (PGOOD)
The NCP3237 provides a window comparator to monitor
the voltage at FB pin. The open−drain PG goes high when
the device is operating in a normal operating condition (no
UVLO, UVP, OVP, OCP or TSD faults). Connect a pull up
resistor to VCC for simplicity or to an external voltage to
interfacing to another logic rail such as 3.3 V. When a fault
occurs, PGOOD goes low. Choose a pull up to limit the sink
current to 4 mA. During soft start, PGOOD stays low until
the feedback voltage is within the specified range for about
100 ms. The PGOOD pin de−asserts as the EN pin pulled low
for 1 ms. For an under−voltage event on VCC, PGOOD goes
low immediately.
External VCC Supply
The NCP3237 can operate with an external voltage supply
to the VCC pin in place of the internal LDO. When operating
with V > 5 V, a constant voltage greater than 5.15 V
IN
(recommended 5.2 V) must be supplied to the VCC pin to
override the internal LDO output. To prevent forward
biasing the LDO body diode, V must be always greater
IN
than the external VCC.
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12
NCP3237
LAYOUT GUIDELINES
Electrical Layout Considerations
Good electrical layout is a key to ensure proper operation,
high efficiency, and noise reduction.
• Ground: It would be good to have separated ground
planes for PGND and AGND and connect the AGND
planes to the exposed pad GND through vias.
• Power Paths: Use wide and short traces for power
paths (such as VIN, VOUT, SW, and PGND) to reduce
parasitic inductance and high−frequency loop area. It is
also good for efficiency improvement.
• Power Supply Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to VIN and PGND pins.
• Voltage Sense: Route a “quiet” path for the output
voltage sense. AGND could be used as a remote ground
sense when differential sense is preferred.
• Compensation Network: The compensation network
should be close to the NCP3237. Keep FB trace short to
minimize it capacitance to ground.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small−form factor VR with reduced temperature rise.
• The exposed pads must be well soldered on the board.
• VCC Decoupling: Place decoupling caps as close as
possible to VCC pin. The filter resistor at VCC pin
should be not higher than 4.7 W to prevent large voltage
drop.
• Output Decoupling: The output capacitors should be
as close as possible to the load. If the load is
distributed, the capacitors should also be distributed
and generally placed in greater proportion where the
load is more dynamic.
• Switching Node: SW node should be a copper pour,
but compact because it is also a noise source.
• Bootstrap: The bootstrap cap and an option resistor
need to be very close and directly connected between
pin 17 (BST) and pin 16 (SW).
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN18 3.5x3.5, 0.5P
CASE 485FR
ISSUE O
DATE 28 MAR 2018
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84703G
QFN18 3.5x3.5, 0.5P
PAGE 1 OF 1
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