NCP3284AMNTXG [ONSEMI]

Single-Phase Voltage Regulator;


型号：	NCP3284AMNTXG
厂家：	ONSEMI
描述：	Single-Phase Voltage Regulator
文件：	总13页 (文件大小：383K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Single-Phase Voltage

Regulator

High Efficiency, Integrated Power MOSFETs

NCP3284, NCP3284A

The NCP3284/A, a single−phase synchronous buck regulator,

integrates power MOSFETs to provide a high−efficiency and

compact−footprint power management solution. The NCP3284 is able

to deliver up to 30 A TDC output current, 35 A TDC for NCP3284A,

over a wide input and output operating voltage range. Operating in

high switching frequency up to 1 MHz allows employing small size

inductors and capacitors while maintaining high efficiency due to

integrated solution with high performance power MOSFETs. It

provides differential voltage sense, flexible soft−start programming,

and comprehensive protections.

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MARKING

DIAGRAM

NCP3284x

AWLYWWG

PQFN37 5x6, 0.5P

CASE 483BZ

Features

• V = 4.5 V ~ 18 V with Input Feedforward

= Assembly Site

= Wafer Lot Number

= Year of Production

= Work Week Number

= Pb−Free Designator

• V

= 0.8 V ~ 5.5 V with Remote Voltage Sense

OUT

• Fsw = 500k/600k/800k/1 MHz Switching Frequency

• Output Current: NCP3284 up to 30 A Continuous, 45 A Pulsed

Output Current: NCP3284A up to 35 A Continuous, 50 A Pulsed

• Integrated 5 V LDO or External 5 V Supply

PINOUT

• Enable with Programmable V UVLO

• Selectable Forced CCM and Auto DCM/CCM for High Efficiency at

Light Load

• Programmable Soft Start

ILIM

VOS

• Output Discharge in Shutdown

PGOOD

27 EN

• Programmable Current Limit

VIN

BOOT

• Under−Voltage Protection and Over−Voltage Protection

• Recoverable Thermal Shutdown Protection

• Selectable Protection Mode (Latch−off or Hiccup)

• Power Good Indicator

VCC

25 PHASE

24 PVIN

23 PVIN

22 PVIN

VDRV

PGND

PVIN

PGND

• PQFN37, 5x6 mm, 0.5 mm Pitch Package

• This Device is Pb−Free and is RoHS Compliant

PVIN

PGND

PVIN

PGND

Typical Applications

• Point of Load

• Telecom and Networking

• Server and Storage System

• Computing Applications

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information on page 11 of

this data sheet.

Publication Order Number:

February, 2021 − Rev. 7

NCP3284/D

NCP3284, NCP3284A

VIN

PVIN

VIN

PGND

BOOT

VDRV

VCC

PHASE

VOUT

NCP3284/A ^SW

AGND

PGOOD

VSNS −

VOS

MODE/

FSET

ILIM

Figure 1. Typical Application Circuit with Single Input Power Supply (LDO Enabled)

+5V

VIN

PVIN

VIN

PGND

VDRV

VCC

BOOT

PHASE

VOUT

NCP3284/A

AGND

PGOOD

VSNS −

VOS

MODE/

FSET

ILIM

Figure 2. Typical Application Circuit with External 5 V Supply for VCC (LDO Disabled)

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NCP3284, NCP3284A

VIN

BOOT

PHASE

MOSFETs

VDRV

PVIN

LDO

VDRV

Gate Drive

VDRV

Vref

VCC

PGND

Gate Driver

Control Logic

Protections

PWM

VR Ready

EN_INT

PGOOD

Soft Start

Vref

HICC

UP#

PWM

Control

COMP

VSNS

−

VIN

AGND

VOS

MODE

/FSET

Controller

Programming

Detection

ILIM

Figure 3. Functional Block Diagram

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NCP3284, NCP3284A

PIN DESCRIPTION

Name

ILIM

Type

Description

Analog Output

Logic Output

Current Limit. A resistor between this pin and AGND to program current limit.

PGOOD

Power Good. Open−drain output. Provides a logic high valid power good output

signal, indicating the regulator’s output is in regulation window.

VIN

Power Input

Power Supply Input of LDO. Power supply input pin of internal 5 V LDO. A 1.0 mF

or more ceramic capacitor must bypass this input to power ground.

The capacitor should be placed as close as possible to this pin. A direct short

from this pin to VDRV (pin 5) disables the internal LDO for applications with an

external 5 V supply as power of VDRV and VCC.

VCC

Analog Power

Supply Voltage Input of Controller. A 2.2 mF or larger ceramic capacitor bypasses

this input to GND. This capacitor should be placed as close as possible to this pin.

VDRV

Output of LDO and Supply Voltage Input of Gate Drivers. Output of integrated

5.0 V LDO and power supply input of gate drivers. A 4.7 mF/25 V or larger

ceramic capacitor bypasses this pin to PGND. The capacitor should be placed as

close as possible to this pin.

Analog Output

Power Ground

Gate of Low−Side MOSFET. Internally connected to the gate of the low−side

power MOSFET. No external connection required.

7~10,19

PGND

Power Ground. These pins are the power supply ground pins of the device, which

are connected to source of internal low−side power MOSFET. Must be connected

to the system ground.

11~18

20~24

Power

Switch Node. Pins to be connected to an external inductor. These pins are

Bidirectional

interconnection between internal high−side MOSFET and low−side MOSFET.

PVIN

Power Input

Power Supply Input. These pins are the power supply input pins of the device,

which are connected to drain of internal high−side power MOSFET. A 22 mF or

more ceramic capacitor must bypass this input to PGND. The capacitors should

be placed as close as possible to these pins.

PHASE

BOOT

Power Return

Phase Node. Provides a return path for integrated high−side gate driver.

It is internally connected to source of high−side MOSFET.

Power

Bidirectional

Bootstrap. Provides bootstrap voltage for high−side gate driver. A 0.22 mF/25 V

ceramic capacitor is required from this pin to PHASE (pin 25).

Logic Input

Analog Input

Enable. Logic high enables controller while logic low disables controller. Input

supply UVLO can be programmed at this pin.

VOS

Voltage Sense. Remote output voltage sense. Connect to VOUT through 1 kW

series resistor.

Soft Start. A resistor between this pin and GND to program the soft−start slew

rate and options.

Analog Input

Feedback. Inverting input to error amplifier.

VSNS−

Voltage Sense Negative Input. Connect this pin to remote voltage negative sense

point.

AGND

Analog Ground Analog Ground. Ground of controller. Must be connected to the system ground.

33~34

−

No Connection.

HICCUP#

Analog Input

Latch−Off / Hiccup#. Float this pin to enable latch−off mode protections (OCP/

UVP/OVP); Ground this pin to ground to enable hiccup mode protections.

MODE/FSET

Analog Input

Mode and Frequency Set. A resistor between this pin and AGND to program

operation mode and nominal switching frequency.

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NCP3284, NCP3284A

MAXIMUM RATINGS

Value

MIN

MAX

Rating

Symbol

Unit

Power Supply Voltage to PGND

PHASE/SW to PGND

, V

VIN

PVIN

, V

−0.6

−5 (<50 ns)

PHASE

28 (<10 ns)

PVIN to SW/PHASE

−0.3

−5 (<10 ns)

PVIN_SW

33 (<10 ns)

Driver Supply Voltage to PGND

Analog Supply Voltage to AGND

BOOT to PGND

−0.3

5.5

6.5

VDRV

VCC

BOOT_PGND

33 (<10 ns)

BOOT to PHASE/SW

GL to PGND

BOOT_PHASE/SW

−0.3

6.5

−0.3

−2 (<200 ns)

VDRV+0.3

VSNS− to AGND

VSNS−

−0.2

−0.3

0.2

0.3

PGND to AGND

PGND

Other Pins

VCC+0.3

2000

100

Human Body Model (HBM) ESD Rating are (Note 1)

Charge Device Model (CDM) ESD Rating are (Note 1)

Latch up Current: (Note 2)

ESD HBM

ESD CDM

−100

−40

−55

_C/W

Operating Junction Temperature Range

Operating Ambient Temperature Range

Storage Temperature Range

125

100

STG

150

Thermal Resistance Junction to Top Case(Note 3)

Thermal Resistance Junction to Board (Note 3)

Thermal Resistance Junction to Ambient (Note 3)

Maximum Power Dissipation (Note 4)

Moisture Sensitivity Level (Note 5)

0.8

0.9

26.7

3.75

MSL

−

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.

2. Latch up Current per JEDEC standard: JESD78 class II.

3. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based

on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and

2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference

EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as

inductors, resistors etc.)

4. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB

layout. The reference data is obtained based on T

= 125°C and T = 25°C.

JMAX

5. Moisture Sensitivity Level (MSL): IPC/JEDEC standard: J−STD−020A.

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NCP3284, NCP3284A

ELECTRICAL CHARACTERISTICS (V = 12 V, typical values are referenced to T = T = 25°C, Min and Max values are referenced

to T = T = −40°C to 125°C. unless other noted.)

Characteristics

Test Conditions

Symbol

MIN

TYP

MAX

UNITS

SUPPLY VOLTAGE MONITOR

VCC Under−Voltage (UVLO) VCC falling

4.0

DDUV−

Threshold

VCC OK Threshold

VCC rising

DDOK

4.5

VCC UVLO Hysteresis

SUPPLY CURRENT

PVIN Shutdown Current

200

DDHYS

EN low

−

4.8

3.5

SDPVIN

Quiescent Supply

EN high, no switching

EN low

LDO enabled,

6.4

QVIN

Current

VIN = 18 V, VCC = VDRV

(VCC Current Included)

LDO disabled,

VIN = VDRV = VCC = 4.5 V

−

3.5

6.4

Shutdown Current

LDO enabled,

VIN = 18 V, VCC = VDRV

SDVIN

(VCC Current Included)

T = T = 25 °C

A J

LDO disabled,

VIN = VDRV = VCC = 4.5 V

150

5 V LINEAR REGULATOR

Output Voltage

6V < VIN < 18 V, IDRV = 0 to 30 mA (External)

EN high, no switching

DRV

4.8

5.07

5.4

Dropout Voltage

VIN = 5 V, IDRV = 50 mA (External), EN high,

no switching

200

PWM MODULATION

Minimum On Time

(Note 6)

on_min

Minimum Off Time

150

off_min

VOLTAGE REGULATION

Regulated Feedback Voltage FB to VSNS−

795

800

805

VOLTAGE ERROR AMPLIFIER

FB, VSNS− Bias Current

= V

= 1.0 V

−50

VSNS−

CURRENT−SENSE AMPLIFIER

Closed−Loop DC Gain

GAIN

−10

−

V/V

MHz

−3 dB Gain Bandwidth

Input Offset Voltage

ENABLE

(Note 6)

= V

– V

(Note 6)

osCS

−500

500

osCS

PGND

EN On Threshold

rising

1.32

1.11

1.43

1.22

1.54

1.31

EN_THR

EN Off Threshold

falling

EN_TH

Hysteresis Resistance

Hysteresis Current

EN Input Leakage Current

SWITCHING FREQUENCY

HYS

5.4

EN_HYS

EN = 5 V

1.0

EN_LK

Switching Frequency in

CCM

1% Resistor from

MODE/FSET Pin to

AGND,

Vout = 5 V

(Note 6)

kHz

2.49k or 14.0k

12.1k or float

0 or 10.5k

1000

800

600

500

4.99k or 7.50k

Source Current from Mode/

FSET Pin

FSET

SOFT START

System Reset Time

Measured from EN to start of soft start

RST

0.7

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NCP3284, NCP3284A

ELECTRICAL CHARACTERISTICS (V = 12 V, typical values are referenced to T = T = 25°C, Min and Max values are referenced

to T = T = −40°C to 125°C. unless other noted.)

Characteristics

Test Conditions

Symbol

MIN

TYP

MAX

UNITS

SOFT START

Soft Start Time

1% Resistor from SS

Pin to AGND

0 or 4.53k

1.0

2.0

4.0

8.0

1.1

2.2

4.4

8.8

1.5k or 5.76k

12.1k or float

3.48k or 8.87k

Source Current from SS Pin

PGOOD

PGOOD Shutdown Delay

From EN to PGOOD de−assertion

(Note 6)

1.0

PGOOD Low Voltage

PGOOD Leakage Current

PROTECTIONS

= 4 mA Sink

0.3

1.0

PGOOD

lPGOOD

PGOOD = 5 V

lkgPGOOD

Valley Current Limit

Threshold

NCP3284

= 24.9 kW

= 21.5 kW

= 16.2 kW

= 12.1 kW

= 33.2 kW

= 30.1 kW

= 24.9 kW

= 21.5 kW

= 16.2 kW

= 12.1 kW

36.5

31.5

24.0

18.0

49.5

45.5

37.5

32.5

24.5

18.0

LIM

T = T = −40°C to 125°C

NCP3284A

(Note 6)

Valley Current Limit

Accuracy

T = 25°C

−5

OC_ACCY

T = −40°C to 125°C (Note 6)

−10

0.15

Fast Under Voltage

Protection (FUVP)

Threshold

FB to AGND

0.2

0.25

Fast Under Voltage

(Note 6)

1.0

3.0

Protection (FUVP) Delay

Slow Under Voltage

Protection (SUVP)

Threshold

COMP to GND (Note 6)

Slow Under Voltage

Protection (SUVP) Delay

(Note 6)

Over Voltage Threshold

FB rising

0.95

140

1.0

1.05

Over Voltage Protection

Hysteresis

FB falling (Note 6)

−10

Over Voltage Debounce

Time

FB rising to GL high

1.0

Hiccup Idle Time

Pin 35 is grounded (Note 6)

(Note 6)

Thermal Shutdown (TSD)

Threshold

150

°C

Recovery Temperature

Threshold

(Note 6)

rec

125

°C

Thermal Shutdown (TSD)

Debounce Time

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. Guaranteed by design, not tested in production.

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NCP3284, NCP3284A

DETAILED DESCRIPTION

General

power MOSFETs. It provides differential voltage sense,

flexible soft−start programming, and comprehensive

The NCP3284/A, a single−phase synchronous buck

regulator, integrates power MOSFETs to provide a

high−efficiency and compact−footprint power management

solution. The NCP3284/A is able to deliver up to 30 A TDC

output current on a wide output voltage range. Operating in

high switching frequency up to 1 MHz allows employing

small size inductors and capacitors while maintaining high

efficiency due to integrated solution with high performance

protections.

Operation Modes

Operation mode and switching frequency are

programmed at MODE/FSET pin with a 1% tolerance

resistor as shown in Table 1.

Table 1. MODE AND SWITCHING FREQUENCY CONFIGURATION

Resistance @ MODE/FSET Pin (W, + 1%)

Frequency (kHz)

Operation Mode

FCCM

600

1000

500

2.49k

4.99k

7.5k

FCCM

Auto CCM/DCM

FCCM

500

10.5k

12.1k

14.0k

Float

600

Auto CCM/DCM

FCCM

800

1000

800

Current−Mode RPM Operation

inductor current is continuous and the device operates in

quasi−fixed switching frequency in medium and heavy load

range, while the inductor current becomes discontinuous

and the device automatically operates in PFM mode with an

adaptive fixed on time and variable switching frequency in

light load range.

The NCP3284/A operates with the current−mode

Ramp−Pulse−Modulation (RPM) scheme. In Forced CCM

mode, the inductor current is always continuous and the

device operates in quasi−fixed switching frequency, which

has a typical value programmed by users through a resistor

at the MODE/FSET pin. In Auto CCM/DCM mode, the

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NCP3284, NCP3284A

Soft Start and Shut Down

period TRST , 0.7 ms typical, after the device is enabled.

When the device is disabled or UVLO happens, the device

shuts down immediately and both high−side and low−side

MOSFETs are off. A timing diagram of power up/down is

shown in Figure 4.

The NCP3284/A has a soft start function which also

operates well under a pre−biased output condition. The

NCP3284/A’s soft start time is externally programmed at SS

pins. The output starts to ramp up following a system reset

Enable

VDRV

T_RST

T_BST

T_SS

Vout

PGOOD

GH−SW

240 ns

2.0 ms

= 10 ms

T_BST

Figure 4. Timing Diagram of Power Up/Down Sequence

Bootstrap Capacitor Voltage Refreshing

special care needs to be taken in applications with Vout

≥ 1.8 V and auto DCM/CCM mode enabled. To make sure

the bootstrap capacitor has an enough voltage level for

proper operation of high−side gate driver, there is a

minimum load requirement to limit the minimum switching

frequency not to go below 2 kHz. For a typical 5 V output

application with auto DCM/CCM mode enabled, the

minimum load current may need to be higher than 2 mA.

In the NCP3284/A, a bootstrap circuit is employed to

provide supply voltage for the high−side gate driver. An

external 0.22 mF/25 V ceramic capacitor is connected

between BOOT pin and PHASE pin to hold up the bootstrap

voltage. In order to charge up this capacitor just before a soft

start, 5 consecutive pulses are sent to GL, gate of the

low−side MOSFET, as shown in Figure 4.

In forced CCM mode, the bootstrap voltage is refreshed

cycle−by−cycle and always fully charged. However, a

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NCP3284, NCP3284A

Enable and Input UVLO

limit I

can be calculated from the programmed valley

LMT

The NCP3284/A is enabled when the voltage at EN pin is

higher than a summing voltage level of an internal threshold

current limit I

and inductor current ripple.

LMT_Valley

V_o (V_IN* V_o)

2 V_In L F_SW

I_LMT+ I_{LMT_Valley}

)

EN_TH

and a hysteresis. The hysteresis can be programmed

by an external resistor R connected to EN pin as shown in

V_o (V_IN* V_o)

2 V_IN L F_SW

Figure 5. The high threshold V

in ENABLE signal is

(eq. 7)

EN_H

+ 1.5412 R_Ilim

)

V_{EN_H}+ V_{EN_TH}) V_{EN_HYS}

(eq. 1)

where R

is resistance of the programming resistor at

Ilim

ILIM pin, V is input voltage, V is output voltage, L is

filter inductance, and F is nominal switching frequency.

OCP detection starts from the beginning of soft−start time

V_{EN_TH}

EN_Int

, and it ends in shutdown, latch−off, and hiccup idle time.

V_{EN_H}

The inductor current is monitored by voltage sensing

between the SW pin and PGND pin. If over current happens

and lasts for more than 50 ms, the device turns to either

latch−off or hiccup. The device may enter into under voltage

protection before OCP latch−off/hiccup happens if the

output voltage drops down very fast.

V_{EN_L}

ENABLE

R_EN

R_HYS

I_{EN_HYS}

Figure 5. Enable and Hysteresis Programming

Under Voltage Protection (UVP)

UVP detection starts when PGOOD delay T

The low threshold V

in ENABLE signal is

EN_L

d_PGOOD

expired right after a soft start, and it ends in shutdown,

latch−off, and hiccup idle time. The NCP3284/A pulls

PGOOD low and turns off both high−side and low−side

MOSFETs once FB voltage drops below 0.2 V for more than

1.0 ms.

V_{EN_L}+ V_{EN_TH}

(eq. 2)

(eq. 3)

The hysteresis V

EN_HYS

V_{EN_HYS}+ I_{EN_HYS} (R_HYS) R_EN

)

A UVLO function for input power supply can be

implemented at EN pin. As shown in Figure 6, the UVLO

threshold can be programmed by two external resistors. The

Over Voltage Protection (OVP)

OVP detection starts from the beginning of soft−start time

low threshold V

in V signal is

IN_L

, and it ends in shutdown, latch−off, and hiccup idle time.

R_EN1

R_EN2

During normal operation the output voltage is monitored at

the FB pin. If FB voltage exceeds the OVP threshold for

more than 1 ms, OVP is triggered and PGOOD is pulled low.

Meanwhile, the high−side MOSFET is latched off and the

low−side MOSFET is turned on. After the OVP trips, the

DAC ramps slowly down to zero, having a negative slew rate

at the same value of soft start to reduce the negative output

voltage spike. The low−side MOSFET toggles between on

and off as the output voltage follows the DAC ramping

down. After the DAC gets to zero, the high−side MOSFET

holds off and the low−side MOSFET remains on.

₊ǒ Ǔ

V_{IN_L}

) 1 V_{EN_TH}

(eq. 4)

(eq. 5)

The high threshold V

in V signal is

IN_H

V_{IN_H}+ V_{IN_L}) V_{IN_HYS}

The hysteresis V

IN_HYS

R_EN1

R_EN2

ǒ ǒ_{1 )}Ǔ Ǔ

V_{IN_HYS}+ I_{EN_HYS}

R_HYS

) R_EN1

(eq. 6)

V_{IN_H}

V_{IN_L}

V_{EN_TH}

VIN

EN_Int

Latch−Off or Hiccup in Protections

The NCP3284/A can be configured to have either

latch−off mode or hiccup mode, for the protections (OCP,

UVP, and OVP), by means of leaving pin 35 float or shorting

it to ground.

R_EN1

R_HYS

R_EN2

I_{EN_HYS}

To restart the device after latch−off, the system needs to

cycle either VCC or EN to an off state, then restore, before

a normal power−up sequence follows including system reset

and auto calibration.

Figure 6. Enable and Input Supply UVLO Circuit

If hiccup mode is selected, the NCP3284/A starts to count

idle time of 32 ms once PGOOD is pulled low due to any of

the protections. After the end of the hiccup idle time, a

normal power up sequence occurs, including system reset

and auto calibration.

To avoid undefined operation, EN pin should not be left

floating in applications.

Over Current Protection (OCP)

The NCP3284/A protects the converter from over current

using a cycle−by−cycle current limit. The average current

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NCP3284, NCP3284A

Thermal Shutdown (TSD)

The NCP3284/A has an internal thermal shutdown

protection to protect the device from overheating in an

• VCC Decoupling: Place decoupling caps as close as

possible to the controller VCC and VDRV pins. The

filter resistor at the VCC pin should not be higher than

2.2ĂW to prevent large voltage drops.

• Switching Node: SW node should be a copper pour, but

compact because it is also a noise source

• Bootstrap: The bootstrap cap and optional resistor need

to be very close and directly connected between pin 26

(BST) and pin 25 (PHASE). No need to externally

connect pin 25 to SW node because it has been

internally connected to other SW pins.

• Ground: It is good to have multiple layers of GND

planes on the PCB. Directly connect the exposed

PGND pad to GND planes through multiple vias.

Connect AGND pin to GND planes through a via close

to the AGND pin.

extreme case that the die temperature exceeds 150°C. T

detection is activated when VCC and EN are valid. Once the

thermal protection is triggered, the whole chip shuts down.

If the temperature drops below 125°C, the system

automatically recovers and a normal power−up sequence

follows.

Power Good (PGOOD)

PGOOD is asserted in normal operation after soft start

ends, and it is pulled low in protections and shutdown. The

PGOOD pin is an open−drain pin and its internal pull−down

control circuit is powered by VCC. To avoid an invalid

PGOOD indication when VCC is not ready, it is

recommended to have the external pull−up resistor at the

PGOOD pin connected to VCC. If VCC is provided by an

external source, it should be applied prior to VIN to avoid

erroneous PGOOD glitches.

• Voltage Sense: Use a Kelvin sense pair and arrange a

“quiet” path for the differential output voltage sense.

Keep the FB trace short to minimize its capacitance to

ground.

LAYOUT GUIDELINES

Thermal Layout Considerations

Electrical Layout Considerations

Good thermal layout helps high power dissipation from a

small package with reduced temperature rise. Thermal

layout guidelines are:

Good electrical layout is key to ensure proper operation,

high efficiency, and noise reduction. Electrical layout

guidelines are:

• Power Paths: Use wide and short traces for power paths

(such as VIN, VOUT, SW, and PGND) to reduce

parasitic inductance, high−frequency loop area, and

undesirable copper losses.

• Power Supply Decoupling: The device should be well

decoupled by input capacitors and input loop area

should be as small as possible to reduce parasitic

inductance, input voltage spike, and noise emission.

Usually, a small low−ESL MLCC is placed very close

to PVIN and PGND pins

• The exposed pads must be well soldered to the board.

• A four or more layers PCB board with solid ground

planes is preferred for better heat dissipation.

• More free vias are welcome around the IC and

underneath the exposed pads to connect the inner

ground layers to reduce the IC thermal impedance path.

• Use large area copper pours to help thermal conduction

and radiation.

• Do not put the inductor too close to the IC, thus the heat

sources are distributed.

DEVICE ORDERING INFORMATION

†

Device

NCP3284MNTXG

NCP3284AMNTXG

Current

30 A

Package

Shipping

PQFN37

(Pb−Free)

2500 / Tape & Reel

35 A

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

PQFN37 5x6, 0.5P

CASE 483BZ

ISSUE O

DATE 13 DEC 2017

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON66497G

PQFN37 5X6, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

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NCP3284AMNTXG [ONSEMI]

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