NCP382HD05AAR2G [ONSEMI]
Fixed Current-Limiting Power-Distribution Switches; 固定限流配电开关
| 型号： | NCP382HD05AAR2G |
| 厂家： | 
ONSEMI |
| 描述： | Fixed Current-Limiting Power-Distribution Switches |
| 文件： | 总12页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP382
Fixed Current-Limiting
Power-Distribution
Switches
The NCP382 is a single input dual outputs high side
power−distribution switch designed for applications where heavy
capacitive loads and short−circuits are likely to be encountered. The
device includes an integrated 80 mW, P−channel MOSFET. The
device limits the output current to a desired level by switching into a
constant−current mode when the output load exceeds the current−limit
threshold or a short is present. The current−limit threshold is internally
fixed. The power−switches rise and fall times are controlled to
minimize current ringing during switching.
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MARKING
DIAGRAMS
1
XXXXX
XXXXX
ALYWG
G
1
DFN8 3x3
CASE 506BW
The FLAG logic output asserts low during overcurrent or
overtemperature conditions. The switch is controlled by a logic enable
input active high or low.
8
1
Features
8
XXXXXX
ALYWX
G
• 2.5 V – 5.5 V Operating Range
• 80 mW High−Side MOSFET
• Current Limit: Fixed 500 mA, 1 A, 1.5 A and 2 A
• Undervoltage Lock−Out (UVLO)
• Soft−Start Prevents Inrush Current
• Thermal Protection
1
SOIC−8 NB
CASE 751
XXXXX = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
• Soft Turn−Off
= Year
• Enable Active High or Low (EN or EN)
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• Compliance to IEC61000−4−2 (Level 4)
♦ 8.0 kV (Contact)
♦ 15 kV (Air)
• UL Listed − File No. E343275
• IEC60950 − Edition 2 − Amendment 1 Certified (CB Scheme)
• These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Typical Applications
• Laptops
• USB Ports/Hubs
• TVs
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
February, 2012 − Rev. 8
NCP382/D
NCP382
USB
DATA
D+
D−
VBUS
GND
USB INPUT
5V
USB
Port
OUT1
IN
Rfault
1 mF
NCP382
120 mF
100 kW
USB
DATA
FLAG1
FLAG1
EN1
EN1
D+
D−
VBUS
GND
FLAG2
EN2
USB
Port
FLAG2
EN2
OUT2
GND
120 mF
Figure 1. Typical Application Circuit
1
2
3
4
8
GND
IN
FLAG1
OUT1
OUT2
FLAG2
GND
IN
FLAG1
OUT1
OUT2
FLAG2
1
2
3
4
8
7
6
5
7
6
5
DFN8
SOIC−8
EN1
EN2
EN1
EN2
(Top View)
Figure 2. Pin Connections
PIN FUNCTION DESCRIPTION
Pin Name
EN1
Type
Description
I
I
Enable 1 input, logic low/high (i.e. EN or EN) turns on power switch.
Enable 2 input, logic low/high (i.e. EN or EN) turns on power switch.
Ground connection.
EN2
GND
IN
P
P
Power−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to
the IC.
FLAG1
FLAG2
OUT1
O
O
O
Active−low open−drain output 1, asserted during overcurrent or overtemperature conditions. Connect a 10 kW or
greater resistor pull−up, otherwise leave unconnected.
Active−low open−drain output 2, asserted during overcurrent or overtemperature conditions. Connect a 10 kW or
greater resistor pull−up, otherwise leave unconnected.
Power−switch output1; connect a 1 mF ceramic capacitor from OUT1 to GND, as close as possible to the IC.
This minimum value is recommended for USB requirement in terms of load transient response and strong short
circuits.
OUT2
O
Power−switch output2; connect a 1 mF ceramic capacitor from OUT2 to GND, as close as possible to the IC.
This minimum value is recommended for USB requirement in terms of load transient response and strong short
circuits.
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2
NCP382
MAXIMUM RATINGS
Rating
Symbol
,V
Value
Unit
V
From IN to OUT1, From IN to OUT2 Supply Voltage (Note 1)
IN, OUT1,OUT2, EN1, EN2, FLAG1, FLAG2 (Note 1)
V
V
−7.0 to +7.0
−0.3 to +7.0
IN , OUT1 OUT2
V
V
V
V
V
V
IN, OUT1, OUT2, EN1, EN2,
V
, V
FLAG1
FLAG2
FLAG1, FLAG2 sink current
I
1.0
mA
kV
SINK
ESD Withstand Voltage (IEC 61000−4−2) (output only, when
bypassed with 1.0 mF capacitor minimum)
ESD IEC
15 Air, 8 contact
Human Body Model (HBM) ESD Rating are (Note 2)
Machine Model (MM) ESD Rating are (Note 2)
ESD HBM
ESD MM
LU
2000
200
V
V
Latch−up protection (Note 3)
− Pins IN, OUT1, OUT2, FLAG1, FLAG2
− EN1, EN2
mA
100
Maximum Junction Temperature (Note 4)
Storage Temperature Range
T
−40 to + TSD
−40 to + 150
Level 1
°C
°C
J
T
STG
Moisture Sensitivity (Note 5)
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) +/−200 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: $100 mA per JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol
Parameter
Operational Power Supply
Enable Voltage
Conditions
Min
2.5
0
Typ
Max
5.5
5.5
+85
1
Unit
V
IN
V
V
ENX
T
A
Ambient Temperature Range
FLAG sink current
−40
25
°C
mA
mF
I
SINK
C
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction−to−Air
1
IN
C
USB port per Hub
120
mF
OUTX
R
DFN−8 package (Notes 6 and 7)
SOIC−8 package (Notes 6 and 7)
140
210
25
°C/W
°C/W
°C
q
JA
T
J
Junction Temperature Range
−40
+125
2
I
Recommended Maximum DC
current
DFN−8 package
SOIC−8 package
A
OUTX
1.5
A
P
D
Power Dissipation Rating (Note 8)
T
v 25°C
DFN−8 package
SOIC−8 package
DFN−8 package
SOIC−8 package
850
570
428
285
mW
mW
mW
mW
A
T = 85°C
A
6. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
7. The R
is dependent of the PCB heat dissipation. Announced thermal resistance is the unless PCB dissipation and can be improve with
q
JA
final PCB layout.
8. The maximum power dissipation (P ) is given by the following formula:
T
JMAX * TA
D
PD
+
RqJA
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3
NCP382
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C and T up to + 125°C for V between
A
J
IN
2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to T = + 25°C and V = 5 V.
A
IN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POWER SWITCH
R
Static drain−source on−state resistance
(SOIC−8 Package)
T = 25°C, V = 3.6 V to 5 V
80
80
110
140
95
mW
mW
ms
DS(on)
J
IN
V
= 5 V
–40°C < T < 125°C
J
IN
R
Static drain−source on−state resistance
(DFN8 Package)
T = 25°C, V = 3.6 V to 5 V
DS(on)
J
IN
V
V
= 5 V
–40°C < T < 125°C
100
1.5
1.0
0.5
0.5
IN
J
T
R
Output rise time
Output fall time
= 5 V
C
LOAD
= 1 mF,
LOAD
= 100 W (Note 9)
0.3
0.2
0.1
0.1
1.0
IN
R
V
IN
= 2.5 V
0.65
T
F
V
IN
= 5 V
V
IN
= 2.5 V
ENABLE INPUT ENx OR ENx
V
High−level input voltage
Low−level input voltage
Input current
1.2
V
IH
V
0.4
0.5
3.0
3.0
V
IL
I
V
= 0 V, V = 5 V
ENx
−0.5
1.0
mA
ms
ms
ENx
ENx
T
ON
Turn on time
C
= 1 mF, R
= 100 W (Note 9)
LOAD
LOAD
T
OFF
Turn off time
1.0
CURRENT LIMIT
I
Current−limit threshold (Maximum DC
V
V
V
= 5 V, Fixed 0.5 A
= 5 V, Fixed 1.0 A
= 5 V, Fixed 1.5 A
0.5
1.0
1.5
2
0.6
1.2
0.7
1.4
2.0
2.5
A
OCP
IN
IN
IN
output current I delivered to load)
OUTX
1.75
2.25
2.0
V
= 5 V, Fixed 2 A
IN
T
Response time to short circuit
Regulation time
V
IN
= 5 V
ms
ms
ms
DET
REG
OCP
T
T
2.0
14
3.0
4.0
26
Over current protection time
20
UNDERVOLTAGE LOCKOUT
V
V
IN pin low−level input voltage
IN pin hysteresis
V
rising
2.0
25
2.35
40
2.5
60
15
V
UVLO
HYST
IN
T = 25°C
J
mV
ms
T
Re−arming Time
V
IN
rising
5.0
10
RUVLO
SUPPLY CURRENT
I
Low−level output supply current
V
IN
= 5 V, No load on OUTX, Device OFF
2.0
3.0
mA
mA
INOFF
V
= 0 V or V
= 5 V
ENX
ENX
I
High−level output supply current
0.5 A
T = 25°C
J
95
100
INON
J
T = 85°C
1 and 1.5 A
2 A
T = 25°C
J
115
125
J
T = 85°C
T = 25°C
130
140
J
T = 85°C
J
I
Reverse leakage current
V
= 5 V,
T = 25°C
J
1.0
2.0
mA
REV
OUTX
IN
V
= 0 V
FLAG PIN
V
FLAGX output low voltage
Off−state leakage
I
= 1 mA
400
1
mV
mA
OL
FLAGX
I
V
= 5 V
0.02
6
LEAK
FLAGX
T
FLG
FLAGX deglitch
FLAGX de−assertion time due to
4
6
9
ms
overcurrent
T
FOCP
FLAGX deglitch
FLAGX assertion due to overcurrent
8
12
ms
THERMAL SHUTDOWN
T
Thermal shutdown threshold
140
125
115
°C
°C
°C
SD
T
Thermal regulation threshold
SDOCP
T
RSD
Thermal regulation rearming threshold
9. Parameters are guaranteed for C
10.DFN package only.
and R
connected to the OUTX pin with respect to the ground.
LOAD
LOAD
11. Guaranteed by characterization.
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4
NCP382
VIN
IN
OUT1
mF
1
NCP382
CLOAD
RLOAD
OUT2
CLOAD
RLOAD
GND
Figure 3. Test Configuration
50%
VENx
VENx
VOUTx
TR
TF
90%
10%
VOUTx
10%
TOFF
TON
90%
10%
Figure 4. Voltage Waveform
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5
NCP382
BLOCK DIAGRAM
Control logic
and timer
EN1
EN block
/FLAG 1
OUT1
Flag
Current
Limiter
Gate Driver
GND
Oscilator
Blocking control
Blocking control
Channel 1
Channel 2
VREF
UVLO
TSD
IN
OUT2
Current
Limiter
Gate Driver
Flag
/FLAG2
Control logic
and timer
EN block
EN2
Figure 5. Block Diagram
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6
NCP382
FUNCTIONAL DESCRIPTION
Overview
VOUTX
Timer
Regulation
Mode
Thermal
Regulation
Threshold
The NCP382 is a dual high side power distribution
switches designed to protect the input supply voltage in case
of heavy capacitive loads, short circuit or over current. In
addition, the high side MOSFETs are turned off during
undervoltage or thermal shutdown condition. Thanks to the
soft start circuitry, NCP382 is able to limit large current and
voltage surges.
IOUTX
IOCP
Overcurrent Protection
TOCP
TREG
NCP382 switches into a constant current regulation mode
Figure 8. Short−Circuit
when the output current is above the I
threshold.
OCP
Depending on the load, the output voltage is decreased
accordingly.
− In case of hot plug with heavy capacitive load, the
output voltage is brought down to the capacitor voltage.
Then, the device enters in timer regulation mode, described
in 2 phases:
− Off−phase: Power MOSFET is off during T
to allow
OCP
the die temperature to drop.
The NCP382 will limit the current to the I
threshold
OCP
− On−phase: regulation current mode during T
The
REG.
value until the charge of the capacitor is completed.
current is regulated to the I
level.
OCP
The timer regulation mode allows the device to handle
high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
NCP382 stays in on−phase/off−phase loop until the over
current condition is removed or enable pin is toggled.
Remark: other regulation modes can be available for
different applications. Please contact our On Semiconductor
representative for availability.
VOUTX
Drop due to
capacitor charge
IOUTX
IOCP
FLAG Indicator
Figure 6. Heavy Capacitive Load
The FLAG pin is an open−drain MOSFET asserted low
during overcurrent or overtemperature conditions. When an
overcurrent fault is detected on the power path, FLAG pin
is asserted low at the end of the associate deglitch time
(TFOCP). Thanks to this feature, the FLAG pin is not tied
low during the charge of a heavy capacitive load or a voltage
transient on output. The FLAG pin remains low until the
fault is removed. Then, the FLAG pin goes high at the end
− In case of overload, the current is limited to the I
OCP
value and the voltage value is reduced according to the
load by the following relation:
V
OUTX + RLOAD2 IOCP
(eq. 1)
VOUTX
IOUTX
of T
FGL
IOCP x RLOAD
Undervoltage Lock−out
Thanks to a built−in under voltage lockout (UVLO)
circuitry, the output remains disconnected from input until
V
voltage is above V
. This circuit has a V
IN
UVLO HYST
IOCP
hysteresis witch provides noise immunity to transient
condition.
Figure 7. Overload
Thermal Sense
Thermal shutdown turns off the power MOSFET if the die
− In case of short circuit or huge load, the current is
limited to the I value within T time until the
temperature exceeds T . A built-in hysteresis prevents the
SD
OCP
DET
part from turning on until the die temperature cools at
TRSD.
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction
temperature of the chip exceeds T
value and the
SDOCP
device enters in thermal shutdown (MOSFET is
turned−off).
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7
NCP382
Enable Input
leakage current I
from OUTX to IN. In this mode, anode
REV
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND or VIN. A logic
low on ENX or high on ENX turns−on the device. A logic
high on ENX or low on ENX turns off device and reduces
of the body diode is connected to IN pin and cathode is
connected to OUTX pin. In operating condition, anode of
the body diode is connected to OUTX pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
the current consumption down to I
.
INOFF
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
APPLICATION INFORMATION
Power Dissipation
Power dissipation in regulation mode can be calculated by
The junction temperature of the device depends on
different contributing factors such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in term of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
taking into account the drop V −V
the following relation:
link to the load by
IN
OUTX
+ ǒǒV
OCPǓ) ǒV
OCPǓǓ
P
* R
I
* R
I
LOAD2
D
IN
LOAD1
IN
I
OCP
(eq. 4)
P
= Power dissipation (W)
= Input Voltage (V)
= Load Resistance on channel X (W)
D
V
R
IN
ǒ
Ǔ2
ǒ
Ǔ2
ǒI
Ǔ
(eq. 2)
LOADX
OCP
P
D + RDS(on)
) IOUT2
OUT1
I
= Output regulated current (A)
P
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current in channel X (A)
D
PCB Recommendations
R
DS(on)
OUTx
The NCP382 integrates two PMOS FET rated up to 2 A,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. The DFN8 PAD1 must
be connected to ground plane to increase the heat transfer if
necessary. Of course, in any case, this pad must not connect
I
TJ + PD RqJA ) TA
(eq. 3)
T
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
J
R
T
qJA
to any other potential. By increasing PCB area, the R
the package can be decreased, allowing higher current.
of
qJA
A
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8
NCP382
Figure 9. USB Host Typical Application
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9
NCP382
ORDERING INFORMATION
IEC6095
0 Ed2
(CB
Active
Enable
Level
Over
Current
Limit
IEC6095
0 Ed2
Ad1
Evaluation
Board
UL
2367
†
Device
Marking
Scheme)
Package
Shipping
NCP382LMN05A-
ATXG
382
L05
0.5 A
1.0 A
1.5 A
2.0 A
0.5 A
1.0 A
1.5 A
2.0 A
0.5 A
1.0 A
1.5 A
0.5 A
1.0 A
1.5 A
NCP382LM
N05AGEVB
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
NCP382LMN10A-
ATXG
382
L10
NCP382LM
N10AGEVB
ENx
Low
NCP382LMN15A-
ATXG
382
L15
NCP382LM
N15AGEVB
NCP382LMN20A-
ATXG
382
L20
NCP382LM
N20AGEVB
DFN8
(Pb−Free)
3000 /
Tape / Reel
NCP382HMN05A-
ATXG
382
H05
NCP382HM
N05AGEVB
NCP382HMN10A-
ATXG
382
H10
NCP382HM
N10AGEVB
ENx
High
NCP382HMN15A-
ATXG
382
H15
NCP382HM
N15AGEVB
NCP382HMN20A-
ATXG
382
H20
NCP382HM
N20AGEVB
NCP382LD05AA
R2G
382L05
382L10
382L15
382H05
382H10
382H15
NCP382LD
05AAGEVB
NCP382LD10AA
R2G
NCP382LD
10AAGEVB
ENx
Low
NCP382LD15AA
R2G
NCP382LD
15AAGEVB
SOIC−8
(Pb−Free)
2500 /
Tape / Reel
NCP382HD05AA
R2G
NCP382HD
05AAGEVB
NCP382HD10AA
R2G
NCP382HD
10AAGEVB
ENx
High
NCP382HD15AA
R2G
NCP382HD
15AAGEVB
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
NCP382
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506BW
ISSUE O
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
MILLIMETERS
PIN ONE
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
REFERENCE
2X
A
EXPOSED Cu
MOLD CMPD
0.10
C
A3
b
0.20 REF
0.25
0.35
D
2X
0.10
C
C
D2 2.30
E
E2 1.55
e
K
L
TOP VIEW
DETAIL B
A
C
DETAIL B
(A3)
OPTIONAL
0.05
CONSTRUCTIONS
L1 0.00
0.05
C
NOTE 4
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
A1
SIDE VIEW
D2
DETAIL A
8X
0.62
2.50
1
4
8X
L
E2
3.30
1.75
8X
K
8
5
8X b
1
e/2
08.4X0
0.10 C A B
0.65
PITCH
e
DIMENSIONS: MILLIMETERS
NOTE 3
C
0.05
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
NCP382
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
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