NCP383LMUAJAATXG [ONSEMI]
配电开关，电流限制，可调;
| 型号： | NCP383LMUAJAATXG |
| 厂家： | 
ONSEMI |
| 描述： | 配电开关，电流限制，可调 开关 |
| 文件： | 总11页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP383
Adjustable Current-Limiting
Power-Distribution
Switches
The NCP383 is a single input dual outputs power−distribution
switch designed for applications where heavy capacitive loads and
short−circuits are likely to be encountered, incorporating two very low
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MARKING
R , N−channel MOSFETs in a single package. Each channel of
DS(on)
the device limits the output current to a desired level by switching into
a constant−current mode when the output load exceeds the
current−limit threshold or a short circuit is present. The current−limit
threshold is externally fixed by a pull down resistor placed between
DIAGRAM
383
ALYWG
G
I
and GND. The power−switches rise and fall times are controlled to
UDFN10
CASE 517CC
lim
minimize current ringing during turn on/off.
An internal reverse−voltage detection comparator disables the
power−switch if the output voltage is higher than the input voltage to
protect devices on the input side of the switches.
A
L
= Assembly Location
= Wafer Lot
The /FLAGx logic output asserts low during over−current,
reverse−voltage or over temperature conditions. The switch is
controlled by a logic enable input active low.
Y
W
G
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
Features
• 2.7 V – 5.5 V Operating Range
• Current limit: Adjustable up to 2.8 A
PIN CONNECTIONS
•
7.5% Current Limit Accuracy at 2.8 A
1
2
10
9
GND
IN
/FLAG1
OUT1
OUT2
• Very fast Over−Current Detection Response: 2 ms (typ)
• 1 mA Maximum Standby Supply Current
• Under Voltage Lock−out (UVLO)
• Soft−Start Prevents Inrush Current
• Thermal Protection
IN
3
4
5
8
7
6
EN1
EN2
ILIM
/FLAG2
• Soft Turn−off
(Top View)
• Reverse Voltage Protection
Exposed pad must be soldered to PCB Ground plane.
• Enable Active Low
• mDFN 3x3 mm
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
• Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact) − 15 kV (Air)
• UL Listed – File E343275
• CB − IEC60950−ED2 Certified
• CB – IEC60950−ED2−AM1 Certified
• This is a Pb−Free Device
Typical Applications
• Laptops
• USB Ports/Hubs
• TVs
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
October, 2012 − Rev. 2
NCP383/D
NCP383
USB
Data
D+
USB
Port
USB INPUT
5 V
D−
IN
IN
OUT1
VBUS
GND
1 mF
R
fault
120 mF
100 kW
NCP383
USB
Data
FLAG1
/FLAG1
/EN1
EN1
ILIM
D+
D−
USB
Port
/FLAG2
/EN2
FLAG2
EN2
OUT2
VBUS
GND
120 mF
GND
Figure 1. Typical Application Circuit: NCP383xMUAJxx
Adjustable Current limit on Channel 1 and Channel 2
PIN FUNCTION DESCRIPTION
Pin Name
GND
Number
Type
P
Description
1
Ground connection.
IN
2, 3
P
Power−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC. Both IN pins must be hardwired together on the PCB.
/EN1
/EN2
4
5
6
I
I
Enable 1 input, logic low turns on power switch 1 – If channel 1 is not used, do not leave this
pin unconnected. Pull it to V
IN
Enable 2 input, logic low turns on power switch 2. If channel 2 is not used, do not leave this
pin unconnected. Pull it to V
IN
/FLAG2
O
Active−low open−drain output 2, asserted during overcurrent, overtemperature, or reverse−
voltage conditions. Connect a 10kW or greater resistor pull−up, otherwise leave unconnec-
ted.
ILIM
7
8
O
O
External resistor used to set current−limit threshold; recommended 20kW < R
< 120 kW.
ILIM
OUT2
Power−switch output2; connect a 1 mF ceramic capacitor from OUT2 to GND as close as
possible to the IC is recommended. A 120 mF or greater ceramic capacitor from OUT2 to
GND must be connected if the USB requirement is not met.
OUT1
/FLAG1
PAD
9
O
O
Power−switch output1; connect a 1 mF ceramic capacitor from OUT1 to GND as close as
possible to the IC is recommended. A 120 mF or greater ceramic capacitor from OUT1 to
GND must be connected if the USB requirement is not met.
Active−low open−drain output 1, asserted during overcurrent, overtemperature, or reverse−
voltage conditions. Connect a 10 kW or greater resistor pull−up, otherwise leave unconnec-
10
11
ted.
Therm
Exposed Thermal Pad: Must be soldered to PCB Ground plane
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2
NCP383
Control logic
and timer
/EN1
EN block
/FLAG1
Flag
Current
Limiter
Charge Pump
Gate Driver
GND
OUT1
Osc
Vref
UVLO
TSD
Blocking control
Blocking control
IN
OUT2
Charge Pump
Gate Driver
Current
Limiter
ILIM
Flag
/FLAT2
Control logic
and timer
EN block
/EN2
Figure 2. Block Diagram
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3
NCP383
MAXIMUM RATINGS
Rating
Symbol
,V
Value
Unit
From IN to OUT1, From IN to OUT2 Supply Voltage
(Note 1)
V
V
−7.0 to +7.0
V
IN , OUT1 OUT2
IN, OUT1,OUT2, /EN1, /EN2, /FLAG1, /FLAG2, ILIM
Pins: In/Output (Note 1)
V
V
V
V
V
−0.3 to +7.0
V
IN , OUT1, OUT2, EN1 , EN2 ,
V
,V
V
FLAG1 FLAG2, ILIM,
/FLAG1, /FLAG2 Sink Current
I
2
mA
kV
SINK
ESD Withstand Voltage (IEC 61000−4−2) (output only,
when bypassed with 1.0 mF capacitor minimum)
ESD IEC
15 Air, 8 contact
Human Body Model (HBM) ESD Rating are (Note 2)
Machine Model (MM) ESD Rating are (Note 2)
Latch−up protection (All Pins) (Note 3)
Maximum Junction Temperature (Note 4)
Storage Temperature Range
ESD HBM
ESD MM
LU
2000
200
V
V
100
mA
°C
°C
T
−40 to + TSD
−40 to + 150
Level 1
J
T
STG
Moisture Sensitivity (Note 5)
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) 200 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: +100 mA per JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020
OPERATING CONDITIONS
Symbol
Parameter
Conditions
Min
2.7
0
Typ
Max
5.5
5.5
+85
1
Unit
V
IN
Operational Power Supply
Enable Voltage
V
V
ENX
T
A
Ambient Temperature Range
/FLAG sink current
−40
25
°C
mA
mF
I
SINK
C
IN
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction to Air
Junction Temperature Range
Recommended Maximum DC current
Power Dissipation Rating (Note 8)
1
C
OUTX
USB port per Hub
120
mF
R
q
JA
DFN−10−12 package (Notes 6 and 7)
85
25
°C/W
°C
T
−40
+125
2.5
J
I
Per Channel
A
OUTX
P
D
T
≤ 25 °C
DFN−10 package
DFN−10 package
850
428
mW
A
T = 85 °C
A
6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020
7. The R is dependent of the PCB heat dissipation. Announced thermal resistance is the unless PCB dissipation and can be improve with
q
JA
final PCB layout.
8. The maximum power dissipation (P ) is given by the following formula:
D
T
JMAX * TA
PD
+
RqJA
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4
NCP383
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C and T up to + 125°C for V between
A
J
IN
2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to T = + 25°C and V = 5 V.
A
IN
Symbol
Parameter
Conditions
Conditions
Min
Typ
45
Max
Unit
POWER SWITCH
T = 25°C
70
95
4
J
Static drain−source on−state
resistance, per channel
R
DS(on)
mW
–40°C < T < 125°C
J
C = 1mF,
LOAD
= 100 W
T
Output rise time
Output fall time
V
V
= 5 V
= 5 V
1.5
0.1
2.5
R
IN
R
ms
LOAD
T
0.5
(Note 9)
F
IN
Logic Pins
V
High−level input voltage
Low−level input voltage
Input current
1.2
V
V
IHEN
V
0.4
0.5
9
ILEN
I
V
= 0 V, V
= 5 V
−0.5
1
mA
ms
ms
ENx
ENx
/ENx
T
Turn on time
−
ON
C
LOAD
= 1mF, R
= 100 W (Note 9)
LOAD
T
Turn off time
1
3
OFF
CURRENT LIMIT
Ilimx = 90k (Note 10)
Ilimx = 56k
0.5
0.9
0.6
1
0.7
1.1
Current−limit threshold (Max-
imum DC output current
delivered to load)
I
A
OCP
I
OUTX
Ilimx = 20k (Note 10)
2.58
2.8
2
3.01
T
Response time to short circuit
Regulation time
V
IN
= 5 V (Note 10)
ms
ms
ms
DET
REG
OCP
T
T
1
2
3
Over current protection time
19
24
29
UNDERVOLTAGE LOCKOUT
V
IN pin low−level input voltage
IN pin hysteresis
V
rising
−
25
7
2.45
12
2.5
15
V
UVLO
IN
V
T = 25°C
J
mV
ms
HYST
T
Re−arming Time
RUVLO
SUPPLY CURRENT
Low−level output supply cur-
V
= 5 V, No load on OUTX, Device OFF
IN
V
I
1
99
1
mA
mA
mA
INOFF
rent.
= 0 V or V
= 5 V – T = 25°C
ENX
/ENX J
High−level output supply cur-
rent.
V
IN
= 5 V, No load on OUTX
I
INON
Device ON − R
= 56 kW − V
= 5 V
ILIM
ENX
V
= 5 V,
OUTX
IN
I
Reverse leakage current
T = 25°C
J
REV
V
= 0 V
/FLAGx PINS
V
/FLAGX output low voltage
Off−state leakage
/FLAGX deglitch
I
= 1 mA
400
1
mV
mA
OL
/FLAGX
I
V
= 5 V
LEAK
/FLAGX
T
/FLAGX de−assertion time due to overcurrent
/FLAGX assertion due to overcurrent
3
5
3
5
7
5
7
ms
ms
ms
FGL
T
/FLAGX deglitch
12
7
FOCP
T
/FLAGX deglitch
/FLAGX assertion due to reverse−voltage
FREV
REVERSE VOLTAGE PROTECTION
V
Reverse voltage threshold
V
− V drop
150
30
mV
mV
REV
OUT
IN
Reverse voltage threshold
hysteresis
V
V
− V drop decrease
OUT IN
RHYST
THERMAL SHUTDOWN
T
Thermal shutdown threshold
Thermal regulation threshold
140
125
°C
°C
SD
T
SDOCP
Thermal regulation rearming
threshold
T
115
°C
RST
9. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground.
10.Guaranteed by design and by characterization
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5
NCP383
TR
TF
50%
VEN
90%
10%
VOUT
TOFF
10%
TON
90%
VOUT
10%
Figure 3. Ton, Toff, Trise, and Tfall
FUNCTIONAL DESCRIPTION
Overview
VOUTX
The NCP383 is a dual high side N channel MOSFET
power distribution switches designed to protect the input
supply voltage in case of heavy capacitive loads, short
circuit or over current. In addition, the high side MOSFETs
are turned off during under voltage, thermal shutdown or
reverse voltage condition. Thanks to the soft start circuitry,
NCP383 is able to limit large current and voltage surges.
IOCP x RLOAD
IOUTX
IOCP
Figure 5. Overload
Overcurrent Protection
NCP383 switches into a constant current regulation mode
− In case of short circuit or huge load, the current is
limited to the I value within T time until the
when the output current is above the I
threshold.
OCP
OCP
DET
Depending on the load, the output voltage is decreased
accordingly.
− In case of hot plug with heavy capacitive load, the
output voltage is brought down to the capacitor voltage.
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction
temperature of the chip exceeds T
value and the
SDOCP
device enters in thermal shutdown (MOSFET is
turned−off).
The NCP383 will limit the current to the I
threshold
OCP
value until the charge of the capacitor is completed.
VOUTX
VOUTX
Timer
Regulation
Mode
Thermal
Regulation
Threshold
Drop due to
capacitor charge
IOUTX
IOUTX
IOCP
IOCP
TOCP
TREG
Figure 4. Heavy Capacitive Load
Figure 6. Short Circuit
− In case of overload, the current is limited to the I
OCP
value and the voltage value is reduced according to the
load by the following relation:
Then, the device enters in timer regulation mode,
described in 2 phases:
V
OUTX + RLOADX IOCP
(eq. 1)
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6
NCP383
− Off−phase: Power MOSFET is off during T
to allow
temperature conditions. When an over current or a reverse
OCP
the die temperature to drop.
− On−phase: regulation current mode during T
voltage fault is detected on the power path, /FLAGx pins are
asserted low at the end of the associate deglitch time (see
electrical characteristics). Due to this feature, the /FLAGx
pins are not tied low during the charge of a heavy capacitive
The
REG.
current is regulated to the I
level.
OCP
The timer regulation mode allows the device to handle
high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
load or a voltage transient on output. Deglitch time is T
FOCP
for over current fault and T
for reverse voltage. The
FREV
NCP383 stays in on−phase/off−phase loop until the over
current condition is removed or enable pin is toggled.
Remark: other regulation mode can be available for
/FLAGx pins remain low until the fault is removed. Then,
the /FLAG pins go high at the end of T
FGL
Undervoltage Lock−out
different
applications.
Please
contact
our
Due to a built−in under voltage lockout (UVLO) circuitry,
the output remains disconnected from input until V
ON Semiconductor representative for availability.
IN
voltage is above V
witch provides noise immunity to transient condition.
. This circuit has a V
hysteresis
Adjustable Current−Limit Programming
NCP383xMUAJxx Version
UVLO
HYST
The R
resistor connected between ILIM pin and GND
LIM
Thermal Sense
Thermal shutdown turns off the power MOSFET if the die
temperature exceeds T . A Hysteresis of T prevents
determine the current limit threshold according to the
electrical characteristic table.
SD
HYST
the part from turning on until the die temperature cools at
− T
T
.
SD
HYST
Enable Input
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND or VIN. A logic
low turns−on the device. A logic high on /ENX turns off
device and reduce the current consumption down to I
.
INOFF
Remark: Active high can be available for different
applications. Please contact our ON Semiconductor
representative for availability.
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
leakage current I
from OUTX to IN. In this mode, anode
REV
of the body diode is connected to IN pin and cathode is
connected to OUTX pin. In operating condition, anode of
the body diode is connected to OUTX pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
Figure 7. Typical Ilim Curve vs Rlim External Resistor
/FLAGx Indicators
The /FLAGx pin are an open−drain MOSFET asserted
low during over current, reverse−voltage or over
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7
NCP383
APPLICATION INFORMATION
Power Dissipation
Power dissipation in regulation mode can be calculated by
The device’s junction temperature depends on different
contributor factor such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in term of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
taking into account the drop V −V
the following relation:
link to the load by
IN
OUTX
(eq. 4)
ǒǒV
OCPǓ ) ǒV
OCPǓǓ
P
* R
I
* R
I
LOAD2
D
IN
LOAD1
IN
I
OCP
P
V
= Power dissipation (W)
= Input Voltage (V)
D
Ǔ2
ǒ
Ǔ2
IN
ǒ
ǒ
Ǔ
(eq. 2)
P
D + RDS(on)
IOUT1 ) IOUT
R
I
= Load Resistance on channel X (W)
= Output regulated current (A)
LOADX
OCP
P
D
= Power dissipation (W)
R
I
= Power MOSFET on resistance (W)
= Output current in channel X (A)
DS(on)
OUTx
PCB Recommendations
The NCP383 integrates two up to 3 A rated NMOS FETs,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. The DFN10 PAD1 must
be connected to ground plane to increase the heat transfer if
necessary. Of course, in any case, this pad must not connect
TJ + PD RqJA ) TA
(eq. 3)
T
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
J
R
T
qJA
A
to any other potential. By increasing PCB area, the R
of
qJA
the package can be decreased, allowing higher current.
CIN / COUT1 / COUT2:
* AS CLOSE AS POSSIBLE TO NCP383
* DIRECTLY CONNECTED TO GND PLANE (LOW IMPEDANCE CONNECTION)
* TRY TO AVOID VIAS BETWEEN PIN AND CAPACITOR
* IF 120 mF COUT1 and COUT2 ARE LOCATED FAR AWAY FROM NCP383, TRY TO ADD
EXTRA LOWER VALUE ( ~ 0.1 mF) CAPACITOR AS CLOSE AS POSSIBLE TO NCP383
AS MUCH AS POSSIBLE VIA TO INNER
GROUND PLANE (BEST POWER DISSIPATION)
GND TOP LAYER PLANE
COUT1
CIN
VOUT1 TOP LAYER PLANE
VOUT2 TOP LAYER PLANE
COUT2
+5V Local Plane
RLIM
GND TOP LAYER PLANE
Figure 8. Layout Recommendations
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8
NCP383
ORDERING INFORMATION
Device
†
Package
Shipping
NCP383LMUAJAATXG
UDFN10
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP383xMUAJxxTXG
Tape and Reel for UDFN
d. Regulation option
c. Auto−discharge option
b. Current option
UDFN Package
a. I = Active Low
Code
Contents
a
b
c
d
L: active low
AJ: adjustable current limit
A: No autodischarge output path
A: standard regulation (CC + TSD warning +
timer)
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN10 3x3, 0.5P (Leads 2 & 3 Tied)
CASE 517CC
ISSUE O
SCALE 2:1
DATE 10 OCT 2011
D
A
B
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
EXPOSED Cu
MOLD CMPD
DETAIL B
ALTERNATE
PIN ONE
REFERENCE
CONSTRUCTION
MILLIMETERS
DIM
A
MIN
0.45
0.00
MAX
0.55
0.05
(0.17)
L1
L
2X
0.15 C
A1
A3
b
0.13 REF
2X
0.15
C
0.15
2.39
0.25
TOP VIEW
D
3.00 BSC
D2
E
2.59
1.79
A
L
3.00 BSC
DETAIL B
DETAIL A
A3
0.10
0.08
C
E2
e
1.59
ALTERNATE TERMINAL
CONSTRUCTIONS
A1
C
0.50 BSC
L
0.35
---
0.45
0.15
L1
C
SEATING
PLANE
NOTE 4
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
DETAIL A
XXXXX
XXXXX
ALYWG
G
1
5
A
L
= Assembly Location
= Wafer Lot
E2
Y
W
G
= Year
= Work Week
= Pb−Free Package
10
6
10X b
10X
L
(Note: Microdot may be in either location)
0.10
C
C
A
B
e
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
NOTE 3
0.05
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
2.63
0.50
PITCH
10X
0.62
3.30
1.81
PACKAGE
OUTLINE
1
9X
0.80
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON59624E
UDFN10 3X3, 0.5P (LEADS 2 & 3 TIED)
PAGE 1 OF 1
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