NCP3901FCCT1G [ONSEMI]
Dual Input, Single Output Power Source Multiplexer;
| 型号： | NCP3901FCCT1G |
| 厂家： | 
ONSEMI |
| 描述： | Dual Input, Single Output Power Source Multiplexer |
| 文件： | 总13页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP3901
Dual Input, Single Output
Power Source Multiplexer
The NCP3901 integrated circuit is a dual input, single output power
source multiplexer. It is optimized for multiplexing 2 different
charging inputs to feed a single input battery charger. To address all
types of applications, the device is able to support autonomous and
slave modes of operation. Reverse USB on−the−go is fully supported.
www.onsemi.com
MARKING
DIAGRAM
Features
• 3 A DC Minimum Current through Power Paths
• Reverse 5 V OTG Support through VINA Path
• Maximum 20 V Over Voltage Threshold
• 28 V Absolute Maximum Voltage on VINA
• Compliance with IEC61000−4−5 at 100 V for VINA
• Indication of Presence of Second Input
• Autonomous Priority Selection and Switch Over Lock
• Small Footprint: 3.1 x 1.65 mm WLCSP28 0.4 mm Pitch
• 30 ms Minimum Break−before−make Time
• This is a Pb−Free Device
3901
AWLYWW
G
WLCSP28
FCC SUFFIX
CASE 567KR
3901= NCP3901
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
A
Y
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 11 of this data sheet.
Typical Applications
• Handheld Devices
• Tablets
• Smart Phone
• PDAs
VINA
CHANNEL 1 BACK
TO BACK MOSFETS
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VINA
VINA
VINA
PRIMARY
VINA
CHARGING
SOURCE
(i.e. USB)
VINA
Battery /
System
OUTPUT
DICHARGE
VINA
HV SBC
SYSTEM
VOVLO
VUVLO
IN1 PROTECTED SENSE
OUT
VINA_S
GND
GND
OTG_EN / VINA_EN
CTRL
INTERNALPOWER
1.8V
GND
GND
GND
SUPPLY
/
LDO
REFERENCE
VOLTAGE
MODE
LOGIC CONTROL
DRIVERS
1.8V
VOVLO
FLAG / VINB_EN
VUVLO
FLAG
VINB
VINB
SECONDARY
CHARGING
SOURCE
(i.e. A4WP,
Dock)
VINB
VINB
CHANNEL 2 BACK
TO BACK MOSFETS
NCP3901
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2016 − Rev. 2
NCP3901/D
NCP3901
Table 1. PIN FUNCTIONAL DESCRIPTION
Pin
A1
A2
A3
A4
A5
A6
A7
C4
B5
B6
B7
C5
C6
C7
B1
B2
B3
C2
C3
D4
D5
D6
D7
C1
Name
Type
Description
Channel 1 power input path. These pins must be decoupled with a
VINA
POWER
1 mF input capacitor.
Output power path. Connected to battery charger. These pins must
be decoupled with a 4.7 mF input capacitor.
OUT
POWER
GND
VINB
GROUND
POWER
Ground. Must be connected to a ground plane.
Channel 2 power input path. These pins must be decoupled with a
1 mF input capacitor.
MODE
CRTL
DIGITAL INPUT
DIGITAL INPUT
Digital Input Pin. Used to determine autonomous−or slave mode.
Digital Input Pin. Used to determine autonomous−locked or autono-
mous−not locked mode.
D1
B4
D2
VINA_S
ANALOG OUTPUT
DIGITAL INPUT
Image of VINA input when VINA is within the operating range.
Used to select USB On−The−Go mode on channel 1
VINA_EN/OTG_EN
DIGITAL INPUT / OPEN
DRAIN OUTPUT
VINB valid indicator. This pin is used to indicate VINB is valid. Can
also be used as an input to enable both VINA and VINB channels.
D3
VINB_EN/FLAG
Pin Out
1
2
3
4
5
6
7
VINA
VINA
VINA
VINA
VINA
VINA
VINA
GND
GND
GND
GND
GND
VINA_S
OUT
OUT
OUT
MODE
CRTL
OUT
OUT
OUT
OUT
VINA_EN VINB_EN
/OTG_EN /FLAG
VINB
VINB
VINB
VINB
Figure 2. Package TOP VIEW
www.onsemi.com
2
NCP3901
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to +29
100
Unit
V
VINA, (Note 1)
V
INA
V
INB
VINA, (Note 2)
V
VINB, VINA_S (Note 1)
OUT (Note 1)
−0.3 to +21
−0.3 to +18
−0.3 to +6
−65 to +150
−40 to +TSD
Level 1
V
V
OUT
V
CTRL, MODE, VINA_EN/OTG_EN, VINB_EN/FLAG (Note 1)
Storage Temperature Range
V
CTRL
V
T
STG
°C
°C
Maximum Junction Temperature (Note 3)
Moisture Sensitivity (Note 4)
T
J
MSL
ESD HBM
ESD CDM
ILU
Human Body Model (HBM) ESD Rating (JEDEC standard: JESD22−A114)
Charged Device Model (CDM) ESD Rating (JEDEC standard: JESD22−A114)
Latch up Current (JEDEC standard: JESD78 class II):
2500
V
V
2000
100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. With Respect to GND. According to JEDEC standard JESD22−A108.
2. With Respect to GND. According to standard IEC61000−4−5 1.2/50 ms.
3. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
Table 3. OPERATING CONDITION
Symbol
Parameter
Operational Power Supply on VINA
Operational Power Supply on VINB
Operational Supply
Conditions
Min
0
Typ
Max
28
Unit
V
V
INA
V
INB
0
20
V
V
,V
,
0
5.5
V
CTRL MODE
V
,
INA_EN/OTG_EN
V
INB_EN/FLAG
I
Operational Output Current
Operational Supply on OUT
0
0
3
A
V
OUT
V
OTG mode,
5.5
OUT
VINA = VINB = 0 V
Charging mode
0
17.3
V
mF
C
Input Capacitor
1
IN
C
Output Capacitor
4.7
60
25
mF
OUT
R
Thermal Resistance Junction to Air
Junction Temperature Range
(Notes 3 and 5)
°C/W
°C
JA
J
T
−40
+125
5. The R
is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.
q
JA
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C and T up to + 125°C for V
IN
A
J
between V
Symbol
CORE
to V
(Unless otherwise noted) Typical values are referenced to T = + 25°C and V = 5 V (Unless otherwise noted).
UVLO
OVLO A IN
Parameter
Conditions
Min
Typ
Max
Unit
V
Under Voltage Lockout ap-
plied to VINA, VINB or OUT
Rising
Falling
Rising
Falling
−
−
−
3.0
−
V
V
UVLO
2.45
V
OVLO
Over Voltage Lockout Re-
ferred to VINA or VINB
17
16.4
20
V
V
I
Stand by current
Measured on VOUT, VINA and VINB < UVLO,
OTG mode off
mA
OFF
I
Quiescent Current
VINB > UVLO
100
200
2
ON
VINA and VINB > UVLO (including FLAG pull down)
Measured on FLAG pin or MODE pin
V
Internal pull up
1.6
2.2
1.8
V
V
INTPUP
V
CTRL High− input voltage
5.5
CTRLH
6. Guaranteed by design and characterization.
www.onsemi.com
3
NCP3901
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C and T up to + 125°C for V
IN
A
J
between V
Symbol
CORE
to V
(Unless otherwise noted) Typical values are referenced to T = + 25°C and V = 5 V (Unless otherwise noted).
UVLO
OVLO A IN
Parameter
Conditions
Min
Typ
Max
Unit
V
MODE, VINA_EN/OTG_EN, VINB_EN/FLAG, CTRL High−level input voltage
MODE, VINA_EN/OTG_EN, CRTL, VINB_EN/FLAG, CTRL Low−level input voltage
VINB_EN/FLAG Low−level output voltage
1.2
0
5.5
0.4
0.4
V
V
IH
V
IL
V
FLGL
0
V
R
VINB_EN/FLAG pull up resistance
50
kW
kW
kW
W
FLGPUP
R
MODE pin pull up resistance
100
500
500
MODEPUP
R
VINA_EN/OTG_EN, CRTL pins pull down resistance
PULDN
R
Output Discharge Resistance
During Break before make transition, measured on
OUT pin
DIS
POWER
R
R
On resistance input VINA
On resistance input VINB
Soft Start on both channel
V
V
> 4 V
> 4 V
50
50
80
80
mW
mW
ms
DSONA
DSONB
INA
INB
T
RIN
From 10% to 90% of VINA or VINB, CLOAD =
800
4.7 mF, RLOAD = 500 W.
T
Soft Start on both channel
Inrush current
VOUT = 5V. From 10% to 90% of VINA or VINB,
CLOAD = 4.7 mF, RLOAD = 500 W.
800
800
ms
ROUT
I
Supply on VINA = 5 V or 10 V or VINB = 5 V or 10 V
or VOUT = 5 V CLOAD = 4.7 mF, RLOAD = 500 W.
(Note 6)
mA
RHMX
Total charge on C
during T time (Note 6)
50
1
mC
OUT
ON
Supply on VINA or VINB or VOUT CLOAD = 4.7 mF,
RLOAD = 500 W. (Note 6)
A
T
ON
Turn−on time
Slave Mode, from V
= 1 to V = 90% of
OUT
800
ms
INA_EN
V
INA
or V
= 1 to V
= 90% of V
.
INB_EN
OUT
INB
V
VOUT maximum voltage
17.3
V
VINA from 0 V to 28 V in 3 V/ms and COUT = 4.7 mF
VINB from 0 V to 20 V in 3 V/ms and COUT = 4.7 mF
OUTMAX
100 V surge holdoff to support IEC 61000−4−5 on
VINA. (Note 6)
CONTROL and TIMING
T
Debounce time for V
valid
valid
From V
(excluding soft start)
< V
< V
< V
to V
to V
enable
enable
15
1
ms
ms
DEBINA
INA
INB
UVLO
INA
OVLO
INA
T
Debounce time for V
From V < V
DEBINB
UVLO
INB
OVLO
INB
(excluding soft start)
T
CRTL pin deglitcher
OTG wait time
100
10
ms
CRTL
T
OTG1
Autonomous Mode, VINB valid, From VINA_EN/
OTG_EN = 1 to VINA valid (excluding soft start)
ms
T
Autonomous Mode, VINB not valid, From VINA_EN/
OTG_EN = 1 to VINA valid (excluding soft start)
1
ms
ms
OTG2
T
Break before make time
Autonomous Mode, From VINA valid to VINB valid or
from VINB valid to VINA valid
30
BBM
INPUT SENSE PIN
V
Voltage Drop VINA – VINA_S
20 mA sink on V
(Note 6)
200
20
mV
V
INSDRP
INA_S
V
Max Voltage on VINA_S volt-
age sense
INSNSMX
THERMAL SHUTDOWN
Thermal Shutdown
T
SD
Temperature Rising
Temperature Falling
150
135
°C
6. Guaranteed by design and characterization.
www.onsemi.com
4
NCP3901
Functional Description
VINA
VINA
VINA
CHANNEL 1 BACK
TO BACK MOSFETS
OUT
OUT
OUT
VINA
VINA
OUT
OUT
VINA
VINA
OUT
OUT
OUTPUT
DICHARGE
VOVLO
VUVLO
IN 1 PROTECTED SENSE
OUT
VINA_S
GND
GND
OTG_EN / VINA_EN
CTRL
INTERNAL POWER
1.8V
GND
GND
GND
SUPPLY
/
LDO
REFERENCE
VOLTAGE
LOGIC CONTROL
MODE
1.8V
VOVLO
VUVLO
DRIVERS
FLAG / VINB_EN
FLAG
VINB
VINB
VINB
VINB
CHANNEL 2 BACK
TO BACK MOSFETS
NCP 3901
Figure 3. Block Diagram
Overview
The IC contains a VINB_EN/FLAG input that informs
the controlling logic if the secondary channel is conducting
or not.The VINB_EN/FLAG pin can also be used as an input
signal in order to enable both inputs at the same time.
The IC features a VINA_S protected and current limited
output as soon as the VINA voltage is valid (operating
range).
The NCP3901 is a 2 to 1 flexible power source selector
with arbitration logic. A primary power path (VINA) and
secondary power path (VINB) are switched to a single pin
(OUT) that provides power to a system (battery charger
input).The two inputs (VINA and VINB) are Over Voltage
protected. The Over Voltage Threshold is set in such a way
that, considering pass MOSFET turn off time, the absolute
highest voltage at the OUT pin with a 3 V/ms rising input
voltage will be 20 V.
In addition, VINA is connected to an active clamp that
protects all downstream circuitry up to a high voltage surge
of 100 Vas defined by the IEC61000−4−5 1.2/50 ms and
10/700 ms standard. The IC is protected against reverse
voltage applied to the OUT pin on both inputs by use of back
to back power MOSFETs.
Depending on the MODE pin level, the IC will operate in
“Autonomous” or “Slave” mode.
• If MODE pin is high the part operates in Slave Mode
• If MODE pin is low the part operates in Autonomous
Mode
In Autonomous mode, the CTRL pin will prevent, if
pulled high, the part from switching from one input to the
other one. MODE digital pin, if pulled high, can also be used
to do this.
Finally, a thermal protection will stop the IC when
exceeding the TSD threshold. The IC function will be
enabled automatically when the part cools down.
When a valid voltage is applied to the OUT pin, a digital
input VINA_EN/OTG_EN pin will allow this voltage to
pass through the power channel 1 from OUT to VINA.
www.onsemi.com
5
NCP3901
Mode Selection
Mode 1 – Slave Mode
Mode selection to support multiple applications is based
on the CTRL and MODE pins, as depicted in the table below.
If no external components are connected to the CRTL and
MODE pins, the device is configured in slave mode.
In slave mode, the NCP3901 is directly control by the
host. The OTG and FLAG pins are respectively assigned to
VINA_EN and VINB_EN, directly controlling input
channel A and input channel B.
MODE Pin
Low
CTRL Pin
Low
PMUX behavior
VINA_EN
Low
VINB_EN
Low
Selected Path
None
Autonomous mode – Not Locked
Autonomous mode – Locked
Low
High
Low (default)
High
High (default)
Low
VINB Conducting
VINA Conducting
VINB and VINA Conducting
High
Low
Slave mode
High
High
High
High
VINA
OVLO
UVLO
VINB
OVLO
UVLO
VINA_EN
VINB_EN
OUT
UVLO
Figure 4. Signal Timing in Slave Mode
www.onsemi.com
6
NCP3901
Mode 2 – Autonomous Mode
transition, a break−before−make operation is performed
within 30 ms in order to avoid cross conduction between
VINA and VINB and to ensure proper operation. A 500 W
pulldown resistor on OUT is enabled for the entire duration
of the break−before−make time. As the PMUX is able to turn
on channel VINA or VINB, a FLAG pin indicates to the
system the active path. When the VINB path is active, FLAG
pin is high. As a consequence, if a valid voltage is present on
the OUT pin and if FLAG is low, VINA is active.
Autonomous Mode − Not Locked
In autonomous not locked mode, the device uses its own
logic to determine which input path is conducting and
provides information to the system and priority is given to
the VINA channel. If a VINA supply is detected valid while
VINB is conducting, the PMUX will automatically switch
the conducting input from VINB to VINA. During this
INA
O VLO
UVLO
INB
O VLO
UVLO
OTG_EN
FLAG
OUT
5V
Figure 5. Signal Timing in Autonomous Mode – Charging Example
Autonomous Mode − Locked
the VINA output is powered from VOUT and is soft−started
for 1 ms.
Autonomous locked mode is set when the CTRL pin is
high. In this mode, the first valid input is active till this input
becomes not valid. This feature can be used to lock the VINB
channel in case of a weak battery for example.
For VINB to supply the OTG accessory (connected on
VINA) though OUT, both channels must be activated. This
can be done by asserting the FLAG pin low. Usually used as
an output, the FLAG pin is also sensed by the PMUX in
autonomous mode. When VINB is valid, the FLAG pin open
drain is open. Thus asserting the FLAG pin low will turn on
the VINA path with VINB already active.
OTG Mode
5 V is applied on the output of the device during OTG
mode. This 5 V will pass through the VINA path when the
OTG_EN pin is driven high. When enabling the OTG mode,
1.8V
Schmitt
Trigger
FLAG INPUT
(Digital Input)
50 k
FLAG INPUT
FLAG
FLAG OPEN DRAIN
(Digital Input)
FLAG OPEN DRAIN
Inverter
Figure 6. FLAG Functional Diagram
www.onsemi.com
7
NCP3901
INA
O VLO
5V
UVLO
INB
O VLO
5V
Disconnected
UVLO
OTG_EN
FLAG
OUT
Flag as input is forced to 0
5V
Figure 7. Signal Timing in Autonomous Mode – USB On The Go Example
Autonomous Mode Functional Diagram
Break Before Make
VINA and VINB not conducting
FLAG is Low
VINA VALID
VINA VALID (Not Locked mode)
VINB VALID and
VINA NOT VALID
VINB VALID and
VINA NOT VALID
Discharge path is enable
VINA conducting
VINB conducting
VINA and
VINB NOT VALID
FLAG is Low
FLAG is high
Discharge path is disable
Discharge path is disable
OFF Mode
VINA VALID
VINB VALID
FLAG is Low
VINB and
VINB NOT VALID
Discharge path is disable
VINA NOT VALID
FLAG PIN LOW
VINB NOT VALID
FLAG PIN
HIGH
OTG mode, VINA conducting
VINA and VINB conducting
OTG EN
OTG DISABLE
FLAG is Low
FLAG is high but forced Low
Discharge path is disable
Discharge path is disable
Figure 8. Functional Diagram
www.onsemi.com
8
NCP3901
VINA Sense Output
The IC features a protected VINA Sense to the processor.
This output is 0V when the VINA voltage level is lower than
will disable both VINA and VINB when the voltage applied
to VINA or VINB will exceed the OVLO thresholds. The
response time of the overvoltage lock out is fast enough to
prevent a voltage of maximum of 20 V at VOUT.
In compliance with IEC 61000−4−5, both 1.2/50 ms and
10/700 ms surge waveforms up to 100 V, the PMUX clamp
input voltage surges on VINA to 28 V and hold off the
voltage. During these surges, the voltage at VOUT will not
exceed 20 V.
V
UVLO
and higher than V
and equal to VINA when the
OVLO
VINA voltage is within the operation range.
Input Voltage Protection
The device can withstand a maximum of 28 V DC on
VINA and 20 V DC on VINB. Embedded OVP thresholds
www.onsemi.com
9
NCP3901
TYPICAL CHARACTERISTICS
I
= 200 mA
LOAD
I
= 200 mA
LOAD
Figure 9. VINA ON Resistance vs. VINA
Figure 10. VINB ON Resistance vs. VINB
I
= 2 A
I
= 2 A
LOAD
LOAD
Figure 11. VINA ON Resistance vs. VINA
Figure 12. VINB ON Resistance versus VINB
Figure 14. VINB ION vs VINB
(including FLAG pull−up)
Figure 13. VINA ION vs VINA
www.onsemi.com
10
NCP3901
APPLICATION INFORMATION
Typical Application
VINA
VINA
VINA
VINA
CHANNEL 1 BACK
TO BACK MOSFETS
OUT
OUT
OUT
PRIMARY
VINA
OUT
OUT
CHARGING
VINA
Battery /
System
SOURCE
OUT
OUT
OUTPUT
DICHARGE
VINA
(i.e. USB)
HV SBC
SYSTEM
VOVLO
VUVLO
IN1 PROTECTED SENSE
OUT
VINA_S
OTG_EN
CTRL
GND
GND
INTERNALPOWER
1.8V
GND
GND
GND
SUPPLY
REFERENCE
VOLTAGE
/
LDO
MODE
LOGIC CONTROL
1.8V
VOVLO
DRIVERS
FLAG
VUVLO
FLAG
VINB
VINB
SECONDARY
CHARGING
SOURCE
(i.e. A 4WP,
Dock)
VINB
VINB
CHANNEL 2 BACK
TO BACK MOSFETS
Figure 15. Autonomous Mode
VINA
VINA
VINA
CHANNEL 1 BACK
TO BACK MOSFETS
OUT
OUT
OUT
VINA
VINA
PRIMARY
CHARGING
SOURCE
OUT
OUT
VINA
VINA
Battery /
System
OUT
OUT
OUTPUT
DICHARGE
(i.e. USB)
HV SBC
SYSTEM
VOVLO
VUVLO
IN1 PROTECTED SENSE
OUT
VINA_S
VINA_EN
CTRL
GND
GND
INTERNALPOWER
1.8V
GND
GND
GND
SUPPLY
REFERENCE
VOLTAGE
/
LDO
MODE
LOGIC CONTROL
1.8V
VOVLO
VUVLO
DRIVERS
VINB_EN
FLAG
VINB
VINB
SECONDARY
CHARGING
SOURCE
(i.e. A 4WP,
Dock)
VINB
VINB
CHANNEL 2 BACK
TO BACK MOSFETS
Figure 16. Salve Mode
ORDERING INFORMATION
Part Number
†
Marking Diagram
Shipping
NCP3901FCCT1G
3901
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP28, 3.1x1.65, 0.4P
CASE 567KR
ISSUE O
DATE 23 SEP 2014
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
D
A
B
E
PIN A1
REFERENCE
MILLIMETERS
DIM
A
A1
A2
A3
b
MIN
−−−
0.17
0.33
0.02
0.24
MAX
0.60
0.23
0.39
0.04
0.28
A2
DIE COAT
(OPTIONAL)
A3
2X
0.10
0.10
C
2X
C
D
E
e
3.10 BSC
1.65 BSC
0.40 BSC
TOP VIEW
DETAIL A
A2
GENERIC
MARKING DIAGRAM*
DETAIL A
A
C
0.10
0.05
C
XXXXXX
AWLYWW
G
C
SEATING
PLANE
A1
NOTE 3
SIDE VIEW
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
e
28X
b
Y
0.05
0.03
C A B
e
D
C
B
G
= Pb−Free Package
C
e/2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
A
1
2
3
4
5
6
7
RECOMMENDED
SOLDERING FOOTPRINT*
BOTTOM VIEW
PACKAGE
OUTLINE
A1
0.40
28X
0.25
PITCH
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON91880F
WLCSP28, 3.1X1.65, 0.4P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明