NCP4307FASNT1G_技术文档

DATA SHEET

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Secondary Side Synchronous

Rectification Driver for High

Efficiency SMPS Topologies

1

TSOP−6

SN SUFFIX

CASE 318G−02

NCP4307

The NCP4307 is high performance driver tailored to control a

synchronous rectification MOSFET in switch mode power supplies.

Thanks to its high performance drivers and versatility, it can be used in

various topologies such as DCM or CCM flyback, quasi resonant

flyback and forward.

Internal minimum off−time and on−time blanking periods help to

fight the ringing induced by the PCB layout and other parasitic

elements. A reliable and noise less operation of the SR system is

ensured due to the Self Synchronization feature. The NCP4307 also

utilizes Kelvin connection of the driver to the MOSFET to achieve

high efficiency operation at full load and utilizes a light load detection

architecture to achieve high efficiency at light load.

MARKING DIAGRAM

XXXAYWG

G

1

XXX = Specific Device Code

A

Y

W

= Assembly Location

= Year

= Work Week

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

The precise turn−off threshold, extremely low turn−off delay time

and high sink current capability of the driver allow the maximum

synchronous rectification MOSFET conduction time and enables

maximum SMPS efficiency.

Self−supply capability allows to use NCP4307 in high side

configuration and/or in low output voltage SMPS without auxiliary

winding or other power source.

Features

Typical Applications

• Self−Contained Control of Synchronous Rectifier in CCM, DCM and • Notebook Adapters

QR for Flyback Applications

• Precise True Secondary Zero Current Detection

• High Power Density AC/DC Power Supplies

(Cell Phone Chargers)

• LCD TVs

• Typically 15 ns Turn off Delay from Current Sense Input to Driver

• Rugged Current Sense Pin (up to 200 V)

• All SMPS with High Efficiency

Requirements

• Self−Supply Capability in Case of High Side Operation or Low

V

OUT

• Ultrafast Turn−off Trigger Interface/Disable Input (10.5 ns)

• Internal Minimum ON−Time With Reverse Current Protection

• Internal Minimum OFF−Time with Ringing Detection

• Improved Robust Self Synchronization Capability

• 7 A / 2 A Peak Current Sink / Source Drive Capability

• Operating Voltage Range up to V = 35 V

CC

• Automatic Light−Load Disable Mode

• High Side Operation Capability without External Components or

Auxiliary Winding

• Two VCC Pins Option Allows to Optimize Power Consumption in

Wide V

Range Applications

OUT

• Low Startup and Disable Current Consumption

• TSOP6 Package

• These are Pb−Free Devices

1

Publication Order Number:

NCP4307/D

May, 2022 − Rev. 0

NCP4307

ORDERING INFORMATION

Device Order Number

NCP4307FASNT1G

†

Specific Device Marking

Package Type

Shipping

7FA

7F2

TSOP−6

(Pb−Free)

3000 / Tape and Reel

NCP4307FBSNT1G

NCP4307AASNT1G

7AA

7WA

NCP4307WASNT1G

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Figure 1. Typical Application Example – DCM, CCM or QR Flyback Converter

Figure 2. Typical Application Example – DCM, CCM or QR Flyback Converter with Two VCC Sources

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2

NCP4307

Figure 3. Typical Application Example – DCM, CCM or QR Flyback Converter with NCP4307 in High Side

Configuration with Self−Supply

Figure 4. Typical Application Example – DCM, CCM or QR Flyback Converter with NCP4307 in High Side

Configuration with Dual Aux Supply

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NCP4307

Figure 5. Typical Application Example – Two Switch Forward with Freewheeling and Forward Synchronous

Rectifications. Forward SR Uses Special Version with Trigger Blocking Function

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NCP4307

PIN FUNCTION DESCRIPTION

TSOP6

Pin Name

DRV

Description

1

2

Driver output for the SR MOSFET

GND

Ground connection for the SR MOSFET driver and V

decoupling capacitor.

CCL

GND pin should only be connected directly to the SR MOSFET source terminal/soldering point using Kelvin

connection.

3

4

CS

Current sense pin detects if the current flows through the SR MOSFET and/or its body diode. Basic turn−

off detection threshold is 0 mV. Internal current source takes supply from this pin for SR self−supply.

TRIG/DIS

Ultrafast turn−off input that can be used to turn off the SR MOSFET in CCM applications in order to im-

prove efficiency. Activates disable mode if pulled−up for more than 100 ms. It is also used as +dV/dt detec-

tor pin or driver blocking in special cases. This pin is mostly active high (positive logic), but some device

versions may have active low (negative logic) option. See OPN coding table for details.

5

6

VCCH

VCCL

Connected to higher than VCCL pin voltage in VCCH range, or connect it to VCCL pin if not used

Main supply voltage pin. Decoupling capacitor should be connected to this pin and GND pin. Connect it to

power source with voltage of V

wanted

range via diode or connect capacitor there, in case if self−supply is

CCL

DISABLE

LLD detection

RESET

Minimum ON time

generator

ELAPSED

EN

INT_ADJ

DRV

DRV Out

DRIVER

−dV/dt

CS_ON

CS_OFF

CS_RESET

Control logic

CS

detection

CS

V_DD

RESET

ELAPSED

EN

Minimum OFF

time generator

VCCL

V_CCmanagment

UVLO

INT_ADJ

DISABLE

+dV/dt

TRIG

TRIG / DIS

CTRL

Level cmp

Disable

detection

+dV/dt cmp

VCCH

GND

Current source

+ TSD

CTRL

INT_ADJ

Current source

+ TSD

Figure 6. Internal Circuit Architecture – NCP4307

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NCP4307

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Value

−0.3 to 37.0

−0.3 to 17.0

−1 to 200

−10 to 200

−3 to 12

3

Unit

V

Supply Voltage at VCCL Pin

Supply Voltage at VCCH Pin

TRIG/DIS Pin Voltage

CCL

CCH

V

TRIG/DIS

V

DRV

Driver Output Voltage

V

Current Sense Input Voltage

Current Sense Dynamic Input Voltage (t

V

CS

V

= 200 ns)

PW

V

CS_DYN

I

DRV Pin Current (t

= 4 ms)

A

DRV_DYN

PW

I

VCCL Pin Current (t

= 4 ms)

PW

A

VCCL_DYN

I

CS Pin Current

250

mA

°C/W

°C

V

CS

J−A_TSOP6

R

Junction to Air Thermal Resistance, TSOP6

Maximum Junction Temperature

Storage Temperature

250

q

T

150

JMAX

T

STG

−60 to 150

2000

ESD

ESD Capability, Human Body Model (Note 1)

ESD Capability, Charged Device Model (Note 1)

HBM

1000

V

CDM

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E.

Charged Machine Model per JEDEC Standard JESD22−C101F

2. This device meets latch−up tests defined by JEDEC Standard JESD78D.

RECOMMENDED OPERATING CONDITIONS

Symbol

, V

Parameter

Maximum Operating Voltage

Operating Junction Temperature

Min

−

Max

35

Unit

V

CCL

CCH

T

J

−40

125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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NCP4307

ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 125°C; V

= 12 V; V

= 0 V; C

= 0 nF; V

= 0 V (V = 5 V

TRIG/DIS

J

CCL

CCH

DRV

TRIG/DIS

or V

whichever is lower for negative trigger logic); V = 0 V, unless otherwise noted. Typical values are at T = +25°C)

CCL

CS

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

SUPPLY SECTION

V

VCCL UVLO

V

rising

3.7

3.2

−

4.0

3.5

0.5

55

4.2

3.7

−

V

CCL_ON

CCL

V

falling

CCL_OFF

CCL_HYS

CCL

VCCL UVLO Hysteresis

V

t

Start−up Delay

V

CCL

rising from 0 to V + 1 V

CCL_ON

−

80

ms

START_DEL

@ t = 10 ms

R

I

Dynamic Current Consumption

C

CS

= 0 nF,

V

= 10 V

−

0.8

1.8

1.2

12

1.6

3.0

2.4

18

mA

CCL_D

DRV

DRVMAX

f

= 100 kHz

= 5 V

= 10 V

= 5 V

= 10 V

= 5 V

C

= 1 nF,

= 100 kHz

DRV

f

CS

C

= 10 nF,

= 100 kHz

DRV

f

CS

6.0

0.50

50

12

I

Quiescent Current Consumption

Current Consumption below UVLO

0.75

80

mA

CCL_Q

I

positive trigger logic,

= V – 0.1 V

mA

CCL_UVLO

V

CCL

CCL_OFF

negative trigger logic,

−

60

90

V

= V

– 0.1 V

CCL

CCL_OFF

I

Current Consumption in Light Load Mode

Current Consumption in Disable Mode

V

= 4 V; t > t

LLD

−

185

45

250

70

mA

CCL_LL

CS

I

positive trigger logic, V

= 5 V

−

CCL_DIS

TRIG/DIS

negative trigger logic, V

= 0 V

−

55

80

TRIG/DIS

I

VCCH Current

V

CCL

V

CCH

V

CCH

V

CCH

V

CCH

= 4.0 V, V

= 12 V, V

= 16 V, V

= 12 V, V

= 16 V, V

= 12.0 V

20

4.4

8.4

4.9

8.9

30

40

mA

V

CCH

V

VCCH Current Activation Threshold

= 4.7 V

= 9.0 V

= 4.7 V

= 9.0 V

4.7

8.9

5.2

9.4

4.9

9.4

5.4

9.9

CCL_SB_A

VCCH Current Deactivation Threshold

V

CCL_SB_D

DRIVER OUTPUT

t

Output Voltage Rise−Time

C

CS

= 10 nF, 10 % to 90 % V

,

−

60

25

100

50

ns

R

DRV

DRVMAX

V

= 4 to −1 V

t

Output Voltage Fall−Time

C

= 10 nF, 90 % to 10 % V

DRV

F

DRVMAX

V

CS

= −1 to 4 V

R

Driver Source Resistance

Driver Sink Resistance

Guaranteed by Design

−

2

0.5

2

−

W

DRV_SOURCE

R

DRV_SINK

DRV_SOURCE

I

t

Output Peak Source Current

Output Peak Sink Current

Maximum Driver Pulse Length

A

I

7

A

DRV_SINK

If it takes longer, DRV output voltage

and comparators thresholds may be

affected

4

ms

DRV_ON_MAX

V

Maximum Driver Output Voltage

Minimum Driver Output Voltage

V

= 35 V, C

DRV

DRVMAX

> 1 nF,

9

10

11

V

DRV_MAX

CCL

= 10 V

V

= 35 V, C

> 1 nF,

4.5

5.0

5.5

CCL

DRVMAX

DRV

= 5 V

V

CCL

V

CCL

= 3.8 V, V

= 10 V

3.6

3.8

4.0

DRV_MIN

DRVMAX

= 5 V

DRVMAX

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NCP4307

ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 125°C; V

= 12 V; V

= 0 V; C

= 0 nF; V

= 0 V (V

= 5 V

J

CCL

CCH

DRV

TRIG/DIS

or V

whichever is lower for negative trigger logic); V = 0 V, unless otherwise noted. Typical values are at T = +25°C) (continued)

CCL

CS

J

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

CS INPUT

t

Total Propagation Delay From CS to

DRV Output On

V

CS_F

goes down from 4 to −1 V,

−

30

15

60

23

ns

CS_ON_PD

CS

t

≤ 5 ns

t

Total Propagation Delay From CS to

DRV Output Off

V

CS_R

goes up from −1 to 4 V,

≤ 5 ns

CS_OFF_PD

CS

t

V

Turn On CS Threshold Voltage

Turn Off CS Threshold Voltage

Turn Off Timer Reset Threshold Voltage

Off Comparator Blanking Time

−120

−1

−85

−40

0

mV

V

CS_ON

V

Guaranteed by Design

CS_OFF

V

0.4

0.5

0.6

CS_RESET

t

_

Minimum on time is running;

−20%

t

+30%

ns

CS OFF_BLK

CS_OFF

_BLK

t

= 105, 155 ns

CS_OFF_BLK

Minimum on time is running;

= 205, 255, 300, 390,

−15%

+15%

t

CS_OFF_BLK

485, 600 ns

I

CS Leakage Current

V

= 200 V

−

10

−

mA

V

CS_LEAKAGE

CS

V

−dV/dt Detector High Threshold

−dV/dt Detector Low Threshold

−dV/dt Detector Threshold

3

CS_DVDT_H

V

−

0.5

45

−

V

CS_DVDT_L

t

Note 3

t

= 45 ns

= 35 ns

= 25 ns

= 15 ns

−

ns

CS_−DV/DT

−

35

−

18

−

25

32

−

15

I

Supply Current

V

J

= 50 V, V

= 4 V, V

= 0 V,

90

105

120

mA

CS_SS

CS

CCL

CCH

T = 25°C

V

J

= 50 V, V

= 0 V, V

= 0 V,

−

10

−

CS

CCL

CCH

T = 25°C

TSD

Supply Block Thermal Shut Down

−

170

20

−

°C

SS

TSD

Supply Block Thermal Shut Down

Hysteresis

SS_H

V

Supply Block Activation Threshold

V

CS

V

CS

V

CS

V

CS

= 20 V, V

= 4.7 V

= 9.0 V

= 4.7 V

= 9.0 V

4.4

8.4

4.9

8.9

4.7

8.9

5.2

9.4

4.9

9.4

5.4

9.9

V

CCL_SB_A

V

Supply Block Deactivation Threshold

CCL_SB_D

TRIGGER DISABLE INPUT

t

Minimum Trigger Pulse Duration

V

= 5 V (V = 0 V for

TRIG/DIS

−

10

ns

TRIG_PW_MIN

TRIG/DIS

negative trigger logic); Shorter pulses

may be not proceeded

V

Trigger Threshold Voltage

1.7

2.0

5

2.3

15

V

TRIG_TH

t

Trigger to DRV Propagation Delay

positive trigger logic, V

goes

−

ns

TRIG_PD

TRIG/DIS

from 0 to 5 V, t

≤ 5 ns

TRIG/DIS_R

negative trigger logic, V

goes

−

30

75

−

11

50

20

70

TRIG/DIS

≤ 5 ns

from 5 to 0 V, t

TRIG/DIS_R

t

Trigger Blank Time After DRV Turn−on

V

CS

drops below V

CS_ON

ns

ms

TRIG_BLANK

Event

t

Delay to Disable Mode

Disable Recovery Timer

V

goes from 0 − 5 V (5 − 0 V

100

1.5

125

3.0

DIS_TIM

TRIG/DIS

for negative trigger logic)

t

V

goes down from 5 − 0 V

DIS_REC

TRIG/DIS

(0 − 5 V for negative trigger logic)

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NCP4307

ELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 125°C; V

= 12 V; V

= 0 V; C

= 0 nF; V

= 0 V (V

= 5 V

J

CCL

CCH

DRV

TRIG/DIS

or V

whichever is lower for negative trigger logic); V = 0 V, unless otherwise noted. Typical values are at T = +25°C) (continued)

CCL

CS

J

Symbol

Parameter

Test Conditions

Min

Typ

−

Max

Unit

t

Minimum Pulse Duration to Disable

Mode End

V

= 0 V; Shorter pulses may

be not proceeded

−

200

ns

DIS_END

TRIG/DIS

I

Positive Trigger Logic, Pull Down Current

Negative Trigger Logic, Pull Up Current

Maximum Transition Time

V

= 5 V

5

−14

−

10

−10

−

14

−5

10

mA

TRIG/DIS

= 0 V

t

goes from 1 to 3 V or from 3

ms

TRIG_TRAN

to 1 V

V

+dV/dt Detector Threshold

1.70

1.95

2.20

V

TRIG_DVDT

MINIMUM t AND t

ON

OFF

t

Minimum On Time

t

= 500, 600, 800, 900, 1100,

−10%

t

+10%

ns

ON_MIN

1400, 1700, 2000 ns

t

Initial On Blank Time

t

= 55 ns

= 90 ns

= 200 ns

33

70

50

90

72

120

ON_INIT_BLK

170

−10%

200

230

t

Internal Minimum t

Time

= 1.00, 1.75, 2.50, 3.25,

t

+10%

ms

OFF_MIN

OFF

OFF_MIN

4.00, 4.75, 5.50, 6.25 ms

OFF_MIN

LIGHT LOAD DETECTION

LLD Main Time

t

V

> V

CS_LLD

80

−

100

−

120

−

ms

mV

ns

LLD

CS

V

LLD Detection Threshold

Light Load Recovery Time

Detected at CS pin

CS_LLD

t

Guaranteed by Design

−

100

LLD_REC

LLD_EXIT_BLK

t

Light Load Exit On Comparator Blank

Time

V

CS

V

CS

V

CS

< 0 V, t

= 45 ns

−30%

−20%

t

+20%

+15%

ns

LLD_EXIT_BLK

LLD_EXIT

_BLK

= 100 ns

= 200, 300 ns −15%

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. Test signal

V_CS[V]

4.0

V_{CS_DVDT_H}

t_{CS_−DV/Dt}

1.5

V_{CS_DVDT_L}

t [ns]

−1.0

Figure 7. Test Signal

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NCP4307

TYPICAL CHARACTERISTICS

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

0.8

0.7

VCCL on

0.6

0.5

0.4

0.3

T = 125°C

J

T = 105°C

J

T = 85°C

J

T = 55°C

J

T = 25°C

J

VCCL off

0.2

T = 0°C

J

T = −20°C

T = −40°C

J

0.1

0

3.4

3.3

−40 −20

0

20

40

60

80

100 120

0

5

10

15

20

(V)

25

30

35

T , JUNCTION TEMPERATURE (°C)

V

CCL

J

Figure 8. V_CCLONand V_CCLOFFLevels

Figure 9. VCCL Quiescent Current

Consumption V_CS= 0 V

250

200

100

90

80

70

60

50

40

30

20

150

100

T = 125°C

J

T = 105°C

J

T = 85°C

J

T = 55°C

J

T = 25°C

T = 125°C

T = 105°C

J

T = 25°C

T = 0°C

J

T = 0°C

J

50

0

T = −20°C

T = 85°C

T = 55°C

J

T = −20°C

T = −40°C

J

T = −40°C

J

10

0

5

10

15

20

(V)

25

30

35

40

0

5

10

15

20

25

30

35

40

V

CCL

(V)

CCL

Figure 10. VCCL Current Consumption in

Disable by LLD Function, V_CS= 4 V, t > t_LLD

Figure 11. VCCL Current Consumption in

Disable by TRIG/DIS Function,

V_CS= 0 V and V_TRIG/DIS= 5 V

800

700

600

500

400

250

230

210

190

170

150

300

200

130

110

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 12. VCCL Quiescent Current

Consumption

Figure 13. VCCL Current Consumption in

Disable Caused by LLD Function

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NCP4307

TYPICAL CHARACTERISTICS

100

90

80

70

60

50

40

80

75

70

65

60

55

50

45

40

30

20

35

30

−40 −20

0

20

40

60

80

100 120

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 14. VCCL Current Consumption in

Disable Activated by TRIG

Figure 15. VCCL Current Consumption Below

UVLO, VCCL = V_CCLOFF– 0.1 V

2.5

2.0

1.4

1.2

1.0

0.8

0.6

0.4

1.5

1.0

T = 125°C

J

T = 105°C

J

T = 85°C

J

T = 55°C

J

T = 25°C

T = 125°C

T = 105°C

J

T = 25°C

T = 0°C

J

T = 0°C

J

0.5

0

T = −20°C

T = 85°C

T = 55°C

J

T = −20°C

T = −40°C

J

0.2

0

J

T = −40°C

J

0

5

10

15

20

(V)

25

30

35

0

5

10

15

20

(V)

25

30

35

V

CCL

V

CCL

Figure 16. VCCL Current Consumption for 10 V

Driver, V_CS= −1 to 4 V, f_CS= 100 kHz, C_DRV= 1 nF

Figure 17. VCCL Current Consumption for 5 V

Driver, V_CS= −1 to 4 V, f_CS= 100 kHz, C_DRV= 1 nF

18

16

14

12

10

8

12

10

8

CDRV = 10 nF

CDRV = 1 nF

6

4

CDRV = 0 nF

4

2

0

CDRV = 1 nF

2

0

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 18. VCCL Current Consumption for 10 V

Figure 19. VCCL Current Consumption for 5 V

Driver, V_CS= −1 to 4 V, f_CS= 100 kHz, V_CCL= 12 V

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NCP4307

TYPICAL CHARACTERISTICS

0.4

0.2

1.2

1.0

0.8

0

−0.2

−0.4

−0.6

−0.8

−1.0

T = 125°C

J

T = 105°C

J

0.6

0.4

T = 85°C

J

T = 55°C

J

T = 25°C

J

T = 125°C

T = 105°C

J

T = 25°C

J

T = 0°C

J

T = 0°C

J

T = −20°C

0.2

0

J

T = 85°C

T = 55°C

J

T = −20°C

J

T = −40°C

J

−1.2

−1.4

T = −40°C

J

−1.0 −0.8 −0.6 −0.4 −0.2

0

0.2 0.4 0.6 0.8 1.0

−1.0 −0.8 −0.6 −0.4 −0.2

0

0.2 0.4 0.6 0.8 1.0

V

CS

(V)

V

CS

(V)

Figure 20. CS Current, V_CCL= 12 V

Figure 21. Supply Current vs. CS Voltage at

_CCL= 12 V

V

−40

−50

−60

−70

−80

−90

−100

1.0

0.5

0

−0.5

−1.0

−1.5

−2.0

−110

−120

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 22. CS Turn−on Threshold

Figure 23. CS Turn−off Threshold

0.60

0.55

0.50

1000

900

800

700

600

500

400

300

200

0.45

0.40

100

0

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 24. CS Reset Threshold

Figure 25. CS Leakage Current V_CS= 200 V

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12

NCP4307

TYPICAL CHARACTERISTICS

60

55

50

45

40

35

30

25

20

24

22

20

18

16

14

12

10

8

15

10

−40 −20

6

4

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 26. Propagation Delay from CS to DRV

Output On

Figure 27. Propagation Delay from CS to DRV

Output Off

2.4

2.2

2.0

2.3

2.2

2.1

2.0

1.9

1.8

1.6

T = 125°C

T = 105°C

J

T = 100°C

T = 25°C

J

T = 90°C

T = 0°C

J

1.8

1.7

1.4

1.2

T = 85°C

T = −20°C

J

T = −40°C

J

T = 55°C

J

4

5

6

7

8

9

10 11

12 13 14

−40 −20

0

20

40

60

80

100

120

V

CCL

(V)

T , JUNCTION TEMPERATURE (°C)

J

Figure 28. Trigger Threshold

Figure 29. Trigger Threshold V_CC= 12 V

2.3

2.2

2.1

2.0

1.9

2.3

2.2

2.1

2.0

1.9

T = 125°C

T = 105°C

J

T = 100°C

T = 25°C

J

T = 90°C

T = 0°C

J

T = 85°C

T = −20°C

J

T = −40°C

J

T = 55°C

J

1.8

1.7

1.8

1.7

0

5

10

15

20

25

30

−40 −20

0

20

40

60

80

100 120

V

CCL

(V)

T , JUNCTION TEMPERATURE (°C)

J

Figure 30. Trigger +dV/dt Threshold

Figure 31. Trigger +dV/dt Threshold

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13

NCP4307

TYPICAL CHARACTERISTICS

15

14

13

12

11

10

9

12

10

8

T = 125°C

J

T = 105°C

6

J

T = 85°C

J

T = 55°C

J

4

T = 25°C

J

T = 0°C

J

2

0

T = −20°C

T = −40°C

J

8

7

−40 −20

0

20

40

60

80

100 120

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

T , JUNCTION TEMPERATURE (°C)

V

TRIG

J

Figure 32. TRIG/DIS Pull Down Current

Figure 33. TRIG/DIS Pull Down Current to

V_TRIG/DIS

17

15

13

11

9

120

115

110

105

100

95

7

90

5

3

85

80

−40 −20

0

20

40

60

80

100

120

−40 −20

0

20

40

60

80

100

120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 34. Propagation Delay from TRIG/DIS to

DRV Output Off

Figure 35. Delay to Disable Mode, V_TRIG= 5 V

1200

1180

1160

1140

1120

1100

1080

1060

1040

1.20

1.18

1.16

1.14

1.12

1.10

1.08

1.06

1.04

T = 125°C

T = 25°C

J

T = 105°C

T = 0°C

J

T = 85°C

J

T = −20°C

J

1020

1000

T = 55°C

T = −40°C

1.02

1.00

J

0

5

10

15

20

(V)

25

30

35

−40 −20

0

20

40

60

80

100 120

V

CCL

T , JUNCTION TEMPERATURE (°C)

J

Figure 36. Minimum On Time

_{ON_MIN}= 1.1 ms

Figure 37. Minimum On Time

t

t_{ON_MIN}= 1.1 ms

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14

NCP4307

TYPICAL CHARACTERISTICS

125

120

115

110

105

100

95

4.6

4.4

4.2

4.0

3.8

90

85

3.6

3.4

80

75

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 38. Initial On Blank Time

Figure 39. Minimum Off−time t_{OFF_MIN}= 4 ms

t

_{ON_INIT_BLK}= 100 ns

310

300

290

280

270

260

250

240

230

300

290

280

270

260

250

240

230

220

T = 125°C

T = 25°C

J

T = 105°C

T = 0°C

J

T = 85°C

T = −20°C

J

220

210

200

T = 55°C

J

T = −40°C

J

−40 −20

0

20

40

60

80

100 120

0

5

10

15

20

(V)

25

30

35

T , JUNCTION TEMPERATURE (°C)

V

CCL

J

Figure 40. Off Comparator Blanking Time

_{CS_OFF_BLK}= 255 ns

Figure 41. Off Comparator Blanking Time

_{CS_OFF_BLK}= 255 ns

t

120

115

110

105

100

95

120

115

110

105

100

95

T = 125°C

T = 105°C

J

T = 25°C

J

T = 0°C

J

90

T = 85°C

T = 55°C

J

T = −20°C

J

T = −40°C

J

85

80

85

80

2

4

6

8

10

12

14

−40 −20

0

20

40

60

80

100 120

V

CCL

(V)

T , JUNCTION TEMPERATURE (°C)

J

Figure 42. Light Load Detection Time

_LLD= 100 ms

Figure 43. Light Load Detection Time

_LLD= 100 ms

t

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15

NCP4307

TYPICAL CHARACTERISTICS

225

220

215

210

205

200

195

190

185

4.90

4.85

4.80

4.75

4.70

4.65

4.60

4.55

4.50

180

175

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 44. LLD Exit On Comparator Blank

Time t_{LLD_EXIT_BLK}= 200 ns

Figure 45. VCCH Current Activation Threshold

_{CCH_SB_A}= 4.7 V

V

9.2

9.1

5.40

5.35

5.30

5.25

5.20

5.15

5.10

9.0

8.9

8.8

8.7

8.6

8.5

5.05

5.00

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 46. VCCH Current Activation Threshold

_{CCH_SB_A}= 9.0 V

Figure 47. VCCH Current Deactivation

Threshold V_{CCH_SB_D}= 5.2 V

V

9.7

9.6

9.5

9.4

9.3

9.2

50

45

40

35

30

25

9.1

9.0

20

15

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 48. VCCH Current Deactivation

Threshold V_{CCH_SB_D}= 9.5 V

Figure 49. CCH Current to VCCL Pin,

V_CCH= 8.0 V, V_CCL= 4.0 V

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16

NCP4307

TYPICAL CHARACTERISTICS

40

35

30

25

20

15

10

120

110

100

90

T = 125°C

80

70

60

50

J

T = 105°C

J

T = 85°C

J

T = 55°C

J

T = 25°C

J

T = 0°C

J

T = −20°C

T = −40°C

J

5

0

40

30

−40 −20

0

5

10

15

(V)

20

25

30

0

20

40

60

80

100 120

V

T , JUNCTION TEMPERATURE (°C)

J

CCH

Figure 50. CCH Current to VCCL Pin,

_CCL= 4.0 V

Figure 51. CS Current to VCCL Pin,

_CS= 50 V, V_CCL= 4.0 V

V

100

90

80

70

60

50

40

30

20

10.4

10.2

10.0

9.8

T = 125°C

J

T = 105°C

J

T = 85°C

J

VCCL = 12 V, CDRV = 0 nF

9.6

T = 55°C

J

VCCL = 12 V, CDRV = 1 nF

VCCL = 12 V, CDRV = 10 nF

VCCL = 35 V, CDRV = 0 nF

VCCL = 35 V, CDRV = 1 nF

VCCL = 35 V, CDRV = 10 nF

T = 25°C

J

9.4

T = 0°C

J

T = −20°C

J

9.2

9.0

10

0

T = −40°C

J

0

10

20

30

40

(V)

50

60

70

80

−40 −20

0

20

40

60

80

100 120

V

T , JUNCTION TEMPERATURE (°C)

CS

J

Figure 52. CS Current to VCCL Pin,

_CCL= 4.0 V

Figure 53. Driver Output Voltage, 10 V

V

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

38

33

28

VCCL = 12 V, CDRV = 0 nF

VCCL = 12 V, CDRV = 1 nF

VCCL = 12 V, CDRV = 10 nF

VCCL = 35 V, CDRV = 0 nF

VCCL = 35 V, CDRV = 1 nF

VCCL = 35 V, CDRV = 10 nF

23

4.4

4.2

4.0

18

13

−40 −20

0

20

40

60

80

100

120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 54. Driver Output Voltage, 5 V

Figure 55. Negative dV/dt Detector Threshold

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17

NCP4307

INITIAL INFORMATION

APPLICATION INFORMATION

General Description

An ultrafast trigger input offers the possibility to further

increase efficiency of synchronous rectification systems

operated in CCM mode (for example, CCM flyback or

forward). The time delay from trigger input to driver turn off

The NCP4307 is designed to operate either as a standalone

IC or as a companion IC to a primary side controller to help

achieve efficient synchronous rectification in switch mode

power supplies. This controller features a high current gate

driver along with high−speed logic circuitry to provide

appropriately timed drive signals to a synchronous

rectification MOSFET. With its novel architecture, the

NCP4307 has enough versatility to keep the synchronous

rectification system efficient under any operating mode.

The NCP4307 works from an available voltage with range

event is t

. Additionally, the trigger input can be used

TRIG_PD

to disable the IC and activate a low consumption standby

mode. This feature can be used to decrease standby

consumption of an SMPS. If the trigger input is not wanted,

then the trigger pin can be tied to GND (or tied to V

case of negative TRIG/DIS logic).

in

CCL

An output driver features capability to keep SR transistor

turned−off even when there is no supply voltage for the

NCP4307. SR transistor drain voltage goes up and down

during SMPS operation and this is transferred through drain

gate capacitance to gate and may open transistor. The

NCP4307 keeps DRV pin pulled low even without any

supply voltage and thanks to this the risk of turned−on SR

from 4.0 / 3.5 V to 35 V (typical). The wide V

range

CCL

allows direct connection to the SMPS output voltage of most

adapters such as notebooks, cell phone chargers and LCD

TV adapters. If system offers two different voltage levels,

V

CCH

pin can be used for higher one. NCP4307 selects

better voltage from V

and V

to minimize power

CCL

CCH

consumption. Self−supply feature allows to use controller in

system without suitable supply voltage that is mainly case of

high side configuration.

Compared to other SR controllers that provide turn−off

thresholds in the range of −10 mV to −5 mV, the NCP4307

offers a turn−off threshold of 0 mV. When using a low

transistor, before enough V

is eliminated.

is applied to the NCP4307,

CCL

Finally, the NCP4307 features a Light Load Detection

(LLD) function. This function detects light load or no load

conditions, and decreases current consumption during and

between conduction phases. This helps to improve SMPS

efficiency.

R

DS_ON

SR (1 mΩ) MOSFET, our competition, with a

−10 mV turn off, will turn off with 10 A still flowing through

the SR FET, while our 0 mV turn off turns off the FET at 0A;

significantly reducing the turn−off current threshold and

improving efficiency. Many of the competitor parts

maintain a drain source voltage across the MOSFET,

causing the SR MOSFET to operate in the linear region to

reduce turn−off time. NCP4307 significantly reduces turn

off time, allowing for a minimal drain source voltage to be

utilized and efficiency maximized, thanks to the 7 A sink

current.

To overcome false triggering issues after turn−on and

turn−off events, the NCP4307 provides internal fixed

minimum on−time and off−time blanking periods. Blanking

times can be set internally during production.

An extremely fast turn−off comparator, implemented on

the current sense pin, allows for NCP4307 implementation

in CCM applications without any additional components or

external triggering.

Supply Section

Supply section block diagram is shown in Figure 56. Main

supply voltage pin is VCCL. Minimum voltage for proper

operation is typically 4.0 / 3.5 V and maximum level is

35 V. Decoupling capacitor between VCCL and GND pin is

needed for proper operation and its recommended value is

1 mF. Voltage to VCCL pin can be delivered from external

power source through external diode or from VCCH or CS

pin via internal current sources. Internal current sources are

activated in case of low voltage at VCCL (voltage threshold

depends on version). Current source from VCCH has higher

priority than current source from CS pin, because of lower

power loss in case of VCCH. If VCCH doesn’t have enough

voltage, CS current source is used. Higher capacitance of

capacitor at VCCL pin is needed in case of supply from CS

pin, because energy from CS is not delivered constantly, but

just according to voltage situation at SR transistor drain.

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18

NCP4307

To ext. source

VCCL

To ext. source

VCCH

Supply

block

Driver

DRV

Supply

control block

To SR tran. drain

CS

Self supply

block

Figure 56. Supply Section Block Diagram

SR transistor is usually used in low side configuration

(placed in return path), but it may be also used in high side

configuration (placed in positive line). It is not possible to

use SMPS output voltage for SR supply in high side

configuration so it is needed to provide supply differently.

One possibility is to use auxiliary winding as shown at

Figure 4. It is also possible to use AUX winding with two

outputs and connect it to VCCL and VCCH pins. If auxiliary

winding is not acceptable, SR transistor drain voltage can be

used as supply source (Figure 3). Drain voltage is used as

supply source for internal current source that charges

external VCCL capacitor. Operation of CS current supply

block is shown in Figure 57. CS current is reduced when

VCCL is low to avoid CS current block damage in case of

shorted VCCL pin and when VCCL gets higher CS current

gets its nominal value. Supply current is activated when CS

voltage is high enough and VCCL is below V

CCL_SB_A

level. CS current is also activated for short time when V

CS

goes high even when there is high enough voltage at VCCL

pin, this is beneficial to limit voltage overshoot at SR

transistor.

V_DS= V_CS

V_{CCL_SB_D}

Condensed

V_CCL

V_{CCL_SB_A}

CS current is activated also at begin of primary

on time even when there is enough voltage to

minimize voltage overshoot

time

CS current is reduced to avoid VCCL short difficuilties

I_CS

Figure 57. CS Current Source Operation

Current Sense Input

Figure 58 shows the internal connection of the CS

circuitry on the current sense input. When the voltage on the

secondary winding of the SMPS reverses, the body diode of

SR transistor M1 starts to conduct current and the voltage of

M1’s drain drops to approximately −1 V. Once the voltage

on the CS pin is lower than V

threshold, M1 is

CS_ON

turned−on. Because of parasitic impedances, significant

ringing can occur in the application. To overcome false

sudden turn−off due to mentioned ringing, the minimum

conduction time of the SR MOSFET is activated.

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19

NCP4307

Figure 58. Current Sensing Circuitry Functionality

V

+ V

RDSON

L_DRAIN L_SOURCE

V

L_SOURCE

L_DRAIN

RDSON

I

SD

Figure 59. Current Sensing Equivalent Circuit

Sensing equivalent circuit is shown in Figure 59. SR

MOSFET consists of silicon die with channel resistance

to positive values and causes SR transistor turn−off sooner

than current reaches 0 A. Secondary side current also

usually has ringing with very high dI/dt, that leads to

positive drop at SR transistor even when there is still current

in correct direction. This situation has to be solved by SR

controller to avoid incorrect very early turn−off of SR

transistor. Example of sensed voltages for 65 kHz flyback

R

DS_ON

and from bonding connection to drain and source.

These connections have not just resistance, but also

inductance, so sensed voltage is sum of drops at all of these

elements. Flyback secondary side current shape is

triangular, which means it is decreasing most time of

conduction phase. dI/dt of secondary current makes drop at

inductive part of equivalent MOSFET circuit that is opposite

to drop at resistive part. Inductive drop moves overall drop

with parameters of SR transistor R

= 4 mW and

DS_ON

L

+ L

= 1.5 nH is shown in Figure 60.

DRAIN

SOURCE

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20

NCP4307

I

SD

Real turn−off

Ideal turn−off

V

+ V

L_SOURCE

L_DRAIN

V

CS_OFF

V

RDSON

V

DS

= V

+ V

RDSON

L_SOURCE

L_DRAIN

DRV

MIN_TON

Figure 60. Drops at SR Transistor in Flyback Application

The SR MOSFET is turned−off as soon as the voltage on

the CS pin is higher than V (typically −0.5 mV). For

reset comparator if some spurious ringing occurs on the CS

input after SR MOSFET turn−off event. This feature

significantly simplifies SR system implementation in

flyback converters.

CS_OFF

the same ringing reason, a minimum off−time timer is

asserted once the V goes above V . The

CS

CS_RESET

minimum off−time generator can be re−triggered by CS

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21

NCP4307

V_DS= V_CS

I_SEC

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

V_DRV

Turn−on delay

Turn−off delay

t

timer was

OFF_MIN

Min ON−time

Min OFF−time

stopped here because of

V

t_{ON_MIN}

< V

CS

CS_RESET

t_{OFF_MIN}

t

Figure 61. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback

Minimum On Time Generation

Minimum on−time purpose is to blank noisy current

during beginning of conduction phase to minimize risk of

early turn−off of SR transistor. Off comparator is blanked

during minimum on−time (except initial blank where OFF

comparator is fully ignored, initial blank should cover SR

with initial on blank time (t

) at the beginning of

ON_INIT_BLK

secondary side conduction phase. OFF comparator is fully

disabled during t , but it is just partly blanked

ON_INIT_BLK

during minimum on−time interval. If OFF comparator

detects higher voltage than V for shorter time than

CS_OFF

transistor turn−on time) for t

. If CS pin voltage

t

, SR transistor is kept on, but if OFF

CS_OFF_BLK

is above turn−off threshold for more than t

transistor is turned−off. OFF comparator reacts within

propagation delay when minimum on time elapses.

, SR

comparator stays high longer, SR transistor is turned−off.

This helps with minimizing risk of negative current or cross

conduction conditions.

CS_OFF_BLK

Minimum on−time interval (t

) starts simultaneously

ON_MIN

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22

NCP4307

V_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

DRV

Turn−off delay

Turn−on delay

Min ON−time

t_{ON_MIN}

OFF−cmp blanked for limited time (t_{CS_OFF_BLK}) during t_{ON_MIN}

No blanking after t_{ON_MIN}

OFF cmp

Initialblanking

t_{ON_INIT_BLK}

Min t_OFFtimer was

stopped here because

of V_CS<V_{CS_RESET}

Min OFF−time

t_{OFF_MIN}

t

Figure 62. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback

The fact that driver can be turned off also during minimum

on time helps to solve reverse current issue. This means, that

when current starts to flow in opposite direction for any

reason (too long minimum on time, primary side turns on,

through condition. Figure 63 shows situation when primary

switch suddenly turns on during minimum on time. Driver

is turned off very soon after reverse condition is detected and

minimizes impact of shot through condition even when

minimum on time is still running.

etc.), driver is turned off after blank time t

CS_OFF_BLK

elapses. This significantly reduces risk and impact of shot

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23

NCP4307

V_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

V_DRV

Turn−on delay

Turn−off delay

Min ON−time

t_{ON_MIN}

OFF−cmp blanked for limited time (t_{CS_OFF_BLK}) during t_{ON_MIN}

OFF cmp

Initial blanking

t_{ON_INIT_BLK}

Blanking elapsed, OFF_cmp still high −> turn driver off

Min OFF−time

t_{OFF_MIN}

t

Figure 63. Driver Behavior in Case of Suddenly Turned on Primary Side Switch

Minimum on time should be set longer than current

ringing takes at the beginning of conduction phase in

different operation conditions. Longer than necessary

minimum on time is not an issue, because the driver can also

be safely turned off during the minimum on time interval, so

there is no risk of deep reverse conduction or shot through

event.

conduction phase. This ringing may take drain voltage down

below V

and driver may be incorrectly triggered

CS_ON

without off timer. Off timer is started after conduction phase

when CS pin voltage (SR transistor V voltage) goes above

DS

V

. If V drops down below V

during

CS_RESET

CS

CS_RESET

timer execution, timer is reset and next start is triggered by

getting V above V (see Figure 62). This happens

CS

CS_RESET

until minimum off time completely elapses during V

>

CS

Minimum Off Time Generation

Main purpose of minimum off time timer is to blank ON

comparator during DCM ringing at SR transistor drain after

V . SR controller is then ready to turn on driver

CS_RESET

when ON comparator detects that V < V

. Minimum

CS

CS_ON

off time should be set to longer time than ringing period.

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24

NCP4307

Negative dV/dt Detection

switch is turned on and off again so SR controller doesn’t

turn on SR MOSFET. Whole secondary side current then

flows through body diode that makes power loss. Figure 64

shows situation without −dV/dt detection. Here it can be

seen that without –dV/dt detection next conduction cycle

may not be taken through activated SR transistor. Reason is

not elapsed minimum off−time blanking interval before next

conduction cycle begins.

The NCP4307 includes optional feature for flyback type

converters, which operates with shorter primary on−time

than ringing period after demagnetization phase during

medium/high loads. These applications are for example

USB−PD, Quick Charge adapters or other SMPS with wide

range input and output voltage. Difficulty with this situation

is that minimum off−time doesn’t elapse before primary side

Primary on−time is very

short (shorter than ringing

t

has to be set

to longer time than

OFF_MIN

period) for low V

and

OUT

V

falls below V

CS

CS_ON

OFF_MIN

length of ringing period

sooner than t

elapses

t_{OFF_MIN}

V

_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

Driver is not turned−on

because t interval

V_DRV

OFF_MIN

doesn’t elapse

Turn−on delay

Turn−off delay

t

timer is

OFF_MIN

Min ON−time

Min OFF−time

stopped here because

of V < V

t_{ON_MIN}

CS

CS_RESET

t_{OFF_MIN}

t

Figure 64. Situation without −dV/dt Detection Feature

Figure 65 shows how system with activated −dV/dt

detection behaves. Minimum off−time blanking interval is

also reset during voltage drops at CS pin, but if high negative

demagnetization. Thanks to this we can safely differentiate

end of primary on−time (and beginning of secondary side

conduction period) from ringing. Negative dV/dt at CS pin

is detected as time that CS voltage needs to fall from 3.0 V

dV/dt event occurs at CS pin, t

interval is shorted

OFF_MIN

and SR controller is ready to detect CS voltage lower than

and turn SR transistor on. Negative dV/dt at CS pin

(V

) down to 0.5 V (V

). If CS voltage

in shorter time than

CS_DVDT_H

CS_DVDT_L

V

goes from V

to V

CS_ON

CS_DTDT_H

CS_DVDT_L

when primary low side switch is turned off is high in

compare to slope that comes during ringing after

t , negative dV/dt is detected.

CS_−DVDT

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25

NCP4307

t

has to be set

OFF_MIN

to longer time than

length of ringing period

t_{OFF_MIN}

V

_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

V_DRV

Turn−on delay

Turn−off delay

Turn−on delay

CS voltage drops below V

CS_ON

Min ON−time

Min OFF−time

but at time when t

doesn’t

t

timer is

OFF_MIN

t_{MIN_ON}

elapse and just low −dV/dt is

detected so DRV is not activated

stopped here because

of V < V

CS

CS_RESET

t_{OFF_MIN}

Negative dV/dt

detector at CS

t

timer doesn’t

OFF_MIN

elapse but high −dV/dt is

detected so DRV is enable

t

Figure 65. Situation with Enabled −dV/dt Detection

Positive dV/dt Detection

clamp transistor pulse sequence starts at 200 ns and

increases in 200 ns increments the ideal minimum on time

to set for the transition from ACF to DCM (LEM) would be

less than 200 ns. Unfortunately, during normal operation for

DCM or ACM the small minimum on time would result in

poor efficiency, because necessary minimum on time for

normal DCM and ACM operation is significantly longer to

keep SR transistor on during current oscillations than clamp

transistor on−time. Primary low side transistor is turned on

soon after the turn−off of clamp transistor, which can occur

while the SR transistor is still conducting. If the SR

transistor is still conducting when the low side transistor

turns on this can cause a cross current condition between

primary and secondary side. The cross conduction decreases

Active clamp flyback SMPS such as the NCP1568

operates in DCM (discontinuous conduction mode) at light

load and in ACM (active clamp mode) during heavy load.

When load is changed from light load to heavy load, the

SMPS operation changes from DCM to ACM where

primary high side (clamp) transistor is activated with slowly

increasing on−time. This transition, often referred to as

leading edge modulation (LEM), results in very difficult

operating conditions for the SR controller. The main issues

arise at the start of clamp transistor activation. The high side

clamp transistor is turned on for very short time (low

hundreds of ns) at the beginning of transition. When the

clamp transistor is turned on, secondary side current flows

such that the SR transistor is (can be) turned−on, because

secondary side current flows from source to drain. Since the

efficiency and increases overshoots at SR transistor V

See Figure 65.

.

DS

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26

NCP4307

Low side

transistor is

turned on

Clamp transistor

is turned on

t

has to be set

OFF_MIN

to longer time than

length of ringing period

t_{OFF_MIN}

V_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

CS voltage drops below

V

but at time when

CS_ON

t

doesn’t elapse and

OFF_MIN

just low −dV/dt is detected

so DRV is not activated

Primary and

secondary side

cross conduction

V_DRV

Turn−on delay

Turn−off delay

Turn−on delay

Min ON−time

Min OFF−time

t_{MIN_ON}

t

elapses

OFF_BLK

t_{MIN_ON}

driver goes off

t_{OFF_BLK}

t

timer is

OFF_MIN

stopped here because

of V < V

t_{OFF_MIN}

t

CS

CS_RESET

t

timer doesn’t

OFF_MIN

Negative dV/dt

detector at CS

elapse but high −dV/dt

is detected so DRV

can be turend−on

t

Figure 66. Situation with Disabled Positive dV/dt Detection

The SR needs to differentiate between conduction cycles

on the secondary side caused by the primary clamp transistor

or by the end of the primary low side switch conduction

phase. A positive dV/dt detector is used to identify the LEM

process. There is high positive dV/dt at the SR transistor

drain voltage when primary low side switch is turned on. If

high dV/dt is detected it is clear that the next SR conduction

cycle will be a normal ACM or DCM operation and a long

minimum on−time can be used by the SR transistor without

any risk. When the SR conduction phase ends the SR

controller waits again for positive dV/dt detection before it

allows activation of the driver by CS on comparator.

Figure 67 illustrates the activated positive dV/dt function in

action.

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27

NCP4307

Clamp transistor

has to be set to is turned on

t

OFF_MIN

longer time than length of

ringing period

t_{OFF_MIN}

V_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

V_{CS_ON}

CS voltage drops below V

CS_ON

but at time when t

doesn’t

OFF_MIN

elapse and just low −dV/dt is

detected so DRV is not activated

V_DRV

Turn−on delay

Turn−off delay

Turn−on delay

No positive dV/dt was

detected after last driver

turn−off event → driver

can’t be turned on

Min ON−time

Min OFF−time

t

timer is

OFF_MIN

t_{MIN_ON}

stopped here because

of V < V

CS

CS_RESET

t_{OFF_MIN}

Negative dV/dt

detector at CS

t

timer doesn’t

OFF_MIN

elapse but high −dV/dt

is detected so off

timer is done

Positive dV/dt

detector at

Positive dV/dt detected,

TRIG/DIS pin

t

done, driver

OFF_MIN

can be activated when

V

CS

goes below V

CS_ON

t

Figure 67. Situation with Enabled Positive dV/dt Detection that Fully Blocks Driver

Fully disabled driver until +dV/dt is detected may cause

issue for some application in different operation conditions.

No driver output then causes lower efficiency and may lead

to over temperature. It may be better not to block driver fully,

but it may be advantageous to allow driver to turn−on, but

without full minimum on−time. Minimum on−time should

be shortened just to t

that minimizes risk of

ON_INIT_BLK

potential cross conduction and also even so short minimum

on−time is usually enough in conditions with low dV/dt.

Operation with short minimum on−time when no +dV/dt is

detected is shown in Figure 68.

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28

NCP4307

Clamp transistor

is turned on

t

has to be set to

OFF_MIN

longer time than length

of ringing period

t_{OFF_MIN}

V

_DS= V_CS

I_SEC= I_SD

V_{CS_RESET}

V_{CS_OFF}

CS voltage drops below V

CS_ON

V_{CS_ON}

but at time when t

doesn’t

OFF_MIN

elapse and just low −dV/dt is de-

tected so DRV is not activated

V_DRV

Turn−off delay

Turn−on delay

Turn−off delay

No positive dV/dt was detect-

ed after last driver turn−off

event → driver can be turned

Min ON−time

Min OFF−time

t_{ON_MIN}

on just with t

min-

ON_MIN_INIT

imum on time interval

t_{ON_INIT_BLK}

t_{OFF_MIN}

Negative dV/dt

detector at CS

t

timer doesn’t

OFF_MIN

t

timer is

OFF_MIN

elapse but high −dV/dt

is detected so off timer

is done

stopped here because

of V < V

CS

CS_RESET

Positive dV/dt

detector at

TRIG/DIS pin

Positive dV/dt detected,

t

done, driver can

OFF_MIN

be activated when V

CS

goes below V

CS_ON

t

Figure 68. Situation with Enabled Positive dV/dt Detection that Shorts Minimum On−Time

Positive dV/dt is detected by external RC network

connected from the SR transistor drain to the TRIG/DIS pin

that has modified operation. There is a comparator at

at TRIG/DIS pin crosses threshold +dV/dt flag is set that

means driver can be activated when other parameters

(elapsed minimum off time, V below CS on threshold) are

CS

TRIG/DIS pin with V

threshold. When voltage

fulfilled.

TRIG_DVDT

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29

NCP4307

Figure 69. +dV/dt Detector Schematic in ACF SMPS (TRIG/DIS Pin Operation Changed)

Trigger/Disable Input

The NCP4307 features an ultrafast trigger input that

exhibits a maximum of t delay from its activation to

the start of SR MOSFET turn−off process. This input can be

used in applications operated in deep Continues Conduction

Mode (CCM) to further increase efficiency and/or to

activate disable mode of the SR driver in which the

a cross current condition. It may be advantageous to use

triggering from primary side to speed up turn−off process in

these cases.

TRIG_PD

Trigger reacts normally within t

when TRIG signal comes during t

except situation

TRIG_PD

interval that

TRIG_BLANK

starts from driver turn−on event. This interval protects

against false TRIG detection during SR transistor turn−on

process that may be very noisy. The trigger input has higher

priority than CS input except during trigger blank period.

TRIG/DIS signal turns the SR transistor off or prohibits its

turn−on when TRIG/DIS pin voltage is pulled above

consumption of the NCP4307 is reduced to I

.

CCL_DIS

Trigger pin input is mainly positive logic (active high), but

specific versions may be in negative logic (active low).

Please see OPN coding table for details. Following text will

show and describe just positive trigger logic, negative logic

works the same way just with inverted signal.

V

.

TRIG_TH

The NCP4307 is capable to turn−off the SR MOSFET

reliably in CCM applications based solely on CS pin

information, without using the trigger input. However, high

frequency applications, with small parasitics, feature very

fast and strong secondary side current changes that do not

allow even for a few ns prolonging of turn off event without

Same pin can be used also to activate disable mode when

it is pulled up for longer than t . Supply current is

DIS_TIM

significantly reduced down to I . IC exits disable

CCL_DIS

mode when TRIG/DIS pin goes back low below V

TRIG_TH

at least for t

time.

DIS_END

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30

NCP4307

V

DS

= V

CS

V

CS_RESET

V

CS_OFF

V

CS_ON

t

TRIG_BLANK

t_{TRIG_PD}

TRIG_BLANK

No reaction to TRIG

during blank time

V

TRIG/DIS

Driver is not activated,

Driver is turned off

because TRIG was high at

begin of conduction phase

when t

V

DRV

TRIG_BLANK

elapses

t

t22

t12

t10

t14 t16

t18 t20

t19

t1 t3

t2

t6

t8

t4

t5

t11

t17

t21

t7

t9

t13 t15

Figure 70. Trigger Input Functionality Waveforms Using the Trigger to Turn−off and Block the DRV Signal

Figure 70 shows basic TRIG/DIS pin functionality.

TRIG/DIS is pulled low at time t1 for normal operation, CS

is also no reaction to TRIG/DIS pin rise up at time t9,

because driver is off. TRIG/DIS goes low at time t11, next

conduction cycle starts at t12 and driver is turned on after on

propagation delay at time t13. TRIG/DIS blanking time

pin voltage goes below V

at time t2 that actives driver

CS_ON

at time t3 (after turn on propagation delay t

).

CS_ON_PD

Trigger blanking starts also at time t3 that means no reaction

to TRIG/DIS pin until t elapses. TRIG/DIS

(t

) is also started at t13. TRIG/DIS goes high at

TRIG_BLANK

t14, which is during the t

period. That is why

TRIG_BLANK

goes high at time t4 that causes after t

driver turn−off

there is no reaction until blanking time elapses at t15 and

driver goes low. Last example shows beginning of

conduction phase at time t18, driver activation and

TRIG_PD

event (t5) and rest of conduction period is taken through

bodydiode. Next conduction cycle begins at time t7, but

driver is not turned−on because TRIG/DIS pin is high.

TRIG/DIS falls down at time t8 during same conduction

cycle that causes no change, because driver can be

turned−on just at the beginning of conduction cycle. There

t

at t19. There is some noise at TRIG/DIS

TRIG_BLANK

during t

that has no effect on system and driver

TRIG_BLANK

is kept on up to point t21 where V voltage reaches

CS

V

.

CS_OFF

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31

NCP4307

Figure 71. Optional Triggering from Primary Side through Signal Transformer

Possible usage of triggering is shown in Figure 71. If

desired, the trigger can be connected with primary side via

small signal transformer. Signal at primary side DRV pin

comes sooner than primary transistor is turned−on (turn−on

process is slowed down by gate resistor) and it goes through

transformer TR2 to secondary side with almost no delay.

TR2 secondary winding is connected directly to TRIG/DIS

pin. SR transistor starts to turn off after propagation delay

and SR transistor is turned off sooner than primary side

switch is fully turned−on. This ensures no risk of cross

conduction between primary and secondary side.

Continuous conduction mode (CCM) operation without

triggering is shown in Figure 72. Left side shows overall

operation, right side is zoomed in grey area to show timing

details during turning off of the SR transistor at the end of

secondary side conduction cycle. The primary side driver is

activated at time t1 (blue line) that causes charging of the

primary transistor gate capacitance via the gate resistor (red

R

multiplied by current level plus drop at package

DSON

parasitic inductance multiplied by dI/dt and dI/dt changes

significantly. That’s why voltage drop measured by the SR

controller seems to be positive even when there is still

current that flows from source to drain (normal direction).

Voltage drop across the SR transistor DS is shown in blue

and its vertically zoomed level by red color. Once SR V

crosses V

event and starts to turn−off driver after propagation delay at

time t3. Turn off process takes t to time t4, where gate

voltage drops below threshold. Turn−off process is done

sooner than secondary side current falls below 0 A and

changes it direction so there is no cross current condition in

properly set system. Secondary side current goes negative

little bit, because it is needed to charge transistor output

capacitance and other parasitics. This also causes some

DS

(time t2) SR controller detects turn−off

CS_OFF

F

overshoot at SR transistor V . Properly set system can be

DS

identified by simple test, check CCM operation waveforms

with activated SR controller and compare them to

waveforms with disabled SR controller (TRIG/DIS pin held

high). Secondary side current waveform and the SR

line). The primary transistor V

voltage gets to the

GS

threshold level around time t2 that causes start of the turn−on

phase. The primary transistor V voltage starts to decrease,

DS

secondary side current changes its dI/dt. The SR transistor

drop across drain source also changes, because it is given by

transistor V waveform should be similar in both cases.

DS

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NCP4307

ISEC

SR V

DS

Zoomed

SR V

DS

V

CS_OFF

SR

t

CS_OFF_PD

V

DRV

t

F

Prim V

DRV

Prim V

GS

Prim V

DS

t

1

3

5

4

2

6

Figure 72. CCM Operation without Triggering from Primary Side

Operation waveforms for CCM system with triggering

from primary side are shown in Figure 73. Figure is done

similarly as previous one, there is just added TRIG/DIS

signal that comes from primary side through signal

transformer like is shown in Figure 71. This signal comes

from primary DRV pin with short delay to secondary side

TRIG/DIS pin. When the TRIG/DIS voltage rises above

is practically turned−off at time t4, when its gate voltage

drops below V . This happens sooner that secondary

GS(TH)

side current changes its direction, so rest of the conduction

phase up is taken by transistor’s bodydiode. Optional

solution with triggering turns SR transistor off sooner than

without it, which gives more confidence, that there will be

no cross current condition and that there will be long enough

deadtime between SR turn−off and primary on time.

V

(time t2) the SR controller starts with turn−off

TRIG_TH

process after propagation delay t

at t3. SR transistor

TRIG_PD

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33

NCP4307

ISEC

SR V

DS

Zoomed

SR V

DS

V

CS_OFF

t

TRIG_PD

SR V

DRV

t

F

Prim V

DRV

Prim V

GS

DS

Prim V

t

TRIG_TH

V

TRIG/DIS

t

1

3

5

4

7

2

6

8

Figure 73. CCM Operation with Triggering from Primary Side

The TRIG/DIS pin allows to send IC into disable mode by

pulling this pin up for more than t . Pulling pin up

Figure 74. The TRIG/DIS pin goes high at t3, driver stays

low from that time and after t

(at t4) disable mode is

DIS_TIM

disables SR operation and significantly decreases current

consumption. Disable mode activation is shown in

activated.

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34

NCP4307

V

DS

= V

CS

V

CS_RESET

V

CS_OFF

V

CS_ON

V

TRIG/DIS

t

DIS_TIM

Min ON−time

V

DRV

I

CCL

t

t0

t1

t2 t3

t4

Figure 74. Disable Mode Activation by TRIG/DIS Pin

Trigger Blocking Option

The disable mode is ended when the TRIG/DIS pin

voltage falls below V for more than t . There

The trigger input can be changed to different function. The

trigger keeps state machine at state “Waiting for CS_ON”

when is triggered at TRIG pin (high for positive logic setting

and low for negative logic pin setting). TRIG signal operates

normally during time when driver is turned on. The trigger

signal has to be well synchronized to the primary side

otherwise there is a risk of losing synchronization and

improper SR transistor control. Target of this feature is SR

controller driving the SR transistor at position of forward

diode in forward convertor.

TRIG_TH

DIS_END

is recovery phase where internal references are stabilized

that takes t . Recovery phase is finished at t3. The SR

DIS_REC

controller starts synchronization phase where it waits for

to get above V for more than t or for

V

CS

CS_RESET

OFF_MIN

negative dV/dt detector trigger. Picture shows situation with

disabled negative dV/dt detector, in case of enabled −dV/dt,

controller turns driver on at t4 (high enough −dV/dt is

detected).

Secondary side of forward converter is shown in

Figure 75.

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35

NCP4307

I

L

V

DS2

I

SD1

I

SD2

V

DS1

Forward SR

TRIG1 − Driver (state machine) blocking input −

negative trigger logic, low level blocks operation

Figure 75. Secondary Side of Forward Converter with SRs

Operation with two similar SR controllers without trigger

blocking function is shown in Figure 76. Difficult situation

may appear when a transformer is demagnetized sooner than

a freewheeling conduction period ends, because part of a

freewheeling current may start to flow through a forward

diode and a secondary transformer winding. This situation

activates the forward SR controller that turns on the SR

transistor (current flows in correct direction). A minimum

on−time blanking interval may elapse sooner than real

forward conduction cycle begins. This causes an issue,

because there is noise during this reconfiguration that can

trigger the forward SR controller off comparator. The SR

controller has to turn its driver off, because its off

comparator is not blanked after the minimum on−time

blanking interval ends. Rest of the forward conduction cycle

is taken through the SR transistor bodydiode with high

power loss.

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NCP4307

Transformer gets

demagnetized

V

= V

I

DS1

CS1

SD1

= V

I

DS2

CS2

SD2

I

L

Driver goes off, because minimum

on−time elapses and change in

SMPS operation causes noise that

triggers off cmp

DRV1

DRV2

Figure 76. Operation without Trigger Blocking Option at Forward Position

The situation can be solved by the trigger blocking

function that doesn’t allow the forward SR driver to be

activated until the freewheeling conduction ends. Forward

SR controller has set trigger blocking function with negative

logic (high level – controller enabled, low level – controller

blocked) for easier implementation. Pin is connected via

diode (to minimize risk of the TRIG/DIS pin damage by high

voltage) to drain of the freewheeling SR (if a diode rectifier

is used instead of a SR, use rectifier’s cathode voltage).

Freewheeling drain voltage is low whenever current flows

through freewheeling SR. Improved behavior is shown in

Figure 77.

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37

NCP4307

Driver is not turned on even

when CS is low and current

flows in correct direction,

because controller is blocked

via TRIG signal

V

= V

I

DS1

CS1

SD1

= V

I

DS2

CS2

SD2

I

L

DRV1

DRV2

Trigger blocking

function with

negative logic

TRIG1

(blocked at low level)

Figure 77. Operation with Trigger Blocking Option at Forward Position

Light Load Detection

V

CS

< V

long enough so the driver can be activated

CS_ON

Internal light load detection is tailored to detect no or light

load condition and lower power consumption of the SR

during this conditions. CS pin signal is used to detect if there

is a light load condition or not. A light load is detected in case

without any risk. Figure 78 shows typical behavior of the

LLD circuit in flyback application. The SR controller is in

normal mode from time 0, the driver is activated according

to the secondary side conduction phase, and current

when there is the V above the V

for more than

consumption is I

plus short peaks caused by charging

CS

CS_LLD

CCL_Q

t

. A current consumption is reduced to I

during

the SR MOSFET gate charge. V stays above V

LLD

CCL_LL

CS

CS_LLD

the light load mode. The light load mode is ended when the

CS voltage goes below V . The IC needs t

from time 1, because skip mode was activated (no switching

at primary side). t is running from time 1 and elapses at

CS_LLD

LLD_REC

LLD

time to recover from the light load mode, to establish voltage

references etc. The first driver pulse after the light load mode

pulse is generated just in case that the V is below V

time 2. The light load mode is activated at time 2 that means

decrease of current consumption down to I . The

CCL_LL

controller stays in the light load mode up to time when V

CS

CS_ON

CS

for more than t

. Reason for this is that a

falls below 0 V (time 3) that starts a wake up process. This

LLD_EXIT_BLK

primary voltage clamp is discharged during long no

switching time and part of the first pulse energy is used to

recharge it instead of going to the secondary side so there is

long and deep ringing that would cause longer period when

part is showed in detail in Figure 79. The wake−up process

takes approximately t

and ends at time 4 during

LLD_REC

which current consumption returns back to I . The

CCL_Q

controller now waits for signal from the CS on comparator

(threshold V ) that takes longer than t

V

CS

> V

than t

and the driver will be

CS_OFF

CS_OFF_BLK

CS_ON

LLD_EXIT_BLK

incorrectly turned immediately off. Ringing elapses when

(blank interval is showed by grey box or dimensions). There

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38

NCP4307

are two high level outputs from the CS on comparator that

are shorter than t so no action is taken by the

leads to the driver turn−on at time 9. There are just 2 pulses

in this skip burst that ends at time 10. The LLD timer elapses

at time 11 and the light load mode is activated again.

LLD_EXIT_BLK

driver, the third pulse is longer than t

that

LLD_EXIT_BLK

V

DS

= V

CS

t

LLD_EXIT_BLK

t

LLD

DRV

t

LLD_REC

Light Load

I

CCL_Q

I

CC

CCL_LL

0

1

2

3

9

11

10

Figure 78. Light Load Detection Waveforms

V

DS

= V

CS

t

LLD_EXIT_BLK

t

LLD_EXIT_BLK

DRV

t

LLD_REC

t

LLD_EXIT_BLK

ON cmp

ON cmp blanking

Light load

ON cmp high after

blanking → DRV activated

ON cmp goes low during

blanking → no action

I

CC

3 5

4 6

7

9

8

Figure 79. Light Load Detection Waveforms – Detail of LLD Exit

Operation Flow

color. There are two operation options of blocking function

and just one of them can be active at same time. Operation

starts in the bubble start where the system comes when

VCCL is higher than UVLO level and/or the disable mode

is activated (by the TRIG/DIS pin).

Following bubble diagram at Figure 80 shows overall

operation flow. Black bubbles are fundamental parts of the

system. States for −dV/dt feature are colored by blue color,

states for minimum on time generation are in red and states

for +dV/dt are green. The trigger blocking option is in violet

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NCP4307

Figure 80. Overall Operation Bubble Diagram

OPN CODING

OPN

FA

10 V

FB

10 V

AA

10 V

WA

10 V

500 ns

NA

V

DRV

t

1100 ns

250 ns

4.00 ms

24 ns

200 ns

4.7 V

No

1100 ns

250 ns

4.00 ms

24 ns

200 ns

8.9 V

No

1400 ns

155 ns

ON_MIN

CS_OFF_BLK

t

4.00 ms

24 ns

1.00 ms

NA

OFF_MIN

t

CS_−DV/DT

t

200 ns

4.7 V

No

LLD_EXIT_BLK

V

4.7 V

CCL_SB_A

+dV/dT

Yes/Short min_ton

−

Extra

−

Negative TRIG/DIS logic,

TRIG blocking function,

CS reset level disabled

Target application

Flyback/Forward

freewheel position

Flyback/Forward

freewheel position

Active clamp flyback

Forward forward position

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40

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSOP−6

CASE 318G−02

ISSUE V

1

DATE 12 JUN 2012

SCALE 2:1

NOTES:

D

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

H

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM H.

6

1

5

4

L2

GAUGE

PLANE

E1

E

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

2

3

L

MILLIMETERS

SEATING

M

C

NOTE 5

DIM

A

A1

b

c

D

E

E1

e

MIN

0.90

0.01

0.25

0.10

2.90

2.50

1.30

0.85

0.20

NOM

1.00

MAX

1.10

0.10

0.50

0.26

3.10

3.00

1.70

1.05

0.60

PLANE

b

DETAIL Z

e

0.06

0.38

0.18

3.00

c

2.75

A

0.05

1.50

0.95

L

0.40

A1

L2

M

0.25 BSC

−

DETAIL Z

0°

10°

STYLE 1:

STYLE 2:

PIN 1. EMITTER 2

2. BASE 1

STYLE 3:

PIN 1. ENABLE

2. N/C

STYLE 4:

PIN 1. N/C

2. V in

STYLE 5:

PIN 1. EMITTER 2

2. BASE 2

STYLE 6:

PIN 1. DRAIN

2. DRAIN

3. GATE

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

3. COLLECTOR 1

4. EMITTER 1

5. BASE 2

3. R BOOST

4. Vz

5. V in

6. V out

3. NOT USED

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

4. SOURCE

5. DRAIN

6. DRAIN

4. GROUND

5. ENABLE

6. LOAD

4. EMITTER

5. COLLECTOR

6. COLLECTOR

6. COLLECTOR 2

STYLE 7:

STYLE 8:

PIN 1. Vbus

2. D(in)

STYLE 9:

STYLE 10:

PIN 1. D(OUT)+

2. GND

STYLE 11:

STYLE 12:

PIN 1. I/O

2. GROUND

3. I/O

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

PIN 1. LOW VOLTAGE GATE

2. DRAIN

PIN 1. SOURCE 1

2. DRAIN 2

3. D(in)+

4. D(out)+

5. D(out)

6. GND

3. SOURCE

3. D(OUT)−

4. D(IN)−

5. VBUS

6. D(IN)+

3. DRAIN 2

4. N/C

5. COLLECTOR

6. EMITTER

4. DRAIN

4. SOURCE 2

5. GATE 1

4. I/O

5. DRAIN

5. VCC

6. I/O

6. HIGH VOLTAGE GATE

6. DRAIN 1/GATE 2

STYLE 13:

STYLE 14:

STYLE 15:

PIN 1. ANODE

2. SOURCE

3. GATE

STYLE 16:

STYLE 17:

PIN 1. EMITTER

2. BASE

PIN 1. GATE 1

2. SOURCE 2

3. GATE 2

PIN 1. ANODE

2. SOURCE

PIN 1. ANODE/CATHODE

2. BASE

3. GATE

3. EMITTER

3. ANODE/CATHODE

4. ANODE

5. CATHODE

6. COLLECTOR

4. DRAIN 2

5. SOURCE 1

6. DRAIN 1

4. CATHODE/DRAIN

5. CATHODE/DRAIN

6. CATHODE/DRAIN

4. DRAIN

4. COLLECTOR

5. ANODE

5. N/C

6. CATHODE

GENERIC

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT*

6X

0.60

XXXAYWG

XXX MG

G

1

6X

0.95

3.20

IC

STANDARD

XXX = Specific Device Code

A

Y

W

G

=Assembly Location

= Year

= Work Week

M

G

= Date Code

= Pb−Free Package

0.95

= Pb−Free Package

PITCH

DIMENSIONS: MILLIMETERS

*This information is generic. Please refer to device data

sheet for actual part marking. Pb−Free indicator, “G”

or microdot “G”, may or may not be present. Some

products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB14888C

TSOP−6

PAGE 1 OF 1

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the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

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


型号：	NCP4307FASNT1G
厂家：	ONSEMI
描述：	Secondary Side Synchronous Rectification Driver with Dual Supply
文件：	总42页 (文件大小：838K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP4307FASNT1G [ONSEMI]

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