NCP4318ALGPDR2G [ONSEMI]
Dual Channel Synchronous Rectification Controller;
| 型号： | NCP4318ALGPDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual Channel Synchronous Rectification Controller |
| 文件： | 总25页 (文件大小：1379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Advanced Synchronous
Rectifier Controller for LLC
Resonant Converter
8
8
1
1
SOIC−8 EP
CASE 751AC
SOIC−8, 150 mils
CASE 751BD
NCP4318
MARKING DIAGRAM
NCP4318 is an advanced synchronous rectification (SR) controller
for LLC resonant converter with minimum external components. It
has two gate drivers for driving the SR MOSFETs rectifying the
outputs of the secondary transformer windings. The two gate drivers
have their own drain and source sensing pins and operate
independently of each other. The advanced adaptive dead time control
compensates the voltage across parasitic inductance to minimize the
body diode conduction and maximize the system efficiency. The
advanced turn−off control algorithm allows stable SR operation over
entire load range. NCP4318 has two versions of pin assignment –
NCP4318A, NCP4318B, and two types of package – SOIC−8 and
SOIC−8 EP.
8
NCP4318
UVWX
AWLYYWW
1
U
V
= Pin Layout, A and B
= Frequency, H: High, L: Low
WX = Additional IPT Option
= Assembly Location
WL = Wafer Lot Traceability
YYWW = Date Code
A
Features
• Mixed Mode SR Turn−off Control
PIN CONNECTIONS
• Anti Shoot−through Control for Reliable SR Operation
• 200 V−rated Drain Sensing and Dedicated Source Sensing Pins
• Advanced Adaptive Dead Time Control
NCP4318AXX
GATE1
GND
VS1
GATE2
VDD
VD2
• SR Current Inversion Detection
• Adaptive Minimum Turn−on Time for Noise Immunity
• SR Conduction Time Increase Rate Limitation
• Multi−level Turn−off Threshold Voltage
VD1
VS2
• Adaptive Gate Voltage (10 V, 6 V)
NCP4318BXX
• Low Operating Current (100 mA) in Green Mode
• Soft Start with 0 V / 6 V Gate Output Voltage
• Short Turn−on and Turn−off Delay Time (30 ns / 30 ns)
• High Gate Sourcing and Sinking Current (1.5 A / 4.5 A)
• Wide Operating Supply Voltage Range from 6.5 V to 35 V
• Wide Operating Frequency Range (22 kHz to 500 kHz)
• SOIC−8 and SOIC−8 EP Packages
GATE1
GND
VD1
GATE2
VDD
VD2
VS1
VS2
(Top View)
• These Devices are Pb−Free and are RoHS Compliant
Applications
• High Power Density Adapters
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 3 of this data sheet.
• Large Screen LED−TV and OLED−TV Power Supplies
• High Efficiency Desktop and Server Power Supplies
• Networking and Telecom Power Supplies
• High Power LED Lighting
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
March, 2023 − Rev. 8
NCP4318/D
NCP4318
M2
Optional
Roffset2
Bridge
Diode
Q1
EMI
Filter
PFC
Stage
VAC
C
in
Cr
Lr
VO
Q2
Lp
RO
CO
Roffset1
Optional
M1
LLC
Controller
Shunt
Regulator
Figure 1. Typical Application Schematic of NCP4318
VD1_HIGH
VD2_HIGH
SR
Conduction
SR
Conduction
SRCOND1
SRCOND2
VTH−HGH
VTH−HGH
IOFFSET1
IOFFSET2
DLY_EN1
DLY_EN2
RUN
RUN
SET
CLR
DSET
D
Q
Q
Q
Q
Adaptive
turn−on
delay
Adaptive
turn−on
delay
VD1
VD2
VS2
VTH−ON
VTH−ON
Turn−on
Turn−on
CLR
VTH−OFF1
VTH−OFF2
VS1
Turn−off
Turn−off
Adaptive
Tmin−on
Adaptive
Tmin−on
SRCINV1
SRCINV2
Adaptive
VGATE
Adaptive
VGATE
Adaptive
dead time
control
Adaptive
dead time
control
IOFFSET1
VTH−OFF1
IOFFSET2
VD1−HGH
VTH−OFF2
VD2−HGH
GATE
CLAMP
GATE
CLAMP
VG1
VG2
GATE1
GATE2
VD1
GREEN
VD2
SR Current Inversion detect
SRCINV1
DLY_EN1
DLY_EN2
RUN
SRCINV2
VDD−GATE−ON / VDD−GATE−OFF
SRCOND1,2
VD1_HGH
GREEN
GREEN MODE
GREEN
SS_7V
Protections
SOFT
START
SRCOND1
SRCOND2
VTH−OFF1
HFS
Adaptive
VGATE
VGATE
Control
OTP1
VDD
GND
Figure 2. Internal Block Diagram of NCP4318
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2
NCP4318
PIN DESCRIPTION
Pin Number
NCP4318A
NCP4318B
Name
GATE1
GND
Description
1
2
3
4
1
2
4
3
Gate drive output for SR MOSFET1
Ground
VS1
Synchronous rectifier source sense input for SR1
Synchronous rectifier drain sense input. I
VD1
current source flows out of the VD1
OFFSET1
pin such that an external series resistor can be used to adjust the synchronous rectifi-
er turn−off threshold. The I current source is turned off when V is under−
OFFSET1
DD
voltage or when switching is disabled in green mode
5
6
5
6
VS2
VD2
Synchronous rectifier source sense input for SR2
Synchronous rectifier drain sense input. I
current source flows out of the VD2
OFFSET2
pin such that an external series resistor can be used to adjust the synchronous rectifi-
er turn−off threshold. The I current source is turned off when V is under−
OFFSET2
DD
voltage or when switching is disabled in green mode
7
8
7
8
VDD
Supply Voltage
GATE2
Gate drive output for SR MOSFET2
ORDERING INFORMATION
Ordering Code
†
Device Marking
Package
Shipping
NCP4318AHDDR2G
NCP4318AHJDR2G
NCP4318ALCDR2G
NCP4318ALKDR2G
NCP4318ALLDR2G
NCP4318ALSDR2G
NCP4318BLCDR2G
NCP4318ALFPDR2G
NCP4318ALGPDR2G
NCP4318AHD
NCP4318AHJ
NCP4318ALC
NCP4318ALK
NCP4318ALL
NCP4318ALS
NCP4318BLC
SOIC−8
2500 / Tape & Reel
(Pb−Free)
NCP4318ALFP
NCP4318ALGP
SOIC−8 EP
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NCP4318
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
V
V
Power Supply Input Pin Voltage
Drain Sense Input Pin Voltage
Gate Drive Output Pin Voltage
−0.3 to 37
−4 to 200
−0.3 to 17
DD
V
V
V
D1, D2
V
V
V
GATE1,
GATE2
V
V
Source Sense Input Pin Voltage
−0.3 to 5.5
−4 to 5.5
V
V
S1, S2
V
Source Sense Input Pin Dynamic Voltage (Pulse Width = 200 ns)
S1−DYN,
V
S2−DYN
P
D
Power Dissipation (T = 25°C)
W
A
SOIC−8
0.625
3.7
SOIC−8 EP (Note 3)
T
Maximum Junction Temperature
−40 to 150
−60 to 150
260
°C
°C
°C
kV
J
T
Storage Temperature Range
STG
T
L
Lead Temperature (Soldering, 10 Seconds)
Electrostatic Discharge Capability Human Body Model,
ESD
3
ANSI / ESDA / JEDEC JS−001−2012
(except VD1, VD2 pin)
Human Body Model,
2
VD1−GND, VD2−GND pin to pin with 330−pF (Note 2)
capacitance on VD1 and VD2 pin
Charged Device Model, JESD22−C101
1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values are with respect to the GND pin.
2. The capacitance can be replaced by C
3. Same test condition as in Note 5.
of MOSFET.
OSS
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
R
Thermal Resistance, Junction−to−Ambient.
SOIC−8 (Note 4)
SOIC−8 EP (Note 5)
°C/W
q
JA
165
27
R
Thermal Characterization Parameter between Junction and the Center of the Top of the Package.
°C/W
y
JT
SOIC−8 (Note 4)
22
3
SOIC−8 EP (Note 5)
4. JEDEC standard: JESD51−2 (still air natural convection) and JESD51−3 (1s0p).
5. JEDEC standard: JESD51−2 (still air natural convection) and JESD51−7 (2s2p) with four 0.2−mm−in−diameter Cu−plated thermal vias under
the exposed pad. The vias connect to all buried planes and a bottom−side trace of the test board.
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
VDD Pin Supply Voltage to GND (Note 6)
Drain Sense Input Pin Voltage
Min
0
Max
35
Unit
V
V
DD
V
D1
, V
D2
−0.7
−0.3
−40
180
5
V
V
S1
, V
S2
Source Sense Input Pin Voltage
V
T
J
Operating Junction Temperature
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Allowable operating supply voltage V can be limited by the power dissipation of NCP4318 related to switching frequency, load capacitance
DD
and ambient temperature.
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4
NCP4318
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to 125°C unless otherwise specified.)
DD
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE AND CURRENT SECTION
V
Turn−on Threshold
V
DD
V
DD
V
DD
V
DD
rising with 4.3 V / 1 ms
−
3.6
−
4.0
3.8
6.5
6.0
4.3
−
V
V
V
V
DD−ON
V
Turn−off Threshold
< V
> V
< V
DD−OFF
DD−GATE−ON
DD−OFF
V
SR Gate Enable Threshold Voltage
7.1
−
DD−GATE−ON
DD−GATE−OFF
V
SR Gate Disable Threshold Voltage
(Note 7)
5.0
DD−GATE−OFF
I
I
Operating Current
f
f
= 100 kHz, C
= 100 kHz, C
= 1 nF
= 0 nF
−
−
−
−
8
−
10
6
mA
mA
mA
DD−OP1
SW
GATE
Operating Current
DD−OP0
SW
GATE
I
Start−up Current
V
= V − 0.1 V
DD−ON
−
100
210
DD−START
DD
DD
I
Operating Current in Green Mode
V
= 12 V (no V
switching)
100
mA
DD−GREEN
D1/2
GREEN1 enable at T = 25°C
J
Excluding ALFP and ALGP.
h
−
Number of V
Alternative
V
falling lower than V
& V
D1/2
−
255
0
−
Cycle
mV
SS SKIP
D1/2
D1/2
TH−ON
Switching for Soft Start Skipping
rising higher than V
& No GATE
TH−HGH
output at f
= 200 kHz, C
= 0 nF
SW
GATE
DRAIN VOLTAGE SENSING SECTION
V
OSI
Comparator Input Offset Voltage
(Note 7)
−1
1
I
Drain Pin Leakage Current
V
= 200 V
−
−
−
1
mA
DRAIN−LKG
D1/2
V
Turn−on Threshold (Note 7)
R
= 0 W (includes comparator
−100
−
mV
TH−ON
OFFSET
input offset voltage)
From V higher than V
TH−HGH
in ALS
in AHD, AHJ
in ALC, ALK, ALL, BLC, ALFP, ALGP
t
Minimum Off−time
ns
OFF−MIN
D1/2
450
750
1400
800
1150
2000
1150
1550
2800
t
Turn−on Propagation Delay
Turn−on comparator delay
−
30
80
ns
ns
ON−DLY
From V
= −0.2 to V
= 1 V, when
D1/2
GATE
DLY_EN = 0
t
Turn−on De−bounce Time when
Turn−on comparator delay
ON−DLY2
Additional Turn−on Delay is Enabled From V
= −0.2 to V
GATE
= 1 V, when
D1/2
(Note 7)
DLY_EN = 1.
in AHD, AHJ, ALC, ALK, ALL, ALS, BLC,
ALFP, ALGP
−
−
240
30
−
t
Turn−off Propagation Delay
Turn−off comparator delay
80
ns
OFF−DLY
From V
= 0.6 to V
= 5.7 V
D1/2
GATE
V
Minimum Turn−off Threshold Voltage
(Note 7)
R
= 0 W (includes comparator
mV
TH−OFF−MIN
OFFSET
input offset voltage)
in ALC, ALK, ALL, ALS, BLC, ALFP
in AHD, AHJ, ALGP
−
−
−6
−14
−
−
V
Step Size of Adaptive Turn−off
R
R
R
= 0 W
mV
mV
mV
%
TH−OFF−STEP
OFFSET
Threshold Voltage (Note 7)
−
−
4
8
−
−
in AHD, AHJ, ALC, BLC, ALL, ALFP,
ALGP
in ALK, ALS
V
Maximum Turn−off Threshold
Voltage (Note 7)
= 0 W,
OFFSET
TH−OFF−MAX
in ALC, BLC, ALL, ALFP
in ALK, ALS
−
−
−
118
242
110
−
−
−
in AHD, AHJ, ALGP
V
Reset Value of Turn−off Threshold
Voltage (Note 7)
= 0 W,
OFFSET
TH−OFF−RST
in ALC, BLC, ALL, ALFP
in ALK, ALS
−
−
−
2
−
−
−
10
in AHJ, ALGP
−10
K
Ratio of Second−step V
TH−OFF
to
LLD = 0.
If LLD ≥ 1, 2 step V
−
60
−
2ND−VOFF
TH−OFF
nd
V
(Note 7)
= V
TH−OFF TH−OFF
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NCP4318
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to 125°C unless otherwise specified.) (continued)
DD
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DRAIN VOLTAGE SENSING SECTION
K
Effective On−time Duration Ratio to
On−time of Last Switching Cycle for
LLD = 0, t
VG1
(n−1) = 8 ms, and K *
2ND−TOFF
−
70
−
%
2ND−TOFF
VG1
t
(n−1) > t
MIN−ON.
the Second Step V
(Note 7)
If K
VG1−70
* t
(n−1) < t
,
TH−OFF
2ND−TOFF VG1
MIN−ON
t
= t
MIN−ON
V
Drain Voltage High Detect Threshold
Voltage (Note 7)
V
rising
V
TH−HGH
D1/2
in AHD, AHJ, ALC, ALK, ALL, BLC,
−
−
0.85
1.5
−
−
ALFP, ALGP
in ALS
t
Minimum SR Conduction Time to
Enable SR when DLY_EN = 0
TH−OFF1 or 2
when Gate Skip is Triggered)
The duration from turn−on trigger to V
ns
GATE−SKIP1
D1/2
rising higher than V
DLY_EN = 0
,when
TH−HGH
(3 Steps V
Decrease
in ALC, ALK, ALL, ALS, BLC, ALFP,
500
350
710
550
−
−
ALGP
in AHD, AHJ
t
Minimum SR Conduction Time to
Enable SR when DLY_EN = 1
TH−OFF1 or 2
when Gate Skip is Triggered)
(Note 7)
The duration from turn−on trigger to V
ns
GATE−SKIP2
D1/2
rising higher than V
DLY_EN = 1
, when
TH−HGH
(3 Steps V
Decrease
in AHD, AHJ
−
−
385
510
−
−
in ALC, ALK, ALL, ALS, BLC, ALFP,
ALGP
MINIMUM ON−TIME AND MAXIMUM ON−TIME SECTION
K
Adaptive Minimum On Time Ratio
when DLY_EN = 0
DLY_EN=0 & t
(n−1) = 8 ms
%
%
TON1
SRCOND
t
= K
* t
(n−1)
MIN−ON
in ALGP
TON1 SRCOND
29
43
34
50
39
57
in ALC, ALK, ALL, ALS, AHD, AHJ,
BLC, ALFP
K
TON2
Adaptive Minimum On Time Ratio
when DLY_EN = 1
DLY_EN=1 & t
(n−1) = 8 ms
SRCOND
t
= K
* t
(n−1)
MIN−ON
TON2 SRCOND
in ALGP
−
−
17
20
−
−
in ALC, ALK, ALL, ALS, AHD, AHJ,
BLC, ALFP
t
t
Upper Limit of Minimum On−time
200 ns < t
< t
,
4
2
−
−
−
5
6
3
−
−
−
ms
ms
MIN−ON−U1
MIN−ON
MIN−ON−U1
when DLY_EN = 0
DLY_EN = 0
Upper Limit of Minimum On−time
when DLY_EN = 1
200 ns < t
< t
,
2.5
MIN−ON−U2
MIN−ON
MIN−ON−U2
DLY_EN = 1
K
K
SR Current Inversion Detection Win- DLY_EN = 0
dow Ratio when DLY_EN = 0
K
%
INV1
TON1
SR Current Inversion Detection Win- DLY_EN = 1
dow Ratio when DLY_EN = 1
K
%
INV2
TON2
h
Consecutive Normal Switching
Cycles to Exit SR Current Inversion
State DLY_EN = 1 (Note 7)
Without parasitic V
oscillation
16k
cycle
INV−EXT
D1/2
t
Maximum SR Turn−on Time (Note 7) in none
21
−
30
Inf.
39
−
ms
SR−MAX−ON
in ALC, ALK, ALS, AHD, AHJ, BLC,
ALFP, ALGP
f
Minimum Switching Frequency
(Note 7)
1 / (t
+ t )
SR−MAX−ON−CH2
kHz
MIN
SR−MAX−ON−CH1
in none
−
−
−
−
22
0
in ALC, ALK, ALL, ALS, AHD, AHJ, BLC,
ALFP, ALGP
DEAD TIME REGULATION SECTION
I
Maximum of Adaptive Offset Current
which have 31 Steps and 10 mA of
Resolution
V
D1
= V = 0
285
310
335
mA
OFFSET
D2
t
Lower Band of Dead Time Regula-
tion (Note 7)
From V
falling below V
GATE−LOW
ns
DEAD−LBAND
GATE
in ALC, ALK, ALL, ALS, BLC, ALFP,
−
−
90
−
−
ALGP
in AHD, AHJ
170
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6
NCP4318
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to 125°C unless otherwise specified.) (continued)
DD
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DEAD TIME REGULATION SECTION
t
Upper Band of Dead Time Regula-
tion (Note 7)
From V
falling below V
,
−
−
t
−
−
ns
DEAD−HBAND
GATE
GATE−LOW
DEAD−LBAND
when LLD = 0
+ 90
h
LLD1
First Light Load Detection (LLD1)
hV
≤ h
7
TH−OFF−CNT
LLD1
LLD2
Step Number based on V
Modulator (Note 7)
TH−OFF
h
LLD2
Second Light Load Detection (LLD2) hV
≤ h
−
3
−
TH−OFF−CNT
Step Number based on V
Modulator (Note 7)
TH−OFF
GREEN MODE SECTION
t
Non−switching Period of SR Gate to
When SRCOND1, 2 are both low for
t , GREEN1 = HIGH.
GRN1−ENT
in ALC, ALK, ALL, ALS, BLC
in AHD, AHJ
ms
ms
GRN1−ENT
Enter Green Mode
45
25
60
40
75
55
t
Non−switching Period of SR Gate to
When SRCOND1, 2 are both low for
GRN2−ENT
Reset V
and Set DLY_EN
t
, generate GREEN2 pulse.
TH−OFF
GRN2−ENT
in ALC, ALK, ALL, ALS, BLC, ALFP,
4.5
6
7.5
ALGP
in AHD, AHJ
2.5
4
4
5.5
h
−
Number of Buffer Switching Cycle to
Recover I when IC Exits from
Number of switching with V > V
TH−HGH
−
−
cycle
CSW EXT
D1
to exit GREEN1
DD−OP
Green mode
Excluding ALFP and ALGP.
PROTECTION SECTION
V
Threshold Voltage of Current
LLD = 0
−
−
0
−
−
mV
ns
SRCINV
Inversion Detection (Note 7)
LLD ≥ 1, Virtual V
V
TH−OFF
TH−OFF
t
Debounce Time of SR Current
Inversion Detection (Note 7)
V
> 4.5 V & V
> V for t
SRCINV INV
INV
GATE1/2
in AHD, AHJ, ALGP
D1/2
−
−
−
170
320
520
−
−
−
in ALC, ALK, ALL, BLC, ALFP
in ALS
V
Drain Threshold Voltage for Primary
Shutdown Protection (Note 7)
V
V
V
V
> 4.5 V with 200−ns delay &
SD−PRI
mV
SD−PRI
GATE1/2
D1/2
GATE1/2
> V
when DLY_EN = 0.
> 4.5V with 100−ns delay &
> V when DLY_EN = 1.
D1/2
SD−PRI
in AHD, AHJ
−
−
−
−
100
150
500
200
−
−
−
−
in ALC, ALK, BLC, ALFP, ALGP
in ALL
in ALS
K
Detection Window Time Ratio Based LLD = 0, t
(n−1) = 8 ms, and
65
70
75
%
V
SD−PRI
VG1
* t
on t
(n−1) for the Primary
K
(n−1) > t
.
VG1
2ND−TOFF VG1
MIN−ON
MIN−ON
Shutdown Protection (Note 7)
If K
*t
(n−1) < t
,
2ND−TOFF VG1
t
= t
MIN−ON.
VG1−70
V
Drain Threshold Voltage to Trigger
Abnormal VD Sensing Protection
(Note 7)
V
> V
& V
> 4.5 V with
ABN−VD
D1/2
ABN−VD
GATE1/2
SD−PRI
100−ns delay within K
.
V
= V
ABN−VD
TH−HGH
in AHD, AHJ, ALC,ALK, ALL, BLC, ALFP,
−
−
0.85
1.5
−
−
ALGP
in ALS
T
T
Over Temperature Protection
T > T
& V =6.7V
GATE
°C
°C
°C
OTP1
J
OTP1
Reducing V
(Note 7)
in AHJ, ALC, BLC
in AHD, ALK, ALL, ALS, ALFP, ALGP
−
−
105
130
−
−
GATE
Over Temperature Protection
Stopping Gate Operation (Note 7)
T > T
& No gate output
OTP2
J
OTP2
in AHJ, ALC, BLC
−
−
140
disable
−
−
in AHD, ALK, ALL, ALS, ALFP, ALGP
T
Reset Level of Over Temperature
Protection (Note 7)
T < T , OTP1 and OTP2 are reset
J OTP−RST
−
80
−
OTP−RST
GATE DRIVER SECTION
Gate Clamping Voltage (Note 7)
V
12 V < V < 33 V, C = 4.7 nF at
GATE
J
9
10.5
12
V
GATE−MAX
DD
OTP1
T < T
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7
NCP4318
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to 125°C unless otherwise specified.) (continued)
DD
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
GATE DRIVER SECTION
V
Gate Clamping Voltage for Adaptive
Gate Voltage Control (Note 7)
V
DD
= 12 V, C = 4.7 nF in ALC, BLC
GATE
5.0
6.7
8.2
V
GATE−MAX−6V
t
Adaptive Gate Control Enabling
Switching Period (Note 7)
The time duration from V
(n−1) rising
ms
HFS−EN
GATE1
edge to V
(n) rising edge at
GATE1
OTP1
T <T
J
.
in ALC, ALK, ALL, ALS, BLC, ALFP,
ALGP
in AHD, AHJ
4
5
6.1
−
−
4
−
−
I
Peak Sourcing Current of Gate
Driver (Note 7)
1.5
A
A
SOURCE
I
Peak Sinking Current of Gate Driver
(Note 7)
−
−
−
−
−
4.5
8
−
−
SINK
R
Gate Driver Sourcing Resistance
(Note 7)
W
W
ns
ns
DRV−SOURCE
R
Gate Driver Sinking Resistance
(Note 7)
1.5
50
30
−
DRV−SINK
t
R
Rise Time
V
V
= 12 V, C = 3.3 nF,
GATE
150
50
DD
= 1 → 6 V at T = 25°C
GATE
J
t
F
Fall Time
V
V
= 12 V, C
GATE
= 3.3 nF,
J
DD
GATE
= 6 → 1 V at T = 25°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Not tested but guaranteed by design
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8
NCP4318
IC OPTIONS
Option
Drain Sensing Pin
#4, #6
Frequency
H−version
H−version
L−version
L−version
L−version
L−version
L−version
L−version
L−version
DLY_EN
Variable
Variable
Variable
Variable
Variable
Variable
Always High
Variable
Variable
V
t
T
/ T
GATE
GATE−LIM
OTP1 OTP2
NCP4318AHD
NCP4318AHJ
NCP4318ALC
NCP4318BLC
NCP4318ALK
NCP4318ALL
NCP4318ALS
NCP4318ALFP
NCP4318ALGP
1−Level (10V)
1−Level (10V)
2−Level (10V, 6V)
2−Level (10V, 6V)
1−Level (10V)
1−Level (10V)
1−Level (10V)
1−Level (10V)
1−Level (10V)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
130°C / Disable
105°C / 140°C
105°C / 140°C
105°C / 140°C
130°C / Disable
130°C / Disable
130°C / Disable
130°C / Disable
130°C / Disable
#4, #6
#4, #6
#3, #6
#4, #6
#4, #6
#4, #6
#4, #6
#4, #6
t
t
t
t
t
(ns) /
(ns)
t
(ms) /
(ms)
f
HFS−EN
(kHz)
INV
ON−DLY2
(ns)
DEAD−
OFF−MIN
(ms)
GATE−SKIP1
GRN1−ENT
(ns)
170
170
320
320
320
320
520
320
170
(ns)
t
t
Option
LBAND
GATE−SKIP2
550 / 385
550 / 385
710 / 510
710 / 510
710 / 510
710 / 510
710 / 510
710 / 510
710 / 510
GRN2−ENT
NCP4318AHD
NCP4318AHJ
NCP4318ALC
NCP4318BLC
NCP4318ALK
NCP4318ALL
NCP4318ALS
NCP4318ALFP
NCP4318ALGP
240
240
240
240
240
240
240
240
240
170
1.15
1.15
2
40 / 4
250
250
200
200
200
200
200
200
200
170
90
90
90
90
90
90
90
40 / 4
60 / 6
60 / 6
60 / 6
60 / 6
60 / 6
n.a. / 6
n.a. / 6
2
2
2
0.8
2
2
V
Range
V
TH−OFF−STEP
TH−OFF
(mV)
(mV)
Option
V
(V)
V
(mV)
V
(mV)
K
TON1
(%) / K
(%)
TH−HGH
TH−OFF−RST
SD−PRI
TON2
NCP4318AHD
NCP4318AHJ
NCP4318ALC
NCP4318BLC
NCP4318ALK
NCP4318ALL
NCP4318ALS
NCP4318ALFP
NCP4318ALGP
0.85
−14 ~ 110
−14 ~ 110
−6 ~ 118
−6 ~ 118
−6 ~ 242
−6 ~ 118
−6 ~ 242
−6 ~ 118
−14 ~ 110
4
4
4
4
8
4
8
4
4
−10
100
52 / 22
52 / 22
52 / 22
52 / 22
52 / 22
52 / 22
52 / 22
52 / 22
34 / 17
0.85
0.85
0.85
0.85
0.85
1.5
−10
2
100
150
150
150
500
200
150
150
2
10
2
10
2
0.85
0.85
−10
8. f
= 1 / t
.
HFS−EN
HFS−EN
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9
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. IOFFSET1 vs. Temperature
Figure 5. tMIN−ON−U1−CH1 vs. Temperature
Figure 7. VTH−ON−CH1 vs. Temperature
Figure 4. IOFFSET2 vs. Temperature
Figure 6. tMIN−ON−U1−CH2 vs. Temperature
Figure 8. VTH−ON−CH2 vs. Temperature
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10
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. VTH−OFF−STEP−CH1 vs. Temperature
Figure 10. VTH−OFF−STEP−CH2 vs. Temperature
Figure 12. VDD−OFF vs. Temperature
Figure 11. VDD−ON vs. Temperature
Figure 13. VDD−GATE−ON vs. Temperature
Figure 14. IDD−START vs. Temperature
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11
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. IDD−OP1 vs. Temperature
Figure 17. IDD−GREEN vs. Temperature
Figure 19. tON−DLY−CH1 vs. Temperature
Figure 16. IDD−OP0 vs. Temperature
Figure 18. nSS−SKIP vs. Temperature
Figure 20. tON−DLY−CH2 vs. Temperature
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12
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. tOFF−DLY−CH1 vs. Temperature
Figure 23. KTON1−CH1 vs. Temperature
Figure 25. KINV1−CH1 vs. Temperature
Figure 22. tOFF−DLY−CH2 vs. Temperature
Figure 24. KTON1−CH2 vs. Temperature
Figure 26. KINV1−CH2 vs. Temperature
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13
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 27. VGATE−MAX−CH1 vs. Temperature
Figure 29. VGATE−MAX−7V−CH1 vs. Temperature
Figure 31. tR−CH1 vs. Temperature
Figure 28. VGATE−MAX−CH2 vs. Temperature
Figure 30. VGATE−MAX−7V−CH2 vs. Temperature
Figure 32. tR−CH2 vs. Temperature
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14
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 33. tF−CH1 vs. Temperature
Figure 35. VTH−HIGH−CH1 vs. Temperature
Figure 37. tOFF−MIN−CH1 vs. Temperature
Figure 34. tF−CH2 vs. Temperature
Figure 36. VTH−HIGH−CH2 vs. Temperature
Figure 38. tOFF−MIN−CH2 vs. Temperature
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15
NCP4318
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 39. tGATE−SKIP1−CH1 vs. Temperature
Figure 40. tGATE−SKIP1−CH2 vs. Temperature
Figure 42. tGRN2−ENT vs. Temperature
Figure 41. tGRN1−ENT vs. Temperature
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16
NCP4318
APPLICATIONS INFORMATION
Basic Operation Principle
Figure 45, the instantaneous drain voltage V is compared
D
NCP4318 controls the SR MOSFETs based on the
instantaneous drain−to−source voltage sensed across the
drain and source pins of the MOSFET. Before SR gate
turning on, SR body diode operates as the conventional
diode rectifier. Referring to Figure 46, the conducting body
diode makes the drain−to−source voltage drops below the
with a virtual V
to turn off the SR gate. The virtual
TH−OFF
V
is adaptively changed to compensate the effect of
TH−OFF
stray inductance and regulate
a
t
between
DEAD
t
and t . Therefore, NCP4318 can
DEAD−LBAND
DEAD−HBAND
show robust operation with very small dead time
turn−on threshold voltage V
and triggers the turn−on
TH−ON
IOFFSET
of the SR gate. After the SR gate turning on, the product of
on resistance R of the SR MOSFET and the
instantaneous SR current determines the drain−to−source
voltage.
DLY_EN
RUN
DS−ON
COM 1
COM 2
VG
D SET
Q
Q
GATE
Adaptive
turn−on
delay
VD
VS
VTH−ON
Turn−on
CLR
When the drain−to−source voltage reaches the turn−off
Turn−off
VTH−OFF
threshold voltage V , as SR MOSFET current
TH−OFF
decreases to near zero, NCP4318 turns off the gate. If SR
dead time is larger or smaller than the dead time regulation
target, NCP4318 adaptively changes a virtual turn−off
threshold voltage to regulate the dead time between
Figure 43. VDS−sensing Circuit
t
and t
, so to maximize system
by body diode conduction
TH−ON
DEAD−LBAND
DEAD−HBAND
efficiency.
ISR
SR Turn−on Algorithm
When V is lower than V
D
VD
of SR MOSFET, turn−on comparator COM1 toggles high.
If an additional delay flag signal DLY_EN is low, VG goes
high with only 30 ns of t
and GATE sources 1.5 A of
ON−DLY
VTH−ON
I
to turn on the SR MOSFET.
SOURCE
On the other hand, if the DLY_EN flag is HIGH due to
tON−DLY2
current inversion detection SRCINV or green−mode
preparationGREEN2, additional turn−on delay is applied by
an adaptive turn−on delay block. In this case, SR gate is
turned on when the body diode conduction time is confirmed
VGATE
DLY_EN=0 DLY_EN=1
Figure 44. SR Turn−on Algorithm
to be longer than t
.
ON−DLY2
Present information
= instantaneous Vdrain type
Present information + Previous cycle information
= mixied type control
SR Turn−off Algorithm
The SR turn−off method determines safe and stable SR
operation. One of the conventional methods turns off the SR
gate based on the instantaneous drain voltage (present
information). This method is widely used and easy to
realize, and it can prevent late turn−off with appropriate
turn−off threshold voltage. However, it frequently shows
premature turn−off due to parasitic stray inductances of PCB
trace and package of the SR MOSFET. On the other hand,
SR gate on−time is predicted by inspecting previous−cycle
drain voltage information. It can prevent the premature
turn−off, providing good performance for the system with
constant operating frequency and SR conduction duration.
However, in case of the frequency changing, the on−time
prediction may lead to late turn−off during frequency
increasing event, leading to negative current flowing in the
secondary side of the LLC converter.
RUN
VG
Q
SET
D
GATE
Turn−on
CLR Q
VD
Virtual
VTH−OFF
Control
Turn−off
Virtual VTH−OFF
Previous cycle dead time information
= Prediction type
Figure 45. SR Turn−off Algorithm
Hysteresis−Band Dead−Time Regulation
The stray inductance of SR MOSFET induces a positive
offset voltage across drain and source when the SR current
decreases. This makes drain−to−source voltage of SR
MOSFET higher than the product of R
and the
To gain the advantages of both methods, NCP4318 adopts
a mixed type turn−off algorithm, which modulate a virtual
DS−ON
instantaneous SR current, which results in premature SR
turn−off as shown in Figure 46 (a). The induced offset
voltage changes as the output load varying, so, to keep a
turn−off threshold voltage (V ) to regulate the
TH−OFF
turn−off dead time within a hysteresis band. As shown in
www.onsemi.com
17
NCP4318
fixed SR dead time, the turn−off threshold voltage needs to
be tuned. NCP4318 utilizes the virtual V , which is
cycle. When the dead time is placed between t
DEAD−LBAND
and t
as in Figure 49, the virtual V
stays
TH−OFF
DEAD−HBAND
TH−OFF
comprised of 31 steps of turn−off threshold voltages
and 31 steps of offset current I as
as−is. Therefore, the dead time is regulated between
t and t regardless of parasitic
DEAD−LBAND
V
TH−OFF(n)
OFFSET(n)
DEAD−HBAND
shown in Figure 46 (b) and Figure 47. The turn−off
condition and the virtual turn−off threshold voltage can be
expressed as:
inductances. This hysteresis−band dead−time control
provides stable operation across load variation by
minimizing the variation of the dead time.
The initial and reset condition of the virtual V
is
TH−OFF
V
DS ) IOFFSET @ ROFFSET * VTH*OFF + 0
(eq. 1)
(eq. 2)
V
= V
and I
= 310 mA.
TH−OFF
TH−OFF−RST
OFFSET
Virtual VTH*OFF + VTH*OFF * ROFFSET @ IOFFSET
Virtual VTH_OFF
VTH−OFF(4)
Heavy Load
VTH−OFF(4) − ROFFSET x IOFFSET(0)
VTH−OFF(5) − ROFFSET x IOFFSET(31)
where R
is the external drain sensing resistance.
OFFSET
V
modulates between
V
and
Virtual VTH_OFF trajectory when load °
TH−OFF
TH−OFF−MIN
VTH−OFF(4) Range
V
with a step size of V
varies between 0 and 310 mA with 10 mA of step
, and
TH−OFF−MAX
TH−OFF−STEP
VTH−OFF(3)
VTH−OFF(3) − ROFFSET x IOFFSET(0)
VTH−OFF(4) − ROFFSET x IOFFSET(31)
I
OFFSET
size. I
means to provide a finer tuning on the virtual
OFFSET
VTH−OFF(3) Range
V
. When the I
has saturated to maximum or
changes to its next step for a
TH−OFF
OFFSET
VTH−OFF(2)
VTH−OFF(2) − ROFFSET x IOFFSET(0)
VTH−OFF(3) − ROFFSET x IOFFSET(31)
minimum values, V
TH−OFF
coarse control. So, designing the R
resistance as
OFFSET
VTH−OFF(2) Range
V
/ 310 mA gives a linear virtual V
TH−OFF−STEP
TH−OFF
VTH−OFF(1)
VTH0−OFF(1) − ROFFSET x IOFFSET(0)
VTH−OFF(2) − ROFFSET x IOFFSET(31)
sweeping range. Typically, 30−W R
is used when
OFFSET
V
is 8 mV, and 15 W for 4 mV.
TH−OFF−STEP
VTH−OFF(1R) ange
Dead time is defined as the duration from V
turning
GATE
VTH−OFF(0)
VTH−OFF(1) − ROFFSET x IOFFSET(0)
VTH−OFF(1) − ROFFSET x IOFFSET(31)
off to V exceeding V
. In Figure 48 (a), the
D
TH−HGH
measured dead time t
is larger than upper band of
DEAD
VTH−OFF(0) Range
t
. To reduce t
, the virtual V
will
within 128
DEAD−HBAND
DEAD
TH−OFF
Virtual VTH−OFF−MIN
Light Load
VTH−OFF(0) − ROFFSET x IOFFSET(31)
increased by one−step decrease of I
OFFSET
t
switching cycles. As a result, t
decreases and becomes
DEAD
Figure 47. Virtual VTH−OFF Trajectory when Load
Increases
much closer to t
, as shown in Figure 46 (b).
DEAD−HBAND
ISR
ISR1
V
D1
VD − VS
VLS1
VD1 − VS1
Virtual
VTH−OFF
VTH−OFF
VTH−ON
VTH−ON
VGATE1
VS1
VGATE1
VLS1
ISR1
tDEAD
tDEAD−HBAND
(a) t
> t
DEAD−HBAND
(a) Premature SR Turn−off by Stray Inductance
DEAD
ISR1
IOFFSET
Turn−off
ROFFSET
VD
VS
VD1 − V
S1
VTH−OFF
VDS
Virtual
VTH−OFF
COM2
VTH−ON
VGATE1
(b) Detailed SR Turn−off Circuitry
tDEAD
tDEAD−HBAND
Figure 46. Virtual VTH−OFF
(b) t
≈ t
DEAD−HBNAD
DEAD
Similarly, when the dead time is shorter than t
,
DEAD−LAND
the virtual V
will reduce in the following switching
Figure 48. Dead−time Regulation
TH−OFF
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18
NCP4318
changes in accordance with the SR conduction time
(n−1) measured in previous switching cycle. The
ISR1
t
SRCOND
SR conduction time is measured from SR gate rising edge to
the drain sensing voltage V being higher than V
VD1 − VS1
.
TH−HGH
D
t
in the n−th switching cycle is defined as 50% of
MIN−ON
Virtual
VTH_OFF
t
(n−1) as shown in Figure 52. During t
, SR
SRCOND
MIN−ON
gate won’t be turned off by the virtual V
. The
TH−OFF
VTH−ON
minimum and maximum values of t
are defined as
MIN−ON
VGATE1
200 ns and t
respectively. When the additional
MIN−ON−U1
t DEAD−LBAND
turn−on delay flag DLY_EN is high in the light load
t DEAD
t DEAD−HBAND
condition, t
becomes 20% of t
(n−1) as shown
MIN−ON
SRCOND
in Figure 53.
Figure 49. tDEAD Q [tDEAD-LBAND, tDEAD-HBAND
]
VD1 −VS1
Light Load Detection (LLD)
When the output load increases, due to larger current
amplitude in the SR current, the dead−time regulation
Turn−off mis−trigger is prohibited
during t MIN_ON
VD > VTH−HGH
VTH−HGH
VTH−OFF
modulates the V
the output load condition.
There are totally 31 steps of V
higher. Thus, the V
indicates
TH−OFF
TH−OFF
VD − VS > VTH−OFF
VTH−ON
t MIN_MIN = 50% of tSR_COND
of previous cycle
, noted as
TH−OFF
V
~V
. When the output load increases,
TH−OFF(0)
TH−OFF(31)
SR conduction time = t SRCOND
VGATE1
by the dead−time regulation, V
When V
NCP4318 detects a light load condition. So, light load
tends to increase.
’s step number n ≤ h on channel 1,
LLD1
TH−OFF
tON−DLY
tDEAD
TH−OFF
ISR
detection flag signal LLD set to ‘1’. When the load keeps
reducing, making n ≤ h
, LLD is set to ‘2’. At heavier
, LLD becomes ‘0’. This LLD signal is
LLD2
t
load and n > h
LLD1
used for SRCINV detection threshold voltage control and
adaptive V control.
Figure 51. Minimum Turn−on time and Turn−off
Mis−triggering
GATE
VTH−OFF
VTH−OFF−MAX
n
LLD
31
30
29
VGATE1
VGATE2
0
9
8
7
6
5
4
3
2
1
0
tSRCOND (n−1) tMIN−ON = 50% of tSRCOND (n−1)
VTH−OFF−STEP
VD1
1
2
VTH−OFF−RST
0
VTH−OFF−MIN
Figure 52. Minimum Turn−on Time tMIN−ON when
DLY_EN=0
Figure 50. VTH−OFF Steps and the LLD Flag (hLLD1 = 7,
hLLD2 = 3, hVTH−OFF−RST = 3)
VGATE1
VGATE2
Advanced Adaptive Minimum Turn−on Time
When SR gate is turning on, there may be severe
oscillation in the drain−to−source voltage of the SR
MOSFET, which may result in several turn−off
mis−triggering as shown in Figure 51. To provide stable SR
gate signal without short pulses, it is desirable to have large
turn−off blanking time (= minimum turn−on time) until the
drain voltage oscillation attenuates. However, too large
blanking time results in an inversion current problem under
light load condition where the SR conduction time may be
shorter than the minimum turn−on time.
t SRCOND (n−1) t MIN−ON = 20% of tSRCOND (n−1)
VD1
Figure 53. Minimum Turn−on Time tMIN−ON when
DLY_EN=1
To solve this issue, NCP4318 has an adaptive minimum
turn−on time, t
, where the turn−off blanking time
MIN−ON
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19
NCP4318
Multi−step VTH−OFF
SR turn−on mis−trigger By capacitive current spike
In heavy−load conditions, V
tends to be high.
TH−OFF
VGATE1
When the switching frequency on the primary side suddenly
increases from the heavy−load condition, the SR current
conduction duration reduces accordingly. To make the SR
controller timely reacts to this transition, we implements a
ISR
VDS
multi−step V
function to reduce the effective
TH−OFF
V
, turning off the SR gate earlier, during this
TH−OFF
Capacitive
current spike
Leading edge inversion current
transition. Referring to the SR gate on−time of previous
switching cycle, before the SR gate on−time reaches 70%
(K
Figure 55. Leading Edge Inversion Current
) of the previous−cycle on−time, the effective
2ND−TOFF
V
is temporarily reduces to 60% (K ) of its
2ND−VOFF
TH−OFF
real value. Thus, the SR gate can be turned off with a lower
during the frequency−increasing transition,
t MIN_ON
V
VGATE1 VGATE2
TH−OFF
providing a safer operation. The multi−step V
function is active when LLD = 0.
TH−OFF
VDS spike
ISR
ISR
VDS
Trailing edge inversion current
VDS
Multistep
VTH−OFF
Virtual
VTH−OFF
Figure 56. Trailing Edge Inversion Current
To prevent both leading edge and trailing edge inversion
currents, NCP4318 has a current inversion detection
t ON−MIN
VGATE(n)
70% * VGATE(n−1)
VTH−ON
function SRCINV. This function is effective during t
.
MIN−ON
When the SR gate is turned on and the inversion current
occurs, the drain sensing voltage of SR MOSFET becomes
Figure 54. tDEAD Q [tDEAD-LBAND, tDEAD-HBAND
]
a positive value. In this condition, if V is higher than 0 mV
DS
for t
of the detection confirmation time, SRCINV will be
INV
Current Inversion Detection
triggered and turn off the SR gate immediately. Then, the
During SR operation, two types of inversion current may
occur. First, in light load condition, capacitive current spike
causes leading edge inversion current. In heavy load
condition, the body diode of SR MOSFET starts conducting
right after the primary side switching transition taking place.
However, when the resonance−capacitor voltage amplitude
is not large enough in light load condition, the voltage across
the magnetizing inductance of the transformer is smaller
than the reflected output voltage. Thus, the secondary side
SR body diode conduction is delayed until the magnetizing
inductor voltage builds up to the reflected output voltage.
However, the primary side switching transition can cause
capacitive current spike and turn on the body diode of SR
MOSFET for a short time as shown in Figure 55, which
induces SR turn−on mis−trigger. As a result, the turn−on
mis−trigger makes leading edge inversion current in the
secondary side.
DLY_EN flag goes high and the turn−on delay is increased
to t
for the following switching cycles.
ON−DLY2
When the LLD flag is high, V
tends to be low, and
TH−OFF
the V
replaces the 0−mV threshold voltage for
TH−OFF
SRCINV. If the gate on−time is longer than t
, the
MIN−ON
virtual V
properly.
turn−off mechanism will turn off the gate
TH−OFF
ISR
VDS
0 mV
tINV
VGATE
The second inversion current is trailing edge inversion
current caused by excessive SR gate on−time, which is
Figure 57. Triggering SRCINV by Leading−edge
Inversion Current
generally due to the minimum on−time t
. If t
MIN−ON
MIN−ON
is longer than current transferring duration, trailing edge
inversion current can happen as shown in Figure 56. If there
is no proper algorithm to prevent this inversion current,
severe drain voltage spike can happen due to SR MOSFET
hard switching.
Green Mode
In NCP4318, there are two stages to trigger GREEN
function. GREEN1 is for low power consumption in light
load condition, and GREEN2 is for preparing a GREEN1
triggering.
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20
NCP4318
Adaptive VGATE Control
When the LLC controller in the primary side operates in
Lowering the gate clamping voltage V
drive power consumption. Adaptive V
reduces gate
control reduces
skip mode under light load conditions, making V shows
GATE
D1
no switching waveform for longer than t , the
GRN1−ENT
GATE
V
GATE
level when it is a better choice of operation. In
GREEN1 mode will be activated as shown in Figure 58.
Once NCP4318 is in the GREEN1 mode, all the major
functions are disabled to reduce the operating current down
NCP4318, there are three condition to trigger the adaptive
. First is the output load condition. In light load
V
GATE
condition, to save the SR gate driving current and maximize
efficiency, NCP4318 adaptively changes V . As shown
to 100 mA of I
when four switching cycles are observed from V as shown
. NCP4318 exits from GREEN1
DD−GREEN
GATE
D1
in Figure 60, when LLD goes from ‘0’ to ‘1’, the gate clamp
voltage reduces from 10 V to 6 V. It could save 40% of gate
in Figure 59.
Before GREEN1 being triggered, if the duration of no
switching operation is longer than t
GREEN2 pulse is generated to reset the virtual V
assert DLY_EN. LLD may also be asserted when V
driving power consumption. In heavy load condition, V
, a short
and
TH−OFF
. Doing so, GREEN2
GATE
GRN2−ENT
resumes to 10 V for lower turn−on resistance R
of the
DS−ON
TH−OFF
SR MOSFET, as depicted in Figure 61. There is also a
3−level−V
option which set V
= 5 V when
resets to a level lower than h
GATE
GATE
LLD1
LLD = 2.
prepares new SR operation starting condition and allows
soft increment of SR gate pulses for the next switching
bundle.
The second condition is the operating frequency. If the
LLC operating frequency is higher than 200 kHz of
f
= 1/t
in L−version and 250 kHz in
HFS−EN
HFS−EN
H−version, NCP4318 reduces V
for lowering SR gate
GATE
driving current.
The last condition is junction temperature T of the IC.
VGATE1
VGATE2
GREEN1 trigger
J
When T is higher than 105°C of T
, V
GATE
reduces to
resumes to
J
OTP1 GATE
6 V to reduce heat dissipation of the IC. V
10 V when T is lower than 80°C of T
tGRN1−ENT
VDS1
VDS2
.
J
OTP−RST
LLD
VGATE1
VGATE2
Figure 58. Entering GREEN1
Adaptive VGATE control enter @ LLD=1
VDS1
VDS2
VGATE1
VGATE2
1
2
3
4
GREEN1 exit
VDS1
VDS2
Figure 60. VGATE Reduces when LLD is High
LLD
VGATE1
VGATE2
Adaptive VGATE control exit @ LLD1=0
Figure 59. Exit from GREEN1
Limitation on SR Gate On−time Increasing Rate
To better cope with transitions of operating frequency,
NCP4318 has an optional SR gate on−time increasing−rate
limitation function. When this function is enable, the
on−time of consecutive SR−gate pulses won’t increase too
much from their precedent pulse. The increase rate is limited
VDS1
VDS2
as 550 ns of t
between two consecutive pulses. In
GATE−LIM
Figure 61. VGATE Resumes When LLD is Low
Soft Start
At the beginning of LLC startup, the operating frequency
is severely changed, and the symmetrical duty cycles
between the high−side and low−side power switches on the
primary side sometimes cannot be guaranteed. To avoid SR
other words, when the on−time should change from a
smaller value to a larger value, the SR gate takes a few
switching cycle to increase its pulse width gradually.
More, when this function is enabled, the maximum pulse
width of the SR gate start from 1.2 ms after a GREEN2 or
SRCINV event. The maximum pulse width increases up to
t
.
SR−MAX−ON
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21
NCP4318
operation during the startup transition, NCP4318
V
GATE
> 4.5 V. In that condition, NCP4318 triggers the
implements a soft−start function. After V
exceeds
abnormal drain sensing protection, turns off the SR gate and
makes GREEN1 high.
DD
V
, the SR gate skips the initial 256 consecutive
DD−GATE−ON
V
D1
and V switching cycles to check whether LLC
To protect NCP4318 from overheating, NCP4318 stops
D2
system is stable or not. After the first 256 cycles, NCP4318
starts generating SR gate pulses with V = 6 V and
operation when its junction temperature exceeds T
.
OTP2
GATE
V
= V
GATE
. If LLD−based adaptive V
stays 6 V until LLD signal goes to zero.
is
TH−OFF
TH−OFF−RST
GATE
ISR
enabled, V
Otherwise, V
stays 6 V for another 256 cycles. This
GATE
allows soft−increment of SR gate pulses and gradual
reduction of the SR dead time at startup.
VDS
VSD−PRI
0 mV
Protections
t INV
For higher system reliability, two protections are
implemented in NCP4318. First one is the primary
shutdown protection. In SR controller point of view,
NCP4318 cannot know directly the primary side abnormal
gate off, such as by a certain LLC protection or power−off.
In that condition, SR gate should be turned off as soon as
possible even in minimum on−time. Though SRCINV
function can turn−off SR gate at that moment, it has a certain
VGATE
Figure 62. Triggering Primary Shutdown Protection
Recover From tON−DLY2
When the DLY_EN flag has been asserted, SR gate turns
on after the body diode of the SR MOSFET conducts for
t
. NCP4318 clears the DLY_EN flag by observing
ON−DLY2
delay time t
for the confirmation. For a faster turning off,
INV
the V < V
event. Before the SR gate turning on, if V
D
TH−ON
D
a primary shutdown protection is implemented.
crosses below V
adds by one. This counter resets when the V < V
event happens more than one time in one switching cycle.
When the h
for only one time, a h
counter
TH−ON
INV−EXT
When the LLC gate signal in the primary side suddenly
cuts down, SR current shows a downward transition, which
induces a high dV/dt on the drain sensing voltage. If the
D
TH−ON
counter has elapsed, the DLY_EN flag
INV−EXT
dV/dt is higher than V /t , the primary shutdown
SD−PRI INV
is cleared.
protection is triggered and the SR gate turns off
immediately. In addition, it asserts GREEN1, which makes
4 cycles of SR gate skipping to ignore turn−on mis−trigger
caused by energy bouncing in the secondary side. The
primary shutdown protection is effective in the leading edge
of the SR gate for 70% of its previous−cycle SR gate
on−time.
ISR
VD
Two times
One time
The other protection is the abnormal drain sensing
protection. In normal condition, when the SR gate is turn on
VTH
VGATE
and higher than 4.5 V, the drain sensing voltage V is
D
t ON−DLY2
t ON−DLY2
expected low, which in any case should not exceed
V
. However, in abnormal condition, due to V
Figure 63. Criterion of Clearing the DLY_EN Flag
TH−HGH
D
fluctuation, V can be higher than V
even when
D
TH−HGH
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22
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE E
8
1
DATE 05 OCT 2022
SCALE 1:1
GENERIC
MARKING DIAGRAM*
8
*This information is generic. Please refer to
XXXXXX = Specific Device Code
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.
XXXXX
AYWWG
G
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14029D
SOIC−8 EP
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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