NCP4318ALS_技术文档

Advanced Synchronous

Rectifier Controller for LLC

Resonant Converter

NCP4318

NCP4318 is an advanced synchronous rectification (SR) controller

for LLC resonant converter with minimum external components. It

has two gate driver stages for driving the SR MOSFETs which are

rectifying the outputs of the secondary transformer windings. The two

gate driver stages have their own Drain and Source sensing inputs and

operate independently of each other. The advanced adaptive dead time

control compensates a voltage across parasitic inductance to minimize

the body diode conduction and maximize the system efficiency. The

advanced turn−off control algorithm allows stable SR operation over

entire load range. NCP4318 has two versions of pin assignment –

NCP4318AXX, NCP4318BXX.

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SOIC 8, 150 mils

CASE 751BD

MARKING DIAGRAM

Features

8

• Mixed Mode SR Turn−off Control

• Anti Shoot−through Control for Reliable SR Operation

NCP4318

UVW

AWLYYWW

• Separate 200 V Rated Sense Pins for the Drain and Dedicated Source

1

Sense Pins

• Advanced Adaptive Dead Time Control

• SR Current Inversion Detection

U

V

W

A

= Pin Layout, A and B

= Frequency, H: High, L: Low

= Additional IPT option

= Assembly Location

• Adaptive Minimum Turn−on Time for Noise Immunity

• SR Conduction Time Increase Rate Limitation

• Multi−level Turn−off Threshold Voltage

WL = Wafer Lot Traceability

YYWW = Date Code

• Adaptive Gate Voltage Control (10 V, 6 V)

PIN CONNECTIONS

• Low Operating Current (100 mA) in Green Mode

• Soft Start for 512 Switching Cycle with 0 V/6 V Gate Output Voltage

• Very Fast Turn−on and Turn−off Delay Time (30 ns/30 ns)

• Large Gate Sourcing and Sinking Current (1.5 A/4.5 A)

• Wide Operating Supply Voltage Range from 6.5 V to 35 V

• Wide Operating Frequency Range (22 kHz to 500 kHz)

• SOIC−8 Package

NCP4318AXX

GATE1

GND

VS1

GATE2

VDD

VD2

VD1

VS2

• These Devices are Pb−Free and are RoHS Compliant

NCP4318BXX

Applications

• High Power Density Adapters

• Large Screen LED−TV and OLED−TV Power Supplies

• High Efficiency Desktop and Server Power Supplies

• Networking and Telecom Power Supplies

• High Power LED Lighting

GATE1

GND

VD1

GATE2

VDD

VD2

VS1

VS2

(Top View)

ORDERING INFORMATION

See detailed ordering, marking and shipping information on

page 3 of this data sheet.

1

Publication Order Number:

March, 2021 − Rev. 1

NCP4318/D

NCP4318

M2

Optional

R_offset2

Bridge

Diode

Q₁

Q₂

EMI

Filter

PFC

Stage

V_AC

C_in

C_r

L_r

V_O

L_p

R_O

C_O

R_offset1

Optional

M1

LLC

Controller

Shunt

Regulator

Figure 1. Typical Application Schematic of NCP4318

V_{D1_HGH}

V_{D2_HGH}

SR

Conduction

SR

Conduction

SR_COND1

SR_COND2

V_{TH_HGH}

I_OFFSET1

I_OFFSET2

DLY_EN1

DLY_EN2

RUN

SET

CLR

SET

CLR

Q

D

Adaptive

turn−on

delay

Adaptive

turn−on

delay

VD1

VS1

VD2

VS2

V_{TH_ON}

Turn−on

V_{TH_OFF1}

V_{TH_OFF2}

Turn−off

Adaptive

Tmin_on

Adaptive

Tmin_on

SRC_INV1

SRC_INV2

Adaptive

V_GATE

Adaptive

dead time

control

Adaptive

dead time

control

I_OFFSET1

V_{TH_OFF1}

I_OFFSET2

V_{TH_OFF2}

V_{D1_HGH}

V_{D2_HGH}

GATE

CLAMP

VG1

VG2

GATE1

GATE2

V_D1

GREEN

V_D2

SR Current Inversion detect

SRC_INV1

DLY_EN1

DLY_EN2

RUN

SRC_INV2

V_{DD_GATE_ON}/V_{DD_GATE_OFF}

SR_COND1,2

GREEN

V_{D1_HGH}

GREEN MODE

GREEN

Protections

SOFT

START

SR_COND1

SR_COND2

Adaptive

V_GATE

V_{TH_OFF1}

HFS

SS_7V

V_GATE

Control

OTP1

VDD

GND

Figure 2. Internal Block Diagram of NCP4318

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2

NCP4318

PIN DESCRIPTION

Pin Number

NCP4318A

NCP4318B

Name

GATE1

GND

Description

1

2

3

1

2

4

Gate drive output for SR MOSFET1

Ground

VS1

Synchronous rectifier source sense input for SR1

Synchronous rectifier drain sense input. I

current source flows out of the

OFFSET1

VD1 pin such that an external series resistor can be used to adjust the synchronous

4

5

6

3

5

6

VD1

VS2

VD2

rectifier turn−off threshold. The I

current source is turned off when V is

OFFSET1

DD

under−voltage or when switching is disabled in green mode

Synchronous rectifier source sense input for SR2

Synchronous rectifier drain sense input. I

current source flows out of the

OFFSET2

VD2 pin such that an external series resistor can be used to adjust the synchronous

rectifier turn−off threshold. The I current source is turned off when V is

OFFSET2

DD

under−voltage or when switching is disabled in green mode

7

8

7

8

VDD

Supply Voltage

GATE2

Gate drive output for SR MOSFET2

ORDERING INFORMATION

Device (Ordering Code)

NCP4318ALC

Device Marking

NCP4318ALC

NCP4318BLC

NCP4318ALS

NCP4318AHJ

Package

Shipping^†

NCP4318BLC

SOIC 8

(Pb−Free)

2500 / Tape & Reel

NCP4318ALS

NCP4318AHJ

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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3

NCP4318

MAXIMUM RATINGS

Symbol

Parameter

Min

−0.3

−4

Max

37

Unit

V

Power Supply Input Pin Voltage

Drain Sense Input Pin Voltage

Gate Drive Output Pin Voltage

DD

V

200

17

V

D1, D2

V

−0.3

V

GATE1,

GATE2

V

Source Sense Input Pin Voltage

−0.3

−4

5.5

V

S1, S2

V

Source Sense Dynamic Input Pin Voltage (pulse width = 200 ns)

S1_DYN,

V

S2_DYN

P

Power Dissipation (T = 25°C)

0.625

150

260

3

W

°C

kV

D

A

T

Maximum Junction Temperature

Storage Temperature Range

−40

−60

J

T

STG

T

Lead Temperature (Soldering, 10 Seconds)

L

ESD

Electrostatic Discharge Capability Human Body Model, ANSI / ESDA / JEDEC

JS−001−2012 (except VD1, VD2 pin)

Human Body Model, VD1−GND, VD2−GND pin to

2

pin with 330pF capacitance on VD1 and VD2 pin

Charged Device Model, JESD22−C101

1

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All voltage values are with respect to the GND pin.

2. The capacitance can be replaced by C

of MOSFET.

OSS

THERMAL CHARACTERISTICS

Rating

Symbol

Value

22

Unit

°C/W

Thermal Characteristics

R

y

JT

R

165

q

JA

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

0

Max

35

Unit

V

DD

(Note 3)

VDD Pin Supply Voltage to GND

V

,V

Drain Sense Input Pin Voltage

Source Sense Input Pin Voltage

Operating Ambient Temperature

−0.7

−0.3

−40

180

5

D1 D2

V

S1 S2

T

J

+125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

3. Allowable operating supply voltage V can be limited by the power dissipation of NCP4318 related to switching frequency, load capacitance

DD

and ambient temperature.

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4

NCP4318

ELECTRICAL CHARACTERISTICS

V

DD

= 12 V and T = −40°C to 125°C unless otherwise specified

J

Symbol

Parameter

Conditions

Min

Typ

Max

4.3

Unit

Supply Voltage and Current Section

V

Turn−on threshold

V

DD

V

DD

V

DD

V

DD

rising with 4.3 V / 1 ms

4.0

3.8

6.5

6.0

V

DD_ON

V

Turn−off threshold

< V

> V

< V

3.6

5.0

DD_OFF

DD_GATE_ON

DD_OFF

V

SR gate enable threshold voltage

SR gate disable threshold voltage

7.1

DD_GATE_ON

DD_GATE_OFF

V

DD_GATE_OFF

(Note 4)

I

Operating current

f

= 100 kHz, C

= 1 nF

8

10

6

mA

DD_OP1

SW

GATE

I

Operating current

= 0 nF

0

DD_OP

SW

GATE

I

Start−up current

V

= V - 0.1 V

DD_ON

100

210

DD_START

DD

I

Operating current in green mode1

= 12 V (no V

switching)

100

255

mA

DD_GREEN

DD

D1/2

GREEN1 enable at T = 25°C

J

h

_

Number of V

alternative

V

falling lower than V

& V

D1/2

Cycle

SS SKIP

D1/2

TH_ON

switching for soft start skip range

rising higher than V

& No GATE

= 0 nF

GATE

TH_HGH

output at f

= 200 kHz, C

SW

Drain Voltage Sensing Section

V

(Note 4)

Comparator input offset voltage

Drain pin leakage current

Turn−on threshold

−1

0

1

mV

mA

OSI

I

V

= 200 V

DRAIN_LKG

D1/2

V

(Note 4)

R

= 0 W (includes comparator in-

OFFSET

−100

mV

TH_ON

put offset voltage)

From V higher than V

TH_HGH

t

Minimum off-time

1400

2000

2800

ns

OFF_MIN

D1/2

in ALC, BLC

in ALS

450

750

800

1150

30

1150

1550

80

ns

In AHJ

t

Turn−on propagation delay

Turn−on comparator delay

From V = −0.2 to V

DLY_EN = 0

ON_DLY

= 1 V, when

D1/2

GATE

t

(Note 4) Turn−on de−bounce time for L−ver- Turn−on comparator delay

240

ns

ON_DLY2

sion when additional turn−on delay

is enabled in light load condition

From V

= −0.2 to V

D1/2

GATE

DLY_EN = 1 in ALC, BLC, ALS, AHJ

t

Turn−off propagation delay

Turn−off comparator delay

30

80

ns

OFF_DLY

From V

= 0.6 to V

= 5.7 V

D1/2

GATE

V

Minimum turn−off threshold voltage

mV

R

= 0 W (includes comparator in-

−6

TH_OFF_MIN

(Note 4)

OFFSET

put offset voltage) in ALC, BLC, ALS

In AHJ

−14

4

mV

%

V

One step size of turn−off threshold

voltage

R

= 0 W, in ALC, BLC, AHJ

= 0 W, in ALC, BLC

TH_OFF_STEP

(Note 4)

OFFSET

in ALS

8

V

Maximum turn−off threshold volt-

age

R

118

242

110

2

TH_OFF_MAX

(Note 4)

OFFSET

in ALS

In AHJ

V

Turn−off threshold voltage reset

value

R

= 0 W, in ALC, BLC

TH_OFF_RST

(Note 4)

OFFSET

in ALS

In AHJ

10

−6

60

K

Ratio of the second step V

LLD1 is low.

If LLD1 is high, 2 step V

2ND_VOFF

(Note 4)

TH_OFF

in one

based on nominal V

switching cycle

nd

rd

TH_OFF

= 3

TH_OFF

step V

TH_OFF

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5

NCP4318

ELECTRICAL CHARACTERISTICS (continued)

= 12 V and T = −40°C to 125°C unless otherwise specified

V

DD

J

Symbol

Drain Voltage Sensing Section

Effective time ratio based on

Parameter

Conditions

Min

Typ

Max

Unit

K

LLD1 = 0 & t

(n−1) = 8 μs & t <

MIN_ON

(n−1).

70

%

2nd_TOFF

VG1

2nd_TOFF VG1

nd

(Note 4)

t

(n−1) for the 2 step V

K

*t

VG1

TH_OFF

in one switching cycle

If t

> K

*t

(n−1),

MIN_ON

2nd_TOFF VG1

= t

MIN_ON

t

VG1_70

V

(Note 4) Drain voltage high detect threshold

voltage

V

Rising in ALC, BLC, AHJ

0.85

1.5

V

TH_HGH

D1/2

in ALS

t

Minimum SR conduction time to

enable SR when DLY_EN = 0

TH_OFF1 or 2

when gate skip is triggered)

The duration from turn−on trigger to

500

350

710

ns

GATE_SKIP_L1

V

rising higher than V ,when

D1/2

TH_HGH

(3 steps V

decrease

DLY_EN = 0 in ALC, BLC, ALS

In AHJ

550

510

ns

t

Minimum SR conduction time to

enable SR when DLY_EN = 1 (3

The duration from turn−on trigger to

V rising higher than V ,when

D1/2

GATE_SKIP_L2

(Note 4)

TH_HGH

steps V

decrease

DLY_EN=1 in ALC, BLC, ALS

TH_OFF1 or 2

when gate skip is triggered)

In AHJ

385

ns

Minimum On−Time and Maximum On−Time Section

K

Adaptive minimum on time ratio

when DLY_EN = 0

DLY_EN=0 & t

(n−1) = 8 ms

/ t (n−1)

43

50

20

57

%

TON1

SR_COND

K

TON

= t

MIN_ON SR_COND

Adaptive minimum on time ratio

when DLY_EN = 1

DLY_EN=1 & t

(n−1) = 8 ms

/ t (n−1)

TON2

SR_COND

K

TON

= t

MIN_ON SR_COND

t

Minimum on−time upper limit when

t

< t

, when

4

2

5

6

3

ms

%

MIN_ON_U1

MIN_ON_U2

MIN_ON_L

MIN_ON

MIN_ON_U

DLY_EN = 0

Minimum on−time upper limit when

DLY_EN = 1

t

< t

MIN_ON

2.5

50

MIN_ON_L

MIN_ON_U

DLY_EN = 1

= K when DLY_EN = 0

INV1,

K

Adaptive SR current inversion de-

tection window ratio when DLY_EN

= 0

K

43

57

INV1

INV2

TON1

t

= t

MIN_ON

INV_WIN

K

Adaptive SR current inversion de-

tection window ratio when DLY_EN

= 1

K

= K

when DLY_EN = 1

20

16k

30

%

TON2

INV2,

= t

MIN_ON

t

INV_WIN

h

(Note 4) Normal consecutive switching cy-

cles to exit SR current inversion

Without parasitic V

oscillation

cycle

INV_EXT

D1/2

state which has t

ON_DLY2

t

Maximum SR turn−on time

21

39

22

ms

SR_MAX_ON

(Note 4)

f

(Note 4)

Minimum switching frequency

1/(t

+ t

)

kHz

MIN

SR_MAX_ON_CH1

SR_MAX_ON_CH2

Dead Time Regulation Section

I

Maximum of adaptive offset current

which have 31 steps and 10μA of

resolution

V

= V = 0

285

310

90

335

mA

OFFSET

D1

D2

t

Lower band of dead time regula-

tion

From V

in ALC, BLC, ALS

falling below V

GATE_LOW

ns

DEAD_LBAND

(Note 4)

GATE

In AHJ

170

ns

t

Upper band of dead time regula-

tion

From V

when LLD1 = 0

falling below V

,

t

DEAD_L

BAND

+90

DEAD_HBAND

(Note 4)

GATE

GATE_LOW

h

LLD1

(Note 4)

First light load detection (LLD1)

ηV

≤ h

LLD1

7

TH_OFF_CNT

threshold number of V

ulator output

mod-

TH_OFF

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6

NCP4318

ELECTRICAL CHARACTERISTICS (continued)

= 12 V and T = −40°C to 125°C unless otherwise specified

V

DD

J

Symbol

Dead Time Regulation Section

(Note 4)

Parameter

Conditions

Min

Typ

Max

Unit

h

LLD2

Second light load detection (LLD2) ηV

≤ h

3

TH_OFF_CNT

LLD2

threshold number of V

ulator output

mod-

TH_OFF

Green Mode Section

t

Non−switching period of SR gate

to Enter Green Mode 1 for L−ver-

sion

When SR_COND1, 2 are both low for

, the green mode1 is

45

60

75

ms

GRN1_ENT

t

GRN1_ENT_L

enabled in ALC, BLC, ALS

in AHJ

25

40

6

55

ms

t

Non−switching period of SR gate

to Enter Green Mode 2 for L−ver-

sion

When SR_COND1, 2 are both low for

4.5

7.5

GRN2_ENT

t

, the green mode2 is

GRN2_ENT_L

enabled in ALC, BLC, ALS

in AHJ

2.5

4

5.5

ms

h

_

Number of buffer switching cycle to Number of switching with V > V

TH_HGH

cycle

CSW EXT

D1

(Note 4)

recover I

when IC exits from

GREEN1 exit only

DD_OP

green mode 1.

Protection Section

V

(Note 4) Threshold voltage of current inver-

sion detection

LLD1 = 0

0

mV

ns

SRC_INV

LLD1 = 1, Virtual V

V

TH_OFF

TH_OF

F

t

(Note 4)

Debounce time of SR current

inversion detection for L−version

V

INV

> 4.5 V & V

> V for

SRC_INV

320

INV

GATE1/2

D1/2

t

In ALC, BLC

In ALS

520

170

150

ns

In AHJ

V

(Note 4)

Drain threshold voltage for the

primary shutdown protection

V

D1/2

> 4.5 V with 200 ns delay &

GATE1/2

mV

SD_PRI

V

> V

when DLY_EN = 0,

SD_PRI

V

> 4.5 V with 100 ns delay &

SD_PRI

ALC, BLC

GATE1/2

D1/2

> V

when DLY_EN = 1 in

in ALS

200

100

70

mV

%

In AHJ

K

(Note 4)

Detection window time ratio based

LLD1 = 0 & t

(n−1) = 8 ms & t <

MIN_ON

65

75

SD_PRI

VG1

on t

(n−1) for the primary shut-

K

*t

(n−1).

VG1

2nd_TOFF VG1

down protection

If t

VG1_70

> K

MIN_ON

*t

(n−1),

MIN_ON

2nd_TOFF VG1

t

= t

V

(Note 4) Drain threshold voltage to trigger

abnormal VD sensing protection

V

> V

& V

> 4.5V with

in ALC,

0.85

V

ABN_VD

D1/2

ABN_VD

GATE1/2

SD_PRI

100 ns delay within K

BLC, AHJ

V

= V

TH_HGH

ABN_VD

in ALS

T > T

1.5

V

T

(Note 4)

Over temperature protection1

Over temperature protection2

& V = 6.7 V in ALC,

GATE

°C

105

OTP1

J

OTP1

BLC, AHJ

in ALS

130

140

°C

(Note 4)

T > T

& No gate output in ALC,

OTP2

J

OTP2

BLC, AHJ

in ALS

disable

80

T

(Note 4) Over temperature protection reset

T < T

, OTP1 and OTP2 are

°C

OTP_RST

J

OTP_RST

reset

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7

NCP4318

ELECTRICAL CHARACTERISTICS (continued)

= 12 V and T = −40°C to 125°C unless otherwise specified

V

DD

J

Symbol

Gate Driver Section

Parameter

Conditions

Min

Typ

Max

Unit

V

Gate clamping voltage

12 V < V < 33 V, C = 4.7 nF at

GATE

J OTP1

9

5.0

4

10.5

6.7

5

12

8.2

6.1

V

GATE_MAX

DD

(Note 4)

T < T

V

Gate clamping voltage for adaptive

gate voltage control

V

DD

= 12 V, C

= 4.7 nF

GATE_MAX_7V

GATE

(Note 4)

t

(Note 4) Adaptive gate control enabling

switching period

The time t from V

(n−1) rising edge

ms

HFS1_EN

s

GATE1

to V

(n) rising edge at

GATE1

OTP1

T < T

in ALC, BLC, ALS

J

In AHJ

4

ms

I

(Note 4) Peak sourcing current of gate

driver

1.5

A

SOURCE

I

(Note 4)

Peak sinking current of gate driver

Gate driver sourcing resistance

4.5

8

A

SINK

R

W

DRV_SOURCE

(Note 4)

R

Gate driver sinking resistance

Rise time

1.5

50

30

W

ns

DRV_SINK

(Note 4)

t

R

V

= 12 V, C = 3.3 nF,

GATE

150

50

DD

L

= 1 V ꢀ 6 V at T = 25°C

J

t

F

Fall time

V

= 12 V, C = 3.3 nF,

DD

GATE

L

= 6 V ꢀ 1 V at T = 25°C

J

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Not tested but guaranteed by design

KEY PARAMETERS FOR IPT OPTIONS

NCP4318ALC

#4, #6

NCP4318BLC

#3, #6

NCP4318ALS

#4, #6

NCP4318AHJ

#4, #6

Drain sensing pin

Frequency

L−version

Low / High

320 ns

90 ns

L−version

Low / High

320 ns

90 ns

L−version

Always High

520 ns

90 ns

H−version

Low/High

170 ns

4 ms

DLY_EN

t

f

INV

DEAD_LBAND

GRN2_ENT

HFS_EN

6 ms

200 kHz

2

200 kHz

2

200 kHz

2

250 kHz

1

nV

TH_OFF_RST

V

0.85 V

1.5 V

0.85 V

TH_HGH

2−Level

(10 V, 6 V)

2−Level

(10 V, 6 V)

1−Level

(10 V)

1−Level

(10 V)

GATE_CTRL

t

2 ms

−6 mV

4 mV

2 ms

−6 mV

4 mV

800 ns

−6 mV

8 mV

1.15 ms

−14 mV

4 mV

OFF_MIN

V

TH_OFF_MIN

TH_OFF_STEP

TH_OFF_MAX

TH_OFF_RST

GATE_SKIP_L1

GATE_SKIP_L2

GRN1_ENT

118 mV

2 mV

118 mV

2 mV

242 mV

10 mV

710 ns

510 ns

60 ms

110 mV

−6 mV

550 ns

385 ns

40 ms

t

710 ns

510 ns

60 ms

710 ns

510 ns

60 ms

6 ms

4 ms

GRN2_ENT

V

150 mV

105°C

140°C

5 ms

150 mV

105°C

140°C

5 ms

200 mV

130°C

Disable

5 ms

100 mV

105°C

140°C

4 ms

SD_PRI

OTP1

T

OTP2

t

HFS1_EN

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NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. I_OFFSET1vs. Temperature

Figure 5. t_{MIN_ON_U1_CH1}vs. Temperature

Figure 7. V_{TH_ON_CH1}vs. Temperature

Figure 4. I_OFFSET2vs. Temperature

Figure 6. t_{MIN_ON_U1_CH2}vs. Temperature

Figure 8. V_{TH_ON_CH2}vs. Temperature

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9

NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. V_{TH_OFF_STEP_CH1}vs. Temperature

Figure 10. V_{TH_OFF_STEP_CH2}vs. Temperature

Figure 12. V_{DD_OFF}vs. Temperature

Figure 11. V_{DD_ON}vs. Temperature

Figure 13. V_{DD_GATE_ON}vs. Temperature

Figure 14. I_{DD_START}vs. Temperature

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10

NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 15. I_{DD_OP1}vs. Temperature

Figure 17. I_{DD_GREEN}vs. Temperature

Figure 19. t_{ON_DLY_CH1}vs. Temperature

Figure 16. I_{DD_OP0}vs. Temperature

Figure 18. n_{SS_SKIP}vs. Temperature

Figure 20. t_{ON_DLY_CH2}vs. Temperature

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11

NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 21. t_{OFF_DLY_CH1}vs. Temperature

Figure 23. KTON1_CH1 vs. Temperature

Figure 25. KINV1_CH1 vs. Temperature

Figure 22. t_{OFF_DLY_CH2}vs. Temperature

Figure 24. KTON1_CH2 vs. Temperature

Figure 26. KINV1_CH2 vs. Temperature

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12

NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 27. V_{GATE_MAX_CH1}vs. Temperature

Figure 29. V_{GATE_MAX_7V_CH1}vs. Temperature

Figure 31. t_{R_CH1}vs. Temperature

Figure 28. V_{GATE_MAX_CH2}vs. Temperature

Figure 30. V_{GATE_MAX_7V_CH2}vs. Temperature

Figure 32. t_{R_CH2}vs. Temperature

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13

NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 33. t_{F_CH1}vs. Temperature

Figure 35. V_{TH_HIGH_CH1}vs. Temperature

Figure 37. t_{OFF_MIN_CH1}vs. Temperature

Figure 34. t_{F_CH2}vs. Temperature

Figure 36. V_{TH_HIGH_CH2}vs. Temperature

Figure 38. t_{OFF_MIN_CH2}vs. Temperature

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14

NCP4318

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 39. t_{GATE_SKIP_L1_CH1}vs. Temperature

Figure 40. t_{GATE_SKIP_L1_CH2}vs. Temperature

Figure 42. t_{GRN2_ENT}vs. Temperature

Figure 41. t_{GRN1_ENT}vs. Temperature

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15

NCP4318

APPLICATION INFORMATION

Basic Operation Principle

constant operating frequency and turn−on time. However, in

case of the frequency varying system, it may lead to late

turn−off during frequency increasing so that negative

current can flow in the secondary side.

To achieve both advantages, NCP4318 adopts mixed type

turn−off control method which utilizes a hysteresis band

dead time control. As shown in Figure 44, the instantaneous

NCP4318 controls the SR MOSFET based on the

instantaneous drain−to−source voltage sensed across

DRAIN and SOURCE pins. Before SR gate is turned on, SR

body diode operates as the conventional diode rectifier.

Once the body diode starts conducting, the drain−to−source

voltage drops below the turn−on threshold voltage V

TH_ON

which triggers the turn−on of the SR gate. Then, the

drain−to−source voltage is determined by the product of

drain voltage V is compared with a virtual V

to

D1

TH_OFF1

turn off SR gate. The virtual V

is adaptively

TH_OFF1

turn−on resistance

instantaneous SR current. When the drain−to−source

voltage reaches the turn−off threshold voltage V , as

R

of SR MOSFET and

changed to compensate the stray inductance effect and

regulate t between t and t

DS_ON

DEAD

DEAD_LBAND

DEAD_HBAND

regardless of parasitic inductances. Therefore, NCP4318

can show robust operation with minimum dead time.

TH_OFF

SR MOSFET current decreases to near zero, NCP4318 turns

off the gate. If SR dead time is larger or smaller than the dead

time regulation target. NCP4318 adaptively changes a

virtual turn−off threshold voltage to regulate the dead time

Present information

=instantaneous Vdrain type

Present information+Previous cycle information

=mixed type control

RUN

between t

and t

and to maximize

DEAD_LBAND

DEAD_HBAND

system efficiency.

VG1

SET

D

Q

Turn−on

SR Turn−on Algorithm

CLR

VD1

When V

is lower than V

by body diode

D1

TH_ON

V_OFFSET1,

V_{TH_OFF1}

Control

Turn−off

conduction of SR MOSFET, turn−on comparator COM1

outputs high. If an additional delay flag signal DLY_EN1 is

Virtual V_{TH_OFF1}

low, VG1 goes high with 30 ns of t

is charged by 1.5 A of sourcing current I

and finally GATE1

ON_DLY

Previous cycle dead time information

=Prediction type

of a gate

SOURCE

driver.

On the other hand, if DLY_EN is turned to high by current

inversion detection SRC_INV high or GREEN high,

additional turn−on delay is applied by adaptive turn−on

delay block. In this case, SR gate is turned on after a body

Figure 44. SR Turn−off Algorithm

Hysteresis Band Dead Time Regulation Control

The stray inductance of SR MOSFET induces a positive

voltage offset across drain−to−source voltage when SR

current decreases. This makes drain−to−source voltage of

diode conduction time longer than t

is confirmed.

ON_DLY2

I_OFFSET1

SR MOSFET higher than the product of R

and

DS_ON

DLY_EN1

RUN

instantaneous SR current, which results in premature SR

turn−off as shown in Figure 45. Since the induced offset

voltage is changed as the output load current changes, the SR

dead time needs to tune with the output load variation. To

compensate it, NCP4318 utilizes the virtual turn−off

threshold voltage which is determined by 31 steps of internal

COM1

VG1

SET

CLR

Q

GATE1

D

Adaptive

turn−on

delay

VD1

VS1

V_{TH_ON}

Turn−on

Turn−off

V_{TH_OFF1}

turn−off threshold voltages V

and modulated

TH_OFF(n)

offset voltage V

as shown in Figure 44. The virtual

Figure 43. SR Turn−on Algorithm

OFFSET(n)

turn−off threshold voltage and the offset voltage can be

expressed as:

SR Turn−off Algorithm

Since a SR turn−off method determines SR conduction

time and stable SR operation, the SR turn−off method is one

of important feature of the SR controllers. One of the

conventional method uses present information by an

instantaneous drain voltage. This method is widely used and

easy to realize, and can prevent late turn−off. However, it

frequently shows premature turn−off due to parasitic stray

inductances of PCB pattern and lead frame of SR MOSFET.

In another method, SR conduction time is predicted by using

previous cycle drain voltage information. Since it can

prevent the premature turn−off, it is good for the system with

Virtual V_{TH_OFF1}ꢁ V_{TH_OFF1(n)}ꢂ V_OFFSET1(n)

(eq. 1)

V_OFFSET1(n)ꢁ R_OFFSET1ꢃ I_OFFSET1(n)

(eq. 2)

where, R

is the external drain sensing resistance

OFFSET

and I

has 10 mA of step size. So, V

is used

OFFSET1

for fine tuning of Virtual V

. When V

has

TH_OFF1

OFFSET1

saturated to maximum or minimum values, V

changes to its next step for coarse control.

TH_OFF1

In Figure 46, if a measured dead time T

is larger than

DEAD

upper band of t

, V

is decreased by one

DEAD_HBAND

OFFSET

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16

NCP4318

step decrease of I

next switching cycle. As a result,

I_SR1

OFFSET

the dead time is decreased by increase of virtual V

,

TH_OFF

and becomes closer to t

, as shown in Figure 47.

DEAD_HBAND

If the dead time is placed between lower band t

DEAD_LBAND

V_D1

and upper band t

is and waits until T

in Figure 48, V

is larger than t

stay as

or

DEAD_HBAND

OFFSET

Virtual

V_{TH_OFF}

DEAD

DEAD_HBAND

smaller than t

regulated between the lower band t

Therefore, the dead time is

DEAD_LBAND

V_{TH_ON}

and the

DEAD_LBAND

V_GATE1

t_{DEAD_LBAND}<T_DEAD<t_{DEAD_HBAND}

upper band

t

regardless of parasitic

DEAD_HBAND

inductances. This hysteresis band dead time control

provides stable operation in light load condition by

minimized dead time variation.

t_{DEAD_LBAND}t_{DEAD_HBAND}

Figure 48. When t_{DEAD_LBAND}< T_DEAD< t_{DEAD_HBAND}

I_SR1

V_D1

Advanced Adaptive Minimum Turn−on Time

V_D1

When SR gate is turning on, there may be severe

oscillation in drain−to−source voltage of SR MOSFET,

which results in several turn−off mis−triggering as shown in

Figure 49. To provide stable SR gate signal without short

pulses, it is desirable to have large turn−off blanking time

(=minimum turn−on time) until the drain voltage oscillation

attenuates. However, too large blanking time results in an

inversion current problem under light load condition, where

the SR conduction time is shorter than the minimum turn−on

time.

V_LS1

V_{TH_OFF}

V

V_GATE1

V_LS1

I_SR1

Figure 45. Premature SR Turn−off by Stray Inductor

I_SR1

To solve this issue, NCP4318 has adaptive minimum

turn−on time t

where the turn−off blanking time

MIN_ON

changes in accordance with the SR conduction time

(n−1) measured in previous switching cycle. The

SR conduction time is measured by the time from SR gate

V_D1

t

SR_COND

Virtual

V_{TH_OFF1}

rising edge to where the drain sensing voltage V is higher

V_{TH_ON}

D1

than 0.85 V of V

. So, the adaptive minimum on−time

V_GATE1

_DEAD1>t_{DEAD_HBAND}

TH_HGH

t

is defined by 50% of t

(n−1) as shown in

T

MIN_ON

SR_COND

Figure 50. During the t

, SR turn−off by Virtual

MIN_ON

t_{DEAD_LBAND}

t

V

is prohibited to prevent abnormal turn−off by the

TH_OFF1

Figure 46. When T_DEAD> t_{DEAD_HBAND}

drain sensing noise. The minimum value of t

and the

MIN_ON

maximum value of t

are defined by 200 ns and 5 ms,

MIN_ON

respectively. When the additional turn−on delay flag

DLY_EN1 is high in the light load condition, t

I_SR1

MIN_ON

becomes 20% of t

(n−1) as shown in Figure 51.

SR_COND

V_D1

Virtual

V_{TH_OFF1}

V_{TH_ON}

V_GATE1

T_DEAD1≈t_{DEAD_HBAND}

t_{DEAD_LBAND}

t

Figure 47. When T_DEAD= t_{DEAD_HBAND}

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17

NCP4318

V_D1

shown in Figure 52, which induces SR turn−on mis−trigger.

Turn−off mis−trigger is prohibited

during t_{MIN_ON}

Finally, the turn−on mis−trigger makes leading edge

inversion current in the secondary side.

The second inversion current is trailing edge inversion

V_{TH_HGH}

V_{TH_OFF}

V_{TH_ON}

current caused by minimum on−time t

. If t

is

MIN_ON

t_{MIN_ON}=50% of t_{SR_COND}of

previous cycle

longer than current transfer width from the primary side,

trailing edge inversion current can happen as shown in

Figure 53. If proper algorithm is not provided to prevent this

inversion current, severe drain voltage spike may happen.

To prevent the both leading edge and trailing edge

inversion currents, NCP4318 uses the current inversion

detection function SRC_INV. When SR gate is turned on and

current inversion occurs, the drain sensing voltage of SR

SR conduction time = t_{SR_COND}

t_{ON_DLY}

t_DEAD

V_GATE1

I_SR

MOSFET becomes positive value. In this condition, if V

D1

Figure 49. Minimum Turn−on Time and Turn−off

Mis−triggering

is higher than 0mV with a light load detection flag signal

LLD=0, or the virtual V with LLD = 1 for t of the

TH_OFF

INV

detection debounce time, SR current inversion detection is

triggered and turn−off SR gate immediately. Then, turn−on

delay is increased to t

from next turning−on.

ON_DLY2

V_GATE1

V_GATE2

SR turn−on mis−trigger By capacitive current spike

t_{SR_COND}(n−1) t_{MIN_ON}=50% of t_{SR_COND}(n−1)

V_D1

V

I_SR

V_DS

Figure 50. Minimum Turn−on Time t_{MIN_ON}when

DLY_EN = 0

Capacitive

current spike

Leading edge inversion current

Figure 52. Leading Edge Inversion Current

V_GATE1

V_GATE2

t_{MIN_ON}

V_GATE1V_GATE2

t_{SR_COND}(n−1) t_{MIN_ON}=20% of t_SRCOND(n−1)

V

V_DSspike

I_SR

V_DS

Figure 51. Minimum Turn−on Time t_{MIN_ON}when

Trailing edge inversion current

DLY_EN = 1

Figure 53. Trailing Edge Inversion Current

Current Inversion Detection

During SR operation, two types of inversion current may

occur. First, leading edge inversion current is caused by the

capacitive current spike in light load condition. In heavy

load condition, the body diode of SR MOSFET starts

conducting right after the primary side switching transition

takeing place. However, when the resonance capacitor

voltage amplitude is not large enough in light load condition,

the voltage across the magnetizing inductance of the

transformer is smaller than the reflected output voltage.

Thus, the secondary side SR body diode conduction is

delayed until the magnetizing inductor voltage builds up to

the reflected output voltage. However, the primary side

switching transition can cause capacitive current spike and

turn on the body diode of SR MOSFET for a short time as

Light Load Detection (LLD)

Since NCP4318 adopts the dead time regulation control

algorithm, the output load condition can be detected by the

control variable V

(n). As shown in Figure 54, when

TH_OFF

the output load is increased to the heavy load condition,

V

(n) is also increased. Vice versa. Therefore,

level can represent the output load condition.

TH_OFF

V

TH_OFF

When the control variable number ‘n’ is lower than ‘7’,

NCP4318 detects a light load condition. So, light load

detection flag signal LLD goes high. If ‘n’ is higher than ‘8’,

LLD becomes low. This LLD signal is used for SRC_INV

detection threshold voltage control and adaptive V

control.

GATE

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18

NCP4318

Virtual V_{TH_OFF}

V_{TH_OFF(4)}

Heavy Load

V_{TH_OFF(4)}−R_OFFSETx I_{OFFSET_STEP0}

V_{TH_OFF(5)}−R_OFFSETx I_{OFFSET_STEP31}

V_GATE1

V_GATE2

↑

Virtual V_{TH_OFF}trajectory when load

V_{TH_OFF4}

V_{TH_OFF(3)}

V_{TH_OFF(3)}−R_OFFSETx I_{OFFSET_STEP0}

V_{TH_OFF(4)}−R_OFFSETx I_{OFFSET_STEP31}

1

2

3

4

GREEN1 exit

V_{TH_OFF3}Range

V

V_DS2

V_{TH_OFF(2)}

V_{TH_OFF(2)}−R_OFFSETx I_{OFFSET_STEP0}

V_{TH_OFF(3)}−R_OFFSETx I_{OFFSET_STEP31}

V_{TH_OFF2}Range

V_{TH_OFF(1)}

V_{TH_OFF(1)}−R_OFFSETx I_{OFFSET_STEP0}

V_{TH_OFF(2)}−R_OFFSETx I_{OFFSET_STEP31}

Figure 56. GREEN1 Exits

Adaptive V_GATEControl

V_{TH_OFF1}Range

V_{TH_OFF(0)}

V_{TH_OFF(0)}−R_OFFSETx I_{OFFSET_STEP0}

V_{TH_OFF(1)}−R_OFFSETx I_{OFFSET_STEP31}

In NCP4318, there are three condition to trigger adaptive

control. First one is the output load condition. In light

load condition, to save SR gate driving current and

maximize efficiency, NCP4318 adaptively changes the gate

V_{TH_OFF0}Range

V

GATE

Virtual V_{TH_OFF_MIN}

Light Load

V_{TH_OFF(0)}−R_OFFSETx I_{OFFSET_STEP31}

t

Figure 54. Virtual V_{TH_OFF}Trajectory when Iout

Increases

clamp voltage V

. As shown in Figure 57, when LLD

GATE

goes high, the gate clamp voltage is reduced from 10 V to

6 V. It could save 40% of gate driving power consumption.

Green Mode

In heavy load condition, V

comes back to 10 V for

GATE

In NCP4318, there are two stages to trigger GREEN

function. GREEN1 is for low power consumption in light

load condition and GREEN2 is for preparing GREEN1

triggering.

When the LLC system in the primary side operates with

skip mode under light load condition, NCP4318 can enter

GREEN1 mode to reduce operating current. In that

condition, if V has no switching operation for longer than

, the GREEN1 mode is activated as shown in

Figure 55. Once NCP4318 is in the GREEN1 mode, all the

lower turn−on resistance R

of SR MOSFET in

DS_ON

Figure 58.

The second condition is the operating frequency. If the

LLC operating frequency is higher than 200 kHz of f

HFS_EN

in L−version and 250 kHz in H−version, NCP4318 reduces

for lower SR gate driving current.

V

GATE

The last condition is junction temperature T of IC. When

J

D1

T is higher than 105 °C of T

, V

is changed to 6 V

J

OTP1 GATE

t

GRN1_ENT

to reduce T . V

comes back to 10 V, when T is lower

J

GATE

J

than 80 °C of T

.

OTP_RST

major functions are disabled to reduce the operating current

down to 100 mA of I

exits from the GREEN1 mode, four cycles of V switching

. After then, when NCP4318

DD_GREEN

V

V_GATE2

D1

are required as shown in Figure 56.

Before GREEN1 is triggered, if no switching operation of

Adaptive V_GATEcontrol enter @ LLD1=1

V

D1

is longer than t , 100 ns of GREEN2 pulse is

GRN2_ENT

generated to reset adaptive dead time control variables

including V and I . In addition, the additional

V_DS1

V_DS2

TH_OFF

OFFSET

delay flag signal DLY_EN and the light load detection signal

LLD become high. So, GREEN2 prepares new SR operation

start and allows soft increment of SR gate pulses next

switching bundle.

Figure 57. V_GATEControl Enters when LLD is High

V_GATE1

V_GATE2

V_GATE1

V_GATE2

Adaptive V_GATEcontrol exit @ LLD1=0

GREEN1 trigger

t_{GRN1_ENT}

V

V_DS2

V

V_DS2

Figure 55. GREEN1 Enters

Figure 58. V_GATEControl Exits when LLD is Low

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19

NCP4318

Soft Start

even in minimum on−time. Though SRC_INV function can

turn−off SR gate at that moment, it has longer delay time for

confirmation. For faster turn−off method, the primary

shutdown protection is utilized.

When the LLC gate signal in the primary side is suddenly

disappears, SR current shows inflection point which induces

high dV/dt of drain sensing voltage. If the dV/dt is higher

At the beginning of LLC startup, the operating frequency

is severely changed and sometimes symmetrical 50% duty

cycles between high−side and low−side power switches on

the primary side cannot be guaranteed. It makes SR control

difficult and unstable operation.

To avoid SR operation under the transition, soft−start

function is utilized. In the first region of soft−start, SR gate

is skipped during 256cycles to check whether LLC system

is normal or not. After the first region, NCP4318 starts

than a threshold level V /t , the protection is

SD_PRI INV

triggered and SR gate turns off immediately. In addition, it

turns GREEN1 high making 4 cycles gate skipping to ignore

turn−on mis−trigger caused by energy bouncing in the

secondary side.

The other protection is the abnormal drain sensing

protection. In normal condition, when SR gate is turning on,

generating SR gate pulses with V

= 6 V and V

until LLD signal goes low. This allows

GATE

TH_OFF

= V

TH_OFF_RST

soft−increment of SR gate pulses and gradual reduction of

the SR dead time at startup.

V

is higher than 4.5 V and the drain sensing voltage V

GATE

D

Protection

should be lower than 0.85 V of V

diode conduction. However, in abnormal condition, V can

be higher than V

fluctuation. In that condition, NCP4318 triggers abnormal

drain sensing protection and turns off SR gate and makes

GREEN1 high.

due to the body

TH_HGH

For higher system reliability, two protections are

implemented in NCP4318. First one is the primary side

shutdown protection. In SR controller point of view,

NCP4318 cannot know directly the primary side abnormal

gate off by a certain LLC protection or power−off. In that

condition, SR gate should be turned off as soon as possible

D

even if V > 4.5 V due to V

GATE D

TH_HGH

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20

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

DATE 19 DEC 2008

SYMBOL

MIN

NOM

MAX

1.35

A

1.75

A1

b

0.10

0.33

0.19

4.80

5.80

3.80

0.25

0.51

0.25

5.00

6.20

4.00

c

E1

E

D

E

E1

e

h

L

θ

1.27 BSC

0.25

0.40

0º

0.50

1.27

8º

PIN # 1

IDENTIFICATION

TOP VIEW

D

h

A1

θ

A

c

e

b

L

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34272E

SOIC 8, 150 MILS

PAGE 1 OF 1

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1


型号：	NCP4318ALS
厂家：	ONSEMI
描述：	Advanced Synchronous Rectifier Controller for LLC Resonant Converter
文件：	总22页 (文件大小：1074K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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