首页 |元器件品牌

NCP4390DR2G [ONSEMI]

Resonant Controller with Synchronous Rectifier Control, Enhanced Light Load;
NCP4390DR2G
型号： NCP4390DR2G
厂家： ONSEMI    ONSEMI
描述：

Resonant Controller with Synchronous Rectifier Control, Enhanced Light Load
文件： 总30页 (文件大小：760K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
DATA SHEET  
www.onsemi.com  
Advanced Secondary Side  
LLC Resonant Converter  
Controller with Synchronous  
Rectifier Control  
SOIC−16  
CASE 751B−05  
MARKING DIAGRAM  
NCP4390  
The NCP4390 is an advanced Pulse Frequency Modulated (PFM)  
controller for LLC resonant converters with Synchronous  
Rectification (SR) that offers best in class efficiency for isolated  
DC/DC converters. It employs a current mode control technique based  
on a charge control, where the triangular waveform from the oscillator  
is combined with the integrated switch current information to  
determine the switching frequency. This provides a better  
control−to−output transfer function of the power stage simplifying the  
feedback loop design while allowing true input power limit capability.  
Closed−loop soft−start prevents saturation of the error amplifier and  
allows monotonic rising of the output voltage regardless of load  
condition. A dual edge tracking adaptive dead time control minimizes  
the body diode conduction time thus maximizing efficiency.  
NCP4390  
AWLYWWG  
1
NCP4390  
A
L
Y
WW  
G
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
PIN CONNECTIONS  
5VB  
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Features  
VDD  
PWMS  
FMIN  
FB  
• Secondary Side PFM Controller for LLC Resonant Converter with  
Synchronous Rectifier Control  
• Charge Current Control for Better Transient Response and Easy  
Feedback Loop Design  
• Adaptive Synchronous Rectification Control with Dual Edge  
Tracking  
• Closed Loop Soft−Start for Monotonic Rising Output  
• Wide Operating Frequency (39 kHz ~ 690 kHz)  
PROUT1  
PROUT2  
SROUT1  
COMP  
SS  
SROUT2  
SR1DS  
ICS  
CS  
RDT  
• Green Functions to Improve Light−Load Efficiency  
♦ Symmetric PWM Control at Light−Load to Limit the Switching  
Frequency while Reducing Switching Losses  
♦ Disabling SR at Light−Load Condition  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 3 of  
this data sheet.  
• Protection Functions with Auto−Restart  
♦ Over−Current Protection (OCP)  
♦ Output Short Protection (OSP)  
♦ NON Zero−Voltage Switching Prevention (NZS) by  
Compensation Cutback (Frequency Shift)  
♦ Power Limit by Compensation Cutback (Frequency Shift)  
♦ Overload Protection (OLP) with Programmable Shutdown Delay  
Time  
• Programmable Dead Times for Primary Side Switches and Secondary  
Side Synchronous Rectifiers  
• V Under−Voltage Lockout (UVLO)  
DD  
• Wide Operating Temperature Range −40°C to +125°C  
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS  
Compliant  
Applications  
• Automotive On Board Charger  
• Intelligent 100 W−2 kW+ Off−Line & Industrial Power Supplies  
© Semiconductor Components Industries, LLC, 2018  
1
Publication Order Number:  
November, 2021 − Rev. 2  
NCP4390/D  
NCP4390  
DG1  
RG1  
VIN  
Q1  
Q2  
RGS1  
PRDRV+  
SR2  
SR1  
CIN  
DG2  
RG2  
Ns  
VO  
SRDRV2  
SRDRV1  
PRDRV−  
Np  
COUT  
CR  
RGS2  
Ns  
CT  
RCS2  
RCS1  
RSRDS1  
CVDD  
RSRDS2  
C5VB  
5VB  
GND  
PWMS  
FMIN  
VDD  
RPWMS  
RFMIN  
RFB1  
PRDRV+  
PROUT1  
PROUT2  
RICS  
FB  
PRDRV−  
CCOMP  
COMP  
SS  
SRDRV1  
SRDRV2  
SROUT1  
SROUT2  
CSS  
R
CICS  
ICS  
CS  
SR1DS  
RDT  
CDT  
RDT  
Figure 1. Typical Application Schematic of NCP4390  
Block Diagram  
+
ICS_RST  
−
3V  
HALF_CYCLE  
PWM_CTRL  
14  
13  
PROUT1  
PROUT2  
+
VCT  
1.5V  
VSAW  
CLK1  
CLK2  
Digital  
PFM/PWM  
Block  
Dead Time  
Control  
Block  
+
−
−
3
FMIN  
COMP_I  
PWM  
3/4  
1V  
CT_RST  
CT_RST  
7
ICS  
Dead Time  
Setting  
3
RDT  
OCP2  
Protection  
Block  
ICS_RST  
SR_SKIP  
Current  
Analyzer  
SHUTDOWN  
SKIP  
Auto−Restart  
Control  
SR_SHRNK  
DOWN  
UP1  
UP4  
SR_SKIP  
PWMM  
SR STOP  
RST  
RST  
5V  
Compensation  
Cutback signal  
Generator  
12  
11  
SROUT1  
SROUT2  
6
SS  
PROUT1  
PROUT2  
Dual Edge Adaptive  
Tracking SR Control Block  
+
SR_SHRNK  
+
OSP  
5
COMP  
−
SR1_CND  
SR2_CND  
−
1.2V  
2.4V  
SR Conduction Detect  
Block  
4
10  
15  
FB  
SR1DS  
VDD  
PWM Mode  
Entry Level  
Setting  
+
PWM_CTRL  
2
+
PWMS  
PWMM  
−
−
8.5V/10V  
NON ZVS  
Detect  
8
1 5VB  
BIAS  
CS  
VDD_GOOD  
−
+
−3.5V  
+
16  
GND  
OCP2  
−
3.5V  
Figure 2. Internal Block Diagram of NCP4390  
www.onsemi.com  
2
NCP4390  
PIN DESCRIPTION  
Pin Number  
Pin Name  
5VB  
Description  
1
2
5 V REF  
PWMS  
FMIN  
PWM mode entry level setting.  
Minimum frequency setting pin.  
3
4
FB  
Output voltage sensing for feedback control.  
Output of error amplifier.  
5
COMP  
SS  
6
Soft−start time programming pin.  
7
ICS  
Current information integration pin for current mode control.  
Current sensing for over current protection.  
Dead time programming pin for the primary side switches and secondary side SR switches.  
SR1 Drain−to−source voltage detection.  
Gate drive output for the secondary side SR MOSFET 2.  
Gate drive output for the secondary side SR MOSFET 1.  
Gate drive output 2 for the primary side switch.  
Gate drive output 1 for the primary side switch.  
IC Supply voltage.  
8
CS  
9
RDT  
10  
11  
12  
13  
14  
15  
16  
SR1DS  
SROUT2  
SROUT1  
PROUT2  
PROUT1  
VDD  
GND  
Ground.  
ORDERING AND SHIPPING INFORMATION  
†
Ordering Code  
Device Marking  
NCP4390  
Package  
Shipping  
NCP4390DR2G  
SOIC−16  
Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
www.onsemi.com  
3
NCP4390  
MAXIMUM RATINGS  
Symbol  
Parameter  
Min  
Max  
Unit  
VDD Pin Supply Voltage to GND  
5VB Pin Voltage  
−0.3  
20.0  
V
V
DD  
−0.3  
−0.3  
−0.3  
−0.3  
−0.3  
−0.3  
−0.5  
−5.0  
−0.3  
−0.3  
−0.3  
−0.3  
−0.3  
−0.3  
−40  
5.5  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
V
V
V
5VB  
PWMS Pin Voltage  
FMIN Pin Voltage  
FB Pin Voltage  
V
PWMS  
V
V
FMIN  
V
V
FB  
COMP Pin Voltage  
SS Pin Voltage  
V
V
COMP  
V
V
SS  
ICS Pin Voltage  
V
V
ICS  
CS Pin Voltage  
V
V
CS  
RDT Pin Voltage  
V
V
RDT  
SR1DS Pin Voltage  
PROUT1 Pin Voltage  
PROUT2 Pin Voltage  
SROUT1 Pin Voltage  
SROUT2 Pin Voltage  
Junction Temperature  
V
V
SR1DS  
PROUT1  
PROUT2  
SROUT1  
SROUT2  
V
DD  
V
V
V
V
V
V
DD  
V
V
DD  
V
V
DD  
V
150  
260  
150  
2
°C  
°C  
°C  
kV  
T
J
Lead Soldering Temperature (10 Seconds)  
Storage Temperature  
T
L
−65  
T
STG  
Human body Model,  
ANSI / ESDA / JEDEC  
Electrostatic Discharge  
Capability  
ESD  
JS−001−2012  
Charged Device Model,  
JESD22−C101  
1
kV  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
All voltage values are with respect to the GND pin.  
THERMAL CHARACTERISTICS  
Symbol  
Rθ  
Rating  
Value  
Unit  
Junction−to−Ambient Thermal Characteristics  
115  
°C/W  
JA  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min.  
0
Max.  
18  
Unit  
V
DD  
VDD Pin Supply Voltage to GND  
5VB Pin Voltage  
V
V
V
5VB  
0
5
V
INS  
Signal Input Voltage  
0
5
V
T
J
Operating Junction Temperature  
−40  
+125  
°C  
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond  
the Recommended Operating Ranges limits may affect device reliability.  
Allowable operating ambient temperature can be limited by the power dissipation of NCP4390.  
www.onsemi.com  
4
NCP4390  
ELECTRICAL CHARACTERISTICS (V = 12 V, C  
= 33 nF and T = −40°C to 125°C unless otherwise specified)  
DD  
5VB  
J
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
SUPPLY VOLTAGE (VDD PIN)  
I
Startup Supply Current  
Operating Current  
V
V
= 9 V  
80  
2.8  
10  
115  
mA  
mA  
mA  
STARTUP  
DD  
I
= 0.1 V, V = 3 V, V = 0 V  
FB SS  
DD  
COMP  
I
I
Dynamic Operating Current  
f
= 100 kHz; C = 1 nF, with PR  
DD_DYM1  
SW L  
Operation Only  
Dynamic Operating Current  
f
= 100 kHz; C = 1 nF, with PR &  
13  
mA  
DD_DYM2  
SW  
L
SR Operation  
V
VDD ON Voltage (VDD Rising)  
9
10  
11  
V
V
DD.ON  
V
VDD OFF Voltage  
(VDD Falling)  
8.6  
DD.OFF  
V
UVLO Hysteresis  
0.9  
1.4  
1.9  
V
DD.HYS  
REFERENCE VOLTAGE  
5 V Reference  
V
4.99  
4.90  
5.05  
5.05  
5.11  
5.20  
V
V
T = 25°C  
5VB  
J
−40°C < T < 125°C  
J
ERROR AMPLIFIER (COMP PIN)  
V
Voltage Feedback Reference  
2.37  
2.34  
2.40  
2.40  
300  
2.43  
2.46  
T = 25°C  
V
V
SS.CLMP  
J
−40°C < T < 125°C  
J
gm  
Error Amplifier Gain  
Transconductance  
mmho  
I
Error Amplifier Maximum  
Output Current (Sourcing)  
V
FB  
V
FB  
V
FB  
= 1.8 V, VCOMP = 2.5 V  
= 3.0 V, VCOMP = 2.5 V  
= 1.8 V  
65  
65  
90  
90  
115  
115  
4.6  
mA  
mA  
V
COMP1  
I
Error Amplifier Maximum  
Output Current (Sinking)  
COMP2  
V
Error Amplifier Output High  
Clamping Voltage  
4.2  
4.4  
COMP.CLMP1  
V
V
Internal Clamping  
RPWM = 130 k  
RPWM = 82 k  
RPWM = 82 k  
1.26  
1.4  
1.41  
1.6  
1.56  
1.8  
V
V
V
V
COMP.PWM  
COMP  
Voltage for PWM Operation  
V
PWMS  
PWMS Pin Voltage  
1.9  
2.0  
2.1  
V
VCOMP Threshold for Entering  
Skip Cycle Operation  
1.15  
1.25  
1.35  
COMP.SKP  
V
VCOMP Threshold Hysteresis  
for Entering Skip Cycle  
Operation  
50  
mV  
COMP.SKP.HYS  
DEAD TIME (DT PIN)  
I
Dead−Time Programming  
V
RDT  
= 1.2 V  
140  
0.9  
2.8  
1.2  
150  
1.0  
3.0  
1.4  
160  
1.1  
3.2  
1.6  
mA  
V
DT  
Current  
V
V
First Threshold for Dead−Time  
Detection  
THDT1  
Second Threshold for  
Dead−Time Detection  
V
THDT2  
V
V
Voltage  
V
RDT.ON  
RDT ON  
(VRDT Rising)  
SOFT−START (SS PIN)  
I
Total Soft−Start Current  
V
V
= 1 V  
= 3 V  
32  
40  
52  
mA  
SS.T  
SS  
(Including I  
)
SS.UP  
V
Overload Protection Threshold  
3.45  
8.2  
3.60  
10.5  
3.75  
12.8  
V
OLP  
I
Soft−Start Capacitor Charge  
Current for Delayed Shutdown  
mA  
SS.UP  
SS  
www.onsemi.com  
5
NCP4390  
ELECTRICAL CHARACTERISTICS (V = 12 V, C  
= 33 nF and T = −40°C to 125°C unless otherwise specified)  
DD  
5VB  
J
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
SOFT−START (SS PIN)  
I
Soft−Start Capacitor Discharge  
V
SS  
= 3 V  
8.2  
4.5  
10.5  
4.7  
12.8  
4.9  
mA  
V
SS.DN  
Current  
V
SS Capacitor Maximum  
Charging Voltage  
SS.MAX  
V
SS Capacitor Initialization  
Voltage  
0.01  
0.10  
0.20  
V
SS.INIT  
FEEDBACK (FB PIN)  
V
VFB Threshold for Entering  
Skip Cycle Operation  
V
V
V
= 3 V  
= 3 V  
2.53  
2.18  
1.0  
2.65  
2.30  
1.2  
2.77  
2.42  
1.4  
V
V
V
FB.OVP1  
FB.OVP2  
ERR.OSP  
COMP  
V
VFB Threshold for Exiting Skip  
Cycle Operation  
COMP  
V
Error Voltage to Enable Output  
Short Protection (OSP)  
= 2.4 V  
SS  
OSCILLATOR  
V
FMIN Pin Voltage  
R
R
= 10 kW,  
1.4  
95  
1.5  
1.6  
V
FMIN  
OSC  
FIMN  
f
PROUT Switching Frequency  
= 10 kW, V = 1 V  
= 4.0 V, V  
100  
105  
kHz  
MINF  
CS  
ICS  
V
= 0 V  
COMP  
f
Minimum PROUT Switching  
Frequency (40 MHz/1024)  
R
COMP  
= 40 kW, V = 1 V  
36  
39  
690  
50  
42  
kHz  
kHz  
%
OSC.min  
MINF  
CS  
V
= 4.0 V, V  
= 0 V  
ICS  
f
Maximum PROUT Switching  
Frequency (40 MHz/58)  
R
= 2 kW, V = 1 V  
635  
735  
OSC.max  
MINF  
CS  
ICS  
V
COMP  
= 2.0 V, V  
= 0 V  
D
PROUT Duty Cycle in PFM  
Mode  
R
= 20 kW, V = 1 V  
MINF  
CS  
V
COMP  
= 4.0 V  
INTEGRATED CURRENT SENSING (ICS PIN)  
V
ICS Pin Signal Clamping Voltage  
ICS Pin Clamping MOSFET  
I
I
= 400 mA  
10  
20  
50  
mV  
ICS.CLMP  
CS  
R
= 1.5 mA  
W
.
CS  
DS−ON ICS  
R
DS−ON  
V
SR_SHRNK Enable Threshold  
SR_SHRNK Disable Hysteresis  
SR_SKIP Disable Threshold  
SR_SKIP Enable Threshold  
V
COMP  
V
COMP  
V
COMP  
V
COMP  
V
COMP  
= 2.4 V  
0.15  
0.20  
50  
0.25  
V
mV  
V
TH1  
V
= 2.4 V  
= 2.4 V  
= 2.4 V  
= 2.4 V  
TH1.HYS  
V
V
0.10  
0.025  
1.12  
0.15  
0.075  
1.20  
0.20  
0.125  
1.28  
TH2  
V
TH3  
V
OCL1  
Over−Current Limit First  
Threshold  
V
V
Over−Current Limit Second  
V
V
= 2.4 V  
= 2.4 V  
1.34  
1.34  
1.45  
1.45  
1.56  
1.56  
V
V
OCL2  
COMP  
Threshold  
V
V
Over-Current Limit First  
Threshold in Deep Below  
Resonance Operation  
OCL1.BR  
COMP  
Over−Current Limit Second  
Threshold in Deep Below  
Resonance Operation  
V
COMP  
= 2.4 V  
1.59  
1.70  
1.81  
V
OCL2.BR  
V
Over−Current Protection  
V
V
= 2.4 V  
= 2.4 V  
1.77  
2.02  
1.90  
2.15  
150  
2.03  
2.28  
V
V
OCP1  
COMP  
Threshold  
V
Over−Current Protection  
Threshold  
OCP1.BR  
COMP  
T
Debounce Time for Over−Current  
Protection 1  
ns  
OCP1.DLY  
www.onsemi.com  
6
NCP4390  
ELECTRICAL CHARACTERISTICS (V = 12 V, C  
= 33 nF and T = −40°C to 125°C unless otherwise specified)  
DD  
5VB  
J
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
CURRENT SENSING (CS PIN)  
V
Over−Current Protection  
3.3  
3.5  
150  
−3.5  
0.30  
3.0  
3.7  
V
ns  
V
OCP2P  
Threshold  
T
Debounce Time for Over−Current  
Protection 2  
OCP2.DLY  
V
Over−Current Protection  
Threshold  
−4.0  
0.24  
2.7  
−3.0  
0.36  
3.3  
OCP2N  
V
CS Signal Threshold for Non-ZVS  
Detection  
V
= 3.5 V  
COMP  
V
CS.NZVS  
V
COMP Threshold for Non-ZVS  
Detection  
V
CS  
= 0.1 V  
V
COMP.NZVS  
GATE DRIVE (PROUT1 AND PROUT2)  
I
PROUT Sinking Current  
PROUT Sourcing Current  
Rise Time  
V
V
V
V
& V  
& V  
= 6 V  
= 6 V  
140  
150  
100  
85  
mA  
mA  
ns  
SINK  
PROUT1  
PROUT2  
I
SOURCE  
PROUT1  
PROUT2  
t
= 12 V, C = 1 nF, 10% to 90%  
L
PR.RISE  
PR.FALL  
DD  
DD  
t
Fall Time  
= 12 V, C = 1 nF, 90% to 10%  
ns  
L
SYNCHRONOUS RECTIFICATION (SR) CONTROL  
TRC_SRCD  
(Note 1)  
Internal RC Time Constant SR  
Conduction Detection  
50  
100  
0.25  
0.20  
150  
0.35  
0.30  
0.6  
ns  
V
VSRCD.OFFSET1  
(Note 1)  
Internal Comparator Offset Rising  
Edge Detection  
0.15  
0.10  
0.4  
VSRCD.OFFSET2  
(Note 1)  
Internal Comparator Offset  
Falling Edge Detection  
V
V
SR Conduction Detect threshold  
0.5  
65  
V
SRCD.LOW  
DLY.CMP.SR  
T
SR Conduction Detect  
Comparator Delay  
ns  
V
SR Enable FB Voltage  
SR Disable FB Voltage  
1.6  
1.0  
1.8  
1.2  
2.0  
1.4  
V
V
.
.
FB SR ON  
V
.
.
FB SR OFF  
SR OUTPUT (SROUT1 AND SROUT2)  
PROUT Sinking Current  
V
V
V
V
& V  
& V  
= 6 V  
= 6 V  
140  
150  
100  
85  
mA  
mA  
ns  
I
SROUT1  
SROUT2  
SR.SINK  
PROUT Sourcing Current  
Rise Time  
I
SROUT1  
SROUT2  
SR.SOURCE  
= 12 V, C = 1 nF, 10% to 90%  
t
DD  
DD  
L
SR.RISE  
Fall Time  
=12 V, C = 1 nF, 90% to 10%  
ns  
t
L
SR.FALL  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. These parameters, although guaranteed by design, are not production tested.  
www.onsemi.com  
7
 
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 3. V5VB vs. Temperature  
Figure 4. IDT vs. Temperature  
Figure 5. VFMIN vs. Temperature  
Figure 6. fOSC vs. Temperature  
Figure 7. fOSC.MIN vs. Temperature  
Figure 8. fOSC.MAX vs. Temperature  
www.onsemi.com  
8
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 9. DUTY CYCLE vs. Temperature  
Figure 10. VRDT.OFF vs. Temperature  
Figure 11. VSS.CLMP vs. Temperature  
Figure 12. ISTARTUP vs. Temperature  
Figure 13. IDD vs. Temperature  
Figure 14. IDD_DYM1 vs. Temperature  
www.onsemi.com  
9
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 15. IDD_DYM2 vs. Temperature  
Figure 16. VDD.ON vs. Temperature  
Figure 18. VDD.HYS vs. Temperature  
Figure 17. VDD.OFF vs. Temperature  
Figure 19. gm vs. Temperature  
Figure 20. ICOMP1 vs. Temperature  
www.onsemi.com  
10  
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 21. ICOMP2 vs. Temperature  
Figure 22. VCOMP.CLMP1 vs. Temperature  
Figure 23. VCOMP.PWM vs. Temperature  
Figure 24. VCOMP.SKIP vs. Temperature  
Figure 25. VCOMP.SKIP.HYS vs. Temperature  
Figure 26. VRDT.ON vs. Temperature  
www.onsemi.com  
11  
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 27. VTHDT1 vs. Temperature  
Figure 28. VTHDT2 vs. Temperature  
Figure 30. VOLP vs. Temperature  
Figure 32. VSS.MAX vs. Temperature  
Figure 29. ISS.T vs. Temperature  
Figure 31. ISS.UP vs. Temperature  
www.onsemi.com  
12  
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 33. ISS.DN vs. Temperature  
Figure 34. VSS.INIT vs. Temperature  
Figure 36. VFB.OVP1 vs. Temperature  
Figure 38. VERR.OSP vs. Temperature  
Figure 35. VPWMS vs. Temperature  
Figure 37. VFB.OVP1 vs. Temperature  
www.onsemi.com  
13  
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 39. RDS−ON.ICS vs. Temperature  
Figure 40. VTH1 vs. Temperature  
Figure 41. VTH1 vs. Temperature  
Figure 42. VTH3 vs. Temperature  
Figure 43. VOCL1 vs. Temperature  
Figure 44. VOCL2 vs. Temperature  
www.onsemi.com  
14  
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 45. VOCL1.BR vs. Temperature  
Figure 46. VOCL2.BR vs. Temperature  
Figure 47. VOCP1 vs. Temperature  
Figure 48. VOCP1.BR vs. Temperature  
Figure 49. VOCP2P vs. Temperature  
Figure 50. VOCP2N vs. Temperature  
www.onsemi.com  
15  
NCP4390  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 51. VCS.NZVS vs. Temperature  
Figure 52. VCOMP.NZVS vs. Temperature  
www.onsemi.com  
16  
NCP4390  
APPLICATION INFORMATION  
Operation Principle of Charge Current Control  
current flowing out of the FMIN pin. The FMIN pin voltage  
is regulated at 1.5 V.  
The LLC resonant converter has been widely used for  
many applications because it can regulate the output over  
entire load variations with a relatively small variation of  
switching frequency, and achieve Zero Voltage Switching  
(ZVS) for the primary side switches and Zero Current  
Switching (ZCS) for the secondary side rectifiers over the  
entire operating range. In addition, the resonant inductance  
can be integrated with the transformer into a single magnetic  
component. Figure 53 shows the simplified schematic of the  
LLC resonant converter where voltage mode control is  
employed. Voltage mode control is typically used for the  
LLC resonant converter where the error amplifier output  
voltage directly controls the switching frequency. However,  
the compensation network design of the LLC resonant  
converter is relatively challenging since the frequency  
response with voltage mode control includes four poles  
where the location of the poles changes with input voltage  
and load variations.  
Q1  
VIN  
VO  
CO  
Cr  
Lr  
Q2  
L
VCO  
VC  
VO.REF  
+
Vc  
Driver  
−
Figure 53. LLC Resonant Converter with Voltage  
Mode Control  
NCP4390 employs charge current mode control to  
improve the dynamic response of the LLC resonant  
converter. Figure 54 shows the simplified schematic of a  
half−bridge LLC resonant converter using NCP4390, where  
Lm is the magnetizing inductance, Lr is the resonant  
inductor and Cr is the resonant capacitor. Typical key  
waveforms of the LLC resonant converter for heavy load  
and light load conditions are illustrated in Figure 55 and  
Figure 56, respectively. It is assumed that the operation  
frequency is same as the resonance frequency, as determined  
by the resonance between Lr and Cr. Since the primary−side  
switch current does not increase monotonically, the switch  
VIN  
Q1  
PROUT1  
PROUT2  
Cr  
Lr  
VO  
Q2  
Lm  
Current  
sensing  
ICS  
3/4  
Integrated signal (VICS  
)
VSAW  
Reset  
VREF  
+
−
VCT  
CT  
Digital  
OSC  
1.5V  
1V  
PROUT1  
PROUT2  
+
+
current  
itself  
cannot  
be  
used  
for  
−
−
3V  
pulse−frequency−modulation (PFM) for the output voltage  
regulation. Also, the peak value of the primary−side current  
does not reflect the load condition properly because the large  
circulating current (magnetizing current) is included in the  
primary−side switch current. However, the integral of the  
FMIN  
SS  
VCOMP.I  
PWM  
VCOMP.I  
VSAW  
control  
1V  
U1  
COMP  
Cutback  
2.4V  
PROUT1  
VCOMP  
COMP  
PROUT2  
switch current (V ) does increase monotonically and has  
ICS  
PWMS  
FB  
a peak value similar to that used for peak current mode  
control, as shown in Figure 55 and Figure 56.  
Thus, NCP4390 employs charge current control, which  
compares the total charge of the switch current (integral of  
switch current) to the control voltage to modulate the  
switching frequency. Since the charge of the switch current  
is proportional to the average input current over one  
switching cycle, charge control provides a fast inner loop  
and offers excellent transient response including inherent  
line feed−forward. The PFM block has an internal timing  
capacitor (CT) whose charging current is determined by the  
Figure 54. Schematic of LLC resonant Converter  
Power Stage Schematic  
There is an upper limit (3 V) for the timing capacitor  
voltage, which determines the minimum switching  
frequency for a given resistor connected to the FMIN pin.  
The sawtooth waveform (V ) is generated by adding the  
SAW  
integral of the Q1 switch current (V ) and the timing  
ICS  
www.onsemi.com  
17  
 
NCP4390  
capacitor voltage (V ) of the oscillator. The sawtooth  
waveform (Vsaw) is then compared with the compensation  
To improve the light load efficiency, NCP4390 employs  
hybrid control where the PFM is switched to pulse width  
modulation (PWM) mode at light load as illustrated in  
Figure 57. If want to not uses PWM mode in light load  
condition, adjust PWM entry level using external PWM  
resistor for under skip threshold level. The figure 58 show  
that the switching frequency and duty ratio characteristics in  
disable PWM mode. The typical waveforms for PFM mode  
and PWM mode are shown in Figure 59 and Figure 60,  
respectively. When the error amplifier voltage (VCOMP) is  
below the PWM mode threshold, the internal COMP signal  
is clamped at the threshold level and the PFM operation  
switches to PWM mode.  
CT  
voltage (V ) to determine the switching frequency.  
COMP  
Ip  
Im  
ID  
IDS1  
Switching  
frequency  
Duty cycle  
PFM Mode  
PWM Mode  
Skip cycle  
D=50%  
No  
switching  
V
ICS =  
k ∫ I  
dt  
DS1  
VCOMP  
4.4V  
1.3V  
1.25V  
VCOMP.PWM  
Figure 55. Typical Waveforms of the LLC  
Resonant Converter for Heavy Load Condition  
Figure 57. Mode Change with COMP Voltage  
Duty cycle  
Switching  
Ip  
frequency  
Skip cycle  
PFM Mode  
D=50%  
Im  
No  
switching  
ID  
VCOMP.PWM = Less than 1.25 V  
( Disable PWM mode )  
VCOMP  
4.4V  
1.3V  
1.25V  
Figure 58. Disable PWM mode with COMP Voltage  
IDS1  
Ip  
Im  
VICS  
VCT  
V
ICS =  
k ∫ I  
dt  
DS1  
VCOMP  
Figure 56. Typical Waveforms of LLC Resonant  
3/4*VICS+VCT  
Converter for Light−Load Condition  
Counter of  
Hybrid Control (PWM + PFM)  
The conventional PFM control method modulates only  
the switching frequency with a fixed duty cycle of 50%,  
which typically results in relatively poor light load  
efficiency due to the large circulating primary side current.  
PROUT1  
PROUT2  
Figure 59. Key Waveforms of PFM Operation  
www.onsemi.com  
18  
 
NCP4390  
Ip  
VCTX  
VICS  
Q1  
VICS  
VCT  
PROUT1  
RICS  
PROUT1  
VICS  
PROUT1  
Current  
transformer  
VCOMP.PWM −V  
COMP  
ICS  
VICS  
+
+
VSENSE  
CICS  
VCOMP.PWM −V  
COMP  
VTH.PWM  
3/4*VICS+VCT  
VCOMP  
−
−
PROUT1  
Q2  
RCS2  
Counter of  
digital OSC  
CS  
VCS  
PROUT2  
Main  
RCS1  
transformer  
PROUT1 PROUT2  
Primary  
winding  
Figure 60. Key Waveforms of PWM Operation  
Figure 61. Current Sensing of NCP4390  
In PWM mode, the switching frequency is fixed by the  
clamped internal COMP voltage (VCOMPI) and the duty  
cycle is determined by the difference between COMP  
voltage and the PWM mode threshold voltage. Thus, the  
duty cycle decreases as VCOMP drops below the PWM  
mode threshold, which limits the switching frequency at  
light load condition as illustrated in Figure 57. The PWM  
mode threshold can be programmed between 1.9 V and  
under skip threshold using a resistor on the PWMS pin.  
Disable PWM mode when the PWM mode threshold is set  
below 1.25 V.  
1
0.8  
0.6  
0.4  
0.2  
0
∫ V  
CTX  
dt  
VICS  
4
3
2
1
VCTX  
0
−1  
−2  
−3  
−4  
Current Sensing  
NCP4390 senses instantaneous switch current and the  
integral of the switch current as illustrated in Figure 61.  
Since NCP4390 is located in the secondary side, it is typical  
to use a current transformer for sensing the primary side  
current. While the PROUT1 is LOW, the ICS pin is clamped  
at 0 V with an internal reset MOSFET. Conversely, while  
PROUT1 is high, the ICS pin is not clamped and the integral  
Figure 62. Disable PWM mode with COMP Voltage  
Since the peak value of the integral of the current sensing  
voltage (VICS) is proportional to the average input current  
of the LLC resonant converter, it is used for four main  
functions, listed and shown in Figure 63.  
1. SR Gate Shrink: To guarantee stable SR operation  
during light load operation, the SR dead time (both  
of turn−on and turn−off transitions) is increased  
capacitor (C ) is charged and discharged by the voltage  
ICS  
difference between the sensing resistor voltage (V  
)
SENSE  
and the ICS pin voltage. During normal operation, the  
voltage of the ICS pin is below 1.2 V since the power limit  
threshold is 1.2 V. The current sensing resistor and current  
transformer turns ratio should be designed such that the  
resulting in SR gate shrink when V peak value  
ICS  
drops below V  
(0.2 V). The SR dead time is  
TH1  
reduced to the programmed value when V peak  
ICS  
value rises above 0.25 V  
voltage across the current sensing resistor (V  
) is  
SENSE  
2. SR Disable and Enable: During very light−load  
greater than 4 V at the full load condition. Therefore the  
current charging and discharging C should be almost  
condition, the SR is disabled when the V peak  
ICS  
ICS  
value is smaller than V  
(0.075 V). When the  
proportional to the voltage across the current sensing  
resistor (V ). Figure 62 compares the VICS signal and  
TH3  
V
ICS  
peak value increases above V  
(0.15 V),  
TH2  
SENSE  
the SR is enabled  
the ideal integral signal when the amplitude of V  
is  
SENSE  
4 V. As can be seen, there is about 10% error in the VICS  
signal compared to the ideal integral signal, which is  
acceptable for most designs. If more accuracy of the VICS  
is required, the amplitude of V  
should be increased.  
SENSE  
www.onsemi.com  
19  
 
NCP4390  
3. Over−Current Limit: The V peak value is also  
ICS  
IPR  
used for input current limit. As can be seen in  
Figure 64, there exist two different current limits  
(fast and slow). When the V peak value  
increases above the slow current limit level  
ICS  
PROUT1  
VOCP1  
(V  
) due to a mild overload condition, the  
VOCL2  
VOCL1  
OCL1  
internal feedback compensation voltage is slowly  
reduced to limit the input power. This continues  
until the V peak value drops below V  
.
ICS  
OCL1  
(a) Mild Overload Condition  
During a more severe over load condition, the  
peak value crosses the fast current limit  
V
ICS  
IPR  
threshold (V  
) and the internal feedback  
OCL2  
compensation voltage is quickly reduced to limit  
the input power as shown in Figure 64 (b). This  
continues until the V peak value drops below  
ICS  
PROUT1  
V
OCL2  
. The current limit threshold on the V  
ICS  
V
OCP1  
peak value also changes as the output voltage  
VOCL2  
VOCL1  
sensing signal (V ) decreases such that output  
FB  
current is limited during overload condition as  
shown in Figure65. In addition, these limit  
(b) Severe Overload Condition  
thresholds change to higher values (V  
and  
OCL1.BR  
Figure 64. Current Limit of the ICS Pin by  
Frequency Shift (Compensation Cutback)  
V
) when the converter operates in deep  
OCL2.BR  
below resonance operation for a longer holdup  
time (refer to holdup time boost function)  
4. Over−Current Protection (OCP1): When the V  
ICS  
peak value is larger than V  
(1.9 V), the over  
OCP1  
VOCL2  
VOCL1  
1.45V  
1.2V  
current protection is triggered. 150 ns debounce  
time is added for over−current protection. These  
OCP threshold can be changed to a higher value  
1.0V  
0.75V  
0.5V  
(V  
) when the converter operates in deep  
OCP1.BR  
below resonance operation for a longer holdup  
time (refer to holdup time boost function)  
Output Power  
VFB  
2.4 V  
2.0 V  
Fast Current limit  
Slow Current limit  
Figure 65. Current Limit Threshold Modulation as  
a Function of Feedback Voltage  
SR Shrink  
SR Enable  
SR Disable  
PK  
50mV  
VICS  
1.2V 1.45V  
0.075V  
0.15V  
0.2V  
VICS  
Figure 63. Functions Related to VICS Peak Voltage  
www.onsemi.com  
20  
 
NCP4390  
The instantaneous switch current sensing on the CS pin is  
also used for the following functions.  
Compensation  
Voltage  
COMP  
+
−
3V  
1. Non−ZVS Prevention: When the compensation  
0.3V  
+
Q
D
−
voltage (V  
) is higher than 3 V and V peak  
COMP  
CS  
NON ZVS  
detect  
PFM block  
QN  
PROUT1  
value is smaller than 0.3 V at PROUT1 falling  
edge, non−ZVS condition is detected, which  
decreases the internal compensation signal to  
increase the switching frequency  
+
− 3.5V  
−
Compensation  
Cutback  
OCP2  
CS  
+
OCP  
−
3.5V  
1.9V  
ICS  
+
2. Over−Current Protection (OCP2): When V is  
CS  
−
OCP1  
D
higher than 3.5 V or lower than −3.5 V,  
0.25V /  
0.20V  
+
SR Shrink  
SR Skip  
Q
over−current protection (OCP2) is triggered. The  
instantaneous primary side current is also sensed  
on CS pin. Since the OCP2 thresholds on the CS  
pin are 3.5 V and −3.5 V as shown in Figure 66,  
−
QN  
PROUT1  
0.15V /  
0.075V  
+
Q
D
−
QN  
PROUT1  
the CS signal is typically obtained from V  
by using a voltage divider as illustrated in  
Figure 61. 150 ns debounce time is also added for  
OCP2  
+
SENSE  
Q
D
D
−
OCL1  
Compensation  
Cutback  
QN  
PROUT1  
+
Q
OCL2  
−
QN  
PROUT1  
Figure 67 shows utilization of current sensing by using  
ICS and CS signals.  
Figure 67. Utilization of Current Sensing Signal  
VOCP2P  
(3.5)V  
VCS  
VOCP2N  
(−3.5V)  
PROUT1  
PROUT2  
VOCP2P  
(3.5)V  
VCS  
VOCP2N  
(−3.5V)  
PROUT1  
PROUT2  
Figure 66. Over−Current Protection of the CS Pin  
www.onsemi.com  
21  
 
NCP4390  
VSS  
Soft−Start and Output Voltage Regulation  
4.8V  
3.6V  
Figure 68 shows the simplified circuit block for feedback  
control and closed loop soft−start. During normal, steady  
state operation, the Soft−Start (SS) pin is connected to the  
non−inverting input of the error amplifier which is clamped  
at 2.4 V. The feedback loop operates such that the sensed  
output voltage is same as the SS pin voltage. During startup,  
2.4V  
time  
time  
Ip  
an internal current source (I  
) charges the SS capacitor  
SS.T  
and SS pin voltage progressively increases. Therefore, the  
output voltage also rises monotonically as a result of closed  
loop SS control.  
The SS capacitor is also used for the shutdown delay time  
during overload protection (OLP). Figure 69 shows the OLP  
waveform. During normal operation, the SS capacitor  
voltage is clamped at 2.4 V. When the output is over−loaded,  
Figure 69. Delayed Shutdown with Soft−Start  
Auto−Restart after Protection  
All protections of NCP4390 are non−latching,  
auto−restart, where the delayed restart is implemented by  
charging and discharging the SS capacitor as illustrated in  
Figure 70. During normal operation, the SS capacitor  
voltage is clamped at 2.4 V. Once any protection is triggered,  
the SS clamping circuit is disabled. The SS capacitor is then  
V
COMP  
is saturated to HIGH and the SS capacitor is  
decoupled from the clamping circuit through the SS control  
block. I is blocked by D and the SS capacitor is  
SS  
BLCK  
slowly charged up by the current source I . When the SS  
SS.UP  
capacitor voltage reaches 3.6 V, OLP is triggered. The time  
required for the soft−start capacitor to be charged from 2.4 V  
to 3.6 V determines the shutdown delay time for overload  
protection.  
charged up to 4.7 V by an internal current source (I  
).  
SS.UP  
The SS capacitor is then discharged down to 0.1 V by  
another internal current (I ). After charging and  
SS.DN  
discharging the SS capacitor three more times, auto recovery  
is enabled.  
VIN  
Q1  
Discharged by ISS.DN  
VSS  
Cr  
Lr  
1/8 time scale  
Charged by ISS.UP  
4.7V  
3.6V  
Q2  
VO  
2.4V  
Charged by ISS.T  
Lm  
0.1V  
Shutdown  
delay  
time  
Ip  
time  
PROUT2  
PROUT1  
ICS  
1.2V  
PFM  
UP  
DN  
SS  
Control  
time  
time  
VCOMP  
ISS  
ISS.UP  
10 mA  
Disable SS  
30 mA  
SS  
clamp  
Figure 70. Auto Re−Start after Protection is  
ISS.DN  
2.4V  
Triggered  
DBLCK  
10 mA  
COMP  
FB  
Figure 68. Schematic of Closed Loop Soft−Start  
www.onsemi.com  
22  
 
NCP4390  
5VB  
Output Short Protection  
To minimize the power dissipation through the power  
stage during a severe fault condition, NCP4390 offers  
Output Short Protection (OSP). When the output is heavily  
over−loaded or short circuited, the feedback voltage (output  
voltage sensing) does not follow the reference voltage of the  
error amplifier (2.4 V). When the difference between the  
reference voltage of the error amplifier and the FB voltage  
is larger than 1.2 V, the OSP is triggered without waiting  
until the OLP is triggered as shown in Figure 71.  
RDT  
VRDT  
IDT  
S1  
CDT  
Figure 72. Internal Current Source for of RDT Pin  
Dead−Time Setting  
With a single pin (RDT pin), the dead times between the  
primary side gate drive signals (PROUT1 and PROUT2)  
and secondary side SR gate drive signal (SROUT1 and  
SROUT2) are programmed using a switched current source  
as shown in Figure 72 and Figure 73. Once the 5 V bias is  
enabled, the RDT pin voltage is pulled up. When the RDT  
TSET1 / 64= SROUT Dead Time  
T
SET2 / 32 =PROUT Dead Time  
5V  
4V  
3V  
2V  
1V  
pin voltage reaches 1.4 V, the voltage across C is then  
DT  
discharged down to 1 V by an internal current source I  
.
DT  
I
is then disabled and the RDT pin voltage is charged up  
DT  
TSET1  
TSET2  
by the RDT resistor. As shown in Figure 73, 1/64 of the time  
required (T ) for RDT pin voltage to rise from 1 V to 3 V  
Figure 73. Multi−function Operation of RDT Pin  
SET1  
determines the dead time between the secondary side SR  
gate drive signals.  
The minimum and maximum dead times are therefore  
limited at 75 ns and 375 ns respectively. To assure stable SR  
operation while taking circuit parameter tolerance into  
account, 75 ns dead time is not recommended especially for  
the SR dead time.  
When NCP4390 operates in PWM mode at light−load  
condition, the dead time is doubled to reduce the switching  
loss.  
The switched current source I is then enabled and the  
DT  
RDT pin voltage is discharged. 1/32 of the time required  
(T  
) for the RDT pin voltage to drop from 3 V to 1 V  
SET2  
determines the dead time between the primary side gate  
drive signals. After the RDT voltage drops to 1 V, the current  
source I is disabled a second time, allowing the RDT  
DT  
voltage to be charged up to 5 V.  
Table 1 shows the dead times for SROUT and PROUT  
programmed with recommended RDT and CDT component  
values. Since the time is measured by an internal 40 MHz  
clock signal, the resolution of the dead time setting is 25 ns.  
4.8V  
3.6V  
2.4V  
VSS  
1.2V  
VFB  
Ip  
time  
VICS  
1.2V  
0.0V  
time  
Figure 71. Output Short Protection  
www.onsemi.com  
23  
 
NCP4390  
Table 1. DEAD TIME SETTING FOR PROUT AND SROUT  
C
DT  
= 180 pF  
C
DT  
= 220 pF  
C
DT  
= 270pF  
C
DT  
= 330 pF  
C
DT  
= 390 pF  
C
DT  
= 470 pF  
C
DT  
= 560 pF  
SROUT PROUT SROUT PROUT SROUT PROUT SROUT PROUT SROUT PROUT SROUT PROUT SROUT PROUT  
DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns) DT (ns)  
R
DT  
28 k  
30 k  
33 k  
36 k  
40 k  
44 k  
48 k  
53 k  
58 k  
64 k  
71 k  
78 k  
86 k  
94 k  
104 k  
114 k  
126 k  
138 k  
152 k  
75  
75  
375  
250  
200  
175  
150  
125  
125  
100  
100  
100  
100  
100  
75  
75  
375  
325  
250  
200  
175  
150  
150  
125  
125  
125  
125  
100  
100  
100  
100  
100  
100  
100  
100  
75  
375  
375  
300  
250  
225  
200  
175  
175  
150  
150  
150  
150  
125  
125  
125  
125  
125  
125  
125  
100  
100  
125  
125  
150  
150  
175  
200  
200  
225  
250  
275  
300  
325  
375  
375  
375  
375  
375  
375  
375  
375  
325  
275  
250  
225  
200  
200  
200  
175  
175  
175  
175  
150  
150  
150  
150  
150  
125  
125  
150  
150  
175  
175  
200  
225  
250  
275  
300  
325  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
325  
300  
275  
250  
250  
225  
225  
200  
200  
200  
200  
175  
175  
175  
175  
150  
150  
175  
175  
200  
225  
250  
275  
300  
325  
350  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
350  
325  
300  
300  
275  
250  
250  
250  
225  
225  
225  
225  
225  
225  
175  
175  
200  
225  
250  
275  
300  
325  
350  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
375  
350  
325  
325  
300  
300  
275  
275  
275  
275  
250  
250  
75  
100  
100  
100  
125  
125  
150  
150  
175  
175  
200  
225  
250  
275  
300  
325  
375  
375  
375  
75  
75  
75  
75  
75  
100  
100  
125  
125  
150  
150  
175  
175  
200  
225  
250  
275  
300  
325  
350  
75  
100  
100  
125  
125  
150  
150  
175  
175  
200  
225  
250  
275  
300  
75  
75  
75  
75  
75  
75  
Minimum Frequency Setting  
The minimum switching frequency is limited by  
comparing the timing capacitor voltage (V ) with an  
frequency given by the digital oscillator is 39 kHz  
(40 MHz/1024 = 39 kHz). Therefore, the maximum  
allowable value for R  
is 25.5 KW.  
CT  
FMIN  
internal 3 V reference as shown in Figure 74. Since the rising  
slope of the timing capacitor voltage is determined by the  
PWM Mode Entry Level Setting  
When the COMP voltage drops below V  
as a  
COMP.PWM  
resistor (R ) connected to FMIN pin, the minimum  
FMIN  
result of decreasing load, the internal COMP signal is  
clamped at the threshold level and PFM operation switches  
to PWM Mode. The PWM entry level threshold is  
programmed using a external resistor on the PWMS pin as  
shown in Figure 75. Once NCP4390 enters into PWM mode,  
the SR gate drives are disabled. If want to uses specially  
disable PWM mode, open PWMS pin or connect to 1 MW.  
switching frequency is given as:  
10 kW  
RFMIN  
fSW .MIN + 100 kHz   
(eq. 1)  
The minimum programmable switching frequency is  
limited by the digital counter running on an internal 40 MHz  
clock. Since a 10 bit counter is used, the minimum switching  
www.onsemi.com  
24  
NCP4390  
Ip  
Skip Cycle Operation  
As illustrated in Figure 76, when the COMP voltage drops  
below V (1.25 V) as a result of decreasing load,  
COMP.SKIP  
skip cycle operation is employed to reduce switching losses.  
As the COMP voltage rises above 1.3 V, the switching  
operation is resumed. When the FB voltage rises above  
VCOMP  
V
(2.65 V), the skip cycle operation is also enabled  
FB.OVP1  
to limit the output voltage rising quickly. As the FB voltage  
VCOMP.SKIP  
drops below V  
resumed.  
(2.3 V), the switching operation is  
FB.OVP2  
50mV  
VCOMP  
Figure 76. Skip Cycle Operation  
VCOMP  
VSAW  
NCP4390 uses a dual edge tracking adaptive gate drive  
method that anticipates the SR current zero crossing instant  
with respect to two different time references. Figure 77 and  
Figure 78 show the operational waveforms of the dual edge  
tracking adaptive SR drive method operating below and  
above resonance. To simplify the explanation, the SR dead  
time is assumed to be zero. The first tracking circuit  
measures SR conduction time (TSR_CNDCTN) and uses  
this information to generate the first adaptive drive signal  
(VPRD_DRV1) for the next switching cycle whose duration  
is the same as the SR conduction time of previous switching  
cycle. The second tracking circuit measures the turn−off  
extension time which is defined as time duration from the  
falling edge of the primary side drive to the corresponding  
SR turn−off instant (TEXT). This information is then used  
to generate the second adaptive drive signal (VPRD_DRV2)  
for the next switching cycle. When the turn−off of the  
primary side drive signal is after the turn−off of the  
corresponding SR for below resonance operation, the  
second adaptive SR drive signal is the same as the  
corresponding primary side gate drive signal. However,  
when the turn−off of the primary side drive signal is before  
the turn−off instant of the corresponding SR for above  
resonance operation, the second adaptive SR drive signal is  
generated by extending the corresponding primary side gate  
drive signal by TEXT of the previous switching cycle.  
Since the turn off instant of the second adaptive gate drive  
1V  
3V  
3V  
VCT  
1V  
VCT  
1V  
PROUT1  
PROUT1  
PROUT1  
PROUT1  
PROUT2  
PROUT2  
(a) PFM by COM voltage  
(b) minimum Frequency limit  
ICS  
Integrated signal (VICS  
)
VSAW  
Reset  
VREF  
+
−
VCT  
1.5V  
+
Digital  
OSC  
PROUT1  
+
−
−
CT  
3V  
PROUT2  
VSAW  
Min Freq Comparator  
RFMIN  
VCOMP.I  
VCOMP.I  
FMIN  
1V  
PWM  
control  
1V  
U1  
COMP  
Cutback  
2.4V  
SS  
PROUT1  
VCOMP  
COMP  
PROUT2  
PWMS  
FB  
Figure 74. Minimum Switching Frequency Setting  
signal is extended by T  
with respect to the falling edge  
EXT  
of the primary side gate drive signal, the duration of this  
signal consequentially changes with switching frequency.  
By combining these two signals V  
and  
PRD_DRV1  
V
with an AND gate, the optimal adaptive gate  
PRD_DRV2  
drive signal is obtained.  
The SR conduction times for SR1 and SR2 for each  
switching cycle are measured using a single pin (SR1DS  
pin). The SR1DS voltage and its delayed signal, resulting  
Figure 75. PWM Mode Entry Level Setting  
www.onsemi.com  
25  
 
NCP4390  
SR2_OFF becomes HIGH  
if DV>0.2V  
from a 100 ns RC time constant, are compared as shown in  
SR1_OFF becomes HIGH  
if DV>0.25V  
Figure 79. When the SR is conducting, the SR1DS voltage  
is clamped to either ground or the high voltage rail (2 times  
the output voltage) as illustrated in Figure 80. Whereas,  
SR1DS voltage changes fast when there is a switching  
transition. When both of the SR MOSFETs are turned off,  
the SR1DS voltage oscillates. When the SR1DS voltage  
changes faster than 0.25 V/100 ns on the rising edge and  
0.2 V/100 ns on the falling edge the switching transition of  
the SR conduction state is detected. Based on the detected  
switching transition, NCP4390 predicts the SR current  
zero−crossing instant for the next switching cycle. The  
100 ns detection delay caused by the RC time constant is  
compensated in the internal timing detection circuit for a  
correct gate drive for SR.  
100ns  
DV  
VRC  
VSR1DS  
V
D
ISR2  
0.5V  
SR2  
100ns  
SR1_OFF  
SR2_OFF  
SR2_OFF  
0.5V  
ISR1  
SR1  
+
−
+
SR1_OFF  
SR2_OFF  
−
0.25V  
RDS2  
S
R
Q
Q
VSR1DS  
SR1DS  
VRC  
+
RC  
=100ns  
RDS1  
CDS  
−
IDS.PRI  
IDS.PRI  
0.2V  
Figure 79. SR Conduction Detection with Single  
Pin (SR1DS Pin)  
ISR  
ISR  
TSR_CNDCTN(n+1)  
VPROUT  
TSR_CNDCTN (n)  
Figure 80 and Figure 81 show the typical waveforms of  
SR1DS pin voltage together with other key waveforms.  
Since the voltage rating of SR1DS pin is 5 V, the voltage  
divider should be properly designed such that no  
over−voltage is applied to this pin. Additional bypass  
capacitor (CDS) can be connected to SR1DS pin to improve  
noise immunity. However, the equivalent time constant  
generated from the bypass capacitor and voltage divider  
resistors should be smaller than the internal RC time  
constant (100 ns) of the detection circuit for proper SR  
current zero crossing detection.  
VPROUT  
TSR_CNDCTN* (n−1)  
TSR_CNDCTN* (n)  
VPRD1(n+1)  
TEXT(n+1)  
TEXT* (n)  
TEXT(n)  
V
PRD1(n)  
VPRD2 (n)  
VPRD2 (n+1)  
Figure 77. Operation of Dual Edge Tracking  
Adaptive SR Control (below Resonance)  
IDS.PRI  
IDS.PRI  
VSR1.DS  
5V  
4V  
3V  
2V  
1V  
ISR  
ISR  
T
SR_CNDCTN(n+1)  
TSR_CNDCTN(n)  
VPROUT  
VPROUT  
ISR1  
ISR2  
Ip  
TEXT(n)  
TEXT(n+1)  
TSR_CNDCTN* (n)  
TSR_CNDCTN* (n−1)  
VPRD1 (n+1)  
VPRD1 (n)  
TEXT* (n)  
VPRD2  
V
PRD2 (n)  
Figure 78. Operation of Dual Edge Tracking  
Adaptive SR Control (above Resonance)  
Figure 80. SR Conduction Detection Waveform at  
below Resonance Operation  
www.onsemi.com  
26  
 
NCP4390  
VSR1DS  
5V  
resonance operation during the holdup time as shown in  
Figure 82. This holdup time boost operation is enabled when  
the SR conduction time is smaller than 94% of the half  
switching cycle for longer than 1.6 ms. The current limit  
level on ICS pin is recovered to normal value when the SR  
conduction time is larger than 98% of the half switching  
cycle for longer than 3.2 ms.  
4V  
3V  
2V  
1V  
ISR1  
I
1.7V  
VOCL2  
1.45V  
VOCL1  
1.2V  
Ip  
Ipr  
Figure 81. SR Conduction Detection Waveform at  
above Resonance Operation  
Holdup Time Boost Function  
The holdup time of an off−line supply is defined as the  
time required for the output voltage to remain within  
regulation after the AC input voltage is removed. Since the  
input bulk capacitor voltage drops during the holdup time,  
more current is taken from the bulk capacitor to deliver the  
same power to the load. With a fixed power limit level of  
power supply designed for nominal input voltage, the  
holdup time tends to be limited due to the increased input  
current of the power supply.  
SR c onduc tion time  
< 94%  
Half switc hing period  
SR c onduc tion time  
Half switc hing period  
NCP4390 has a holdup time boost function which  
increases the current limit threshold on the ICS pin voltage  
when the LLC resonant converter operates in deep below  
Figure 82. Holdup Time Boost Function Operation  
www.onsemi.com  
27  
 
NCP4390  
QUICK SETUP GUIDELINE for CURRENT SENSING and SOFT−START  
N
N
R
) R  
CS1 CS2  
Assuming the switching frequency is the same as the  
resonance frequency, the peak v of the secondary side  
S
P
1
CT  
1
1
2
PK  
V
+ I  
 
 
 
 
 
f
t 1.2 V  
SW  
ICS  
O
n
R
C
ICS  
ICS  
voltage of current transformer (V ) is given as:  
SENSE  
[example] Io = 20 A, N = 35, N = 2,  
n
= 50,  
CT  
P
S
NS  
NP  
R
= 30 W, R  
= 70 W, R = 10 kW, C = 1 nF,  
CS1  
CS2 ICS ICS  
PK  
p
2
1
VSENSE + IO  
 
 
 
  (RCS1 ) RCS2  
)
nCT  
f = 100 kHz.  
S
PK  
³ V  
= 1.14 V in nominal load condition (actual  
ICS  
PK  
[example] I = 20 A, N = 35, N = 2,  
n
CT  
= 50,  
V
is lower by about 10% as shown in Figure 62 due to  
O
P
S
ICS  
PK  
R
+ R  
= 100 W ³ V  
= 3.59 V in nominal  
a quasi integral effect).  
CS1  
CS2  
SENSE  
PK  
PKA  
load condition.  
Assuming the actual V  
(V  
) is 1 V, the  
ICS  
ICS  
The voltage divider on the CS pin should be selected such  
that OCP is not triggered during normal operation.  
soft−start capacitor should be selected such that the overload  
protection is not triggered during startup with full load  
condition.  
NS  
NP  
PK  
p
2
1
VCS + IO  
 
 
 
  RCS1 t 3.5 V  
nCT  
C
  2.4 V  
C
  V  
SS  
OUT  
O
T
+
+ 40.8 ms u  
+ 22.5 ms  
SS  
I
PK  
SS  
1.2*V  
ICS  
PK  
  I  
[example] I = 21 A, N = 35, N = 2,  
n
= 50,  
CT  
O
O
P
S
V
ICS  
PK  
R
= 30 W, R  
= 70 W ³ V  
= 1.131 V in nominal  
CS1  
CS2  
CS  
load condition.  
The resistor and capacitor on the ICS pin should be  
selected such that the current limit is not triggered during  
normal operation.  
VSENSE  
VICS  
Q1  
PROUT1  
PROUT1  
PROUT2  
PROUT1  
PROUT1  
Current  
transformer  
ICS  
analyzer  
RICS  
ICS  
Integrated signal (V  
)
ICS  
+
+
VICS  
VSAW  
+
VSENSE  
VREF  
CICS  
−
−
Digital  
OSC  
−
VCT  
1.5V  
+
+
1:nCT  
−
−
CT  
3V  
RCS2  
Primary  
side  
winding  
CS  
VCS  
RFMIN  
Q2  
VCOMP.I  
VCOMP.I  
FMIN  
RCS1  
1V  
U1  
NP  
PWM  
control  
+
PROUT2  
−
3.5V  
OCP  
2.4V  
SS  
COMP  
Cutback  
+
−3.5V  
Main  
transformer  
NS  
NS  
−
VCOMP  
VO  
COMP  
PWMS  
FB  
COUT  
Secondary Side winding  
Figure 83. Basic Application Circuit for Current Sensing and Soft−Start  
www.onsemi.com  
28  
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
SOIC−16  
CASE 751B−05  
ISSUE K  
DATE 29 DEC 2006  
SCALE 1:1  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
−A−  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD  
PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION  
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
16  
9
8
−B−  
P 8 PL  
M
S
B
0.25 (0.010)  
1
MILLIMETERS  
INCHES  
MIN  
0.386  
DIM MIN  
MAX  
MAX  
0.393  
0.157  
0.068  
0.019  
0.049  
A
B
C
D
F
9.80  
3.80  
1.35  
0.35  
0.40  
10.00  
G
4.00 0.150  
1.75 0.054  
0.49 0.014  
1.25 0.016  
F
R X 45  
K
_
G
J
1.27 BSC  
0.050 BSC  
0.19  
0.10  
0
0.25 0.008  
0.25 0.004  
0.009  
0.009  
7
K
M
P
R
C
7
0
_
_
_
_
−T−  
SEATING  
PLANE  
5.80  
0.25  
6.20 0.229  
0.50 0.010  
0.244  
0.019  
J
M
D
16 PL  
M
S
S
A
0.25 (0.010)  
T B  
STYLE 1:  
STYLE 2:  
STYLE 3:  
STYLE 4:  
PIN 1. COLLECTOR  
2. BASE  
3. EMITTER  
4. NO CONNECTION  
5. EMITTER  
6. BASE  
7. COLLECTOR  
8. COLLECTOR  
9. BASE  
10. EMITTER  
11. NO CONNECTION  
12. EMITTER  
13. BASE  
PIN 1. CATHODE  
2. ANODE  
3. NO CONNECTION  
4. CATHODE  
5. CATHODE  
6. NO CONNECTION  
7. ANODE  
8. CATHODE  
9. CATHODE  
10. ANODE  
11. NO CONNECTION  
12. CATHODE  
13. CATHODE  
14. NO CONNECTION  
15. ANODE  
PIN 1. COLLECTOR, DYE #1  
2. BASE, #1  
3. EMITTER, #1  
4. COLLECTOR, #1  
5. COLLECTOR, #2  
6. BASE, #2  
PIN 1. COLLECTOR, DYE #1  
2. COLLECTOR, #1  
3. COLLECTOR, #2  
4. COLLECTOR, #2  
5. COLLECTOR, #3  
6. COLLECTOR, #3  
7. COLLECTOR, #4  
8. COLLECTOR, #4  
9. BASE, #4  
10. EMITTER, #4  
11. BASE, #3  
12. EMITTER, #3  
13. BASE, #2  
7. EMITTER, #2  
8. COLLECTOR, #2  
9. COLLECTOR, #3  
10. BASE, #3  
11. EMITTER, #3  
12. COLLECTOR, #3  
13. COLLECTOR, #4  
14. BASE, #4  
SOLDERING FOOTPRINT  
14. COLLECTOR  
15. EMITTER  
16. COLLECTOR  
14. EMITTER, #2  
15. BASE, #1  
16. EMITTER, #1  
15. EMITTER, #4  
16. COLLECTOR, #4  
8X  
6.40  
16. CATHODE  
16X  
1.12  
STYLE 5:  
STYLE 6:  
STYLE 7:  
PIN 1. SOURCE N‐CH  
PIN 1. DRAIN, DYE #1  
2. DRAIN, #1  
3. DRAIN, #2  
4. DRAIN, #2  
5. DRAIN, #3  
6. DRAIN, #3  
7. DRAIN, #4  
8. DRAIN, #4  
9. GATE, #4  
PIN 1. CATHODE  
2. CATHODE  
3. CATHODE  
4. CATHODE  
5. CATHODE  
6. CATHODE  
7. CATHODE  
8. CATHODE  
9. ANODE  
2. COMMON DRAIN (OUTPUT)  
3. COMMON DRAIN (OUTPUT)  
4. GATE P‐CH  
5. COMMON DRAIN (OUTPUT)  
6. COMMON DRAIN (OUTPUT)  
7. COMMON DRAIN (OUTPUT)  
8. SOURCE P‐CH  
1
16  
16X  
0.58  
9. SOURCE P‐CH  
10. SOURCE, #4  
11. GATE, #3  
12. SOURCE, #3  
13. GATE, #2  
14. SOURCE, #2  
15. GATE, #1  
16. SOURCE, #1  
10. ANODE  
11. ANODE  
12. ANODE  
13. ANODE  
14. ANODE  
15. ANODE  
16. ANODE  
10. COMMON DRAIN (OUTPUT)  
11. COMMON DRAIN (OUTPUT)  
12. COMMON DRAIN (OUTPUT)  
13. GATE N‐CH  
14. COMMON DRAIN (OUTPUT)  
15. COMMON DRAIN (OUTPUT)  
16. SOURCE N‐CH  
1.27  
PITCH  
8
9
DIMENSIONS: MILLIMETERS  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42566B  
SOIC−16  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2019  
www.onsemi.com  
onsemi,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates  
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.  
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any  
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the  
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use  
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products  
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information  
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may  
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license  
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems  
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should  
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
ADDITIONAL INFORMATION  
TECHNICAL PUBLICATIONS:  
Technical Library: www.onsemi.com/design/resources/technical−documentation  
onsemi Website: www.onsemi.com  
ONLINE SUPPORT: www.onsemi.com/support  
For additional information, please contact your local Sales Representative at  
www.onsemi.com/support/sales  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明