NCP459FCT2G [ONSEMI]
4 A Single Load Switch for Low Voltage Rail;
| 型号： | NCP459FCT2G |
| 厂家： | 
ONSEMI |
| 描述： | 4 A Single Load Switch for Low Voltage Rail |
| 文件： | 总13页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP458R, NCP459
4 A Single Load Switch for
Low Voltage Rail
The NCP458R and NCP459 are power load switch with very low
Ron NMOSFET controlled by external logic pin, allowing
optimization of battery life, and portable device autonomy.
Indeed, thanks to a best in class current consumption optimization
with NMOS structure, leakage currents are drastically decreased.
Offering optimized leakages isolation on the ICs connected on the
battery.
http://onsemi.com
MARKING
DIAGRAM
Output discharge path is proposed, in the NCP459 version , to
eliminate residual voltages on the external components connected on
output pin.
Reverse voltage protection, from OUT to IN is offered in the
NCP458R version.
XXXX
AYWWG
WLCSP8
CASE 567HD
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Proposed in wide input voltage range from 0.75 V to 5.5 V, and a
2
very small CSP8 1 x 2 mm .
PINOUT
1
2
Features
• 0.75 V − 5.5 V Operating Range
• 11 mW N−MOSFET
• Vbias Rail Input
EN
IN
GATE
A
B
C
D
• DC Current up to 4 A
• Output Auto−Discharge Option
• Reverse Blocking Option
• Active High EN Pin
OUT
OUT
GND
2
• CSP8, 1 x 2 mm , Pitch 0.5 mm
IN
Typical Applications
• Notebooks
• Tablets
• Wireless
• Mobile Phones
• Digital Cameras
VBIAS
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Vcc
V+
LS
NCP458−459
DCDC Converter
LoDrO
B1
C1
A2
D1
B2
Platform IC’n
IN
IN
OUT
OUT
SMPS
C2
A1
D2
Gate EN
Vbias GND
ENx
EN
0
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
June, 2014 − Rev. 1
NCP458R/D
NCP458R, NCP459
LS
NCP458−459
DCDC Converter
B1
C1
A2
D1
B2
C2
A1
D2
Platform IC’n
IN
IN
OUT
OUT
EN
or
LDO
Gate
Vbias GND
ENx
EN
0
Figure 2. Application Schematic with Vbias Connected to IN and No Gate Delay
PIN FUNCTION DESCRIPTION
Pin Name
EN
Pin Number
A1
Type
Description
Enable input, logic high turns on power switch .
Load−switch input pin.
INPUT
IN
B1, C1
D1
POWER
POWER
INPUT
VBIAS
GATE
OUT
External supply voltage input.
A2
OUT pin slew rate control (t ).
rise
B2, C2
D2
POWER
POWER
Load−switch output pin.
Ground connection.
GND
http://onsemi.com
2
NCP458R, NCP459
BLOCK DIAGRAMS
IN: B1, C1
OUT : B2, C2
GATE : A2
Gate driver
Control
logic
EN: A1
&
Charge
Pump
GND: D2
VBIAS : D1
Figure 3. NCP458R Block Diagram
IN: B1, C1
GATE : A2
OUT : B2, C2
Gate driver
Control
logic
&
Charge
Pump
GND : D2
EN : A1
VBIAS : D1
Figure 4. NCP459 Block Diagram
http://onsemi.com
3
NCP458R, NCP459
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
IN, OUT, EN, VBIAS, GATE Pins: (Note 1)
V
V
V
V
−0.3 to +6.5
V
EN, IN , OUT,
V
BIAS, GATE
From IN to OUT Pins: Input/Output (Note 1) NCP459
From IN to OUT Pins: Input/Output (Note 1) NCP458R
Human Body Model (HBM) ESD Rating are (Note 2)
Machine Model (MM) ESD Rating are (Note 2)
V
V
0 to + 6.5
6.5
V
V
V
V
IN , OUT
V
V
IN , OUT
ESD HBM
ESD MM
2000
200
Latch−up protection (Note 3)
− Pins IN, OUT, EN, VBIAS and GATE
LU
100
mA
°C
Maximum Junction Temperature
Storage Temperature Range
Moisture Sensitivity (Note 4)
T
J
−40 to + 125
−40 to + 150
Level 1
T
STG
°C
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard:
JESD22−A114 for all pins.
Machine Model (MM) 250 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: 100 mA per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol
Parameter
Operational Power Supply
Enable Voltage
Conditions
Min
0.75
0
Typ
Max
5.5
Unit
V
V
IN
V
EN
5.5
V
V
BIAS
Bias voltage (V
≥ best of V V )
IN, OUT
1.2
5.5
V
BIAS
T
Ambient Temperature Range
Decoupling input capacitor
Decoupling output capacitor
− 40
100
100
25
+ 85
°C
nF
nF
°C/W
A
A
C
IN
C
OUT
R
Thermal Resistance Junction to Air
DC current
CSP8 (Note 5)
90
4
q
JA
4.5
5
AC current 1 ms @ 217 Hz
AC current 100 ms spike
A
A
I
OUT
15
P
D
Power Dissipation Rating (Note 6)
0.315
W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. The R
is dependent of the PCB heat dissipation and thermal via.
q
JA
6. The maximum power dissipation ( ) is given by the following formula:
PD
TJMAX * TA
PD
+
RqJA
http://onsemi.com
4
NCP458R, NCP459
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C for V between 0.75 V and 5.5 V,
A
IN
and V
between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to T = + 25°C, V = 3.3 V and
BIAS
A IN
V
BIAS
= 5 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POWER SWITCH
T = 25°C
11
11
20
24
20
24
20
24
20
24
20
24
24
30
30
35
300
A
V
IN
V
IN
V
IN
V
IN
V
IN
= V
= V
= V
= V
= V
= 5.5 V
= 3.3 V
= 1.8 V
= 1.5 V
= 1.2 V
BIAS
BIAS
BIAS
BIAS
BIAS
T = 125°C
J
T = 25°C
A
T = 125°C
J
T = 25°C
A
12
13
13
14
17
230
T = 125°C
J
Static drain−source
on−state resistance
for each rail
T = 25°C
A
mW
R
DS(on)
T = 125°C
J
T = 25°C
A
T = 125°C
J
T = 25°C
A
V
IN
= 1.0 V
= 1.2 V
V
BIAS
T = 125°C
J
T = 25°C
A
V
IN
= 0.8 V
= 1.2 V
V
BIAS
T = 125°C
J
R
Output discharge
path
EN = low, NCP459
W
DIS
TIMINGS
No cap on GATE pin
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate
0.26
1.5
15
Output rise time
From 10% to 90% of
T
ms
R
V
OUT
V
LOAD
LOAD
= 5 V
= 1 mF,
= 25 W
IN
10
ms
ms
Enable time From En
to 10% of V
C
R
T
en
V
ih
OUT
With 1 nF on Gate
60
Fall Time. From 90%
to 10% of V
T
50
ms
ms
F
OUT
Tdis
Disable time
From EN to 90% Vout
No cap on GATE pin
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate, NCP459
Without Cgate, NCP458R
With 1 nF on Gate
75
0.25
1
0.5
Output rise time
From 10% to 90% of
T
R
ms
V
OUT
10
20
50
ms
ms
ms
V
= 3.3 V
= 1 mF,
= 25 W
IN
Enable time
C
LOAD
LOAD
From En V to 10%
90
150
T
en
ih
R
of V
OUT
114
Output fall time
From 90% to 10% of
T
F
60
120
ms
V
OUT
No cap on GATE pin
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate
0.12
0.6
5.5
15
Output rise time From
10% to 90% of V
T
T
ms
R
OUT
V
= 1.8 V
= 1 mF,
= 25 W
IN
C
LOAD
LOAD
ms
ms
Enable time From En
to 10% of V
R
en
V
ih
OUT
With 1 nF on Gate
85
Output fall time From
90% to 10% of V
T
F
35
ms
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Parameters are guaranteed for C
and R
connected to the OUT pin with respect to the ground
LOAD
LOAD
http://onsemi.com
5
NCP458R, NCP459
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C for V between 0.75 V and 5.5 V,
A
IN
and V
between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to T = + 25°C, V = 3.3 V and
BIAS
A IN
V
BIAS
= 5 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TIMINGS
No cap on GATE pin
0.01
1
Output rise time
From 10% to 90% of
V
LOAD
LOAD
= 1 V
= 1 mF,
= 25 W
IN
C
R
Gate capacitor = 1 nF
Gate capacitor = 10 nF
Without Cgate
T
R
ms
V
OUT
13
10
0.4
20
ms
ms
ms
Enable time From En
V
IN
= 1 V
= 1 mF,
= 25 W
T
en
V
ih
to 10% of V
OUT
C
R
With 1 nF on Gate
LOAD
LOAD
T
Output fall time
F
Logic
High−level input
voltage
V
0.9
3
V
IH
Low−level input
voltage
V
0.4
V
IL
R
Pull down resistor
7
MW
EN
REVERSE CURRENT BLOCKING
V
Reverse threshold
V
OUT
− V
IN
45
60
mV
mV
rev_thr
Reverse threshold
hysteresis
V
rev_hyst
Reverse comparator
response time
T
rev
V
OUT
− Vin > V
rev_thr
2.5
ms
QUIESCENT CURRENT− NCP458R
V
Quiescent
BIAS
I
V
= 3.3 V, EN = high
EN = high
1.5
6
mA
mA
mA
VBIAS
BIAS
current
I
IN Quiescent current
0.01
0.01
0.3
0.3
INQ
EN = low, IN standby current, V = 3.3 V, without
IN
I
Standby current IN
STBIN
discharge path.
Standby current
I
V
= 3.3 V EN = low
0.4
1.5
0.5
mA
mA
STDVbias
BIAS
V
BIAS
Output leakage
current
I
IN connected to GND, V
= 5 V
0.01
out_leak
OUT
QUIESCENT CURRENT − NCP459
V
Quiescent
BIAS
I
V
= 3.3 V, EN = high
EN = high
1.3
5
mA
mA
mA
VBIAS
BIAS
current
I
IN Quiescent current
0.01
0.01
0.3
0.3
INQ
EN = low, IN standby current, V = 3.3 V, with
IN
I
Standby current IN
STBIN
discharge path. NCP459.
Standby current
I
V
BIAS
= 3.3 V EN = low
0.4
1.5
mA
STDVbias
V
BIAS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Parameters are guaranteed for C
and R
connected to the OUT pin with respect to the ground
LOAD
LOAD
http://onsemi.com
6
NCP458R, NCP459
TIMINGS
V
IN
EN
V
OUT
T
T
T
EN
R
T
F
DIS
T
T
OFF
ON
Figure 5. Enable, Rise and Fall Time
http://onsemi.com
7
NCP458R, NCP459
TYPICAL CHARACTERISTICS
25
20
15
10
5
6.0
5.8
5.6
5.4
−40°C
125°C
25°C
5.0
85°C
25°C
4.8
4.6
4.4
4.2
4.0
85°C
−40°C
125°C
0
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
(V)
0.5
1.5
2.5
3.5
(V)
4.5
5.5
V
IN
V
EN
Figure 6. RDS(on) (mW) vs VIN (V), Over
Figure 7. Pull Down Resistor (MW) vs VEN (V),
Temperature Range
Over Temperature Range
350
300
250
200
150
100
50
0.60
0.50
0.40
0.30
0.20
0.10
0
−40°C
25°C
85°C
−40°C
25°C
85°C
125°C
125°C
0
0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25
1
2
3
V
4
5
(V)
V
IN
(V)
BIAS
Figure 8. Discharge Resistor (W) vs VIN (V),
Figure 9. NCP458R Standby Current (mA) vs
BIAS (V), Over Temperature Range
Over Temperature Range
V
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
−40°C
25°C
85°C
−40°C
25°C
85°C
125°C
125°C
0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25
(V)
1
2
3
V
4
5
(V)
V
BIAS
BIAS
Figure 10. NCP459 Standby Current (mA) vs
BIAS (V), Over Temperature Range
Figure 11. NCP458R Quiescent Current (mA) vs
BIAS (V), Over Temperature Range
V
V
http://onsemi.com
8
NCP458R, NCP459
TYPICAL CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
10k
1k
−40°C
25°C
85°C
125°C
100
10
1
−40°C
25°C
85°C
125°C
0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25
(V)
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
(V)
V
BIAS
V
IN
Figure 12. NCP459 Quiescent Current (mA) vs
BIAS (V), Over Temperature Range
Figure 13. Enable Time (ms) vs VIN (V) , Over
V
Temperature Range (without Cgate)
10
1.0
0.1
10k
1k
−40°C
25°C
85°C
125°C
100
10
1
−40°C
25°C
85°C
125°C
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
(V)
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
IN
V
IN
(V)
Figure 14. Rise Time (ms) vs VIN (V), Over
Temperature Range (without Cgate)
Figure 15. Disable Time (ms) vs VIN (V), Over
Temperature Range
VBIAS and VIN Tied Together
1k
100
10
1
0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
IN
(V)
Figure 16. Fall Time (ms) vs VIN (V), Over
Temperature Range
V
BIAS and VIN Tied Together
Rload 25 W
http://onsemi.com
9
NCP458R, NCP459
FUNCTIONAL DESCRIPTION
Overview
If Vbias rail is not available or used, Vbias pin and Vin pin
can be connected together as close as possible the DUT. A
minimum of 1.2 V is necessary to control the IC.
The NCP458R and NCP459 are high side N channel
MOSFET power distribution switch designed to isolate ICs
connected on the battery or DCDC supplies in order to save
energy. The part can be used with a wide range of supply
from 0.75 V to 5.5 V.
Output rise time − Gate control
The NMOS is control with internal charge pump and
driver. A minimum gate slew rate is internally set to avoid
huge inrush current when EN is set from low to high. The
default gate slew rate depends on Vin level. The higher Vin
level, the longer rise time.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing NMOS switch off.
The IN/OUT path is activated with a minimum of V
min, Vin min and EN forced to high level.
In addition, an external capacitor can be connected
between Gate pin and GND in order to slow down the gate
rising. See electrical table for more details.
BIAS
Auto Discharge (Optional − NCP459)
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
The auto−discharge is activated when EN pin is set to low
level (disable state).
Cin and Cout Capacitors
100 nF external capacitors must be connected as close as
possible the DUT for noise immunity and better stability. In
case of input hot plug (input voltage connected with fast
slew rate − few ms − it’s strongly recommended to avoid big
capacitor connected on the input. That allows to avoid input
over voltage transients.
The discharge path ( Pull down NMOS) stays activated as
long as EN pin is set at low level.
In order to limit the current across the internal discharge
Reverse Blocking Control (Optional NCP458R)
A reverse blocking control circuitry is embedded to
eliminate leakages from OUT to IN in case of Vout > Vin.
A comparator measures the dropout voltage on the switch
between OUT and IN and turn off the NMOS if this voltage
exceeds specified reverse voltage.
Nmosfet, the typical value is set at R
value.
DIS
Vbias Rail
The core of the IC is supplied thanks to Vbias supply rail
(common +5 V, 3.3 V, 1.8 V, 1.2 V). Indeed, no current
consumption is used on IN pin, allowing to improve power
saving of the rail that must be isolated by the power switch.
http://onsemi.com
10
NCP458R, NCP459
APPLICATION INFORMATION
Demoboard
Power Dissipation
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
The NCP458R and NCP459 integrate a 4 A rated NMOS
FET, and the PCB rules must be respected to properly
evacuate the heat out of the silicon.
The package is a CSP and due to the low thermal
resistance of the silicon, all the balls can be used to improved
power dissipation. Indeed, even if the power crosses the IN
/ OUT pins only, all the balls around this power area should
be connected to the larger PCB area.
In the below PCB example (application demonstration
board), all the PCB areas connected to 6 balls are enlarged.
In addition vias are connected to bottom side with exactly
same form factor of the other PCB side.
(eq. 1)
ǒ
Ǔ2
PD + RDS(on) IOUT
P
D
= Power dissipation (W)
R
I
= Power MOSFET on resistance (W)
= Output current (A)
DS(on)
OUT
TJ + PD RqJA ) TA
(eq. 2)
Additional improvements can be done also by using more
copper thickness and the thinner epoxy as possible.
T
= Junction temperature (°C
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
J
R
T
qJA
A
Figure 18. Demonstration Board
(bottom view)
Figure 17. Demonstration Board (top view)
http://onsemi.com
11
NCP458R, NCP459
IN
OUT
IN_2
OUT_2
U1
B1
C1
A2
D1
B2
IN
OUT
C2
GND
GND
IN
OUT
A1
Gate
Vbias GND
EN
D1
DIODE ZENER1
D2
C2
1μF
D2
DIODE ZENER1
C1
1μF
C3
1nF
NCP458−9
VBIAS
J9
1
2
Bat
100 k
R1
1μF
C4
EN
R2
100 k
Figure 19. Demonstration Board Schematic
BILL OF MATERIAL TABLE
Quantity
Reference schem
Part description
Socket, 4mm, metal, PK5
HEADER200
Part number
B010
Manufacturer
HIRSCHMANN
FC
2
4
1
3
1
1
2
2
1
IN, OUT
IN_2, OUT_2, VBIAS, EN
2.54 mm, 77313-101-06LF
2.54 mm, 77313-101-06LF
GRM155R70J105KA12#
GRM188R60J102ME47#
ESD9x
J9 (Bat)
C1, C2, C4
C3
HEADER200-2
1uF
FC
Murata
1nF, Not mounted
TVS
Murata
D1, D2
GND2,GND
R2, R3
ON Semiconductor
Harvin
GND JUMPER
Resistor 100k 0603
Load switch
D3082F05
MC 0.063 0603 1% 100K
NCP458 - 459
MULTICOMP
ON Semiconductor
U1
ORDERING INFORMATION
Device
†
Options
Marking
Package
Shipping
NCP458RFCT2G
Reverse Voltage Protection
458RdYWW
458RCdYWW
459dYWW
WLCSP 1 x 2 mm
(Pb−Free)
3000 Tape / Reel
3000 Tape / Reel
3000 Tape / Reel
NCP458RFCCT2G
NCP459FCT2G
Reverse Voltage Protection,
Die Coating
WLCSP 1 x 2 mm
(Pb−Free)
Discharge Path
WLCSP 1 x 2 mm
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
12
NCP458R, NCP459
PACKAGE DIMENSIONS
WLCSP8, 2.0x1.0
CASE 567HD
ISSUE O
NOTES:
D
A
B
E
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
PIN A1
REFERENCE
MILLIMETERS
2X
0.25
C
DIM
A
A1
A2
b
D
E
e
MIN
−−−
0.21
0.36 REF
0.29
2.00 BSC
1.00 BSC
0.50 BSC
MAX
0.66
0.27
2X
0.25
C
TOP VIEW
SIDE VIEW
0.34
A
A2
A1
0.10
C
RECOMMENDED
SOLDERING FOOTPRINT*
0.05
C
SEATING
PLANE
NOTE 3
C
PACKAGE
OUTLINE
0.50
PITCH
e/2
e/2
e
8X
b
e
8X
0.25
0.05
0.03
C
C
A B
A1
0.50
PITCH
1
2
DIMENSIONS: MILLIMETERS
A
B
C
D
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP458R/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明