NCP4624DSQ12T1G [ONSEMI]
150 mA, Wide Input Range, LDO Linear Voltage Regulator; 150毫安,宽输入范围, LDO线性稳压器型号: | NCP4624DSQ12T1G |
厂家: | ONSEMI |
描述: | 150 mA, Wide Input Range, LDO Linear Voltage Regulator |
文件: | 总18页 (文件大小:1880K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCP4624
150 mA, Wide Input Range,
LDO Linear Voltage
Regulator
The NCP4624 is a CMOS 150 mA LDO linear voltage regulator
which features high input voltage range while maintaining low
quiescent current 2 mA typically. Several protection features like
Current Limiting and Reverse Current Protection Circuit are fully
integrated to create a versatile device suitable for the power source
being in the standby−mode. A high maximum input voltage (11 V) and
wide temperature range (−40°C to 85°C) makes the NCP4624 device
with output capacitor as low as 0.1 mF an ideal choice for industrial
applications also a portable equipments powered by 2−cell Li−ion
battery.
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MARKING
DIAGRAMS
XXXMM
SOT−23−5
CASE 1212
1
Features
• Operating Input Voltage Range: 2.5 V to Set V
+ 6.5 V, Max.
OUT
11 V
XX
MM
• Output Voltage Range: 1.2 to 5.5 V (available in 0.1 V steps)
2% Output Voltage Accuracy
1
•
1
UDFN4
CASE 517BR
• Output Current: min. 150 mA
• Line Regulation: 0.02%/V
• Current Limit Circuit
• Available in SOT−23−5, UDFN 1.0 x 1.0 mm and SC−88A Package
• Built−in Reverse Current Protection Circuit
• These are Pb−Free Devices
XXXX MG
G
SC−88A
(SC−70−5/SOT−353)
CASE 419A
1
Typical Applications
• Home Appliances, Industrial Equipment
• Cable Boxes, Satellite Receivers, Entertainment Systems
• Car Audio Equipment, Navigation Systems
• Notebook Adaptors, LCD TVs, Cordless Phones and Private LAN
Systems
XX, XXX, XXXX = Specific Device Code
M, MM
= Date Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
• Battery−Powered Portable Communication Equipments
(*Note: Microdot may be in either location)
NCP4624x
VIN
VOUT
VIN
VOUT
C1
C2
0.1mF
CE
0.1mF
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
February, 2012 − Rev. 0
NCP4624/D
NCP4624
NCP4624xxxx
NCP4624Dxx
Vin
Vin
Vout
Vout
Vref
Vref
Current Limit
Current Limit
CE
CE
Reverse Detector
Reverse Detector
GND
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOT−23−5
SC−88A
UDFN 1x1
Pin Name
VIN
Description
1
2
3
4
5
5
3
1
2
4
4
2
3
Input pin
GND
CE
Ground pin
Chip enable pin (“H” active)
Non connected
Output pin
NC
1
VOUT
EP
*EP
Exposed Pad (leave floating or connect to GND)
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
VIN
Value
−0.3 to 12
−0.3 to VIN ≤ 11
−0.3 to VIN ≤ 11
420
Unit
Input Voltage (Note 1)
V
V
Output Voltage
VOUT
VCE
Chip Enable Input
V
Power Dissipation SOT−23−5
Power Dissipation uDFN 1.0 x 1.0 mm
Power Dissipation SC−88A
Junction Temperature
P
D
mW
400
380
TJ
−40 to 150
−55 to 125
2000
°C
°C
V
Storage Temperature
TSTG
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESDHBM
ESDMM
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to Electrical Characteristics and Application Information for safe operating area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
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2
NCP4624
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOT−23−5
RqJA
238
°C/W
Thermal Resistance, Junction−to−Air
Thermal Characteristics, uDFN 1x1
Thermal Resistance, Junction−to−Air
RqJA
RqJA
250
263
°C/W
°C/W
Thermal Characteristics, SC−88A
Thermal Resistance, Junction−to−Air
ELECTRICAL CHARACTERISTICS −40°C ≤ T ≤ 85°C; C = C = 0.1 mF, unless otherwise noted. Typical values are at
OUT
A
IN
T = +25°C.
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Operating Input Voltage
Output Voltage
VIN
V
1.2 V < V
< 4.5 V
2.5
Vset +
6.5
OUT
4.5 V ≤ V
< 5.5 V
> 1.5 V
11
x1.01
x1.018
+15
OUT
VOUT
V
Ta = 25°C, V
x0.99
x0.982
−15
OUT
−40°C < T < 85°C, V
> 1.5V
A
OUT
mV
T = 25°C, V
A
< 1.5 V
OUT
−40°C < T < 85°C, V
< 1.5V
−28
+28
A
OUT
Output Voltage Temp. Coefficient
V
IN
= VOUT + 2 V, I
OUT
= 100 mA, T = −40 to
100
ppm/°C
A
105°C
Line Regulation
Load Regulation
Set V
+ 0.5 V < V < V max, I
= 1 mA
Line
Reg
0.02
−3
0.20
35
%/V
mV
V
OUT
IN
IN
OUT
V
I
= VOUT + 2 V, 0.1mA < IOUT ≤ 150 mA
Load
−35
IN
Reg
= 150 mA
VDO
1.2 V ≤ V
1.3 V ≤ V
1.5 V ≤ V
1.8 V ≤ V
2.3 V ≤ V
3.0 V ≤ V
4.0 V ≤ V
< 1.3 V
< 1.5 V
< 1.8 V
< 2.3 V
< 3.0 V
< 4.0 V
≤ 5.5 V
1.68
1.63
1.48
1.16
0.90
0.61
0.39
2.59
2.49
2.23
2.19
1.47
1.05
0.76
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Dropout Voltage
Output Current
IOUT
150
mA
mA
mA
mA
mA
V
Short Current Limit
Quiescent Current
Standby Current
V
= 0 V
I
45
2.0
0.2
0.3
OUT
SC
Iout = 0 mA
= V , V = 0 V
IQ
3.7
0.6
0.9
V
ISTB
IPD
IN
IN max
CE
CE Pin Pull−Down Current
CE Pin Threshold Voltage
CE Input Voltage “H”
CE Input Voltage “L”
VCEH
1.7
0
V
IN
VCEL
0.8
0.16
100
120
Reverse Current
0 V ≤ V < 11 V, VOUT > 1.5 V
IREV
0
mA
mV
mV
dB
IN
Reverse Current Detection Offset
Reverse Current Release Offset
0 V ≤ V < 11 V, VOUT > 1.5 V
VREV_DET
VREV_REL
PSRR
55
IN
0 V ≤ V < 11 V, VOUT > 1.5 V
70
IN
VIN = V
+ 2.5 V,
= 0.3 V,
= 50 mA, f = 1 kHz
V
OUT
V
OUT
V
OUT
V
OUT
= 1.2 V
27
OUT
IN_PK−PK
ΔV
= 2.5 V
= 3.3 V
= 5.5 V
22
I
OUT
Power Supply Rejection Ratio
Output Noise Voltage
18
15
V
= 1.2 V, I
= 30 mA, f = 100 Hz to 100 kHz VNOISE
105
380
mV
rms
OUT
OUT
Autodischarge NMOS Resist-
ance
VIN = 7.0 V, VCE = 0.0 V (D version only)
RDSON
W
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NCP4624
TYPICAL CHARACTERISTICS
3.5
3
1.4
1.2
1
2.5
2
7.5 V
V
= 2.5 V
0.8
0.6
0.4
0.2
0
4.0 V
5.5 V
IN
1.5
1
V
IN
= 9.8 V
4.3 V
5.8 V
0.5
0
0
50
100 150 200 250 300 350 400
(mA)
0
50
100
150
200
250
300
350
400
I
(mA)
I
OUT
OUT
Figure 3. Output Voltage vs. Output Current
Figure 4. Output Voltage vs. Output Current
1.2 V Version (TJ = 255C)
3.3 V Version (TJ = 255C)
1.4
1.2
1
6
5
4
3
2
1
0
V
IN
= 6.5 V
11 V
1 mA
I
= 50 mA
30 mA
OUT
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
0
50
100
150
200
250
300
350
400
I
(mA)
V
IN
(V)
OUT
Figure 5. Output Voltage vs. Output Current
Figure 6. Output Voltage vs. Input Voltage
1.2 V Version
5.5 V Version (TJ = 255C)
7
6
5
4
3
2
1
0
4
3.5
3
2.5
2
1.5
1
1 mA
1 mA
30 mA
30 mA
0.5
0
I
= 50 mA
OUT
I
= 50 mA
OUT
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10 11
V
IN
(V)
V
IN
(V)
Figure 7. Output Voltage vs. Input Voltage
3.3 V Version
Figure 8. Output Voltage vs. Input Voltage
5.5 V Version
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NCP4624
TYPICAL CHARACTERISTICS
1.22
1.21
1.2
3.33
3.32
3.31
3.3
3.29
3.28
3.27
1.19
1.18
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Output Voltage vs. Temperature,
1.2 V Version
Figure 10. Output Voltage vs. Temperature,
3.3 V Version
5.51
5.5
2
1.6
12
0.8
0.4
0
5.49
5.48
5.47
5.46
5.45
−40
−20
0
20
40
60
80
0
1
2
3
4
5
6
7
8
T , JUNCTION TEMPERATURE (°C)
J
V
IN
(V)
Figure 11. Output Voltage vs. Temperature,
5.5 V Version
Figure 12. Quiescent Current vs. Input
Voltage, 1.2 V Version
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
V
IN
(V)
V
IN
(V)
Figure 13. Quiescent Current vs. Input
Voltage, 3.3 V Version
Figure 14. Quiescent Current vs. Input
Voltage, 5.5 V Version
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NCP4624
TYPICAL CHARACTERISTICS
0.8
0.6
2
1.6
1.2
0.8
0.4
0
T = 85°C
A
T = −40°C
A
0.4
0.2
0
T = 25°C
A
T = 85°C
A
T = −40°C
A
T = 25°C
A
0
30
60
90
120
150
0
30
60
I
90
120
150
(mA)
I
(mA)
OUT
OUT
Figure 15. Dropout Voltage vs. Output Current,
1.2 V Version
Figure 16. Dropout Voltage vs. Output Current,
3.3 V Version
0.5
0.4
0.3
0.2
0.1
0
6
5
4
3
2
1
0
T = 85°C
A
T = −40°C
A
T = 25°C
A
0
30
60
90
120
150
10
100
1k
10k
100k
1M
I
(mA)
FREQUENCY (Hz)
OUT
Figure 17. Dropout Voltage vs. Output Current,
5.5 V Version
Figure 18. Output Voltage Noise, 1.2 V Version,
IN = 2.5 V, IOUT = 30 mA, Cin = Cout = 0.1 mF
V
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Output Voltage Noise, 3.3 V Version,
IN = 4.3 V, IOUT = 30 mA, Cin = Cout = 0.1 mF
Figure 20. Output Voltage Noise, 5.5 V Version,
IN = 6.5 V, IOUT = 30 mA, Cin = Cout = 0.1 mF
V
V
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NCP4624
TYPICAL CHARACTERISTICS
70
60
50
40
30
20
10
0
60
50
40
1 mA
1 mA
30
30 mA
30 mA
20
I
= 50 mA
1k
10
OUT
I
= 50 mA
OUT
0
10
100
1k
10k
100k
1M
10
100
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. PSRR vs. Frequency, 1.2 V Version
Figure 22. PSRR vs. Frequency, 3.3 V Version
60
50
40
30
20
10
1 mA
30 mA
I
= 50 mA
1k
OUT
0
10
100
10k
100k
1M
FREQUENCY (kHz)
Figure 23. PSRR vs. Frequency, 5.5 V Version
4.0
3.5
3.0
2.5
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
t (ms)
Figure 24. Line Transients, 1.2 V Version,
IOUT = 1 mA
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NCP4624
TYPICAL CHARACTERISTICS
5.8
5.3
4.8
4.3
3.9
3.7
3.5
3.3
3.1
2.9
2.7
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
t (ms)
Figure 25. Line Transients, 3.3 V Version,
IOUT = 1 mA
8.0
7.5
7.0
6.5
6.1
5.9
5.7
5.5
5.3
5.1
4.9
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
t (ms)
Figure 26. Line Transients, 5.5 V Version,
IOUT = 1 mA
15
10
5
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 27. Load Transients, 1.2 V Version, Load
Step 1 mA to 10 mA,
V
IN = 2.5 V
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NCP4624
TYPICAL CHARACTERISTICS
15
10
5
0
3.9
3.7
3.5
3.3
3.1
2.9
2.7
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 28. Load Transients, 3.3 V Version, Load
Step 1 mA to 10 mA, VIN = 4.3 V
15
10
5
0
6.1
5.9
5.7
5.5
5.3
5.1
4.9
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 29. Load Transients, 5.5 V Version, Load
Step 1 mA to 10 mA, VIN = 6.5 V
150
100
50
0
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 30. Load Transients, 1.2 V Version, Load
Step 50 mA to 100 mA, VIN = 2.5 V
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NCP4624
TYPICAL CHARACTERISTICS
150
100
50
0
4.5
4.1
3.7
3.3
2.9
2.5
2.1
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 31. Load Transients, 3.3 V Version, Load
Step 50 mA to 100 mA, VIN = 4.3 V
150
100
50
0
6.7
6.3
5.9
5.5
5.1
4.7
4.3
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 32. Load Transients, 5.5 V Version, Load
Step 50 mA to 100 mA, VIN = 6.5 V
4.5
3.0
1.5
0.0
Chip Enable
I
= 1 mA
OUT
1.2
0.9
I
= 30 mA
0.6
OUT
0.3
I
= 150 mA
OUT
0.0
−0.3
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 33. Turn−on Behavior, 1.2 Version,
V
IN = 3 V
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NCP4624
TYPICAL CHARACTERISTICS
6.6
4.4
2.2
0.0
Chip Enable
4.0
3.0
2.0
1.0
0.0
1.0
I
= 1 mA
OUT
I
= 30 mA
OUT
I
= 150 mA
OUT
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 34. Turn−on Behavior, 3.3 Version,
V
IN = 4.3 V
9.75
6.50
3.25
0.00
Chip Enable
6.0
4.5
I
= 1 mA
I
OUT
3.0
I
= 30 mA
OUT
1.5
= 150 mA
OUT
0.0
−1.5
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 35. Turn−on Behavior, 5.5 Version,
V
IN = 6.5 V
4.5
3.0
1.5
0.0
Chip Enable
1.2
0.9
I
= 30 mA
OUT
0.6
I
= 150 mA
OUT
0.3
I
= 1 mA
OUT
0.0
−0.3
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 36. Turn−off Behavior, 1.2 Version,
VIN = 3 V
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NCP4624
TYPICAL CHARACTERISTICS
6.6
4.4
2.2
0.0
Chip Enable
4.0
3.0
I
= 30 mA
OUT
I
= 150 mA
2.0
OUT
1.0
I
= 1 mA
OUT
0.0
−1.0
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 37. Turn−off Behavior, 3.3 Version,
V
IN = 4.3 V
9.75
6.50
3.25
0.00
Chip Enable
= 30 mA
I
6.0
4.5
OUT
I
= 150 mA
OUT
3.0
1.5
I
= 1 mA
OUT
0.0
−1.5
0
40 80 120 160 200 240 280 320 360 400
t (ms)
Figure 38. Turn−off Behavior, 5.5 Version,
V
IN = 6.5 V
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NCP4624
APPLICATION INFORMATION
A typical application circuit for NCP4624 series is shown
in the Figure 39.
down current source which assure off state of LDO in case
the CE pin will stay floating. If the enable function is not
needed connect CE pin to VIN.
The D version of the NCP4624 includes a transistor
between VOUT and GND that is used for faster discharging
of the output capacitor. This function is activated when the
IC goes into disable mode.
NCP4624x
VIN VOUT
VIN
VOUT
C1
C2
0.1mF
CE
GND
0.1mF
Thermal Consideration
As a power across the IC increase, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature affect the rate of temperature increase for the
part. When the device has good thermal conductivity
through the PCB the junction temperature will be relatively
low in high power dissipation applications.
Figure 39. Typical Application Schematic
Input Decoupling Capacitor (C1)
A 100 nF ceramic input decoupling capacitor should be
connected as close as possible to the input and ground pin of
the NCP4624. Higher values and lower ESR improves line
transient response.
Reverse Current Protection Circuit
Internal Reverse Current Circuitry stops the reverse
current from VOUT pin to GND pin and VIN pin when
Output Decoupling Capacitor (C2)
A 100 nF ceramic output decoupling capacitor is
sufficient to achieve stable operation of the IC. If tantalum
capacitor is used, and its ESR is high, the loop oscillation
may result. The capacitor should be connected as close as
possible to the output and ground pin. Larger values and
lower ESR improves dynamic parameters.
V
OUT
goes higher than V voltage or V
voltage. V
SET SET
IN
means voltage given by voltage version. The parasitic diode
of PMOS pass device is internally switched to reverse
direction before V becomes lower than V
. The
OUT
IN
operation coverage of the Reverse Current Protection
Circuit is V > 1.5 V. In order to avoid unstable behavior
OUT
a hysteresis is created by different threshold of detecting
voltage VREV_DET and releasing voltage VREV_REL. See
Figures 40 and 41 for details of configuration.
Enable Operation
The enable pin CE may be used for turning the regulator
on and off. The IC is switched on when a high level voltage
is applied to the CE pin. The enable pin has an internal pull
Vin
Vin
Vout
Vout
Vref
Vref
Current
Limit
Current
Limit
CE
CE
Reverse Detector
Reverse Detector
GND
GND
Figure 40. Normal Operating Mode
Figure 41. Reverse Current Protection Mode
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NCP4624
ESR versus Output Current
• The conditions when the device performs stable
When using the NCP4624 devices, consider the following
points:
operation are marked as the hatched area in the charts.
• The relation between Output Current I
and ESR of
OUT
the output capacitor are shown below in Figures 42, 43
and 44.
NCP4624xxx12xx, V = 2.5 V,
NCP4624xxx33xx, V = 4.3 V,
IN
IN
C
= C
= 0.1 mF, T = 25°C
C
= C = 0.1 mF, T = 25°C
OUT A
IN
OUT
A
IN
Figure 42. ESR vs. Load Current
Figure 43. ESR vs. Load Current
NCP4624xxx55xx, V = 6.5 V,
IN
C
= C = 0.1 mF, T = 25°C
OUT A
IN
Figure 44. ESR vs. Load Current
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NCP4624
ORDERING INFORMATION
Nominal Output
Voltage
Device
Marking
Feature
Package
Shipping
NCP4624DMU12TCG
5A
1.2 V
3.0 V
3.3 V
5.0 V
1.2 V
1.8 V
3.3 V
5.0 V
1.2. V
3.3 V
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
Enable High,
Auto discharge
DFN1010
10000 / Tape & Reel
(Pb−Free)
NCP4624DMU30TCG
NCP4624DMU33TCG
NCP4624DMU50TCG
NCP4624DSN12T1G
NCP4624DSN18T1G
NCP4624DSN33T1G
NCP4624DSN50T1G
NCP4624DSQ12T1G
NCP4624DSQ33T1G
5X
DFN1010
(Pb−Free)
10000 / Tape & Reel
10000 / Tape & Reel
10000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
6A
DFN1010
(Pb−Free)
6T
DFN1010
(Pb−Free)
F12
F18
F31
F50
AT12
AT33
SOT−23−5
(Pb−Free)
SOT−23−5
(Pb−Free)
SOT−23−5
(Pb−Free)
SOT−23−5
(Pb−Free)
SC−88A
(Pb−Free)
SC−88A
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
15
NCP4624
PACKAGE DIMENSIONS
SOT−23 5−LEAD
CASE 1212−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
A
A2
B
A
D
S
A1
0.05
MILLIMETERS
5
1
4
DIM MIN
MAX
1.45
0.10
1.30
0.50
0.25
3.10
3.10
1.80
E
L
A
A1
A2
b
---
0.00
1.00
0.30
0.10
2.70
2.50
1.50
2
3
E1
5X b
L1
C
c
M
S
S
A
D
0.10
C B
e
C
E
E1
e
0.95 BSC
L
0.20
0.45
---
0.75
RECOMMENDED
SOLDERING FOOTPRINT*
L1
5X
0.85
3.30
5X
0.56
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
16
NCP4624
PACKAGE DIMENSIONS
UDFN4 1.0x1.0, 0.65P
CASE 517BR−01
ISSUE O
NOTES:
4X
L3
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
c 0.18
PIN ONE
REFERENCE
typ
L2
E
DETAIL A
2X
0.05
C
MILLIMETERS
DIM MIN
−−−
A1 0.00
MAX
0.60
0.05
A
0.05
C
2X
3X
0.43
4X
0.23
A3
b
D
0.10 REF
0.20
1.00 BSC
0.53
1.00 BSC
0.65 BSC
TOP VIEW
0.30
(A3)
0.05
0.05
C
D2 0.43
E
e
L
A
0.20
0.30
0.37
0.12
3X
0.10
C
L2 0.27
L3 0.02
DETAIL B
SEATING
PLANE
NOTE 4
A1
C
SIDE VIEW
RECOMMENDED
MOUNTING FOOTPRINT*
e
e/2
3X L
D2
DETAIL A
1
4
2
0.65
PITCH
DETAIL B
2X
0.52
D2
PACKAGE
OUTLINE
455
3
1.30
4X b
M
0.05
C A B
NOTE 3
BOTTOM VIEW
4X
0.30
0.53
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
NCP4624
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP4624/D
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