NCP502SQ15T1G [ONSEMI]
80 mA CMOS Low Iq, Low−Dropout Voltage Regulator; 80毫安CMOS低IQ，低压降稳压器
| 型号： | NCP502SQ15T1G |
| 厂家： | 
ONSEMI |
| 描述： | 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator |
| 文件： | 总11页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP502, NCP502A
80 mA CMOS Low Iq, Low−
Dropout Voltage Regulator
The NCP502/A series of fixed output linear regulators are designed
for handheld communication equipment and portable battery powered
applications which require low quiescent. The NCP502/A series
features an ultra−low quiescent current of 40 ꢀ A. Each device contains
a voltage reference unit, an error amplifier, a PMOS power transistor,
resistors for setting output voltage, current limit, and temperature limit
protection circuits.
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MARKING
DIAGRAM
The NCP502/A has been designed to be used with low cost ceramic
capacitors. The device is housed in the micro−miniature SC70−5 and
TSOP−5 surface mount packages. Standard voltage versions are 1.5 V,
1.8 V, 2.5 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.3 V, 3.4 V, 3.5 V, 3.6 V,
3.7 V and 5.0 V. Other voltages are available in 100 mV steps.
5
4
SC70−5
SQ SUFFIX
CASE 419A
xxx MG
5
G
3
2
1
1
1
Features
5
TSOP−5
(SOT23−5, SC59−5)
SN SUFFIX
• Pb−Free Packages are Available
xxx AYWG
5
G
• Low Quiescent Current of 40 ꢀ A Typical
• Excellent Line and Load Regulation
CASE 483
1
• Low Output Voltage Option
• Output Voltage Accuracy of 2.0%
xxx = Specific Device Code
A
Y
W
M
G
= Assembly Location
= Year
• Industrial Temperature Range of −40°C to 85°C
• NCP502: 1.3 V Enable Threshold High, 0.3 V Enable Threshold Low
• NCP502A: 1.0 V Enable Threshold High, 0.4 V Enable Threshold Low
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
Typical Applications
• Cellular Phones
PIN CONNECTIONS
• Battery Powered Consumer Products
• Hand−Held Instruments
• Camcorders and Cameras
V
1
2
V
out
5
in
GND
Enable
3
4
N/C
(Top View)
Battery or
Unregulated
Voltage
Vout
C2
1
2
3
5
4
+
C1
+
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ON
OFF
This device contains 86 active transistors
Figure 1. Typical Application Diagram
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 12
NCP502/D
NCP502, NCP502A
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
2
3
V
Positive power supply input voltage.
Power supply ground.
in
GND
Enable
This input is used to place the device into low−power standby. When this input is pulled low, the device is
disabled. If this function is not used, Enable should be connected to Vin.
4
5
N/C
No internal connection.
V
out
Regulated output voltage.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage
Enable Voltage
Output Voltage
V
in
12
Enable
−0.3 to V +0.3
V
in
V
out
−0.3 to V +0.3
V
in
Power Dissipation and Thermal Characteristics
Power Dissipation
Thermal Resistance, Junction−to−Ambient
P
Internally Limited
400
W
°C/W
D
R
ꢁ
JA
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
T
+125
°C
°C
°C
J
T
A
−40 to +85
−55 to +150
T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
2. Latchup capability (85°C) "100 mA DC with trigger voltage.
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2
NCP502, NCP502A
ELECTRICAL CHARACTERISTICS (V = V
+ 2.0 V, V
= V , C = 1.0 ꢀ F, C
= 1.0 ꢀ F, T = 25°C, unless
out J
in
out(nom.)
enable
in
in
otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage (TA = 25°C, I = 10 mA) V = V (nom.) +1.0 V
V
out
V
out
in
out
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.4 V
3.5 V
3.6 V
3.7 V
5.0 V
1.455
1.746
2.425
2.646
2.744
2.842
2.94
3.038
3.234
3.332
3.43
1.5
1.8
2.5
2.7
2.8
2.9
3.0
3.1
3.3
3.4
3.5
3.6
3.7
5.0
1.545
1.854
2.575
2.754
2.856
2.958
3.06
3.162
3.366
3.468
3.57
3.528
3.626
4.900
3.672
3.774
5.100
Output Voltage (TA = −40°C to 85°C, I = 10 mA) V = V (nom.)
V
out
V
out
in
out
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.4 V
3.5 V
3.6 V
3.7 V
5.0 V
1.455
1.746
2.425
2.619
2.716
2.813
2.910
3.007
3.201
3.298
3.43
1.5
1.8
2.5
2.7
2.8
2.9
3.0
3.1
3.3
3.4
3.5
3.6
3.7
5.0
1.545
1.854
2.575
2.781
2.884
2.987
3.09
3.193
3.399
3.502
3.57
3.528
3.626
4.900
3.672
3.774
5.100
Line Regulation (V = V + 1.0 V to 12 V, I = 10 mA)
Reg
−
−
0.4
0.2
180
3.0
0.8
−
mV/V
mV/mA
mA
in
out
out
line
Load Regulation (I = 1.0 mA to 80 mA)
Reg
out
load
Output Current (V = (V at I = 80 mA) −3%)
I
80
out
out
out
o(nom.)
Dropout Voltage (T = −40°C to 85°C, I = 80 mA, Measured at
out
V −V
in out
mV
A
out
V
−3.0%)
1.5 V−1.7 V
1.8 V−2.4 V
2.5 V−2.6 V
2.7 V−2.9 V
3.0 V−4.0 V
4.1 V−5.0 V
−
−
−
−
−
−
1500
1300
1000
850
850
600
1900
1700
1400
1300
1200
900
Quiescent Current
I
ꢀ
A
Q
(Enable Input = 0 V)
(Enable Input = V , I = 1.0 mA to I
−
−
0.1
40
1.0
90
)
in out
o(nom.)
Output Short Circuit Current (V = 0 V)
I
90
−
200
55
500
−
mA
dB
out
out(max)
Ripple Rejection (f = 1.0 kHz, 15 mA)
RR
Output Voltage Noise (f = 100 Hz to 100 kHz)
V
−
180
−
ꢀ Vrms
V
n
Enable Input Threshold Voltage (NCP502)
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
V
V
th(en)
1.3
−
−
−
−
0.3
Enable Input Threshold Voltage (NCP502A)
V
th(en)
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
1.0
−
−
−
−
0.4
Output Voltage Temperature Coefficient
T
−
100
−
ppm/°C
C
3. Maximum package power dissipation limits must be observed.
T
*T
A
ꢁJA
J(max)
PD +
R
4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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3
NCP502, NCP502A
45
45
40
35
30
25
20
15
V
V
= 5.0 V
= 3.0 V
V
= 3.0 V
IN
OUT
OUT
42.5
40
37.5
35
10
5
32.5
30
0
0
1
2
3
4
5
6
7
−60
−40
−20
0
20
40
60
80 100
V
, INPUT VOLTAGE (V)
IN
T, TEMPERATURE (°C)
Figure 2. Quiescent Current versus Input Voltage
Figure 3. Quiescent Current versus Temperature
6
10
5
V
= 4.0 V to 5.0 V
V
V
= 4.0 V
IN
IN
ENABLE
5
4
= 0 to 4.0 V
0
60
40
20
0
C
= 1.0 ꢀ F
= 30 mA
OUT
I
OUT
3.0
2.0
I
= 30 mA
OUT
C
OUT
= 1.0 ꢀ F
1.0
0
−20
−40
0
10
20 30 40 50 60
70 80 90 100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
t, TIME (ms)
t, TIME (ꢀ s)
Figure 4. Line Transient Response
Figure 5. Enable Response
60
30
0
70
60
50
40
100
50
0
C
= 1.0 ꢀ F
= 3.0 V
= 4.0 V
OUT
V
V
OUT
IN
V
V
= 4.5 V + 0.5 V
P−P
IN
= 3.0 V
OUT
30
20
I
C
= 30 mA
OUT
−50
= 1.0 ꢀ F
OUT
−100
0
50 100 150 200 250 300 350 400 450
0.01
0.1
1.0
FREQUENCY (kHz)
10
100
t, TIME (ꢀ s)
Figure 6. Load Transient Response
Figure 7. Ripple Rejection/Frequency
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NCP502, NCP502A
2.995
2.99
3.5
V
= 12 V
C
C
= 1.0 ꢀ F
I
= 10 mA
IN
IN
OUT
= 1.0 ꢀ F
3
OUT
V
= V
ENABLE
IN
2.985
2.98
2.5
2
V
= 4.0 V
IN
2.975
2.97
1.5
1
2.965
2.96
0.5
0
−60
−40
−20
0
20
40
60
80
100
0
1
2
3
4
5
6
T, TEMPERATURE (°C)
V
, INPUT VOLTAGE (V)
IN
Figure 8. Output Voltage versus Temperature
Figure 9. Output Voltage versus Input Voltage
1200
1000
800
80 mA LOAD
600
40 mA LOAD
10 mA LOAD
400
200
0
−50 −25
0
25
50
75
100
125
T, TEMPERATURE (°C)
Figure 10. Dropout Voltage versus Temperature
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5
NCP502, NCP502A
DEFINITIONS
Load Regulation
Line Regulation
The change in output voltage for a change in output
current at a constant temperature.
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse technique such that the average
chip temperature is not significantly affected.
Dropout Voltage
The input/output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. Measured when the output drops 3.0% below
its nominal. The junction temperature, load current, and
minimum input supply requirements affect the dropout level.
Line Transient Response
Typical over and undershoot response when input voltage
is excited with a given slope.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 160°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Power Dissipation
The maximum total dissipation for which the regulator
will operate within its specifications.
Quiescent Current
The quiescent current is the current which flows through
the ground when the LDO operates without a load on its
output: internal IC operation, bias, etc. When the LDO
becomes loaded, this term is called the Ground current. It is
actually the difference between the input current (measured
through the LDO input pin) and the output current.
Maximum Package Power Dissipation
The maximum power package dissipation is the power
dissipation level at which the junction temperature reaches
its maximum operating value, i.e. 125°C. Depending on the
ambient power dissipation and thus the maximum available
output current.
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6
NCP502, NCP502A
APPLICATIONS INFORMATION
A typical application circuit for the NCP502/A series is
chance to pick up noise or cause the regulator to
shown in Figure 1, front page.
malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short as
possible.
Input Decoupling (C1)
A 1.0 ꢀ F capacitor either ceramic or tantalum is
recommended and should be connected close to the
NCP502/A package. Higher values and lower ESR will
improve the overall line transient response. If large line or
load transients are not expected, then it is possible to operate
the regulator without the use of a capacitor.
Thermal
As power across the NCP502/A increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material and also the
ambient temperature effect the rate of temperature rise for
the part. This is stating that when the NCP502/A has good
thermal conductivity through the PCB, the junction
temperature will be relatively low with high power
dissipation applications.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
Output Decoupling (C2)
The NCP502/A is a stable regulator and does not require
any specific Equivalent Series Resistance (ESR) or a
minimum output current. Capacitors exhibiting ESRs
ranging from a few mꢂ up to 5.0 ꢂ can thus safely be used.
The minimum decoupling value is 1.0 ꢀ F and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum devices. Larger values improve noise rejection and
load regulation transient response.
The maximum dissipation the package can handle is
given by:
T
*T
A
ꢁJA
J(max)
PD +
R
If junction temperature is not allowed above the
maximum 125°C, then the NCP502/A can dissipate up to
250 mW @ 25°C.
The power dissipated by the NCP502/A can be calculated
from the following equation:
TDK capacitor: C2012X5R1C105K, C1608X5R1A105K,
or C3216X7R1C105K
Enable Operation
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
[
]
[
]
* I
P
tot
+ V * I
(I ) ) V * V
in gnd out
in out out
or
)
*
I
be connected to V .
P
V
in
tot
I
out out
) I
V
+
inMAX
gnd
out
Hints
If an 80 mA output current is needed then the ground
current from the data sheet is 40 ꢀ A. For an NCP502/A
(3.0 V), the maximum input voltage will then be 6.12 V.
Please be sure the Vin and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
ꢃ
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NCP502, NCP502A
ORDERING INFORMATION
Nominal
Output Voltage
†
Marking
LCC
Device
NCP502SQ15T1
Package
Shipping
1.5
1.5
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ15T1G
LCC
SC70−5
(Pb−Free)
NCP502SQ18T1
1.8
1.8
LCD
LCD
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ18T1G
SC70−5
(Pb−Free)
NCP502SQ25T1
2.5
2.5
LCE
LCE
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ25T1G
SC70−5
(Pb−Free)
NCP502SQ27T1
2.7
2.7
LCF
LCF
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ27T1G
SC70−5
(Pb−Free)
NCP502SQ28T1
2.8
2.8
LCG
LCG
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ28T1G
SC70−5
(Pb−Free)
NCP502SQ29T1G
2.9
LJI
SC70−5
(Pb−Free)
3000 / Tape & Reel
NCP502SQ30T1
3.0
3.0
LCH
LCH
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ30T1G
SC70−5
(Pb−Free)
NCP502SQ31T1G
3.1
LJJ
SC70−5
(Pb−Free)
3000 / Tape & Reel
NCP502SQ33T1
3.3
3.3
LCI
LCI
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ33T1G
SC70−5
(Pb−Free)
NCP502SQ34T1G
3.4
LJK
SC70−5
(Pb−Free)
3000 / Tape & Reel
NCP502SQ35T1
3.5
3.5
LGO
LGO
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ35T1G
SC70−5
(Pb−Free)
NCP502SQ36T1G
NCP502SQ37T1G
3.6
3.7
LIU
3000 / Tape & Reel
3000 / Tape & Reel
SC70−5
(Pb−Free)
LJQ
SC70−5
(Pb−Free)
NCP502SQ50T1
5.0
5.0
LCJ
LCJ
SC70−5
3000 / Tape & Reel
3000 / Tape & Reel
NCP502SQ50T1G
SC70−5
(Pb−Free)
NCP502ASQ15T1G
NCP502ASQ18T1G
NCP502ASQ25T1G
NCP502ASQ27T1G
NCP502ASQ28T1G
1.5
1.8
2.5
2.7
2.8
LGP
LGQ
LGR
LGS
LGT
SC70−5
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
SC70−5
(Pb−Free)
SC70−5
(Pb−Free)
SC70−5
(Pb−Free)
SC70−5
(Pb−Free)
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8
NCP502, NCP502A
ORDERING INFORMATION
Nominal
Output Voltage
†
Marking
Device
Package
Shipping
NCP502ASQ30T1G
3.0
3.3
3.5
5.0
2.8
2.9
3.0
3.1
3.3
3.4
3.7
5.0
LGU
SC70−5
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NCP502ASQ33T1G
NCP502ASQ35T1G
NCP502ASQ50T1G
NCP502SN28T1G
NCP502SN29T1G
NCP502SN30T1G
NCP502SN31T1G
NCP502SN33T1G
NCP502SN34T1G
NCP502SN37T1G
NCP502SN50T1G
LGV
LGW
LGX
LKD
LJN
LKE
LJO
LKF
LJP
SC70−5
(Pb−Free)
SC70−5
(Pb−Free)
SC70−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
LJT
TSOP−5
(Pb−Free)
LKG
TSOP−5
(Pb−Free)
Additional voltages in 100 mV steps are available upon request by contacting your ON Semiconductor representative.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCP502, NCP502A
PACKAGE DIMENSIONS
SC70−5, SC−88A, SOT−353
SQ SUFFIX
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
NCP502, NCP502A
TSOP−5
CASE 483−02
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
C
D
G
H
J
K
L
M
S
0.90
0.25
0.95 BSC
1.10
0.50
C
SEATING
PLANE
0.05
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
T
10
3.00
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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LITERATURE FULFILLMENT:
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NCP502/D
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