NCP51105ASNT1G [ONSEMI]
Single 2.6 A, Low-Side Gate Driver with OCP;
| 型号： | NCP51105ASNT1G |
| 厂家： | 
ONSEMI |
| 描述： | Single 2.6 A, Low-Side Gate Driver with OCP 栅 |
| 文件： | 总15页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Single 2.6 A, Low-Side Gate
Driver with Over Current
Protection
1
TSOP−6
CASE 318G−02
Product Preview
NCP51105
MARKING DIAGRAM
The NCP51105 is a high current low side gate driver designed to
drive Power MOSFET and IGBT. The logic input is compatible with
CMOS and TTL output. The NCP51105 has OCP pin to provide over
current protection with negative voltage detected across switching
current sensing resistor and EN pin that be able to report faults status
to external controller such as MCU. EN pin must be pulled up to
higher voltage than threshold for normal operation while it will be
XXXAYWG
G
1
XXX = Specific Device Code
A
Y
W
G
=Assembly Location
= Year
= Work Week
pulled down to disable output in all fault conditions. Internal V
DD
circuitry provides an under−voltage lockout function by holding the
output low until supply voltage is recovered into operating range and
fault recovery time can be programmable by time constant set of
resistance and capacitance connected to EN pin.
= Pb−Free Package
(Microdot may be in either location.)
PIN CONNECTIONS
Features
• Wide Operating Voltage Range: up to 25 V
• 2.6 A Peak Sink/Source
IN
OCP
GND
OUT
1
2
3
6
5
• Shorter than 50 ns Propagation Delay Time
• Over Current Protection with Negative Voltage Sensing
• Input Logic Compatible with Wide Voltage Range for TTL & CMOS
• Programmable Fault Clear Time
EN
4
VDD
• Under Voltage Lockout for MOSFET and IGBT
• This Device is Pb−Free, Halide Free and is RoHS Compliant
ORDERING INFORMATION
†
Device
NCP51105ASNT1G
Shipping
Package
Typical Applications
TSOP−6
Tape & Reel
3000
• Switch−Mode Power Supplies
• High−Efficiency MOSFET Switching
• Synchronous Rectifier Circuits
• DC−to−DC Converters
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Motor Control
This document contains information on a product under development. onsemi reserves
the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2023
1
Publication Order Number:
March, 2023 − Rev. P1
NCP51105/D
NCP51105
Vin +
Vout +
VDD
VDD
EN
IN
OUT
GND
4
5
6
3
2
1
I/O
I/O
OCP
mC
Vout −
GND
Vin −
Figure 1. Simplified Application
4
6
VDD
IN
UVLO
VDD
100 k
3
PWM
Logic
OUT
GND
3.3V
2
2.15 M
UVLO
5
EN
VOCP−th
NFET
OCP
1
Figure 2. Internal Block Diagram
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2
NCP51105
PIN CONNECTIONS
OCP
GND
IN
EN
OUT
VDD
Figure 3. Pin Assignments − TSOP−6 (Top View)
PIN FUNCTION DESCRIPTION
Pin Name
OCP
Pin No.
Description
Current sense input with negative voltage
Ground that all signals are referenced
Sourcing and sinking current output of driver
Bias supply input
1
2
3
4
5
GND
OUT
VDD
EN
Enable I/O for three functions,
1. Logic input to enable output at higher V
and to disable output at lower V
ENL
ENH
2. Reporting fault conditions such as over current and under voltage lockout
3. Programming fault clear time with external RC time constant
IN
6
Logic Input for gate driver output
IN / OUTPUT LOGIC TABLE
(1)
(2)
(3)
IN
L
UVLO
OCP
L
EN
OUT
Description
H
H
H
L
H
L
H
L
L
L
OUT = Low by IN = L
OUT = High
H
H
H
X
L
H
L
H
OUT = Low by EN = L
X
L
OUT = Low by EN = L and UVLO = L
OUT = Low by IN = L (Pulled down by internal resistance)
H
X
H
1. UVLO = L is under−voltage lockout protection.
2. OCP = H is over−current protection.
3. EN = L is pulled down by internal N
turned on.
FET
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3
NCP51105
MAXIMUM RATINGS (Note 6)
Symbol
Parameter
Min
−0.3
−0.3
−5
Max
Unit
V
V
DD
Supply voltage range
25
V
O
Gate output voltage range
V
V
V
V
+ 0.3
V
DD
DD
DD
DD
V
OCP
Voltage range at current sense pin
Voltage range at enable pin
Logic input voltage range
+ 0.3
+ 0.3
+ 0.3
V
V
EN
−0.3
−5
V
V
IN
V
T
Storage temperature
−65
−40
−
150
°C
°C
°C
kV
kV
STG
T
J
Junction temperature
150
260
3.5
1.0
T
Lead temperature (soldering, 10 seconds)
L
ESD
ESD
Electrostatic Discharge Capability
(Note 5)
Human Body Model
Charge Device Model
−
HBM
CDM
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
5. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JESD22−A114
ESD Charged Device Model tested per JESD22−C101
Latch up Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78F
6. All voltage values are given with respect to GND pin.
THERMAL CHARACTERISTICS
Symbol
Rating
Junction−to−Ambient Thermal Impedance
Power Dissipation
Value
250
Unit
°C/W
W
R
q
JA
P
D
0.5
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
12.7
GND
−5
Max
Unit
V
V
DD
Supply Voltage Range
25
V
O
Gate output voltage range
Voltage range at current sense pin
Voltage range at enable pin
Logic input voltage range
Ambient temperature
V
DD
V
DD
V
DD
V
DD
V
V
OCP
V
V
EN
0
V
V
IN
−5
V
T
A
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCP51105
ELECTRICAL CHARACTERISTICS
V
DD
= 15 V, for typical values T = 25°C, unless otherwise specified. All voltage and current parameters are given with respect to GND pin.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
STATIC CHARACTERISTICS
VDDUV+ VDD UV start−up voltage threshold
VDDUV− VDD UV shut−down voltage threshold
VDDUVH VDD under voltage lockout voltage hysteresis
11.2
10.3
—
11.9
11.0
0.9
1.0
2.1
1.0
2.1
0.02
0.02
−246
50
12.7
11.8
—
V
V
V
VINL
VINH
VENL
VENH
VOH
Low level input voltage threshold
High level input voltage threshold
Enable signal low threshold
Enable signal high threshold
High level output voltage
0.8
1.9
0.8
1.9
—
1.2
2.3
1.2
2.3
0.1
0.1
−233
70
V
V
V
V
IO = 2 mA
V
VOL
Low level output voltage
—
V
VOCP−th Threshold voltage for over current protection
−259
35
mV
mA
mA
mA
A
IIN+
IIN−
Logic “1” input bias current
VIN = 5 V
VIN = 0 V
Logic “0” input bias current
−1
0
IQCC
IO+
Quiescent VDD supply current
Output sourcing short circuit pulsed current
VIN = 0 V or 5 V
—
700
2.6
2.6
—
1200
—
(7)
(7)
VO = 0 V, PW v 2 ms
VO = 15 V, PW v 2 ms
VEN = 0.4 V
2
IO−
Output sinking short circuit pulsed current
EN pull down sinking current
2
—
A
IFLT
18
—
mA
V
VACTSD
Active shut down voltage
VDD = open, IO+ / IO− = 0.1
—
2
2.3
DYNAMIC CHARACTERISTICS
VIN pulse = 5 V, Cload = 1 nF,
Figure 24
ton
toff
tr
Turn−on propagation delay
Turn−off propagation delay
Turn−on rise time
—
—
—
—
25
25
5
45
45
—
—
ns
ns
ns
ns
tf
Turn−off fall time
5
tDISA
Disable propagation delay
25
45
ns
ns
tOCPDEL Over current protection propagation delay
—
230
350
RFLTC = 10 kW to VDD,
VOCP Pulse = −0.5 V, Cload = 1 nF,
Figure 23
tOCPFLT
tFLTC
OCP to low level EN signal delay
FAULT clear time
—
200
103
320
130
ns
RFLTC = 10 kW to VDD,
VOCP pulse = −0.5 V,
Figure 23
80
ms
VDD = 3.3 V, RFLTC = 1 MW to V
,
DD
CFLTC = 150 pF to GND,
Figures 22, 23
(7)
ns
tBLK
Over current protection blanking time
100
—
180
2
250
—
RFLT = 0 W, CFLT = NC,
VOCP pulse = −0.5 V,
Figures 22, 23
(7)
VDD supply UVLO filter time
tVDDUV
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. This parameter, although guaranteed by design, is not tested in production.
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5
NCP51105
TYPICAL CHARACTERISTICS
Figure 4. IQVDD vs. Temperature
Figure 5. VOCP−th vs. Temperature
Figure 7. VDDUV− vs. Temperature
Figure 6. VDDUV+ vs. Temperature
Figure 8. VINH vs. Temperature
Figure 9. VINL vs. Temperature
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6
NCP51105
TYPICAL CHARACTERISTICS (continued)
Figure 10. VENH vs. Temperature
Figure 12. tON vs. Temperature
Figure 14. tOCPDEL vs. Temperature
Figure 11. VENL vs. Temperature
Figure 13. tOFF vs. Temperature
Figure 15. tOCPFLT vs. Temperature
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7
NCP51105
TYPICAL CHARACTERISTICS (continued)
Figure 16. tBLK vs. Temperature
Figure 17. tDISA vs. Temperature
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8
NCP51105
General Description
VDD bias voltage is dropped by IDD increased suddenly
once switching operation begins. If the VDD is below the
NCP51105 is the single channel low side gate driver
designed to drive Power MOSFET and IGBT with 2.6 A
source and sink peak current capability. The logic threshold
is compatible with both TTL and CMOS output and has
about 1 V hysteresis for strong noise immunity. The over
current of power devices can be detected through OCP pin
by sensing negative voltage and the information for
abnormal operation conditions can be provided by changing
EN pin voltage level. When over current or UVLO
conditions are detected, EN pin voltage is pulled down by
V
DDUV−
(typical 11.0 V for A−Ver and 7.3 V for B−Ver) for
more than filtering time, t , driver output is kept low
VDDUV
regardless of the IN input status and EN pin is pulled down
to GND by turning on internal N . EN pin is charged by
FET
external voltage supply as long as VDD is higher than
V
DDUV+
for more than fault clear time, t , that is
FLTC
determined by capacitance and resistance connected
externally at VDD and EN pins. Driver out is also generated
when IN high signal is applied after EN voltage is higher
turning on internal N
while the voltage is recovered to
than V
. However, for initial power up, EN pin voltage
FET
ENH
certain voltage levels via resistor connected with the internal
or external voltage sources as long as fault conditions are
disappeared. Internal circuitries provide an under−voltage
lockout function holding the output low and allow the fault
clear time to be programmable with external component
values.
can’t be charged until the internal logic configuration is
ended completely after VDD becomes the voltage level, 6 V
that PoR (Power on Reset) circuits are able to operate
properly. Initial logic configuration period, t , as shown
SET
in Figure 18 might be taken for about 13 ~ 15 ms.
As driver IC consumes the current from the VDD pin to
bias the internal circuits, VDD circuits should be designed
not only to supply safely the power required for driver
operation but also to block efficiently noises delivered from
external power switching circuits. Therefore, the bypass
ceramic capacitor of 100 nF is recommended to be designed
together with VDD decoupling capacitor and must be
located as close as possible between VDD and GND pins to
minimize switching noise influences.
VDD Under Voltage Lock Out
NCP51105 has internal UVLO protection circuit which
monitors the VDD supply voltage. The function of the
UVLO circuits is to ensure so that the gate of external power
devices is driven at an optimum voltage. The UVLO circuits
have hysteresis that helps to avoid VDD chattering when the
noise is influenced by switching power supply and when
VDD
VDDUV+
VDDUV−
VPOR
tSET
IN
tVDDUV
tFLTC
VENH
EN
NFET on
OUT
Figure 18. VDD UVLO Protection Timing Diagram
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9
NCP51105
Input Stage
generators such as MCU and stand−alone PWM controllers
used mainly in switching power supplies. NCP51105 has the
feature of input threshold voltage levels with small tolerance
across temperature and has the internal pull−down resistor
so that the output can be held in the low state whenever the
input pin is not connected to PWM controller or floating
condition. Input logics for input signals are defined as shown
Figure 19.
The input pin of NCP51105 is comparable with
industry−standard TTL and CMOS logic thresholds
regardless VDD supply voltage and has been designed with
wider hysteresis voltage, 1.0 V that can provide strong noise
immunity. As high input threshold is 2.1 V [Typ] and low
threshold is 1 V [Typ], NCP51105 can be comparable with
PWM signals delivered from different types of signal
VINH
Input Signal
VINL
Input Logic
Figure 19. VDD UVLO Protection Timing Diagram
Output Stage
discharged by turning on internal Q
when low input
Sink
NCP51105 has composed of single driver to deliver
typical source and sink current, 2.6 A at VDD = 15 V and can
effectively charge and discharge 1 nF load. The bias voltage
VDD charges gate capacitance Cgs of external power switch
signal is delivered. The Figure 20 shows the output stage
structure and the charging and discharging path of the
external power MOSFET. As seen in the Figure 20, the
parasitic inductances are presented in charging and
discharging path of Cgs, so certain ringing voltage might be
occurred in VDD and OUT pins.
by turning on internal Q
when logic high signal is
Source
received from input stage. Similarly, charged Cgs is
Qsource
Lbond
Ltrace
VDD
OUT
MOSFET
CVDD
RDSON
Lbond
Ltrace
Rgate
RDSON
Qsink
Lbond
Ltrace
Ltrace
GND
Figure 20. Sourcing and Sinking Current Path
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10
NCP51105
Enable Input
voltage and internal pull down N
is placed between EN
FET
NCP51105 offers enable functions that allow the device
to be enable or disable the output. Figure 21 is showing the
relationship among IN, OUT and EN signals. If EN pin
pin and GND as shown in Figure 22. Therefore, floating EN
pin can enable the output as long as the fault condition is not
exiting but EN pin should be not only connected to VDD pin
through the external pull−up resistor but also the small
capacitor needs to be designed together with the resister to
ensure proper operation from the noisy circumstance such as
switch mode power supply.
voltage is higher than the threshold, V
, the output will
ENH
be active while it will be kept low if the voltage is lower than
or pulled down to GND. Internal 2.15 MW pull up
V
ENL
resister is connected between EN pin to 3.3 V reference
EN
IN
50%
tDIS
EN
OUT
90%
OUT
Figure 21. IN, EN, OUT Timing Diagram
Over Current Protection
Once the negative voltage for triggering OCP is detected,
the fault signal is generated initially and delivered to force
NCP51105 provides over current protection features by
detecting the negative voltage at OCP pin. When the voltage
drop across the switching current sensing resister is bigger
internal N
to turn on and then EN pin is discharged fully
FET
to GND. As soon as EN pin voltage is lower than V
, gate
ENL
than threshold voltage, V
, OCP is triggered through
output is terminated immediately as seen in Figure 23. The
time period for whole over current protection is completed
OCP−th
protection procedures in the blanking time, t
. The
BLK
purpose of t
is to disable the over current detection to
within over current protection propagation delay, t
BLK
OCPDEL
avoid triggering OCP by high dv/dt oscillations resulting
from the parasitic LC components of the power switches and
that includes the time delay, t
to low since OCP pin voltage had crossed threshold for t
Once OCP fault condition is removed, the internal N
turned off and EN pin is recharged up to VDD. Figure 22 and
Figure 23 are simplified OCP block diagram in boost
converter and the timing diagram respectively.
until EN signal is kept
OCPFLT
.
BLK
PCB traces. NCP51105 provide t
options (200 ns,
is
BLK
FET
250 and 300 ns) but additional filter composed of C
and
FLT
R
FLT
as seen in Figure 22 might be essential in case an
excessive oscillation is longer than t
and can’t ensure
BLK
normal operation in severe noisy systems.
Vin+
Vout +
VDD
3.3V
Rgate
OUT
PWM
RFLTC
2.15 M
NFET
EN
UVLO
GND
VOCP−th
CFLTC
RCS
RFLT
CFLT
OCP
Vout −
Vin−
Figure 22. Simplified OCP Block Diagram & Boost Application
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11
NCP51105
Fault Reporting and Clear Time
conditions are cleared. After the fault condition is
disappeared, N is turned off and capacitor connected at
As NCP51105 have EN pin and it’s able to report fault
status to external controller with voltage change.
Additionally, external RC network connected at both VDD
and EN pins can be utilized to adjust fault clear time. EN pin
voltage level is changed under fault conditions which OCP
and VDD UVLO are triggered. As long as fault conditions
are occurred, EN pin voltage is pulled down by turning on
FET
EN pin is recharged via voltage sources linked with internal
and external resistors. Therefore, external controller can
recognize the status by monitoring EN pin voltage level. The
time period of EN pin voltage charged via internal and
external voltage sources is programmable by time constant
of R
and C
values as shown in Figure 23 and it can
FLTC
FLTC
internal N
after the delay associated with fault types and
be also be changed by VDD level. The fault clear time,
, can be obtained from following equation.
FET
will be remained to lower level than V
until fault
t
ENL
FLTC
R
FLTC ) 2.15M
RFLTC ) 2.15M
2.15M VDD ) 3.3 V RFLTC
+ * ǒ
Ǔ
lnǒ1 * V
Ǔ
tFLTC
CFLTC
ENH
RFLTC 2.15M
IN
50%
OUT
tOCPDEL
VOCP
VOCP−th
tFLTC
tBLK
tOCPFLT
EN
VENH
50%
NFET OFF
Figure 23. OCP Timing Diagram
Propagation Delay
of 90 % to output level of 10 % as shown in Figure 24.
NCP51105 has short propagation delay, 35 ns (typ) and,
allows to operate system with high frequency and to ensure
tiny pulse distortions.
Propagation delay is defined as the time taking from
changing input logic signal to change gate output and is
expressed as the delay time of ton and toff from input level
50%
IN
ton
tr
toff
tf
90%
10%
OUT
Figure 24. Propagation Delay, Rise and Fall Time
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12
NCP51105
Layout Guidelines
• Current loop paths between Gate driver, VDD and
Power switch should be minimized to keep the parasitic
inductance small because high di/dt and severe voltage
transient are occurred in these loops during switching
operation.
The NCP51105 is a high−speed driver suitable for
mid−high power application. To avoid any damage and/or
malfunction during switching (and/or during transients,
overloads, shorts etc.) proper PCB layout is very important
to avoid a high parasitic inductance in high current paths. It
is recommended to fulfill some rules in layout. One of
possible layouts for the IC is depicted in Figure 25.
• Locate the driver device as close as possible to the
power device to minimize the high current traces
between output pin and gate of power transistor.
• Locate the VDD bypass capacitors between VDD and
GND as close as possible to the driver to ensure noise
filtering. For bypass capacitor, the multi−layer ceramic
capacitor of low inductance SMD type is
recommended.
• Separate power traces and signal trances.
• The star connection of ground is popular way to reduce
noises induced from one current loop to another.
Therefore, GND of the driver should be connected to
the other circuit nodes at single point and the connected
length should be as small as possible to minimize
inductances.
• Do not place low voltage and sensitive traces in the
proximity of HV node.
IN
VDD
GND
HV
MOSFET
CVDD
VDD
OUT
GND
EN
IN
OCP
CFLT
RFLT
Vin −
RSense
Figure 25. Recommended PCB Layout
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13
NCP51105
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
M
C
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
PLANE
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
L
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0°
10°
STYLE 1:
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
STYLE 3:
PIN 1. ENABLE
2. N/C
STYLE 4:
PIN 1. N/C
2. V in
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
STYLE 6:
PIN 1. DRAIN
2. DRAIN
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GATE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
3. R BOOST
4. Vz
5. V in
6. V out
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
4. SOURCE
5. DRAIN
6. DRAIN
4. EMITTER
5. COLLECTOR
6. COLLECTOR
6. COLLECTOR 2
6. COLLECTOR 2
STYLE 7:
STYLE 8:
PIN 1. Vbus
2. D(in)
STYLE 9:
STYLE 10:
PIN 1. D(OUT)+
2. GND
STYLE 11:
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
PIN 1. LOW VOLTAGE GATE
2. DRAIN
PIN 1. SOURCE 1
2. DRAIN 2
3. D(in)+
4. D(out)+
5. D(out)
6. GND
3. SOURCE
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
3. DRAIN 2
4. N/C
5. COLLECTOR
6. EMITTER
4. DRAIN
4. SOURCE 2
5. GATE 1
4. I/O
5. DRAIN
5. VCC
6. I/O
6. HIGH VOLTAGE GATE
6. DRAIN 1/GATE 2
STYLE 13:
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
STYLE 16:
STYLE 17:
PIN 1. EMITTER
2. BASE
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
4. CATHODE/DRAIN
4. DRAIN
4. COLLECTOR
5. ANODE
5. CATHODE/DRAIN
6. CATHODE/DRAIN
5. N/C
6. CATHODE
6. CATHODE
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
XXX MG
G
G
1
1
6X
0.95
3.20
IC
STANDARD
XXX = Specific Device Code
XXX = Specific Device Code
A
Y
W
G
=Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
0.95
PITCH
= Pb−Free Package
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
www.onsemi.com
14
NCP51105
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
onsemi Website: www.onsemi.com
◊
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