NCP51560BBDWR2G_技术文档

DATA SHEET

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5 kV_rms4.5-A/9-A Isolated

Dual Channel Gate Driver

SOIC−16 WB

CASE 751G−03

NCP51560

The NCP51560 are isolated dual−channel gate drivers

with 4.5−A/9−A source and sink peak current respectively. They are

designed for fast switching to drive power MOSFETs, and SiC

MOSFET power switches. The NCP51560 offers short and matched

propagation delays.

MARKING DIAGRAM

16

NCP51560

XY

AWLYYWWG

Two independent and 5 kV internal galvanic isolation from input

rms

to each output and internal functional isolation between the two output

drivers allows a working voltage of up to 1500 V . This driver can be

DC

1

used in any possible configurations of two low side, two high−side

switches or a half−bridge driver with programmable dead time.

An ENA/DIS pin shutdowns both outputs simultaneously when set

low or high for ENABLE or DISABLE mode respectively.

The NCP51560 offers other important protection functions such

as independent under−voltage lockout for both gate drivers and a Dead

Time adjustment function

NCP51560 = Specific Device Code

X

= A or B or C or D for UVLO Option

Y

A

WL

YY

WW

G

= A or B for ENABLE/DISABLE

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

 Flexible: Dual Low−Side, Dual High−Side or Half−Bridge Gate

Driver

PIN ASSIGNMENT

 4.5 A Peak Source, 9 A Peak Sink Output Current Capability

INA

INB

V_DD

1

2

3

4

5

6

7

8

16

V

CCA

 Independent UVLO Protections for Both Output Drivers

 Output Supply Voltage from 6.5 V to 30 V with 5−V and 8−V

for MOSFET, 13−V and 17−V UVLO for SiC, Thresholds.

 Common Mode Transient Immunity CMTI > 200 V/ns

 Propagation Delay Typical 38 ns with

 5 ns Max Delay Matching per Channel

 5 ns Max Pulse−Width Distortion

15 OUTA

14 VSSA

13 NC

GND

ENA/DIS

DT

NCP51560

12 NC

11

V

CCB

NC

10 OUTB

VSSB

 User Programmable Input Logic

 DISABLE Mode

V_DD

9

 User Programmable Dead−Time

 Isolation & Safety

 5 kV Isolation for 1 Minute (per UL1577 Requirements)

ORDERING INFORMATION

See detailed ordering and shipping information on page 28 of

this data sheet.

rms

 8000 V Reinforced Isolation Voltage (per VDE0884−11

PK

Requirements)

 CQC Certification per GB4943.1−2011

 SGS FIMO Certification per IEC 62386−1

 These are Pb−Free Devices

Typical Applications

 Motor Drives

 Isolated Converters in DC−DC and AC−DC Power Supply

 Server, Telecom, and Industrial Infrastructures

 Semiconductor Components Industries, LLC, 2021

1

Publication Order Number:

October, 2022 − Rev. 1

NCP51560/D

NCP51560

TYPICAL APPLICATION CIRCUIT

V_DD

HV Rail

16

15

14

13

PWMA

PWMB

VDD

1

2

3

4

5

6

7

8

INA

INB

V_DD

VCCA

OUTA

VSSA

GND

NC

GND

To Load

ENA

NC 12

ENA/DIS

DT

VCCB 11

V

CC

10

9

NC

OUTB

VSSB

V_DD

(a) High and Low Side MOSFET Gate Drive for ENABLE Version

V_DD

HV Rail

16

15

14

13

1

2

3

4

5

6

7

8

PWMA

PWMB

VDD

INA

INB

V_DD

VCCA

OUTA

VSSA

GND

NC

GND

To Load

ENA

ENA/DIS

DT

NC 12

VCCB 11

V

CC

10

9

NC

OUTB

VSSB

V_DD

(b) High and Low Side MOSFET Gate Drive for DISABLE Version

Figure 1. Application Schematic

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2

NCP51560

FUNCTIONAL BLOCK DIAGRAM

V_DD

VDD UVLO

VCCA

OUTA

VSSA

UVLO

INA

INB

INA

(PWM)

INA

LOGIC

Tx

Rx

INB

(NC)

LOGIC

NC

VDD

Functional

Isolation

ENA/DIS

VCCB

OUTB

VSSB

UVLO

NC

DT

INB

DEAD

TIME

CONTROL

LOGIC

Tx

Rx

GND

(a) For Only ENABLE (NCP51560xA) Version

V_DD

VDD UVLO

VCCA

OUTA

VSSA

UVLO

INA

INB

INA

LOGIC

INA

INB

Tx

Rx

LOGIC

NC

Functional

Isolation

ENA/DIS

VCCB

OUTB

VSSB

NC

UVLO

INB

DEAD

TIME

CONTROL

LOGIC

Tx

Rx

DT

GND

(b) For Only DISABLE (NCP51560xB) Version

Figure 2. Simplified Block Diagram

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3

NCP51560

FUNCTIONAL TABLE

INPUT

UVLO

Output Side

Channel A Channel B

GATE DRIVE OUTPUT

ENA/DIS (Note 3)

Input Side

(V

CCA

)

(V

CCB

)

ENABLE

DISABLE

(V

DD

)

INA

X

INB

X

OUTA

OUTB

X

H

L

X

L

H

L

Active

X

L

X

Active

Inactive

Active

L

X

L

Inactive

L

X

H

X

Active

L

H

L

Inactive

L

H

X

Active

H

L

X

Inactive

L

H

L

H

L

H

L (Note 4)

H (Note 5)

L (Note 4)

H (Note 5)

1. “L” means that LOW, “H” means that HIGH and X: Any Status

2. Inactive means that V , V , and V are above UVLO threshold voltage (Normal operation)

DD

CCA

CCB

Active means that UVLO disables the gate driver output stage.

3. Disables both gate drive output when the ENA/DIS pin is LOW in ENABLE version, which is default is HIGH, if this pin is open.

Enables both gate drive output when the ENA/DIS pin is LOW in DISABLE version, which is default is LOW, if this pin is open.

4. DT pin is left open or programmed with R

.

DT

5. DT pin pulled to V

.

DD

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4

NCP51560

PIN CONNECTIONS

V

1

2

3

4

5

6

7

8

INA

INB

V_DD

16

CCA

OUTA 15

VSSA 14

NC 13

GND

ENA/DIS

DT

NC 12

V

11

OUTB 10

VSSB

CCB

NC

V_DD

9

Figure 3. Pin Connections – SOIC−16 WB (Top View)

PIN DESCRIPTION

Pin No.

Symbol

INA

I/O

Description

Logic Input for Channel A with internal pull−down resistor to GND

Logic Input for Channel B with internal pull−down resistor to GND.

Input−side Supply Voltage.

1

2

Input

Power

INB

3, 8

V

DD

It is recommended to place a bypass capacitor from V to GND.

DD

4

5

GND

Power

Input

Ground Input−side. (all signals on input−side are referenced to this pin)

ENA/DIS

Logic Input High Enables Both Output Channels with Internal pull−up resistor for an ENABLE

version. Conversely, Logic Input High disables Both Output Channels with Internal pull−down

resistor for the DISABLE version.

6

DT

Input

Input for programmable Dead−Time

It provides three kind of operating modes according to the DT pin voltage as below.

Mode−A: Cross−conduction both channel outputs is not allowed even though dead−time is less

than maximum 20 ns when the DT pin is floating (Open).

Mode−B: Dead−time is adjusted according to an external resistance (R ).

DT

t

DT

(in ns) = 10 x R (in kW)

DT

Recommended dead−time resistor (R ) values are between 1 kW and 300 kW.

DT

MODE−C: Cross−conduction both channel outputs is allowed when the DT pin pulled to V

.

DD

7

9

NC

−

No Connection; Keep pin floating.

VSSB

OUTB

Power

Output

Power

Ground for Channel B

10

11

Output for Channel B

V

CCB

Supply Voltage for Output Channel B.

It is recommended to place a bypass capacitor from V

No Connection; Keep pin floating

Ground for Channel A

to VSSB.

to VSSA.

CCB

12, 13

14

NC

−

VSSA

OUTA

Power

Output

Power

15

Output of Channel A

16

V

CCA

Supply Voltage for Output Channel A.

It is recommended to place a bypass capacitor from V

CCA

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5

NCP51560

SAFETY AND INSULATION RATINGS

Symbol

Parameter

Min.

Typ.

Max.

Unit

Installation Classifications per DIN VDE 0110/1.89

Table 1 Rated Mains Voltage

I−IV

−

< 150 VRMS

< 300 VRMS

< 450 VRMS

< 600 VRMS

< 1000 VRMS

−

I−IV

−

I−IV

I−III

−

Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)

Climatic Classification

600

40/125/21

CTI

2

Pollution Degree (DIN VDE 0110/1.89)

Input*to*Output Test Voltage, Method b, VIORM  1.875 = VPR, 100%

Production Test with tm = 1 s, Partial Discharge < 5 pC

−

V

PK

VPR

2250

−

V

VIORM

VIOWM

VIOTM

ECR

Maximum Repetitive Peak Isolation Voltage

Maximum Working Isolation Voltage

Maximum Transient Isolation Voltage

External Creepage

1200

8000

8.0

−

PK

V

DC

V

PK

mm



ECL

External Clearance

8.0

DTI

Insulation Thickness

17.3

9

RIO

Insulation Resistance at T , VIO = 500 V

10

S

UL1577

V

TEST

V

TEST

= V

= 5000 V

ISO

, t = 60 sec. (qualification),

RMS

Withstand

isolation voltage

ISO

RMS

VISO

5000

−

V

RMS

= 1.2V

= 6000 V

, t = 1 sec (100% production)

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6

NCP51560

SAFETY LIMITING VALUE

Symbol

Parameter

Side

Min

−

Typ

−

Max

88

Unit

P

S

Safety Supply Power

Maximum Values in Failure; Input Power

Maximum Values in Failure; Output Power

Maximum Values in Failure; Total Power

P

mW

S,INPUT

P

S,OUT

−

1412

1500

150

P

−

S,TOTAL

T

S

Safety Temperature

Maximum Values in Failure; Case

Temperature

−

C

MAXIMUM RATINGS

Symbol

Parameter

Min

−0.3

Max

Unit

V

DD

to GND

Power Supply Voltage – Input Side (Note 7)

Power Supply Voltage – Driver Side (Note 8)

Driver Output Voltage (Note 8)

5.5

33

V

CCA

– VSSA, V

– VSSB

V

CCB

OUTA to VSSA, OUTB to VSSB

V

+ 0.3,

+ 0.3

V

CCA

CCB

OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns (Note 9)

−2

V

+ 0.3,

+ 0.3

V

CCA

CCB

V

INA and INB

ENA/DIS

Input Signal Voltages (Note 7)

−5

−0.3

−5

20

V

5.5

ENA/DIS Transient for 50ns (Note

9)

DT

Dead Time Control (Note 7)

Channel to Channel Voltage

Junction Temperature

Storage Temperature

−0.3

1500

−40

−65

−

V

DD

+ 0.3

V

VSSA−VSSB, VSSB−VSSA

−

V

T

J

+150

2

C

kV

T

S

Electrostatic

Discharge

Capability

HBM (Note 10)

CDM (Note 10)

Human Body Model

Charged Device Model

−

1

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

7. All voltage values are given with respect to GND pin.

8. All voltage values are given with respect to VSSA or VSSB pin.

9. This parameter verified by design and bench test, not tested in production.

10.This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)

Latch up Current Maximum Rating: 100 mA per JEDEC standard: JESD78F.

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NCP51560

RECOMMENDED OPERATING CONDITIONS

Symbol

Rating

Min

3.0

6.5

9.5

14.5

18.5

0

Max

5.0

30

Unit

V

DD

Power Supply Voltage – Input Side

Power Supply Voltage – Driver Side

V

, V

CCB

5−V UVLO Version

V

CCA

8−V UVLO Version

13−V UVLO Version

17−V UVLO Version

30

V

30

V

30

V

IN

Logic Input Voltage at Pins INA, and INB

Logic Input Voltage at Pin ENA/DIS

Ambient Temperature

18

V

0

5.0

+125

V

ENA/DIS

T

A

−40

_C

T

J

Junction Temperature

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

THERMAL CHARACTERISTICS

Symbol

Rating

Condition

Value

Unit

2

R

Thermal Characteristics, (Note 12)

Thermal Resistance Junction−Air

16−SOIC−WB

100 mm , 1 oz Copper, 1 Surface Layer (1S0P)

120

81

C/W

q

JA

2

100 mm , 2 oz Copper, 1 Surface Layer (1S0P)

2

Thermal Resistance Junction−Case

Thermal Resistance Junction−to−Top

Thermal Resistance Junction−to−Board

100 mm , 1 oz Copper, 1 Surface Layer (1S0P)

38

18

55

C/W

W

R

q

JC

Y

JT

JB

2

P

Power Dissipation (Note 12)

16−SOIC−WB

100 mm , 1 oz Copper, 1 Surface Layer (1S0P)

0.8

1.5

D

2

100 mm , 2 oz Copper, 1 Surface Layer (1S0P)

11. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

12.JEDEC standard: JESD51−2, and JESD51−3.

ISOLATION CHARACTERISTICS

Symbol

Parameter

Condition

T = 25C, Relative Humidity < 50%,

Min

Typ

Max

Unit

V

Input to Output Isolation Voltage

−

V

RMS

ISO,INPUT TO

OUTPUT

A

5000

−

t = 1.0 minute, I

10 A, 50 Hz

O

*

I

(Notes 13, 14, 15)

V

OUTA to OUTB Isolation Voltage

Isolation Resistance

−

V

DC

ISO,OUTA TO

OUTB

1500

−

11

R



ISO

V

I_O

= 500 V (Note 13)

10

−

13.Device is considered a two*terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together for input to output isolation

test, and pins 9 to 11 are shorted together and pins 14 to 16 are shorted together for between channel isolation test.

14.5,000 V

for 1*minute duration is equivalent to 6,000 V

for 1*second duration for input to output isolation test,

RMS

and Impulse Test > 10 ms; sample tested for between channel isolation test.

15.The input*output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input*output continuous voltage

rating. For the continuous working voltage rating, refer to equipment*level safety specification or DIN VDE V 0884*11 Safety and Insulation

Ratings Table

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8

NCP51560

ELECTRICAL CHARACTERISTICS (V = 5 V, V

= V

= 12 V, or 20 V (Note 17) and VSSA = VSSB, for typical values

DD

CCA

CCB

T = T = 25C, for min/max values T = −40C to +125C, unless otherwise specified. (Note 16)

J

A

J

Symbol

Parameter

Condition

Min

Typ

Max

Unit

PRIMARY POWER SUPPLY SECTION (V

)

DD

V

= V

DISABLE

= 0 V, V

= V

DD

500

7

780

820

12

1000

16

mA

V

I

V

Quiescent Current

INA

or V

INB

ENABLE

QVDD

DD

= 0 V

V

= V

= 5 V, V

= 0 V

INA

INB

ENABLE

or V

= V

DISABLE

DD

V

= V

DISABLE

= 5 V, V

= 0 V

= V

ENABLE DD

INA

INB

or V

I

V

Operating Current

f = 500 kHz, 50% duty cycle,

IN

C

5.0

2.7

2.6

−

7.15

2.8

9.0

2.9

2.8

−

VDD

DD

= 100 pF

OUT

V

Supply Under−Voltage Positive−Going

V

DD

V

DD

V

DD

= Sweep

DDUV+

DDUV−

DDHYS

DD

Threshold

V

DD

Supply Under−Voltage Negative−Going

2.7

V

Threshold

V

DD

Supply Under−Voltage Lockout Hysteresis

0.1

V

SECONDARY POWER SUPPLY SECTION (V

AND V

)

CCA

CCB

V

= V

= 0 V, per channel

200

300

2.0

280

410

3.0

500

600

5.5

mA

I

V

and V

Quiescent Current

INA

INB

QVCCA

QVCCB

CCA

CCB

= 5 V, per channel

INA

INB

I

V

and V

Operating Current

Current per channel (f = 500 kHz,

50% duty cycle), C

mA

VCCA

VCCB

CCB

IN

OUT

= 100 pF

VCCA and VCCB UVLO THRESHOLD (5−V UVLO VERSION)

V

and V Supply Under−Voltage

CCB

5.7

5.4

6.0

5.7

6.3

6.0

V

CCAUV+

CCBUV+

CCA

Positive−Going Threshold

V

CCA

and V

Supply Under−Voltage

CCAUV−

CCBUV−

CCB

Negative−Going Threshold

V

Under−Voltage Lockout Hysteresis

Under−Voltage Debounce Time (Note 18)

−

0.3

−

V

CCHYS

t

−

10

ms

UVFLT

VCCA and VCCB UVLO THRESHOLD (8−V UVLO VERSION)

V

and V Supply Under−Voltage

CCB

8.3

7.8

8.7

8.2

9.2

8.7

V

CCAUV+

CCBUV+

CCA

Positive−Going Threshold

V

CCA

and V

Supply Under−Voltage

CCAUV−

CCBUV−

CCB

Negative−Going Threshold

V

Under−Voltage Lockout Hysteresis

Under−Voltage Debounce Time (Note 18)

−

0.5

−

V

CCHYS

t

−

10

ms

UVFLT

VCCA and VCCB UVLO THRESHOLD (13−V UVLO VERSION)

V

and V Supply Under−Voltage

CCB

12

11

13

12

14

13

V

CCAUV+

CCBUV+

CCA

Positive−Going Threshold

V

CCA

and V

Supply Under−Voltage

CCAUV−

CCBUV−

CCB

Negative−Going Threshold

V

Under−Voltage Lockout Hysteresis

Under−Voltage Debounce Time (Note 18)

−

1

−

V

CCHYS

t

−

10

ms

UVFLT

VCCA and VCCB UVLO THRESHOLD (17−V UVLO VERSION)

V

and V Supply Under−Voltage

CCB

16

15

17

16

18

17

V

CCAUV+

CCBUV+

CCA

Positive−Going Threshold

V

CCA

and V

Supply Under−Voltage

CCAUV−

CCBUV−

CCB

Negative−Going Threshold

V

Under−Voltage Lockout Hysteresis

Under−Voltage Debounce Time (Note 18)

−

1

−

V

CCHYS

t

−

10

ms

UVFLT

LOGIC INPUT SECTION (INA, AND INB)

V

High Level Input Voltage

Low Level Input Voltage

1.4

0.9

1.6

1.1

1.8

1.3

V

INH

V

INL

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NCP51560

ELECTRICAL CHARACTERISTICS (V = 5 V, V

= V

= 12 V, or 20 V (Note 17) and VSSA = VSSB, for typical values

DD

CCA

CCB

T = T = 25C, for min/max values T = −40C to +125C, unless otherwise specified. (Note 16) (continued)

J

A

J

Symbol

Parameter

Condition

Min

Typ

Max

Unit

LOGIC INPUT SECTION (INA, AND INB)

V

Input Logic Hysteresis

−

20

−

0.5

25

−

V

INHYS

I

High Level Logic Input Bias Current

Low Level Logic Input Bias Current

Logic Input Pull−Down Resistance

V

= 5 V

= 0 V

33

mA

kW

IN+

IN

1.0

250

IN−

IN

R

150

200

IN

LOGIC INPUT SECTION (for ENABLE Version only)

V

Enable High Voltage

Enable Low Voltage

Enable Logic Hysteresis

1.4

0.9

−

1.6

1.1

0.5

1.8

1.3

−

V

ENAH

V

ENAL

V

ENAHYS

LOGIC INPUT SECTION (for DISABLE Version only)

V

Disable High Voltage

Disable Low Voltage

Disable Logic Hysteresis

1.4

0.9

−

1.6

1.1

0.5

1.8

1.3

−

V

DISH

V

DISL

V

DISHYS

DEAD−TIME AND OVERLAP SECTION

t

Minimum Dead−Time

Dead−Time

DT pin is left open

0

10

200

1000

−

29

255

1200

30

ns

V

DT,MIN

145

800

−30

−150

t

DT

R

DT

R

DT

R

DT

R

DT

= 20 kW

= 100 kW

= 20 kW

= 100 kW

Dt

DT

Dead−Time Mismatch between OUTB  OUTA

and OUTA  OUTB

−

150

0.95x

V

DT Threshold Voltage for OUTA & OUTB

Overlap

0.85x 0.9xV

DD

DT,SHORT

V

DD

V

DD

GATE DRIVE SECTION

I

OUTA and OUTB Source Peak Current

(Note 18)

V

= V

= 5 V, PW  5 ms

= 0 V, PW  5 ms

2.6

7.0

4.5

9.0

A

OUTA+,

OUTB+

INA

INB

−

I

OUTA and OUTB Sink Peak Current (Note 18)

OUTA−,

OUTB−

INA

INB

R

Output Resistance at High State

Output Resistance at Low State

I

= 100 mA

−

1.4

0.5

−

2.7

1.0

W

OH

OUTH

R

OL

OUTL

V

High Level Output Voltage (V

− V

)

= 100 mA

270

100

mV

OHA, OHB

CCX

OUTX

OUT

V

Low Level Output Voltage (V

− V )

SSX

−

OLA, OLB

OUTX

DYNAMIC ELECTRICAL CHARACTERISTICS

V

CCA

V

CCA

V

CCA

V

CCA

= V

= 12 V, C

= 0 nF

24

27

24

27

38

41

38

41

57

60

57

60

t

Turn−On Propagation Delay from INx to OUTx

Turn−Off Propagation Delay from INx to OUTx

CCB

LOAD

PDON

ns

= 20 V, C

= 12 V, C

= 20 V, C

t

PDOFF

t

Pulse Width Distortion (t

– t )

PDOFF

−5

−

5

ns

PWD

PDON

t

Propagation Delay Mismatching between

Channels

INA and INB shorted,

= 100 kHz

DM

f

IN

t

Power−up Delay from the V

to Output

See the Figure 52

−

18

9

−

ms

ns

VPOR to OUT

POR

(Note 18)

V

= V = 12 V,

LOAD

16

19

16

19

t

R

Turn−On Rise Time

CCA

CCB

C

= 1.8 nF

V

= V

LOAD

= 20 V,

11

8

CCA

CCB

C

= 1.8 nF

V

= V

LOAD

= 12 V,

t

F

Turn−Off Fall Time

CCA

CCB

C

= 1.8 nF

V

= V

LOAD

= 20 V,

10

CCA

CCB

C

= 1.8 nF

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10

NCP51560

ELECTRICAL CHARACTERISTICS (V = 5 V, V

= V

= 12 V, or 20 V (Note 17) and VSSA = VSSB, for typical values

DD

CCA

CCB

T = T = 25C, for min/max values T = −40C to +125C, unless otherwise specified. (Note 16) (continued)

J

A

J

Symbol

Parameter

Condition

Min

Typ

Max

Unit

DYNAMIC ELECTRICAL CHARACTERISTICS

24

27

−

38

41

15

57

60

30

ns

T

ENABLE or DISABLE to OUTx Turn−On/Off

ENABLE,OUT,

DISABLE,OUT

V

= V

= 12 V

= 20 V

CCA

CCB

T

Propagation Delay

CCA

CCB

t

Minimum Input Pulse Width that Change

Output State

C

= 0 nF

PW

LOAD

CMTI

Common Mode Transient Immunity

(Note 18)

Slew rate of GND versus VSSA

and VSSB. INA and INB both are

200

−

V/ns

tied to V or GND. V = 1500 V

DD

CM

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

16.Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25C.

J

A

17.V

= V

= 12 V is used for the test condition of 8−V UVLO, V

= V

= 20 V is used for 17−V UVLO.

CCA

CCB

CCA

CCB

18.These parameters are verified by bench test only and not tested in production.

INSULATION CHARACTERISTICS CURVES

80

70

60

50

40

30

20

10

0

1800

IVCCA/B for V = 12 V

1600

1400

1200

1000

800

600

400

200

0

CC

IVCCA/B for V = 33 V

CC

0

25

50

75

100

125

150

200

0

25

50

75

100

125

150

200

Ambient Temperature [5C]

Figure 4. Thermal Derating Curve for Safety−related

Limiting Current (Current in Each Channel with

Both Channels Running Simultaneously)

Figure 5. Thermal Derating Curve for

Safety−related Limiting Power

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11

NCP51560

TYPICAL CHARACTERISTIC

Figure 6. Quiescent V_DDSupply Current vs. Temperature

Figure 7. Quiescent V_DDSupply Current vs.

Temperature (V_DD= 5 V,

INA = INB = ENA/DIS = 5 V and No Load)

(V_DD= 5 V, INA = INB = 0 V, ENA/DIS = 5 V or,

INA = INB = 5 V, ENA/DIS = 0 V and No Load)

Figure 8. V_DDOperating Current vs.

Temperature (V_DD= 5 V, No Load, and

Switching Frequency = 500 kHz)

Figure 9. V_DDOperating Current vs.

Temperature (V_DD= 5 V, No Load, and

Different Switching Frequency)

Figure 10. Per Channel V_DDOperating Current vs.

Temperature (V_DD= 5 V, No Load, and Different

Switching Frequency

Figure 11. Per Channel Quiescent V_CCSupply Current

vs. Temperature (INA = INB = 0 V or 5 V, ENA/DIS = 5 V

and No Load

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12

NCP51560

TYPICAL CHARACTERISTIC (CONTINUED)

Figure 12. Per Channel V_CCOperating

Current vs. Temperature (No Load and

Switching Frequency = 500 kHz

Figure 13. Per Channel Operating Current vs.

Frequency (No Load, V_CCA= V_CCB= 12 V, or 25 V)

Figure 14. Per Channel Operating Current vs.

Frequency (C_LOAD= 1 nF, V_CCA= V_CCB= 12 V, or 25 V)

Figure 15. Per Channel Operating Current vs.

Frequency (C_LOAD= 1.8 nF, V_CCA= V_CCB= 12 V, or 25 V)

Figure 16. Per Channel V_CCQuiescent Current vs.

Figure 17. Per Channel V_CCQuiescent Current vs.

V

_CCSupply Voltage (INA = INB = 0 V, ENA = 5 V)

V_CCSupply Voltage (INA = INB = 5 V, ENA = 5 V)

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13

NCP51560

TYPICAL CHARACTERISTIC (CONTINUED)

Figure 18. V_DDUVLO Threshold vs. Temperature

Figure 19. V_DDUVLO Hysteresis vs. Temperature

Figure 20. V_CC5−V UVLO Threshold vs. Temperature

Figure 21. V_CC5−V UVLO Hysteresis vs. Temperature

Figure 22. V_CC8−V UVLO Threshold vs. Temperature

Figure 23. V_CC8−V UVLO Hysteresis vs. Temperature

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14

NCP51560

TYPICAL CHARACTERISTIC (CONTINUED)

Figure 24. V_CC13−V UVLO Threshold vs. Temperature

Figure 25. V_CC13−V UVLO Hysteresis vs. Temperature

Figure 26. V_CC17−V UVLO Threshold vs. Temperature

Figure 27. V_CC17−V UVLO Hysteresis vs. Temperature

Figure 28. Output Current vs. V_CCSupply Voltage

Figure 29. ENA/DIS Delay Time vs. Temperature

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15

NCP51560

Figure 30. Input Logic Threshold vs. Temperature

Figure 31. Input Logic Hysteresis vs. Temperature

(INA, and INB)

Figure 32. ENA/DIS Threshold vs. Temperature

(ENABLE, and DISABLE)

Figure 33. ENA/DIS Hysteresis vs. Temperature

(ENABLE, and DISABLE)

Figure 34. Rise/Fall Time vs. Temperature

(C_LOAD= 1.8 nF)

Figure 35. Rise/Fall Time vs. Temperature

(V_CC= V_CCB= 12 V, and Different Load)

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16

NCP51560

TYPICAL CHARACTERISTIC (CONTINUED)

Figure 36. Dead Time vs. Temperature

Figure 37. Dead Time vs. Temperature

(R_DT= Open)

(R_DT= 100kW)

Figure 38. Dead Time Mismatching vs. Temperature

Figure 39. Dead Time vs. R_DT

Figure 40. Turn−on Propagation Delay vs.

Figure 41. Turn−off Propagation Delay vs.

Temperature

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17

NCP51560

TYPICAL CHARACTERISTIC (CONTINUED)

Figure 42. Pulse Width Distortion vs. Temperature

Figure 43. Propagation Delay Matching vs.

Temperature

Figure 44. Turn−on Propagation Delay vs. V_CC

Figure 45. Turn−off Propagation Delay vs. V_CC

Supply Voltage

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18

NCP51560

PARAMETER MEASUREMENT DEFINITION

Switching Time Definitions

output signals OUTA, OUTB. The typical values of the

propagation delay (t , T ), pulse width distortion

Figure 46 shows the switching time definitions of the

turn−on (t ) and turn−off (t ) propagation delay

PDON PDOFF

(t

) and delay matching between channels times are

PDON

PDOFF

PWD

time among the driver’s two input signals INA, INB and two

specified in the electrical characteristics table.

V_INH

INA

V_INL

(INB)

t_PDON

t_PDOFF

90%

OUTA

(OUTB)

10%

t_F

t_R

Figure 46. Switching Time Definitions

Enable and Disable Function

Figure 47 shows the response time according to an

ENABLE or the DISABLE operating modes. If the

ENA/DIS pin voltage goes to LOW state, i.e. V

shuts down both outputs simultaneously and Pull the

operate normally in an ENABLE mode as shown in

Figure 47 (a). Conversely, if the ENA/DIS pin voltage goes

to HIGH state, i.e. V

 1.6 V shuts down both outputs

DIS

 1.1 V

simultaneously and Pull the ENA/DIS pin LOW (or left

open), i.e. V  1.1 V operate normally in the DISABLE

ENA

DIS

ENA/DIS pin HIGH (or left open), i.e. V

 1.6 V to

mode as shown in Figure 47 (b).

ENA

INA

(INB)

V_ENAH

ENA/DIS

(ENABLE)

V_ENAL

ENABLE low response time

90%

ENABLE high response time

OUTA

(OUTB)

10%

(a) ENABLE Version

INA

(INB)

V_DISH

ENA/DIS

V

INH

(DISABLE)

DISABLE high response time

90%

DISABLE low response time

OUTA

(OUTB)

10%

(b) DISABLE Version

Figure 47. Timing Chart of Enable and Disable Function

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19

NCP51560

Programmable Dead−Time

DT2). Otherwise, if the external input signal dead times are

larger than internal dead− time, the dead time is not modified

by the gate driver and internal dead−time definition as

shown in Figure 48.

Dead time is automatically inserted whenever the dead

time of the external two input signals (between INA and INB

signals) is shorter than internal setting dead times (DT1 and

INA

INB

90%

10%

OUTB

DT1

DT2

OUTA

90%

10%

Figure 48. Internal Dead−Time Definitions

Figure 49 shows the definition of internal dead time and

shoot−through prevention when input signals applied at

same time.

Case − A

Case−B

Case−C

Case−E

INA

INB

Shoot−Through

Prevention

DT

TRIG_INA

TRIG_INB

V_DT

Timer_Cap

OUTA

OUTB

Dead − Time

Shoot−Through Prevention

Gate Driver Output OFF

Case – A : Control signal edges overlapped, but inside the dead−time (Dead−Time)

Case – B : Control signal edges overlapped, but outside the dead−time (Shoot−Through)

Case – C : Control signal edges synchronous (Dead−Time)

Case – D : Control signal edges not overlapped, but inside the dead−time (Dead−Time )

Case – E : Control signal edges not overlapped, but outside the dead−time (Direct Drive)

Figure 49. Internal Dead−Time Definitions

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20

NCP51560

DEVICE INFORMATION

Input to Output Operation Definitions

The NCP51560 provides important protection functions

such as independent under−voltage lockout for both gate

driver; enable or disable function and dead−time control

function. Figure 50 shows an overall input to output timing

diagram when shutdown mode via ENA/DIS pin in the

CASE−A, and Under−Voltage Lockout protection on the

primary− and secondary−sides power supplies events in the

CASE−B. The gate driver output (OUTA and OUTB) were

turn−off when cross−conduction event at the dead time

control mode in the CASE−C.

A

B

C

INA

INB

ENA/DIS

(ENABLE)

Shutdown

ENA/DIS

(DISABLE)

V_DDUV+

V_DD

V_DDUV−

Shoot−Through

(V_CCA, V_CCB

)

Prevention

UVLO

OUTA

OUTB

DT DT

Figure 50. Overall Operating Waveforms Definitions at the Dead−Time Control Mode

Input and Output Logic Table

Table 1 shows an input to output logic table according to

the dead time control modes and an enable or the disable

operation mode.

Table 1. INPUT AND OUTPUT LOGIC TABLE

INPUT

OUTPUT

ENA/DIS

ENABLE

H or Left open

L

DISABLE

L or Left open

H

INA

INB

OUTA

OUTB

NOTE

L

H

L

Programmable dead time control with R .

DT

L

H

L

H

L

H

L

DT pin is left open Or programmed with R .

DT

H

Left open

X

H

Left open

X

H

L

H

L

DT pin pulled to V

.

DD

L

19.“X” means L, H or left open.

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21

NCP51560

PROTECTION FUNCTION

channel supply voltages in secondary−side (e.g. V

, and

CCA

The NCP51560 provides the protection features include

enable or disable function, Cross Conduction Protection,

and Under−Voltage Lockout (UVLO) of power supplies on

V

) need to be greater than specified UVLO threshold

CCB

level in secondary−side to let the output operate per input

signal. The typical V UVLO threshold voltage levels for

each option are per below Table 2.

CCx

primary−side (V ), and secondary−side both channels

DD

(V

, and V ).

CCB

CCA

Table 2. V_CCxUVLO OPTION TABLE

Under−Voltage Lockout Protection V_DDand V_CCx

The NCP51560 provides the Under−Voltage Lockout

Option

5−V

V

CC

UVLO Level

Unit

V

(UVLO) protection function for V in primary−side and

DD

6.0

8.7

13

both gate drive output for V

and V

in

CCA

CCB

8−V

V

secondary−side as shown in Figure 51.

13−V

17−V

V

The gate driver is running when the V supply voltage

DD

is greater than the specified under−voltage lockout threshold

voltage (e.g. typically 2.8 V) and ENA/DIS pin is HIGH or

LOW states for an ENABLE (e.g. NCP51560xA) or the

DISABLE (e.g. NCP51560xB) mode respectively.

17

V

UVLO protection has an hysteresis to provide immunity

to short V drops that can occur.

CC

In addition, both gate output drivers have independent

under voltage lockout protection (UVLO) function and each

Figure 51. Timing Chart Under−Voltage Lockout Protection

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22

NCP51560

Power−Up VCC UVLO Delay to OUTPUT

To provide a variety of Under−Voltage Lockout (UVLO)

thresholds NCP51560 has a power−up delay time during

power−on reset (POR) threshold to output and it is defined

as t . (e.g. typically 18 ms). Figure 52 shows the

VPOR to OUT

initial V

start−up or after POR event.

power−up UVLO delay time diagram for V

.

CCX

CC

Before the gate driver is ready to deliver a proper output

state, there is a power−up delay time from the V

CC

Figure 52. Timing VCC Power−Up UVLO Delay Time

Cross−Conduction Prevention and Allowed

Overlapped Operation

For full topologies flexibility, cross conduction can be

allowed both high− and low−side switches conduct at the

The cross conduction prevents both high− and low−side

switches from conducting at the same time when the dead

time (DT) control mode is in half−bridge type, as shown in

Figure 53.

same time when the DT pin is pulled to V for example, as

DD

shown in Figure 54.

INA

INB

Allowed Overlap

Operation

Shoot−Through

Prevent

DT

After DT

OUTA

OUTB

OUTA

OUTB

(a) In case of Shoot−Through

(b) In case of Shoot−Through

(a) In case of Shoot−Through

(b) In case of Shoot−Through

less than DT

longer than DT

less than DT

longer than DT

Example A

INA

INB

INA

INB

Allowed Overlap

Operation

Shoot−Through

Prevent

DT

OUTA

OUTB

OUTA

OUTB

Always LOW

(a) In case of Shoot−Through

(b) In case of Shoot−Through

(a) In case of Shoot−Through

less than DT

(b) In case of Shoot−Through

less than DT

longer than DT

Example B

Figure 53. Concept of Shoot−Through Prevention

Figure 54. Concept of Allowed the Shoot−Through

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23

NCP51560

Programmable Dead Time Control

Cross−conduction between both driver outputs (OUTA,

and OUTB) is not allowed with minimum dead time

MODE−B. Overlap is not allowed when the dead time (DT)

control mode is activated.

The dead time (DT) between both outputs is set according

(t

) typically 10 ns when the DT pin is open in the

to: DT (in ns) = 10 x R (in k).

DTMIN

DT

MODE−A. External resistance (R ) controls dead time

Overlap is allowed for both outputs when the DT pin is

DT

when the DT pin resistor between 1 kW and 300 kW in the

pulled to V in the MODE−C, as shown in Figure 55.

DD

t_DT[ns]

Output Overlap ENABLED

MODE C – DT pin pull to V_DD

t_DT=0 ns

Minimum Dead−time

MODE A – DT pin Open

t

_DT=10 ns

Cross−conduction prevention disabled

Cross−conduction prevention active

3000

2500

Dead−time Control Range

MODE B – 1 kW <R_DT<300 kW

t_DT[ns]=10 · R_DT[kW]

Cross−conduction prevention active

2000

1500

1000

500

0

300

150

R_DT[kW]

200

250

1

50

100

Figure 55. Timing Chart of Dead−Time Mode Control

Common Mode Transient Immunity Testing

CMTI applies to both rising and falling common−mode

voltage edges. CMTI is tested with the transient generator

connected between GND and VSSA and VSSB.

Figure 56 is a simplified diagram of the Common Mode

Transient Immunity (CMTI) testing configuration.

CMTI is the maximum sustainable common−mode

voltage slew rate while maintaining the correct output.

(V = 1500 V)

CM

V_DD

V_CC

16

INA

VCCA

OUTA

15

14

INB

OUTA

VSSA

V_DD

Monitor V

V_DD

NC 13

NC 12

GND

ENA/DIS

DT

11

VCCB

OUTB

NC

OUTB 10

Monitor V

V_DD

VSSB 9

1.5 kV

0 V

dV/dt

Common Mode Surge

Generator

Figure 56. Common Mode Transient Immunity Test Circuit

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24

NCP51560

APPLICATION INFORMATION

V

DD

This section provides application guidelines when using

the NCP51560.

R1

R2

INA

INB

1

2

Power Supply Recommendations

It is important to remember that during the Turn−On of

switch the output current to the gate is drawn from the V

INA

INB

C1

C2

200 kW

CCA

pins should be

and V

supply pins. The V

and V

CCB

CCA

CCB

bypassed with a capacitor with a value of at least ten times

the gate capacitance, and no less than 100 nF and located as

close to the device as possible for the purpose of decoupling.

A low ESR, ceramic surface mount capacitor is necessary.

We recommend using 2 capacitors; a 100 nF ceramic

surface−mount capacitor which can be very close to the pins

of the device, and another surface−mount capacitor of few

microfarads added in parallel.

V

DD

3

4

5

C3

C4

V

DD

GND

200 kW

ENA/DIS

ENABLE

Input Stage

The input signal pins (INA, INB, and ENA/DIS) of the

NCP51560 are based on the TTL compatible

Figure 57. Schematic of Input Stage

Output Stage

input−threshold logic that is independent of the V supply

DD

The output driver stage of the NCP51560 features a pull

up structure and a pull down structure.

The pull up structure of the NCP51560 consists of a

voltage. The logic level compatible input provides a

typically high and low threshold of 1.6 V and 1.1 V

respectively. The input signal pins impedance of the

NCP51560 is 200 kW typically and the INA, and INB, pins

PMOS stage ensuring to pull all the way to the V rail. The

CC

pull down structure of the NCP51560 consists of a NMOS

device as shown in Figure 58.

The output impedance of the pull up and pull down

switches shall be able to provide about +4.5 A and −9 A peak

currents typical at 25C and the minimum sink and source

peak currents at 125C are −7 A sink and +2.6 A source.

are pulled to GND pin and ENA/DIS pin is pulled to V pin

for an ENABLE version as shown in Figure 57. Conversely,

ENA/DIS pin pulled to GND pin for the DISABLE version.

DD

It is recommended that ENA/DIS pin should be tie to V

DD

or GND pins for ENABLE and DISABLE versions

respectively if the ENA/DIS pin is not used to achieve better

noise immunity because the ENA/DIS pin is quite

responsive, as far as propagation delay and other switching

parameters are concerned.

V_CCx

An RC filter is recommended to be added on the input

signal pins to reduce the impact of system noise and ground

bounce, the time constant of the RC filter. Such a filter

VCC UVLO

LOGIC

OUTx

V_SSx

Rx

INx

Tx

should use an R in the range of 0 W to 100 W and a C

IN

between 10 pF and 100 pF. In the example, an R = 51 W

IN

GND

and a C = 33 pF are selected, with a corner frequency of

IN

approximately 100 MHz. When selecting these

components, it is important to pay attention to the trade−off

between good noise immunity and propagation delay.

Figure 58. Schematic of Output Stage

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25

NCP51560

Consideration of Driving Current Capability

where:

Peak source and sink currents (I , and I

SOURCE

)

SINK

I

: Source peak current

SOURCE

capability should be larger than average current (I

shown in Figure 59.

) as

G, AV

: Sink peak current.

SINK

V

: High level output voltage drop

: Low level output voltage drop

OH

OL

I_SOURCE

I_G,AV

Application Circuits with Output Stage Negative Bias

SiC MOSFET unique operating characteristics need to be

carefully considered to fully benefits from SiC

characteristics. The gate driver needs to be capable of

providing +20 V and −2 V to −5 V negative bias with

minimum output impedance and high current capability.

When parasitic inductances are introduced by non−ideal

PCB layout and long package leads (e.g. TO−220 and

TO−247 type packages), there could be ringing in the

gate−source drive voltage of the power transistor during

high di/dt and dv/dt switching. If the ringing is over the

threshold voltage, there is the risk of unintended turn−on and

even shoot−through. Applying a negative bias on the gate

drive is a popular way to keep such ringing below the

threshold. Negative voltage can improve the noise tolerance

of SiC MOSFET to suppress turning it unintentionally. The

negative gate−source voltage makes the capacitance of Cgd

becoming lower, which can reduce the ringing voltage.

Below are a few examples of implementing negative gate

drive bias. The first example with negative bias with two

isolated−bias power supplies as shown in Figure 60.

I_SINK

V_GS

T_SW,OFF

T_SW,ON

Figure 59. Definition of Current Driving Capability

The approximate maximum gate charge Q that can be

switched in the indicated time for each driver current rating

may be calculate: Needed driver current ratings depend on

G

what gate charge Q must be moved in what switching time

G

t

because average gate current during switching

SW−ON/OFF

is I .

G

Q_G

I_G.AV

+

(eq. 1)

t_SW,ONńOFF

The approximate gate driver source and sink peak currents

can be calculated as below equations

Power supply VHx determines the positive drive output

voltage and VLx determines the negative turn−off voltage

for each channels. This solution requires more power

supplies than the conventional bootstrapped power supply

example; however, it provides more flexibility when setting

the positive, VHx, and negative, VLx, rail voltages.

At turn−on (Sourcing current)

Q_G

I

_SOURCE 1.5

(eq. 2)

(eq. 3)

t_SW,ON

At turn−off (Sinking current)

V_DD

HV Rail

Q_G

I

_SINK 1.5

t_SWOFF

PWMA

PWMB

VDD

1

INA

INB

V_DD

VCCA 16

VHA

VLA

OUTA

VSSA

2

3

4

15

14

where,

Q = Gate charge at V = V

G

GS

CC

GND

NC 13

GND

ENA/DIS

DT

t

= Switch On / Off time

SW, ON/OFF

To Load

ENA

5

6

7

8

12

11

NC

1.5 = empirically determined factor

VCCB

VHB

VLB

(Influenced by I vs. I , and circuit parasitic)

NC

OUTB 10

VSSB

G,AV

DRV

V_DD

9

Consideration of Gate Resistor

The gate resistor is also sized to reduce ringing voltage by

parasitic inductances and capacitances. However, it limits

the current capability of the gate driver output. The limited

current capability value induced by turn−on and off gate

resistors can be obtained with below equation.

Figure 60. Negative Bias with Two Isolated−Bias

Power Supplies

Figure 61 shows another example with negative bias

turn−off on the gate driver using a Zener diode on an isolated

power supply. The negative bias set by the voltage of Zener

diode. For example, if the isolated power supply, VHx for

V

_CC* V_OH

I_SOURCE

+

R_G,ON

(eq. 4)

V

_CC* V_OL

I_SINK

+

R_G,OFF

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26

NCP51560

PCB Layout Guideline

each channels, the turn−off voltage will be –5.1 V and

turn−on voltage will be 20 V − 5.1 V  15 V.

To improve the switching characteristics and efficiency of

design, the following should be considered before beginning

a PCB layout.

V_DD

HV Rail

Component Placement

PWMA

PWMB

VDD

1

INA

INB

VCCA 16

OUTA 15

R_ZA

2

3

4

 Keep the input/output traces as short as possible.

Minimize influence of the parasitic inductance and

capacitance on the layout. (To maintain low signal−path

inductance, avoid using via.)

14

VSSA

V_DD

Z_A

VHA

GND

NC 13

NC 12

GND

ENA/DIS

DT

To Load

ENA

5

6

7

8

VCCB

11

R_ZB

 Placement and routing for supply bypass capacitors for

ANB

V_DD

OUTB 10

V

DD

and V , and gate resistors need to be located as

CC

VSSB

9

close as possible to the gate driver.

Z_B

VHB

 The gate driver should be located switching device as

close as possible to decrease the trace inductance and

avoid output ringing.

Figure 61. Negative Bias with Zener Diode on

Single Isolated−Bias Power Supply

Grounding Consideration

 Have a solid ground plane underneath the high−speed

signal layer.

Moreover, this configuration could easily be changed

negative bias by a using different Zener diode with the same

20 V isolated power supply. This configuration needs two

isolated power supplies for a half−bridge configuration, but

this scheme is very simple.

 Have a solid ground plane next to V

and VSSB pins

SSA

with multiple V

and VSSB vias to reduce the parasitic

SSA

inductance and minimize the ringing on the output

signals.

However, it has the disadvantage of having a steady state

power consumption from R . Therefore, one should be

Zx

careful in selecting the R values. It is recommended that

High−Voltage (V ) Consideration

Zx

ISO

R

allow the minimal current flow to stabilize the Zener

Zx

 To ensure isolation performance between the primary and

secondary side, any PCB traces or copper should be not

placed under the driver device as shown in Figure 63. A

PCB cutout is recommended to avoid contamination that

may impair the isolation performance of NCP51560.

clamping voltage (e.g. I : 5 mA~10 mA).

Z

Typical recommended values are in the few kohm range

(e.g. 1 k~4.7 k) of SiC MOSFETs application.

Experimental Results

Figure 62 show the experimental results of the negative

bias with Zener diode on single isolated power supply of the

NCP51560 for SiC MOSFET gate drive application. The

examples were design to have a +15 V and −5.1 V drive

power supply referenced to the device source by using the

20 V isolated power supply.

High−speed signal

10 mils

0.25 mm

10 mils

0.25 mm

Ground plane

Keep this space free

from traces, pads

and vias

40 mils

1 mm

40 mils

1 mm

Power plane

10 mils

0.25 mm

Low−speed signal

314 mils

8 mm

Figure 63. Recommended Layer Stack

CH1: INPUT [2V/div], and CH2: OUTPUT [5 V/div]

Figure 62. Experimental Waveforms of Negative Bias

with Zener Diode on Single Isolated Power Supply

www.onsemi.com

27

NCP51560

Figure 64 shows the printed circuit board layout of

NCP51560 evaluation board.

(a) Top & Bottom View

(b) Top View

(c) Bottom View

Figure 64. Printed Circuit Board

ORDERING INFORMATION

†

Device

Description

Package

UVLO

ENA/DIS

Shipping

NCP51560ABDWR2G

High current dual

isolated MOS

driver

SOIC−16 WB

(Pb−Free)

5 V

DISABLE

1000 / Tape & Reel

NCP51560BBDWR2G

NCP51560CBDWR2G*

NCP51560DBDWR2G*

SOIC−16 WB

(Pb−Free)

8 V

DISABLE

SOIC−16 WB

(Pb−Free)

13 V

17 V

SOIC−16 WB

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*Option on demand.

www.onsemi.com

28

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−16 WB

CASE 751G

ISSUE E

DATE 08 OCT 2021

1

SCALE 1:1

GENERIC

MARKING DIAGRAM*

16

XXXXXXXXXXX

AWLYYWWG

1

XXXXX = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42567B

SOIC−16 WB

PAGE 1 OF 1

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the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

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For additional information, please contact your local Sales Representative at

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


型号：	NCP51560BBDWR2G
厂家：	ONSEMI
描述：	5 kVRMS Isolated Dual Channel 4.5/9 A Gate Driver 栅
文件：	总30页 (文件大小：3342K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP51560BBDWR2G [ONSEMI]

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