NCP51561DADWR2G [ONSEMI]
5 kVRMS Isolated Dual Channel 4.5/9 A Gate Driver;
| 型号： | NCP51561DADWR2G |
| 厂家： | 
ONSEMI |
| 描述： | 5 kVRMS Isolated Dual Channel 4.5/9 A Gate Driver 栅 |
| 文件： | 总32页 (文件大小：3553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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5 kVrms 4.5-A/9-A Isolated
Dual Channel Gate Driver
SOIC−16 WB
CASE 751G−03
NCP51561
The NCP51561 are isolated dual−channel gate drivers with
4.5−A/9−A source and sink peak current respectively. They are
designed for fast switching to drive power MOSFETs, and SiC
MOSFET power switches. The NCP51561 offers short and matched
propagation delays.
MARKING DIAGRAM
16
NCP51561
XY
AWLYYWWG
Two independent and 5 kV internal galvanic isolation from input
rms
to each output and internal functional isolation between the two output
drivers allows a working voltage of up to 1500 V . This driver can be
DC
1
used in any possible configurations of two low side, two high−side
switches or a half−bridge driver with programmable dead time.
An ENA/DIS pin shutdowns both outputs simultaneously when set
low or high for ENABLE or DISABLE mode respectively.
The NCP51561 offers other important protection functions such as
independent under−voltage lockout for both gate drivers and a Dead
Time adjustment function.
NCP51561 = Specific Device Code
X
= A or B or C or D for UVLO Option
Y
A
WL
YY
WW
G
= A or B for ENABLE/DISABLE
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
PIN ASSIGNMENT
4.5 A Peak Source, 9 A Peak Sink Output Current Capability
Flexible: Dual Low−Side, Dual High−Side or Half−Bridge Gate
Driver
INA
INB
VDD
1
16 VCCA
15 OUTA
14 VSSA
13 NC
Independent UVLO Protections for Both Output Drivers
2
3
4
5
6
7
8
Output Supply Voltage from 6.5 V to 30 V with 5−V and 8−V for
MOSFET, 13−V and 17−V UVLO for SiC, Thresholds.
Common Mode Transient Immunity CMTI > 200 V/ns
Propagation Delay Typical 36 ns with
5 ns Max Delay Matching per Channel
5 ns Max Pulse−Width Distortion
User Programmable Input Logic
Single or Dual−Input Modes via ANB
ENABLE or DISABLE Mode
GND
ENA/DIS
DT
NCP51561
12 NC
11 VCCB
10 OUTB
ANB
VDD
9
VSSB
User Programmable Dead−Time
Isolation & Safety
ORDERING INFORMATION
See detailed ordering and shipping information on page 30 of
this data sheet.
5 kV
Isolation for 1 Minute (per UL1577 Requirements) and
RMS
1500 V Peak Differential Voltage between Output Channels
8000 V Reinforced Isolation Voltage (per VDE0884−11
PK
Requirements)
CQC Certification per GB4943.1−2011
SGS FIMO Certification per IEC 62386−1
These are Pb−Free Devices
Typical Applications
Motor Drives
Isolated Converters in DC−DC and AC−DC Power Supply
Server, Telecom, and Industrial Infrastructures
UPS and Solar Inverters
Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
October, 2022 − Rev. 3
NCP51561/D
NCP51561
TYPICAL APPLICATION CIRCUIT
VDD
HV Rail
16
15
14
13
PWMA
PWMB
VDD
1
2
3
4
5
6
7
8
INA
INB
VDD
VCCA
OUTA
VSSA
GND
NC
GND
To Load
ENA
NC 12
ENA/DIS
DT
VCCB 11
V
CC
10
9
ANB
VDD
OUTB
VSSB
(a) High and Low Side MOSFET Gate Drive for ENABLE Version
VDD
HV Rail
16
15
14
13
1
2
3
4
5
6
7
8
PWMA
PWMB
VDD
INA
INB
VDD
VCCA
OUTA
VSSA
GND
NC
GND
To Load
ENA
ENA/DIS
DT
NC 12
VCCB 11
V
CC
10
9
ANB
VDD
OUTB
VSSB
(b) High and Low Side MOSFET Gate Drive for DISABLE Version
VDD
HV Rail
16
15
14
13
1
2
3
4
5
6
7
8
PWMA
PWMB
VDD
INA
INB
VDD
VCCA
OUTA
VSSA
GND
NC
GND
To Load
ENA
ENA/DIS
DT
NC 12
VCCB 11
V
CC
10
9
ANB
VDD
OUTB
VSSB
(c) High and Low Side MOSFET Gate Drive with PWM Controller for ENABLE Version
Figure 1. Application Schematic
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2
NCP51561
FUNCTIONAL BLOCK DIAGRAM
VDD
VDD UVLO
VCCA
OUTA
VSSA
UVLO
INA
INB
INA
(PWM)
INA
LOGIC
Tx
Rx
INB
(NC)
LOGIC
ANB
NC
NC
Functional
Isolation
VDD
VCCB
OUTB
VSSB
ENA/DIS
UVLO
INB
DEAD
TIME
CONTROL
LOGIC
Tx
Rx
DT
GND
(a) For Only ENABLE (NCP51561xA) Version
VDD
VDD UVLO
VCCA
OUTA
VSSA
UVLO
INA
INB
INA
(PWM)
INA
LOGIC
Tx
Rx
INB
(NC)
LOGIC
ANB
NC
NC
Functional
Isolation
ENA/DIS
VCCB
OUTB
VSSB
UVLO
INB
DEAD
TIME
CONTROL
LOGIC
Tx
Rx
DT
GND
(b) For Only DISABLE (NCP51561xB) Version
Figure 2. Simplified Block Diagram
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3
NCP51561
FUNCTIONAL TABLE
INPUT
UVLO
Output Side
Channel A Channel B
GATE DRIVE OUTPUT
ENA/DIS (Note 3)
Input Side
(V
(V
CCA
)
(V
CCB
)
ENABLE
DISABLE
)
DD
ANB
X
X
L
INA
X
INB
X
OUTA
OUTB
X
X
H
H
H
H
L
X
X
L
L
L
L
H
L
L
L
Active
X
X
X
L
L
X
X
Active
Active
Active
Inactive
Inactive
Active
L
L
X
L
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
L
L
L
X
H
X
Active
L
H
L
L
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Active
L
L
L
H
X
X
Active
H
L
L
X
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Active
L
L
H
H
H
L
L
L
L
L
L
L
H
H
L
H
L
H
L (Note 5)
L (Note 5)
H (Note 6)
H (Note 6)
H
H
H
H
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
L
H
L
X
X
X
X
X
X
X
L
L
H
L
L
L
L
H
L
Active
Inactive
Inactive
Inactive
Inactive
Inactive
L
H
X
L
Active
H
L
Inactive
Inactive
Inactive
H
H
L
H
H
1. “L” means that LOW, “H” means that HIGH and X: Any Status
2. Inactive means that V , V , and V are above UVLO threshold voltage (Normal operation)
DD
CCA
CCB
Active means that UVLO disables the gate driver output stage.
3. Disables both gate drive output when the ENA/DIS pin is LOW in ENABLE version, which is default is HIGH, if this pin is open.
Enables both gate drive output when the ENA/DIS pin is LOW in DISABLE version, which is default is LOW, if this pin is open.
4. When the ANB pin is HIGH, OUTA and OUTB are complementary outputs from PWM input signal on the INA pin regardless the INB signal.
5. DT pin is left open or programmed with R
.
DT
6. DT pin pulled to V
.
DD
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NCP51561
PIN CONNECTIONS
1
2
3
4
5
6
7
8
INA
VCCA 16
INB
OUTA 15
VSSA 14
NC 13
VDD
GND
ENA/DIS
DT
NC 12
VCCB 11
OUTB 10
ANB
VDD
VSSB
9
Figure 3. Pin Connections – SOIC−16 WB (Top View)
PIN DESCRIPTION
Pin No.
Symbol
INA
I/O
Description
Logic Input for Channel A with internal pull−down resistor to GND
Logic Input for Channel B with internal pull−down resistor to GND.
Input−side Supply Voltage.
1
2
Input
Input
Power
INB
3, 8
V
DD
It is recommended to place a bypass capacitor from V to GND.
DD
4
5
GND
Power
Input
Ground Input−side. (all signals on input−side are referenced to this pin)
ENA/DIS
Logic Input High Enables Both Output Channels with Internal pull−up resistor for an ENABLE
version. Conversely, Logic Input High disables Both Output Channels with Internal pull−down
resistor for the DISABLE version.
6
7
DT
Input
Input
Input for programmable Dead−Time
It provides three kind of operating modes according to the DT pin voltage as below.
Mode−A: Cross−conduction both channel outputs is not allowed even though dead−time is less
than maximum 20 ns when the DT pin is floating (Open).
Mode−B: Dead−time is adjusted according to an external resistance (R ).
DT
t
DT
(in ns) = 10 x R (in kW)
DT
Recommended dead−time resistor (R ) values are between 1 kW and 300 kW.
DT
MODE−C: Cross−conduction both channel outputs is allowed when the DT pin pulled to VDD.
ANB
Logic Input to change the input signal configuration with internal pull−down resistor to GND.
OUTA and OUTB work as complementary outputs from INA PWM input signal regardless of the
INB signal when the ANB pin is high. It is recommended to tie this pin to GND or floating (not
recommended) if the ANB pin is not used to achieve better noise immunity.
The ANB pin has a typical 3.3 ms internal filter to improve noise immunity but we
recommend to tie to GND, if the ANB pin is not used.
9
VSSB
OUTB
Power
Output
Power
Ground for Channel B
10
11
Output for Channel B
V
CCB
Supply Voltage for Output Channel B.
It is recommended to place a bypass capacitor from V
No Connection; Keep pin floating
Ground for Channel A
to VSSB.
to VSSA.
CCB
12, 13
14
NC
−
VSSA
OUTA
Power
Output
Power
15
Output of Channel A
16
V
CCA
Supply Voltage for Output Channel A.
It is recommended to place a bypass capacitor from V
CCA
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NCP51561
SAFETY AND INSULATION RATINGS
Symbol
Parameter
Min.
Typ.
Max.
Unit
I−IV
< 150 VRMS
< 300 VRMS
< 450 VRMS
< 600 VRMS
< 1000 VRMS
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains Voltage
I−IV
I−IV
I−IV
I−III
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Climatic Classification
600
40/125/21
2
CTI
Pollution Degree (DIN VDE 0110/1.89)
Input*to*Output Test Voltage, Method b, VIORM 1.875 = VPR, 100%
Production Test with tm = 1 s, Partial Discharge < 5 pC
V
PK
VPR
2250
V
VIORM
VIOWM
VIOTM
ECR
Maximum Repetitive Peak Isolation Voltage
Maximum Working Isolation Voltage
Maximum Transient Isolation Voltage
External Creepage
1200
1200
8000
8.0
PK
V
DC
V
PK
mm
mm
um
ECL
External Clearance
8.0
DTI
Insulation Thickness
17.3
9
RIO
Insulation Resistance at T , VIO = 500 V
10
S
UL1577
V
V
= V
=1.2V
= 5000 V
, t = 60 sec. (qualification),
Withstand
isolation voltage
TEST
ISO
RMS
VISO
5000
V
RMS
= 6000V
,t=1 sec (100% production)
TEST
ISO
RMS
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NCP51561
SAFETY LIMITING VALUE
Symbol
Parameter
Side
Min
−
Typ
−
Max
88
Unit
P
S
Safety Supply Power
Maximum Values in Failure; Input Power
P
mW
S,INPUT
Maximum Values in Failure; Output
Power
P
S,OUT
−
−
1412
Maximum Values in Failure; Total Power
P
−
−
−
−
1500
150
S,TOTAL
T
S
Safety Temperature
Maximum Values in Failure; Case
Temperature
C
MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
V
V
DD
to GND
Power Supply Voltage – Input Side (Note 8)
Power Supply Voltage – Driver Side (Note 9)
−0.3
−0.3
−0.3
5.5
33
V
CCA
– VSSA, V
– VSSB
V
CCB
OUTA to VSSA, OUTB to VSSB Driver Output Voltage (Note 9)
V
V
+ 0.3,
+ 0.3
V
CCA
CCB
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns (Note 10)
−2
V
+ 0.3,
+ 0.3
V
CCA
CCB
V
INA, INB, and ANB
Input Signal Voltages (Note 8)
Input Signal Voltages (Note 8)
−0.3
−5
20
V
V
INA, INB Transient for 50 ns
(Note 10)
20
ENA/DIS
−0.3
−5
5.5
5.5
V
V
ENA/DIS Transient for 50ns
(Note 10)
DT
Dead Time Control (Note 8)
Channel to Channel Voltage
Junction Temperature
−0.3
1500
−40
−65
−
V
DD
+ 0.3
V
VSSA−VSSB, VSSB−VSSA
−
V
T
J
+150
+150
2
C
C
kV
kV
T
S
Storage Temperature
Electrostatic HBM (Note 11) Human Body Model
Discharge
CDM (Note 11) Charged Device Model
−
1
Capability
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
7. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
8. All voltage values are given with respect to GND pin.
9. All voltage values are given with respect to VSSA or VSSB pin.
10.This parameter verified by design and bench test, not tested in production.
11. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latch up Current Maximum Rating: 100 mA per JEDEC standard: JESD78F.
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NCP51561
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Min
3.0
6.5
9.5
14.5
18.5
0
Max
5.0
30
Unit
V
V
DD
Power Supply Voltage – Input Side
Power Supply Voltage – Driver Side
V
, V
CCB
5−V UVLO Version
V
CCA
8−V UVLO Version
13−V UVLO Version
17−V UVLO Version
30
V
30
V
30
V
V
IN
Logic Input Voltage at Pins INA, INB, and ANB
Logic Input Voltage at Pin ENA/DIS
Ambient Temperature
18
V
V
0
5.0
+125
+125
V
ENA/DIS
T
A
−40
−40
_C
_C
T
J
Junction Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL CHARACTERISTICS
Symbol
Rating
Condition
Value
Unit
2
R
Thermal Characteristics, (Note 13)
Thermal Resistance Junction−Air
16−SOIC−WB
100 mm , 1 oz Copper, 1 Surface Layer (1S0P)
120
81
C/W
q
JA
2
100 mm , 2 oz Copper, 1 Surface Layer (1S0P)
2
Thermal Resistance Junction−Case
Thermal Resistance Junction−to−Top
Thermal Resistance Junction−to−Board
100 mm , 1 oz Copper, 1 Surface Layer (1S0P)
38
18
55
C/W
C/W
C/W
W
R
q
JC
Y
Y
JT
JB
2
P
Power Dissipation (Note 13)
16−SOIC−WB
100 mm , 1 oz Copper, 1 Surface Layer (1S0P)
0.8
1.5
D
2
100 mm , 2 oz Copper, 1 Surface Layer (1S0P)
12.Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
13.JEDEC standard: JESD51−2, and JESD51−3.
ISOLATION CHARACTERISTICS
Symbol
Parameter
Condition
T = 25C, Relative Humidity < 50%,
Min
Typ
Max
Unit
V
Input to Output Isolation Voltage
V
RMS
ISO,INPUT TO
OUTPUT
A
5000
t = 1.0 minute, I
10 A, 50 Hz
O
*
I
(Notes 14, 15, 16)
V
OUTA to OUTB Isolation Voltage
Isolation Resistance
Impulse Test > 10 ms (Notes 14, 15)
V
DC
ISO,OUTA TO
OUTB
1500
11
R
ISO
V
I_O
= 500 V (Note 14)
10
14.Device is considered a two*terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together for input to output isolation
test, and pins 9 to 11 are shorted together and pins 14 to 16 are shorted together for between channel isolation test.
15.5,000 V
for 1*minute duration is equivalent to 6,000 V
for 1*second duration for input to output isolation test,
RMS
RMS
and Impulse Test > 10 ms; sample tested for between channel isolation test.
16.The input*output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input*output continuous voltage
rating. For the continuous working voltage rating, refer to equipment*level safety specification or DIN VDE V 0884*11 Safety and Insulation
Ratings Table
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NCP51561
ELECTRICAL CHARACTERISTICS (V = 5 V, V
= V
= 12 V, or 20 V (Note 18) and VSSA = VSSB, for typical values
DD
CCA
CCB
T = T = 25C, for min/max values T = −40C to +125C, unless otherwise specified. (Note 17))
J
A
J
Symbol
Parameter
Condition
Min
Typ
Max
Unit
PRIMARY POWER SUPPLY SECTION (V
)
DD
V
= V
DISABLE
= 0 V, V
= V
DD
500
500
7
780
820
12
1000
1000
16
mA
mA
mA
mA
V
I
V
Quiescent Current
INA
or V
INB
ENABLE
QVDD
DD
= 0 V
V
= V
= 5 V, V
= 0 V
INA
INB
ENABLE
or V
= V
DISABLE
DD
V
= V
DISABLE
= 5 V, V
= 0 V
= V
ENABLE DD
INA
INB
or V
I
V
V
Operating Current
f = 500 kHz, 50% duty cycle,
IN
C
5.0
2.7
2.6
−
7.15
2.8
9.0
2.9
2.8
−
VDD
DD
= 100 pF
OUT
V
V
Supply Under−Voltage Positive−Going
V
DD
V
DD
V
DD
= Sweep
= Sweep
= Sweep
DDUV+
DDUV−
DDHYS
DD
Threshold
V
DD
Supply Under−Voltage Negative−Going
2.7
V
Threshold
V
V
DD
Supply Under−Voltage Lockout Hysteresis
0.1
V
SECONDARY POWER SUPPLY SECTION (VCCA AND VCCB)
V
V
= V
= V
= 0 V, per channel
200
300
2.0
280
410
3.0
500
600
5.5
mA
mA
I
I
V
and V
Quiescent Current
INA
INB
QVCCA
QVCCB
CCA
CCA
CCB
= 5 V, per channel
INA
INB
I
I
V
and V
Operating Current
Current per channel (f = 500 kHz,
50% duty cycle), C
mA
VCCA
VCCB
CCB
IN
OUT
= 100 pF
VCCA and VCCB UVLO THRESHOLD (5−V UVLO VERSION)
V
V
V
and V Supply Under−Voltage
CCB
5.7
5.4
6.0
5.7
6.3
6.0
V
V
CCAUV+
CCBUV+
CCA
Positive−Going Threshold
V
V
V
CCA
and V
Supply Under−Voltage
CCAUV−
CCBUV−
CCB
Negative−Going Threshold
V
Under−Voltage Lockout Hysteresis
Under−Voltage Debounce Time (Note 19)
−
−
0.3
−
V
CCHYS
t
−
10
ms
UVFLT
VCCA and VCCB UVLO THRESHOLD (8−V UVLO VERSION)
V
V
V
and V Supply Under−Voltage
CCB
8.3
7.8
8.7
8.2
9.2
8.7
V
V
CCAUV+
CCBUV+
CCA
Positive−Going Threshold
V
V
V
CCA
and V
Supply Under−Voltage
CCAUV−
CCBUV−
CCB
Negative−Going Threshold
V
Under−Voltage Lockout Hysteresis
Under−Voltage Debounce Time (Note 19)
−
−
0.5
−
V
CCHYS
t
−
10
ms
UVFLT
VCCA and VCCB UVLO THRESHOLD (13−V UVLO VERSION)
V
V
V
and V Supply Under−Voltage
CCB
12
11
13
12
14
13
V
V
CCAUV+
CCBUV+
CCA
Positive−Going Threshold
V
V
V
CCA
and V
Supply Under−Voltage
CCAUV−
CCBUV−
CCB
Negative−Going Threshold
V
Under−Voltage Lockout Hysteresis
Under−Voltage Debounce Time (Note 19)
−
−
1
−
V
CCHYS
t
−
10
ms
UVFLT
VCCA and VCCB UVLO THRESHOLD (17−V UVLO VERSION)
V
V
V
and V Supply Under−Voltage
CCB
16
15
17
16
18
17
V
V
CCAUV+
CCBUV+
CCA
Positive−Going Threshold
V
V
V
CCA
and V
Supply Under−Voltage
CCAUV−
CCBUV−
CCB
Negative−Going Threshold
V
Under−Voltage Lockout Hysteresis
Under−Voltage Debounce Time (Note 19)
−
−
1
−
V
CCHYS
t
−
10
ms
UVFLT
LOGIC INPUT SECTION (INA, INB, AND ANB)
V
High Level Input Voltage
Low Level Input Voltage
1.4
0.9
1.6
1.1
1.8
1.3
V
V
INH
V
INL
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NCP51561
ELECTRICAL CHARACTERISTICS (V = 5 V, V
= V
= 12 V, or 20 V (Note 18) and VSSA = VSSB, for typical values
DD
CCA
CCB
T = T = 25C, for min/max values T = −40C to +125C, unless otherwise specified. (Note 17)) (continued)
J
A
J
Symbol
Parameter
Condition
Min
Typ
Max
Unit
LOGIC INPUT SECTION (INA, INB, AND ANB)
V
Input Logic Hysteresis
−
20
−
0.5
25
−
−
V
INHYS
I
I
High Level Logic Input Bias Current
Low Level Logic Input Bias Current
V
V
= 5 V
= 0 V
33
1.0
mA
mA
IN+
IN
IN−
IN
LOGIC INPUT SECTION (for ENABLE Version only)
V
Enable High Voltage
Enable Low Voltage
Enable Logic Hysteresis
1.4
0.9
−
1.6
1.1
0.5
1.8
1.3
−
V
V
V
ENAH
V
ENAL
V
ENAHYS
LOGIC INPUT SECTION (for DISABLE Version only)
V
Disable High Voltage
Disable Low Voltage
Disable Logic Hysteresis
1.4
0.9
−
1.6
1.1
0.5
1.8
1.3
−
V
V
V
DISH
V
DISL
V
DISHYS
DEAD−TIME AND OVERLAP SECTION
t
Minimum Dead−Time
Dead−Time
DT pin is left open
0
10
200
1000
−
29
255
1200
30
ns
ns
ns
ns
ns
V
DT,MIN
145
800
−30
−150
t
DT
R
DT
R
DT
R
DT
R
DT
= 20 kW
= 100 kW
= 20 kW
= 100 kW
Dt
DT
Dead−Time Mismatch between OUTB OUTA
and OUTA OUTB
−
150
V
DT Threshold Voltage for OUTA & OUTB
Overlap
DT pin Pulled to VDD
0.85x 0.9xV
DD
0.95x
V
DD
DT,SHORT
V
DD
GATE DRIVE SECTION
I
OUTA and OUTB Source Peak Current
(Note 19)
V
V
= V = 5 V, PW 5 ms,
INB
2.6
7.0
4.5
9.0
A
A
OUTA+,
OUTB+
INA
−
−
I
= V
= 12 V
CCA
CCB
I
I
OUTA and OUTB Sink Peak Current (Note 19)
V
V
= V
= 5 V, PW 5 ms
CCB
OUTA−,
OUTB−
INA
CCA
INB
= V
= 12 V
R
Output Resistance at High State
Output Resistance at Low State
I
I
I
I
= 100 mA
= 100 mA
−
−
−
−
1.4
0.5
−
2.7
1.0
W
W
OH
OUTH
OUTL
R
OL
V
V
High Level Output Voltage (V − V
)
= 100 mA
= 100 mA
270
100
mV
mV
OHA, OHB
CC
OUT
OUT
OUT
V
V
Low Level Output Voltage (V
− V )
SS
−
OLA, OLB
OUT
DYNAMIC ELECTRICAL CHARACTERISTICS
V
CCA
V
CCA
V
CCA
V
CCA
= V
= V
= V
= V
= 12 V, C
= 0 nF
= 0 nF
= 0 nF
= 0 nF
22
25
22
25
36
39
36
39
55
58
55
58
t
Turn−On Propagation Delay from INx to OUTx
Turn−Off Propagation Delay from INx to OUTx
CCB
CCB
CCB
CCB
LOAD
LOAD
LOAD
LOAD
PDON
ns
ns
ns
ns
= 20 V, C
= 12 V, C
= 20 V, C
t
PDOFF
t
Pulse Width Distortion (t
– t )
PDOFF
−5
−5
−
−
5
5
ns
ns
PWD
PDON
t
Propagation Delay Mismatching between
Channels
INA and INB shorted,
IN
DM
f
= 100 kHz
V
C
= V
LOAD
= 12 V,
CCB
−
−
−
−
9
11
8
16
19
16
19
ns
ns
ns
ns
t
Turn−On Rise Time
CCA
R
= 1.8 nF
V
= V
= 20 V,
CCA
LOAD
CCB
C
= 1.8 nF
V
= V
= 12 V,
t
Turn−Off Fall Time
CCA
LOAD
CCB
F
C
= 1.8 nF
V
= V
= 20 V,
10
CCA
LOAD
CCB
C
= 1.8 nF
22
25
36
39
55
58
ns
ns
T
ENABLE or DISABLE to OUTx Turn−On/Off
Propagation Delay
ENABLE,OUT,
DISABLE,OUT
V
V
= V
= 12 V
CCA
CCB
T
= V
= 20 V
CCA
CCB
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10
NCP51561
ELECTRICAL CHARACTERISTICS (V = 5 V, V
= V
= 12 V, or 20 V (Note 18) and VSSA = VSSB, for typical values
DD
CCA
CCB
T = T = 25C, for min/max values T = −40C to +125C, unless otherwise specified. (Note 17)) (continued)
J
A
J
Symbol
Parameter
Condition
Min
Typ
Max
Unit
DYNAMIC ELECTRICAL CHARACTERISTICS
t
Minimum Input Pulse Width that Change
Output State
C
LOAD
= 0 nF
−
15
30
ns
PW
T
Glitch Filter on the ANB Pin
2.0
3.3
4.5
ms
FLT,ANB
CMTI
Common Mode Transient Immunity
(Note 19)
Slew rate of GND versus VSSA
and VSSB. INA and INB both are
200
−
−
V/ns
tied to V or GND. V = 1500 V
DD
CM
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
17.Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25C.
J
A
18.V
= V
= 12 V is used for the test condition of 5−V and 8−V UVLO, V
= V
= 20 V is used for 13−V and 17−V UVLO.
CCA
CCB
CCA
CCB
19.These parameters are verified by bench test only and not tested in production.
INSULATION CHARACTERISTICS CURVES
80
70
60
50
40
30
20
10
0
1800
IVCCA/B for V = 12 V
1600
1400
1200
1000
800
600
400
200
0
CC
IVCCA/B for V = 33 V
CC
0
25
50
75
100
125
150
200
0
25
50
75
100
125
150
200
Ambient Temperature [5C]
Ambient Temperature [5C]
Figure 4. Thermal Derating Curve for Safety−related
Limiting Current (Current in Each Channel with
Both Channels Running Simultaneously)
Figure 5. Thermal Derating Curve for
Safety−related Limiting Power
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11
NCP51561
TYPICAL CHARACTERISTIC
Figure 6. Quiescent VDD Supply Current vs.
Temperature (VDD = 5 V, INA = INB = 0 V, ENA/DIS =
5 V or, INA = INB = 5 V, ENA/DIS = 0 V and No Load)
Figure 7. Quiescent VDD Supply Current vs.
Temperature (VDD = 5 V,
INA = INB = ENA/DIS = 5 V and No Load)
Figure 8. VDD Operating Current vs.
Temperature (VDD = 5 V, No Load, and
Switching Frequency = 500 kHz)
Figure 9. VDD Operating Current vs.
Temperature (VDD = 5 V, No Load, and
Different Switching Frequency)
Figure 10. Per Channel VDD Operating Current vs.
Temperature (VDD = 5 V, No Load, and Different
Switching Frequency
Figure 11. Per Channel Quiescent VCC Supply Current
vs. Temperature (INA = INB = 0 V or 5 V, ENA/DIS = 5 V
and No Load
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12
NCP51561
TYPICAL CHARACTERISTIC (CONTINUED)
Figure 12. Per Channel VCC Operating
Current vs. Temperature (No Load and
Switching Frequency = 500 kHz
Figure 13. Per Channel Operating Current vs.
Frequency (No Load, VCCA = VCCB = 12 V, or 25 V)
Figure 14. Per Channel Operating Current vs.
Frequency (CLOAD = 1 nF, VCCA = VCCB = 12 V,
or 25 V)
Figure 15. Per Channel Operating Current vs.
Frequency (CLOAD = 1.8 nF, VCCA = VCCB = 12 V,
or 25 V)
Figure 16. Per Channel VCC Quiescent Current vs.
Figure 17. Per Channel VCC Quiescent Current vs.
V
CC Supply Voltage (INA = INB = 0 V, ENA = 5 V)
VCC Supply Voltage (INA = INB = 5 V, ENA = 5 V)
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13
NCP51561
TYPICAL CHARACTERISTIC (CONTINUED)
Figure 18. VDD UVLO Threshold vs. Temperature
Figure 19. VDD UVLO Hysteresis vs. Temperature
Figure 20. VCC 5−V UVLO Threshold vs. Temperature
Figure 21. VCC 5−V UVLO Hysteresis vs. Temperature
Figure 22. VCC 8−V UVLO Threshold vs. Temperature
Figure 23. VCC 8−V UVLO Hysteresis vs. Temperature
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14
NCP51561
TYPICAL CHARACTERISTIC (CONTINUED)
Figure 24. VCC 13−V UVLO Threshold vs. Temperature
Figure 25. VCC 13−V UVLO Hysteresis vs. Temperature
Figure 26. VCC 17−V UVLO Threshold vs. Temperature
Figure 27. VCC 17−V UVLO Hysteresis vs. Temperature
Figure 28. Output Current vs. VCC Supply Voltage
Figure 29. ANB Filter Time vs. Temperature
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15
NCP51561
Figure 30. Input Logic Threshold vs. Temperature
Figure 31. Input Logic Hysteresis vs. Temperature
(INA, INB, and ANB)
(INA, INB, and ANB)
Figure 32. ENA/DIS Threshold vs. Temperature
(ENABLE, and DISABLE)
Figure 33. ENA/DIS Hysteresis vs. Temperature
(ENABLE, and DISABLE)
Figure 34. Rise/Fall Time vs. Temperature
(CLOAD = 1.8 nF)
Figure 35. Rise/Fall Time vs. Temperature
(VCC = 12 V, and Different Load)
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16
NCP51561
TYPICAL CHARACTERISTIC (CONTINUED)
Figure 36. ENA/DIS Delay Time vs. Temperature
Figure 37. Dead Time vs. Temperature
(RDT = Open)
Figure 38. Dead Time vs. Temperature
Figure 39. Dead Time vs. Temperature
(RDT = 20kW)
(RDT = 100 kW)
Figure 40. Dead Time Mismatching vs. Temperature
Figure 41. Dead Time vs. RDT
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17
NCP51561
TYPICAL CHARACTERISTIC (CONTINUED)
Figure 42. Turn−on Propagation Delay vs.
Figure 43. Turn−off Propagation Delay vs.
Temperature
Temperature
Figure 44. Pulse Width Distortion vs. Temperature
Figure 45. Propagation Delay Matching vs.
Temperature
Figure 46. Turn−on Propagation Delay vs. VCC
Figure 47. Turn−off Propagation Delay vs. VCC
Supply Voltage
Supply Voltage
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18
NCP51561
PARAMETER MEASUREMENT DEFINITION
Switching Time Definitions
output signals OUTA, OUTB. The typical values of the
propagation delay (t , T ), pulse width distortion
Figure 48 shows the switching time definitions of the
turn−on (t ) and turn−off (t ) propagation delay
PDON PDOFF
(t
) and delay matching between channels times are
PDON
PDOFF
PWD
time among the driver’s two input signals INA, INB and two
specified in the electrical characteristics table.
VINH
INA
VINL
(INB)
tPDON
tPDOFF
90%
90%
OUTA
(OUTB)
10%
10%
tF
tR
Figure 48. Switching Time Definitions
Enable and Disable Function
Figure 49 shows the response time according to an
ENABLE or the DISABLE operating modes. If the
ENA/DIS pin voltage goes to LOW state, i.e. V
shuts down both outputs simultaneously and Pull the
operate normally in an ENABLE mode as shown in
Figure 49 (a). Conversely, if the ENA/DIS pin voltage goes
to HIGH state, i.e. V
1.6 V shuts down both outputs
DIS
1.1 V
simultaneously and Pull the ENA/DIS pin LOW (or left
open), i.e. V 1.1 V operate normally in the DISABLE
ENA
DIS
ENA/DIS pin HIGH (or left open), i.e. V
1.6 V to
mode as shown in Figure 49 (b).
ENA
INA
(INB)
VENAH
ENA/DIS
(ENABLE)
VENAL
ENABLE low response time
90%
ENABLE high response time
OUTA
(OUTB)
10%
(a) ENABLE Version
INA
(INB)
VDISH
ENA/DIS
(DISABLE)
VDISL
DISABLE high response time
90%
DISABLE low response time
OUTA
(OUTB)
10%
(b) DISABLE Version
Figure 49. Timing Chart of Enable and Disable Function
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19
NCP51561
Programmable Dead−Time
DT2). Otherwise, if the external input signal dead times are
larger than internal dead− time, the dead time is not modified
by the gate driver and internal dead−time definition as
shown in Figure 50.
Dead time is automatically inserted whenever the dead
time of the external two input signals (between INA and INB
signals) is shorter than internal setting dead times (DT1 and
INA
INB
90%
10%
OUTB
DT1
DT2
OUTA
90%
10%
Figure 50. Internal Dead−Time Definitions
Figure 51 shows the definition of internal dead time and
shoot−through prevention when input signals applied at
same time.
Case − A
Case−B
Case−C
Case−C
Case−E
INA
INB
Shoot−Through
Prevention
DT
DT
DT
DT
DT
DT
DT
DT
DT
DT
TRIG_INA
TRIG_INB
VDT
Timer_Cap
OUTA
OUTB
Dead − Time
Shoot−Through Prevention
Gate Driver Output OFF
Case – A : Control signal edges overlapped, but inside the dead−time (Dead−Time)
Case – B : Control signal edges overlapped, but outside the dead−time (Shoot−Through)
Case – C : Control signal edges synchronous (Dead−Time)
Case – D : Control signal edges not overlapped, but inside the dead−time (Dead−Time )
Case – E : Control signal edges not overlapped, but outside the dead−time (Direct Drive)
Figure 51. Internal Dead−Time Definitions
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20
NCP51561
DEVICE INFORMATION
Input to Output Operation Definitions
The NCP51561 provides important protection functions
such as independent under−voltage lockout for both gate
driver; enable or disable function and dead−time control
function. Figure 52 shows an overall input to output timing
diagram when shutdown mode via ENA/DIS pin in the
CASE−A, and Under−Voltage Lockout protection on the
primary− and secondary−sides power supplies events in the
CASE−B. The gate driver output (OUTA and OUTB) were
turn−off when cross−conduction event at the dead time
control mode in the CASE−C.
A
B
C
INA
INB
ENA/DIS
(ENABLE)
Shutdown
Shutdown
ENA/DIS
(DISABLE)
VDDUV+
VDD
VDDUV−
Shoot−Through
(VCCA, VCCB
)
Prevention
UVLO
OUTA
OUTB
DT DT
Figure 52. Overall Operating Waveforms Definitions at the Dead−Time Control Mode
Input and Output Logic Table
Table 1 shows an input to output logic table according to
the dead time control modes and an enable or the disable
operation mode.
Table 1. INPUT AND OUTPUT LOGIC TABLE
INPUT
OUTPUT
ENA/DIS
ENABLE
H or Left open
H or Left open
H or Left open
H or Left open
H or Left open
H or Left open
L
DISABLE
L or Left open
L or Left open
L or Left open
L or Left open
L or Left open
L or Left open
H
INA
INB
OUTA
OUTB
NOTE
L
L
L
L
L
H
L
Programmable dead time control with R .
DT
L
H
H
L
H
L
H
H
L
DT pin is left open Or programmed with R .
DT
H
Left open
X
H
Left open
X
H
L
H
L
DT pin pulled to V
.
DD
L
L
20.“X” means L, H or left open.
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21
NCP51561
Input Signal Configuration
the shutdown function (e.g. Disable or Enable mode) as
below Table 2. Unused input pins (e.g. INA, INB, and ANB)
should be tied to GND to achieve better noise immunity. In
addition, the ANB pin has an internal filter time typically
3.3 ms to achieve the noise immunity.
The NCP51561 allows to set the input signal
configuration through the ANB pin for user convenience.
There are four operating modes that allow to change the
configuration of the input to output channels (e.g. single
input – dual output, or dual input – dual output), and select
Table 2. INPUT SIGNAL CONFIGURATION LOGIC TABLE
Functional Input Pin
INA
INA
INA
INA
INA
INB
INB
X
ANB
ENA/DIS
Mode
Input Configuration
1
2
3
4
L
H
L
DISABLE Dual−Input, Dual−Output with disable mode (ENA/DIS = LOW)
DISABLE Single−Input (INA), Dual−Output with disable mode(ENA/DIS = LOW)
INB
X
ENABLE
ENABLE
Dual−Input, Dual−Output with enable mode (ENA/DIS = HIGH)
H
Single−Input (INA), Dual−Output with enable mode (ENA/DISE = HIGH)
Figure 53 shows an operating timing chart of input to
output and shutdown function according to the ANB and
ENA/DIS pins. The ENA/DIS and ANB pins are only
DISABLE (e.g. NCP51561xB) mode. When it is not
possible to connect ANB to GND then external pull−down
resistor few ten kW (e.g. 10 ~47 kW) is recommended to
prevent unwanted ANB activation by external interference
as despite its internal 3.3 ms filter.
The OUTA and OUTB works as complementary outputs
from PWM input signal on the INA pin regardless the INB
signal when the ANB pin is HIGH.
functional when V
stays above the specified UVLO
DD
threshold. It is recommended to tie these pins to Ground if
the ENA/DIS and ANB pins are not used to achieve better
noise immunity, and it is recommended to bypass using a
1 nF low ESR/ESL capacitor close to these pins for the
PWM
(INA)
INA
INB
INB
ANB
ANB
ENA/DIS
(DISABLE)
ENA/DIS
(DISABLE)
OUTA
OUTB
OUTA
OUTB
tDISABLE
tDISABLE
MODE 1 : Dual input mode with DISABLE (ANB = LOW)
MODE 2 : PWM input mode with DISABLE (ANB = HIGH)
PWM
(INA)
INA
INB
INB
ANB
ANB
ENA/DIS
(ENABLE)
ENA/DIS
(ENABLE)
OUTA
OUTA
OUTB
OUTB
tDISABLE
tDISABLE
MODE 3 : Dual input mode with ENABLE (ANB = LOW)
MODE 4 : PWM input mode with ENABLE (ANB = HIGH)
Figure 53. Timing Chart of ENABLE and DISABLE Modes
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22
NCP51561
PROTECTION FUNCTION
channel supply voltages in secondary−side (e.g. V
, and
CCA
The NCP51561 provides the protection features include
enable function, Cross Conduction Protection, and
Under−Voltage Lockout (UVLO) of power supplies on
V
) need to be greater than specified UVLO threshold
CCB
level in secondary−side to let the output operate per input
signal. The typical V UVLO threshold voltage levels for
each option are per below Table 3.
CCx
primary−side (V ), and secondary−side both channels
DD
(V
, and V ).
CCB
CCA
Table 3. VCCx UVLO OPTION TABLE
Under−Voltage Lockout Protection VDD and VCCx
The NCP51561 provides the Under−Voltage Lockout
Option
5−V
V
CC
UVLO Level
Unit
V
(UVLO) protection function for V in primary−side and
DD
6.0
8.7
13
both gate drive output for
V
CCA
and
V
CCB
in
8−V
V
secondary−side as shown in Figure 54.
13−V
17−V
V
The gate driver is running when the V supply voltage
DD
is greater than the specified under−voltage lockout threshold
voltage (e.g. typically 2.8 V) and ENA/DIS pin is HIGH or
LOW states for an ENABLE (e.g. NCP51561xA) or the
DISABLE (e.g. NCP51561xB) mode respectively.
17
V
UVLO protection has an hysteresis to provide immunity
to short V drops that can occur.
CC
In addition, both gate output drivers have independent
under voltage lockout protection (UVLO) function and each
Figure 54. Timing Chart Under−Voltage Lockout Protection
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23
NCP51561
VCCX Power−Up and INX Signal
In case IN pins are active when V
is above 4.7 V,
X
CCX
To provide a variety of Under−Voltage Lockout (UVLO)
thresholds NCP51561 has an internal settling time
outputs would occur until settling time has elapsed as shown
in Figure 55 (A). If IN are only active after settling time has
X
(t
= 18 ms, typical) during initial V
start−up
expired, outputs won’t be active until V
cross
PORUV,OUT
CCX
CCX
or after POR event.
NCP51561 specific V
as shown in Figure 55 (B).
CCUV+
IN
X
t
PORUV,OUT
V
CCUV+
V
CCX
V
= 6.0 V
= 4.7 V
PREUV
V
POR
OUT
X
(A) Power Up with PWM Signals during Preset
IN
X
t
PORUV,OUT
V
CCUV+
V
CCX
V
= 6.0 V
= 4.7 V
PREUV
V
POR
OUT
X
(B) Power Up without PWM Signals during Preset
Figure 55. VCCX Power−up
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24
NCP51561
Cross−Conduction Prevention and Allowed
Overlapped Operation
For full topologies flexibility, cross conduction can be
allowed both high− and low−side switches conduct at the
The cross conduction prevents both high− and low−side
switches from conducting at the same time when the dead
time (DT) control mode is in half−bridge type, as shown in
Figure 56.
same time when the DT pin is pulled to V for example, as
shown in Figure 57.
DD
INA
INA
INB
INB
Allowed Overlap
Operation
Shoot−Through
Prevent
DT
DT
After DT
OUTA
OUTB
OUTA
OUTB
(a) In case of Shoot−Through
(b) In case of Shoot−Through
(a) In case of Shoot−Through
(b) In case of Shoot−Through
less then DT
longer then DT
less then DT
longer then DT
Example A
Example A
INA
INB
INA
INB
Allowed Overlap
Operation
Shoot−Through
Shoot−Through
Prevent
Prevent
DT
DT
OUTA
OUTB
OUTA
OUTB
Always LOW
(a) In case of Shoot−Through
(b) In case of Shoot−Through
(a) In case of Shoot−Through
less then DT
(b) In case of Shoot−Through
less then DT
longer then DT
longer then DT
Example B
Example B
Figure 56. Concept of Shoot−Through Prevention
Figure 57. Concept of Allowed the Shoot−Through
Programmable Dead Time Control
Cross−conduction between both driver outputs (OUTA,
and OUTB) is not allowed with minimum dead time
MODE−B. Overlap is not allowed when the dead time (DT)
control mode is activated.
The dead time (DT) between both outputs is set according
(t
) typically 10 ns when the DT pin is open in the
to: DT (in ns) = 10 x R (in k).
DTMIN
DT
MODE−A. External resistance (R ) controls dead time
Overlap is allowed for both outputs when the DT pin is
pulled to VDD in the MODE−C, as shown in Figure 58.
DT
when the DT pin resistor between 1 kW and 300 kW in the
tDT [ns]
Output Overlap ENABLED
MODE C – DT pin pull to VDD
tDT=0 ns
Minimum Dead−time
MODE A – DT pin Open
t
DT=10 ns
Cross−conduction prevention disabled
Cross−conduction prevention active
3000
2500
Dead−time Control Range
MODE B – 1 kW <RDT<300 kW
tDT[ns]=10 · RDT [kW]
Cross−conduction prevention active
2000
1500
1000
500
0
300
150
RDT [kW]
200
250
1
50
100
Figure 58. Timing Chart of Dead−Time Mode Control
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25
NCP51561
Common Mode Transient Immunity Testing
CMTI applies to both rising and falling common−mode
voltage edges. CMTI is tested with the transient generator
connected between GND and VSSA and VSSB.
Figure 59 is a simplified diagram of the Common Mode
Transient Immunity (CMTI) testing configuration.
CMTI is the maximum sustainable common−mode
voltage slew rate while maintaining the correct output.
(V = 1500 V)
CM
VDD
VCC
16
INA
VCCA
OUTA
15
14
INB
OUTA
VSSA
VDD
Monitor V
VDD
NC 13
NC 12
GND
ENA/DIS
DT
11
VCCB
OUTB
ANB
VDD
OUTB 10
Monitor V
VSSB
9
1.5 kV
0 V
dV/dt
Common Mode Surge
Generator
Figure 59. Common Mode Transient Immunity Test Circuit
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26
NCP51561
APPLICATION INFORMATION
VDD
This section provides application guidelines when using
the NCP51561.
INA
INB
1
2
INA
INB
Power Supply Recommendations
It is important to remember that during the Turn−On of
switch the output current to the Gate is drawn from the V
200 kW
200 kW
R1
R2
C1
C2
CCA
pins should be
and V
supply pins. The V
and V
CCB
CCA
CCB
bypassed with a capacitor with a value of at least ten times
the Gate capacitance, and no less than 100 nF and located as
close to the device as possible for the purpose of decoupling.
A low ESR, ceramic surface mount capacitor is necessary.
We recommend using 2 capacitors; a 100 nF ceramic
surface−mount capacitor which can be very close to the pins
of the device, and another surface−mount capacitor of few
microfarads added in parallel.
VDD
3
4
5
C3
C4
GND
200 kW
ENA/DIS
ENABLE
ANB
ANB
7
200 kW
R3
C5
Input Stage
The input signal pins (INA, INB, ANB, and ENA/DIS) of
the NCP51561 are based on the TTL compatible
Figure 60. Schematic of Input Stage
Output Stage
The output driver stage of the NCP51561 features a pull
up structure and a pull down structure.
input−threshold logic that is independent of the V supply
DD
voltage. The logic level compatible input provides a
typically high and low threshold of 1.6 V and 1.1 V
respectively. The input signal pins impedance of the
NCP51561 is 200 kW typically and the INA, INB, and ANB
The pull up structure of the NCP51561 consists of a
PMOS stage ensuring to pull all the way to the V rail. The
pins are pulled to GND pin and ENA/DIS pin pulled to V
CC
DD
pull down structure of the NCP51561 consists of a NMOS
device as shown in Figure 61.
The output impedance of the pull up and pull down
switches shall be able to provide about +4.5 A and −9 A peak
currents typical at 25C and the minimum sink and source
peak currents at 125C are −7 A sink and +2.6 A source.
pin for an ENABLE mode as shown in Figure 60.
Conversely, ENA/DIS pin pulled to GND pin for the
DISABLE version. It is recommended that ENA/DIS pin
should be tie to V
or GND pins for ENABLE and
DD
DISABLE versions respectively if the ENA/DIS pin is not
used to achieve better noise immunity because the ENA/DIS
pin is quite responsive, as far as propagation delay and other
switching parameters are concerned.
An RC filter is recommended to be added on the input
signal pins to reduce the impact of system noise and ground
bounce, the time constant of the RC filter. Such a filter
VCCx
VCC UVLO
should use an R in the range of 0 W to 100 W and a C
IN
IN
LOGIC
OUTx
VSSx
INx
between 10 pF and 100 pF. In the example, an R = 51 W
IN
and a C = 33 pF are selected, with a corner frequency of
IN
GND
approximately 100 MHz. When selecting these
components, it is important to pay attention to the trade−off
between good noise immunity and propagation delay.
Figure 61. Schematic of Output Stage
www.onsemi.com
27
NCP51561
Consideration of Driving Current Capability
where:
Peak source and sink currents (I , and I
SOURCE
)
SINK
I
I
: Source peak current
SOURCE
capability should be larger than average current (I
shown in Figure 62.
) as
G, AV
: Sink peak current.
SINK
V
V
: High level output voltage drop
: Low level output voltage drop
OH
OL
ISOURCE
IG,AV
Application Circuits with Output Stage Negative Bias
SiC MOSFET unique operating characteristics need to be
carefully considered to fully benefits from SiC
characteristics. The gate driver needs to be capable of
providing +20 V and −2 V to −5 V negative bias with
minimum output impedance and high current capability.
When parasitic inductances are introduced by non−ideal
PCB layout and long package leads (e.g. TO−220 and
TO−247 type packages), there could be ringing in the
gate−source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the
threshold voltage, there is the risk of unintended turn−on and
even shoot−through. Applying a negative bias on the gate
drive is a popular way to keep such ringing below the
threshold. Negative voltage can improve the noise tolerance
of SiC MOSFET to suppress turning it unintentionally. The
negative gate−source voltage makes the capacitance of Cgd
becoming lower, which can reduce the ringing voltage.
Below are a few examples of implementing negative gate
drive bias. The first example with negative bias with two
isolated−bias power supplies as shown in Figure 63. Power
supply VHx determines the positive drive output voltage
and VLx determines the negative turn−off voltage for each
channels. This solution requires more power supplies than
the conventional bootstrapped power supply example;
however, it provides more flexibility when setting the
positive, VHx, and negative, VLx, rail voltages.
ISINK
VGS
TSW,OFF
TSW,ON
Figure 62. Definition of Current Driving Capability
The approximate maximum gate charge Q that can be
switched in the indicated time for each driver current rating
may be calculate: Needed driver current ratings depend on
G
what gate charge Q must be moved in what switching time
G
t
because average gate current during switching
SW−ON/OFF
is I .
G
QG
IG.AV
+
(eq. 1)
tSW,ONńOFF
The approximate gate driver source and sink peak currents
can be calculated as below equations
At turn−on (Sourcing current)
QG
I
SOURCE 1.5
(eq. 2)
(eq. 3)
tSW,ON
At turn−off (Sinking current)
VDD
HV Rail
QG
I
SINK 1.5
tSWOFF
PWMA
PWMB
VDD
1
INA
INB
VDD
VCCA 16
VHA
VLA
OUTA
VSSA
2
3
4
15
14
where,
Q = Gate charge at V = V
G
GS
CC
GND
NC 13
GND
ENA/DIS
DT
t
= Switch On / Off time
SW, ON/OFF
To Load
ENA
5
6
7
8
12
11
NC
1.5 = empirically determined factor
VCCB
VHB
VLB
(Influenced by I vs. I , and circuit parasitic)
ANB
VDD
OUTB 10
VSSB
G,AV
DRV
9
Consideration of Gate Resistor
The gate resistor is also sized to reduce ringing voltage by
parasitic inductances and capacitances. However, it limits
the current capability of the gate driver output. The limited
current capability value induced by turn−on and off gate
resistors can be obtained with below equation.
Figure 63. Negative Bias with Two Isolated−Bias
Power Supplies
Figure 64 shows another example with negative bias
turn−off on the gate driver using a Zener diode on an isolated
power supply. The negative bias set by the voltage of Zener
diode. For example, if the isolated power supply, VHx for
V
CC * VOH
ISOURCE
+
RG,ON
V
CC * VOL
ISINK
+
(eq. 4)
RG,OFF
www.onsemi.com
28
NCP51561
PCB Layout Guideline
each channels, the turn−off voltage will be –5.1 V and
turn−on voltage will be 20 V − 5.1 V 15 V.
To improve the switching characteristics and efficiency of
design, the following should be considered before beginning
a PCB layout.
VDD
HV Rail
Component Placement
PWMA
PWMB
VDD
1
INA
INB
VCCA 16
OUTA 15
RZA
2
3
4
Keep the input/output traces as short as possible.
Minimize influence of the parasitic inductance and
capacitance on the layout. (To maintain low signal−path
inductance, avoid using via.)
14
VSSA
VDD
ZA
VHA
GND
NC 13
NC 12
GND
ENA/DIS
DT
To Load
ENA
5
6
7
8
VCCB
11
RZB
Placement and routing for supply bypass capacitors for
ANB
VDD
OUTB 10
V
DD
and V , and gate resistors need to be located as
CC
VSSB
9
close as possible to the gate driver.
ZB
VHB
The gate driver should be located switching device as
close as possible to decrease the trace inductance and
avoid output ringing.
Figure 64. Negative Bias with Zener Diode on
Single Isolated−Bias Power Supply
Grounding Consideration
Have a solid ground plane underneath the high−speed
signal layer.
Have a solid ground plane next to VSSA and VSSB pins
with multiple VSSA and VSSB vias to reduce the parasitic
inductance and minimize the ringing on the output
signals.
Moreover, this configuration could easily be changed
negative bias by a using different Zener diode with the same
20 V isolated power supply. This configuration needs two
isolated power supplies for a half−bridge configuration, but
this scheme is very simple.
However, it has the disadvantage of having a steady state
power consumption from R . Therefore, one should be
Zx
careful in selecting the R values. It is recommended that
High−Voltage (V ) Consideration
Zx
ISO
R
allow the minimal current flow to stabilize the Zener
Zx
To ensure isolation performance between the primary and
secondary side, any PCB traces or copper should be not
placed under the driver device as shown in Figure 66. A
PCB cutout is recommended to avoid contamination that
may impair the isolation performance of NCP51561.
clamping voltage (e.g. I : 5 mA~10 mA).
Typical recommended values are in the few kW range (e.g.
1 kW~2 kW) of SiC MOSFETs application.
Z
Experimental Results
Figure 65 show the experimental results of the negative
bias with Zener diode on single isolated power supply of the
NCP51561 for SiC MOSFET gate drive application. The
examples were design to have a +15 V and −5.1 V drive
power supply referenced to the device source by using the
20 V isolated power supply.
High−speed signal
10 mils
0.25 mm
10 mils
0.25 mm
Ground plane
Keep this space free
from traces, pads
and vias
40 mils
1 mm
40 mils
1 mm
Power plane
10 mils
10 mils
0.25 mm
0.25 mm
Low−speed signal
314 mils
8 mm
Figure 66. Recommended Layer Stack
Figure 67 shows the printed circuit board layout of
NCP51561 evaluation board.
CH1: INPUT [2V/div], and CH2: OUTPUT [5 V/div]
Figure 65. Experimental Waveforms of Negative Bias
with Zener Diode on Single Isolated Power Supply
www.onsemi.com
29
NCP51561
(a) Top & Bottom View
(b) Top View
(c) Bottom View
Figure 67. Printed Circuit Board
ORDERING INFORMATION
†
Device
Description
Package
UVLO
ENA/DIS
Shipping
NCP51561AADWR2G*
High current dual
isolated MOS
driver
SOIC−16 WB
(Pb−Free)
5 V
ENABLE
1000 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
NCP51561ABDWR2G*
NCP51561BADWR2G
NCP51561BBDWR2G
NCP51561CADWR2G*
NCP51561CBDWR2G*
NCP51561DADWR2G
NCP51561DBDWR2G
SOIC−16 WB
(Pb−Free)
5 V
8 V
DISABLE
ENABLE
DISABLE
ENABLE
DISABLE
ENABLE
DISABLE
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
8 V
SOIC−16 WB
(Pb−Free)
13 V
13 V
17 V
17 V
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Option on demand.
www.onsemi.com
30
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G
ISSUE E
DATE 08 OCT 2021
1
SCALE 1:1
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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