NCP51705MNTXG [ONSEMI]
Single 6 A High-Speed, Low-Side SiC MOSFET Driver;
| 型号： | NCP51705MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | Single 6 A High-Speed, Low-Side SiC MOSFET Driver 驱动 接口集成电路 驱动器 |
| 文件： | 总21页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP51705
Single 6 A High-Speed,
Low-Side SiC MOSFET
Driver
The NCP51705 driver is designed to primarily drive SiC MOSFET
transistors. To achieve the lowest possible conduction losses, the
driver is capable to deliver the maximum allowable gate voltage to the
SiC MOSFET device. By providing high peak current during turn−on
and turn−off, switching losses are also minimized. For improved
reliability, dV/dt immunity and even faster turn−off, the NCP51705
can utilize its on−board charge pump to generate a user selectable
negative voltage rail.
For full compatibility and to minimize the complexity of the bias
solution in isolated gate drive applications the NCP51705 also
provides an externally accessible 5 V rail to power the secondary side
of digital or high speed opto isolators.
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MARKING
DIAGRAM
24
1
ZXYTT
P51705
MPX
QFN24 4x4
MN SUFFIX
CASE 485L
Z
X
Y
TT
MP
X
= Plant Code
= 1−Digit Year Code
= 1−Digit Week Code
= 2−Digit Die Run Code
= Package Type (QFN)
= Package Type (Tape & Reel)
The NCP51705 offers important protection functions such as
under−voltage lockout monitoring for the bias power and thermal
shutdown based on the junction temperature of the driver circuit.
Features
• High Peak Output Current with Split Output Stages to allow
independent Turn−ON/Turn−OFF Adjustment;
♦ Source Capability: 6 A
PIN CONNECTIONS
♦ Sink Capability: 6 A
• Extended Positive Voltage Rating for Efficient SiC MOSFET
Operation during the Conduction Period
• User−adjustable Built−in Negative Charge Pump for Fast Turn−off
and Robust dV/dt Immunity
IN+
IN−
1
2
3
4
5
6
18 OUTSRC
17 OUTSRC
16 PGND
• Accessible 5 V Reference / Bias Rail for Digital Oscillator Supply
XEN
NCP51705
(Top View )
• Adjustable Under−Voltage Lockout
• Desaturation Function
SGND
VEESET
VCH
15 PGND
14 OUTSNK
13 OUTSNK
• Thermal Shutdown Function (TSD)
• Small & Low Parasitic Inductance QFN24 Package
Typical Applications
• Driving SiC MOSFET
• Industrial Inverters, Motor Drivers
• PFC, AC to DC and DC to DC Converters
ORDERING INFORMATION
†
Device
Package
Shipping
NCP51705MNTXG QFN24 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2018 − Rev. 2
NCP51705/D
NCP51705
20V
IN+
IN−
OUTSRC
OUTSRC
PGND
1
2
3
4
5
6
18
17
16
15
14
13
Controller
XEN
NCP51705
(Top View)
SGND
VEESET
VCH
PGND
OUTSNK
OUTSNK
à
à
à
à
VEESET=5 V
VEE = −5 V
VEE = −3.4 V
VEE = −8 V
VEE = 0 V
VEESET=OPEN
VEESET=VDD
VEESET=SGND
CFLY
CVEE
(a) Low Side Switching Configuration
CONTROLLER BIAS(3.3 V or 5 V)
ISOLATOR BIAS
20 V BIAS (isolated)
PWM_HS
Digital Controller
FAULT_HS
XEN_HS
Digital
Isolators
ENABLE
PWM_LS
ISOLATOR BIAS
20 V BIAS (isolated)
FAULT_LS
XEN_LS
Isolation
Boundary
(b) Half Bridge Switching Configuration
Figure 1. Typical Application Schematics
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2
NCP51705
23
24
21
22
V5 V
SVDD
5V REG
UVLO
DESAT /
CURRENT
SENSE
25mA
DESAT
UVSET
20
19
VDD
VDD
TSD
5V_OK
VDD_OK
VEE_OK
RUN
PROTECTION
LOGIC
18
17
OUTSRC
OUTSRC
1
2
3
IN+
IN−
DRIVER
LOGIC
&
INPUT LOGIC
LEVEL
SHIFT
14
13
OUTSNK
OUTSNK
XEN
CHARGE
PUMP REG
16
15
CPCLK
PGND
PGND
4
SGND
CHARGE PUMP
POWER STAGE
11
12
9
10
5
6
7
8
Figure 2. Internal Block Diagram
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3
NCP51705
PIN CONNECTIONS
IN+
IN−
1
2
3
4
5
6
18 OUTSRC
17 OUTSRC
16 PGND
XEN
NCP51705
(Top View)
SGND
VEESET
VCH
15 PGND
14 OUTSNK
13 OUTSNK
Figure 3. Pin Assignments – 24 Leads QFN (Top View)
PIN FUNCTION DESCRIPTION
Pin #
Name
IN+
Description
Input for non−inverting, logic level PWM signal or ENABLE signal.
Input for inverting, logic level PWM signal or DISABLE signal.
Driver state flag. See the application description for details.
Signal ground.
1
2
IN−
3
XEN
4
SGND
VEESET
VCH
5
6
Negative bias voltage select pin.
Regulated bias voltage for the charge pump.
Positive node of the flying charge pump capacitor.
Negative node of the flying charge pump capacitor.
Power ground.
7
C+
8
C−
9,10,15,16
11,12
13,14
17,18
19,20
21
PGND
VEE
Negative drive voltage, the output of the charge pump
Pull down drive.
OUTSNK
OUTSRC
VDD
Pull up drive.
Positive bias voltage for the high current driver section.
Positive bias voltage for the control section of the driver.
Sense input for the desaturation / current limit input of the driver.
External bypass for 5 V controller bias – suitable to power digital isolators
Input for setting the Under voltage lock out threshold. (minimum operating voltage level)
SVDD
DESAT
V5V
22
23
24
UVSET
OUTPUT LOGIC
IN+
IN−
OUTSRC
0 (Note 1)
0
0
0
1
0
0 (Note 1)
1 (Note 1)
0
1
1
1 (Note 1)
1. Default input signal if no external connection is made.
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NCP51705
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−0.3
−0.3
−0.3
−9
Max.
28
Unit
V
V
Power Supply Voltage
Bias Rail
DD
V
V5V
5.5
V
V
CH
Charge Pump Supply Voltage
10
V
V
Charge Pump Output; Negative Gate Drive Voltage
Charge Pump Output Voltage Select
Logic Input Voltage Levels
+0.3
V
EE
V
V
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
+0.3
28
V
VEESET
V
V5V+0.3
V5V+0.3
V5V+0.3
12
V
-
IN+; IN
V
UVLO SET Voltage
V
UVSET
V
XEN
Logic Output Voltage Levels
V
V
Desaturation / Current sense voltage
Positive node of the flying charge pump capacitor
Negative node of the flying charge pump capacitor
Gate Drive Source Output Voltage
Gate Drive Sink Output Voltage
Maximum Operating Frequency (Note 2)
Junction Temperature
V
DESAT
V
V
VCH+0.3
V
C+
V
-0.3
+0.3
+0.3
V
C−
EE
V
V
V
V
-0.3
V
V
OUTSRC
OUTSNK
EE
EE
DD
DD
-0.3
V
V
f
500
kHz
°C
°C
MAX
T
J
−55
−55
150
150
T
STG
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum operating frequency refers to ground reference applications and might be limited by power dissipation below the recommended
value.
THERMAL CHARACTERISTICS
Parameters
Symbol
Value
127
43
Unit
1S0P with thermal vias
1S2P with thermal vias
1S0P with thermal vias
q
JA
Thermal Characteristics, QFN 4x4 24 Leads
Thermal Resistance Junction−Air (Notes 3 & 4)
°C/W
12
Yjt
1S2P with thermal vias
1S0P with thermal vias
3.7
0.98
Power Dissipation (Note 4)
P
D
W
1S2P with thermal vias
2.9
3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
4. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2×114.3×1.6mm PCB (FR−4 glass epoxy material).
1S0P with thermal vias: one signal layer with zero power plane and thermal vias
1S2P with thermal vias: one signal layer with two power plane and thermal vias.
ESD CAPABILITY
Symbol
ESD
Parameter
Human Body Model, JESD22−A114 (Note 5)
Charged Device Model, JESD22−C101 (Note 5)
Value
2000
1000
Unit
V
ESD
V
5. Meets JEDEC standards JESD 22−A114 and JESD 22−C101.
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5
NCP51705
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
10
−8
0
Max.
22
Unit
V
V
DD
Positive Power Supply Voltage
Negative Power Supply Voltage
Charge Pump Power Supply Voltage
5 V internal/external bias output
Logic Enable Voltage
V
0
V
EE
CH
V
8
V
V
0
5.5
5.5
5.5
5.5
22
V
V5V
ENA
V
V
0
V
V
Logic Input Voltage
0
V
IN
Logic Output Voltage
0
V
XEN
V
Charge Pump Output Voltage Setting
UVLO Threshold Setting
0
V
VEESET
V
2
3.5
10
V
UVSET
V
DESAT
Desaturation Voltage
0
V
f
Operating Frequency (Note 6)
Operating Ambient Temperature
500
125
kHz
°C
SW
T
−40
A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Maximum operating frequency refers to ground referenced applications and might be limited by power dissipation below the recommended
value.
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6
NCP51705
ELECTRICAL CHARACTERISTICS (V =20 V, V
= 0 V and C
= 1000 pF for typical values T =25°C, for min/max values
LOAD A
DD
EESET
T =T =−40°C to +125°C, unless otherwise specified.) (Notes 7, 8)
J
A
Symbol
Parameters
Test Conditions
Min.
Typ.
Max. Units
VDD Section
I
Operating V Supply Current
f = 100 kHz, VEESET = 5 V
IN
12
4.5
0.85
25
18
6.5
1
mA
mA
mA
mA
DD
DD
I
I
Quiescent V Supply Current 1
V
V
V
= V
= 0 V, VEESET = 5 V
QDD1
QDD2
DD
IN+
IN−
Quiescent V Supply Current 2
= 0 V, V
= 5 V
DD
IN+
IN−
I
Source Current for UV Voltage Set
= 3 V
22
17
28
UVSET
UVSET
V
DD
Supply Under−Voltage
V
V
V
= 3 V
18
17
19
18
V
V
DDUV+
UVSET
Positive−going Threshold Voltage
V
DD
Supply Under−Voltage
V
= 3 V
16
DDUV−
UVSET
Negative−going Threshold Voltage
V
V
Supply UVLO Hysteresis Voltage
V
V
− V
DDUV−
1
V
V
V
DDHYS
DD
DDUV+
V
UVSET pin short protection Threshold Voltage
UVSET pin short protection Hysteresis
rising
1.55
0.2
UVSET,MIN
UVSET,HYS
UVSET
V
5V Regulator Section
T = 25°C
4.9
5
5
5.1
5.25
50
V
A
V
5 V Bias (Note 9)
V5V
Total Variation
4.75
V
5 V Line Regulation
10 V < V < 22 V, I
= 10 mA
mV
mV
mA
DD
OUT
V
V5V_Reg
5 V Load Regulation
0.1 mA < I
< 10 mA
50
OUT
I
Maximum Output Current (Note 10)
for external load
20
25
5
5V_MAX
VEE Regulator Section
I
Input V
Bias Current
mA
VEESET
EESET
V
Maximum V Output Voltage (Note 10)
10
V
VCH,MAX
CH
Charge Pump Section
V
V
V
= 5 V
− 5.5
−3.8
−5
−3.4
−8
−4.5
−3.0
V
V
V
EESET
EESET
EESET
= open
V
EE
Negative Bias Rail Voltage
= V
DD
C
C
= 0.47 mF, C
LOAD
= 1.5 mF
FYL
VEE
I
Maximum Output Current of V
50
mA
VEE, MAX
EE
= 8.5 nF, VEESET = 5 V
f
Oscillator Switching Frequency for Charge Pump
350
390
430
kHz
OSC
Desaturation Section
I
DC Source Current
V
DESAT
= 0 V
360
7
400
7.5
500
5
440
8
mA
V
DESAT
V
Desaturation Protection Threshold Voltage
Blanking Time after turn−on
Active Pull Down Resistance
TH,DESAT
t
350
650
10
ns
W
DEL,DESAT
R
ON,DESAT
Thermal Shutdown Section
TSD Thermal ShutDown Temperature (Note 10)
TSD TSD Hysteresis (Note 10)
130
150
25
°C
°C
_HYS
7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C.
J
A
9. Exclude overshoot voltage at start−up.
10.This parameter, although guaranteed by design, is not tested in production.
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7
NCP51705
ELECTRICAL CHARACTERISTICS (V =20 V, V
= 0 V and C
= 1000 pF for typical values T =25°C, for min/max values
LOAD A
DD
EESET
T =T =−40°C to +125°C, unless otherwise specified.) (Notes 7, 8)
J
A
Symbol
Parameters
Test Conditions
Min.
Typ.
Max. Units
Input Logic Section; IN+; IN−
High Level Input Voltage
V
IH
1.6
1.2
0.4
50
2.0
V
V
V
IL
Low Level Input Voltage
0.8
V
INHYS
Input Logic Hysteresis
V
I
High Level Logic Input Bias Current
Low Level Logic Input Bias Current
Logic Input Pull−Down Resistance
Logic Input Pull−Up Resistance
V
V
= 5 V
mA
mA
kW
kW
IN+
IN+
I
= 0 V
50
IN−
IN−
R
75
75
100
100
125
125
IN+
R
IN−
Output Logic Section; XEN
V
High Level Output Voltage (V5V−V
)
I
I
= 1 mA
= 1 mA
0
0
0.5
0.2
5
V
V
OHX
OH
OUT
V
Low Level Output Voltage
OLX
OUT
I
High Level Logic Output Source Current (Note 10)
High Level Logic Output Sink Current (Note 10)
mA
mA
XENH
I
5
XENL
Gate Driver Output Section
I
OUTSRC Source Current (Note 10)
OUTSRC = 0 V, VEESET = 5 V
OUTSNK = 20 V, VEESET = 5 V
6
A
SOURCE
I
OUTSNK Sink Current (Note 10)
High Level Output Voltage (VDD−VOUT)
Low Level Output Voltage
6
0
A
V
SINK
V
OH
I
I
= 100 mA
= 100 mA
0.5
0.2
50
50
15
15
OUT
OUT
V
OL
0
V
t
Turn−On Propagation Delay Time
Turn−Off Propagation Delay Time
Turn−On Rise Time
C
C
C
C
= 1 nF
= 1 nF
= 1 nF
= 1 nF
25
25
8
ns
ns
ns
ns
ON
LOAD
LOAD
LOAD
LOAD
t
OFF
t
R
t
F
Turn−Off Fall Time
8
7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C.
J
A
9. Exclude overshoot voltage at start−up.
10.This parameter, although guaranteed by design, is not tested in production.
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8
NCP51705
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and V
= 20 V unless otherwise noted.
DD
Figure 4. Operating Current (IDD) vs. Operating
Voltage (VDD
Figure 5. Operating Current (IDD) vs. Operating
)
Frequency
Figure 6. Propagation Delay Time vs.
Operating Voltage (VDD
Figure 7. Sourcing Current vs. Operating Voltage
)
(VDD)
Figure 8. Sinking Current vs. Operating Voltage
(VDD
Figure 9. Operating Current (IDD) vs.
)
Temperature
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NCP51705
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and V
= 20 V unless otherwise noted.
DD
Figure 10. Quiescent Current 1 (IQDD1) vs.
Figure 11. Quiescent Current 2 (IQDD2) vs.
Temperature
Temperature
Figure 12. VDD UVLO vs. Temperature
Figure 13. UVSET vs. Temperature
Figure 14. UVSET Current (IUVSET) vs.
Figure 15. 5 V Regulated Output Voltage (V5V)
Temperature
vs. Temperature
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NCP51705
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and V
= 20 V unless otherwise noted.
DD
Figure 16. Negative Bias Voltage of Charge
Figure 17. VEE5 Regulated Voltage with
Pump vs. Temperature
IVEE,MAX vs. Temperature
Figure 18. Charge Pump Operating Frequency
Figure 19. Desaturation Current (IDESAT) vs.
(fOSC) vs. Temperature
Temperature
Figure 20. DESAT Threshold Voltage
Figure 21. Desaturation Blanking Time (tDEL,
(VTH,DESAT) vs. Temperature
DESAT) vs. Temperature
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NCP51705
TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and V
= 20 V unless otherwise noted.
DD
Figure 22. DESAT Pull Down Resistance
Figure 23. Input Logic Threshold Voltage vs.
(RDON,DESAT) vs. Temperature
Temperature
Figure 24. Logic Input Resistance vs.
Figure 25. XEN Logic Output Voltage vs.
Temperature
Temperature
Figure 26. Propagation Delay Time vs.
Figure 27. Turn On Rising and Turn Off Falling
Temperature
Time vs. Temperature
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NCP51705
APPLICATIONS INFORMATION
The NCP51705 can be quickly configured by following
the steps outlined in this section. The component references
made throughout this section refer to the schematic diagram
and reference designations shown in Figure 28.
CVDD1
20V
CSVDD
RSVDD
CVDD2
CV5V
RUVSET
RDESAT
DDESAT
CUVSET
IN+
1
OUTSRC
OUTSRC
PGND
18
17
16
15
14
13
IN−
2
3
4
5
6
Controller
XEN
SGND
RSRC
NCP51705
(Top View)
PGND
RSNK
VEESET
VCH
OUTSNK
OUTSNK
à
à
à
à
VEESET=SGND
0 V
VEESET=OPEN
VEESET=V5V
VEESET=SVDD
−3.4 V
−5 V
−8 V
CVCH
CFLY
CVEE2
CVEE1
Figure 28. Application Schematic
Input (IN+, IN−)
function. If IN− is pulled HIGH, the driver output remains
LOW, regardless of the state of IN+. To enable the driver
output, IN− should be tied to SGND through a 10 kW
resistor, as shown in Figure 29, or can be used as an active
LOW enable pull down. The start−up logic waveforms
shown in Figure 30 illustrate the expected behavior when
applying a PWM input signal to the IN+ input while the IN−
input is pulled LOW to SGND. In this example, the PWM
signal is applied prior to the application of VDD. When
VDD is greater than X7.5 V, the NCP51705 internal charge
pump is enabled and begins switching. The output is only
enabled when VDD is greater than the set UVLO ON level
(VON) and VEE is less than 80% of the programmed voltage
level. The output begins switching corresponding to the next
PWM rising edge after both UVLO thresholds have been
crossed. This method of edge detection, assures the output
accurately represents the PWM input while preventing the
output from possibly switching in the middle of an IN+,
PWM pulse on−time.
Both independent PWM inputs are TTL compatible and
are internally pulled to the correct states such that each
corresponding driver input is defaulted to the inactive
(disabled) state. The TTL input thresholds provide buffer
and level translation functions from logic inputs. The input
thresholds meet industry−standard TTL−logic thresholds,
independent of the V voltage, and there is a hysteresis
DD
voltage of approximately 0.4 V. These levels permit the
inputs to be driven from a range of input logic signal levels
for which a voltage over 2 V is considered logic high. The
driving signal for the TTL inputs should have fast rising and
falling edges with a slew rate of 6 V/ms or faster, so a rise
time from 0 to 3.3 V should be 550 ns or less. With reduced
slew rate, circuit noise could cause the driver input voltage
to exceed the hysteresis voltage and retrigger the driver
input, causing erratic operation.
For non−inverting input logic the PWM input signal is
applied to IN+ while the IN− input can be used as an enable
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NCP51705
VDD
VEE
VDD
VEE
IN+
IN+
OUTSRC
OUTSNK
V5V
OUTSRC
OUTSNK
IN−
IN−
Figure 29. Non−inverting input configuration
Figure 31. Inverting input configuration
Table 1. Non−inverting logic, IN+, truth table
Table 2. Inverting logic, IN−, truth table
IN+ (PWM)
IN− (SGND)
OUTSRC
OUTSNK
IN+ (V5V)
IN− (PWM)
OUTSRC
OUTSNK
0
1
0
0
0
1
1
0
1
1
0
1
1
0
0
1
VDD
VON
VDD
VON
7.5 V
0 V
7.5 V
0 V
0 V
0 V
0.8*VEE
VEE
0.8*VEE
VEE
IN+
0 V
IN−
0 V
IN−(0 V)
IN+ (V5V)
0 V
RISING IN+ EDGE
VDD
FALLING IN−EDGE
VDD
OUT
0 V
OUT
0 V
VEE
VEE
VEE VEE
VDD
(EN) (UVLO) (UVLO)
VEE VEE
VDD
(EN) (UVLO) (UVLO)
Figure 30. Non−inverting start−up logic
Figure 32. Inverting start−up logic
Driver State Reporting (XEN)
For inverting input logic the PWM input signal is applied
to IN− while the IN+ input can be used as an enable function.
If IN+ is pulled LOW, the driver output remains LOW,
regardless of the state of IN−. To enable the driver output,
IN+ should be tied to V5V (5 V) through a 10 kW resistor,
as shown in Figure 31, or can be used as an active HIGH
enable pull up. The start−up logic waveforms shown in
Figure 32 illustrate the expected behavior when applying a
PWM input signal to the IN− input while the IN+ input is
pulled HIGH to V5V. In this example, the PWM signal is
applied prior to the application of VDD. When VDD is
greater than 7.5 V, the NCP51705 internal charge pump is
enabled and begins switching. The output is only enabled
when VDD is greater than the set UVLO ON level (VON)
and VEE is less than 80% of the programmed voltage level.
The output begins switching corresponding to the next
PWM falling edge after both UVLO thresholds have been
crossed. This method of edge detection, assures the output
accurately represents the PWM input while preventing the
output from possibly switching in the middle of an IN−,
PWM pulse off−time.
The XEN signal is a 5 V digital output representation of
the output state of the NCP51705 driver. XEN is directly
derived from the output of the driver and should not be
considered as the inverse of the non−inverting logic input to
the driver, IN+. The output of the NCP51705 driver can be
commanded to its OFF state while the input signal is still
HIGH by any of the protection functions of the driver. In
such instances, XEN will accurately represent that the river
is OFF, independent of the input signal to the device.
The intent of this signal is that it can be used as a fault flag
and in half−bridge power topologies, can provide a
synchronization signal for implementing cross−conduction
(overlap) protection for the power transistors.
Whenever XEN is HIGH, V is LOW and the SiC
GS
MOSFET is OFF. Therefore, if XEN and the PWM input
signals are both HIGH, a fault condition is detected and can
be digitally assigned to take whatever precautions might be
desired. XEN can also be used as a control signal for
www.onsemi.com
14
NCP51705
cross−conduction prevention between a high−side and
the V
energy storage capacitor, which provides bias
DD
low−side switch used in a half or full−bridge configuration.
The schematic diagram shown in Figure 33 illustrates a
circuit example how to utilize the XEN signals for fault
detection and cross−conduction prevention. As can be seen
in this implementation, the functions are independent and it
is up to the designer to decide whether any one or both
functions are needed to be implemented in the system.
power during startup until the bootstrap power supply comes
up. The value of the energy storage capacitor is a strong
function of the gate charge requirement of the SiC
MOSFET. It is recommended to use a minimum of 1 mF to
ensure proper operation but the value is primarily dictated
by the biasing scheme and startup time of the system. The
second capacitor shall be a good−quality ceramic bypass
capacitor, located as close as possible to the PGND and
VDD pins to filter the high peak currents of the gate driver
source circuit. A ceramic bypass capacitor in the range of
10 nF to 100 nF is recommended.
PWM_HS
IN+_HS
FLT_HS
XEN_HS
Similarly, two bypass capacitors should be connected
between the VEE pin and the PGND pin. One is the V
FAULT
DETECTION
ANTI CROSS−
CONDUCTION
EE
energy storage capacitor, which smoothes the ripple voltage
seen at output of the internal charge pump power stage. It is
recommended to use a minimum of 470 nF to ensure
accurate DC regulation. The second capacitor shall be a
good−quality ceramic bypass capacitor, located as close as
possible to the PGND and VEE pins to filter the high peak
currents of the gate driver sink circuit. A ceramic bypass
capacitor in the range of 10 nF to 100 nF is recommended.
Note that the exposed metal pad beneath the IC is
thermally conductive but electrically not always connected
to GND potential. Do not connect this pad to SGND or
PGND.
XEN_LS
FLT_LS
IN+_LS
PWM_LS
Figure 33. Examples of XEN signal usage
If XEN_HS transitions from LOW to HIGH while
PWM_HS is HIGH, the PWM pulse width had been
terminated early by one of the protection functions of the
NCP51705. The protection function are; any of the Under
Voltage Lock−Out (UVLO) protections, Thermal Shut
Down (TSD), and Desaturation Detection (DESAT). As
Figure 33 indicates a FAULT signal can be generated by a
simple AND connection of the PWM input signal and the
corresponding XEN output.
In case of cross−conduction prevention, the XEN signal of
one driver is used to enable the operation of the other driver
as depicted in a simplified manner in Figure 33. The
isolation for the high side driver is not shown in the
simplified schematic of Figure 33 but the operation of the
system can be easily followed. While the high−side driver is
ON, XEN_HS is LOW preventing any gate drive to be
applied to the low−side driver. Once the high−side driver
turns OFF its XEN_HS signal transitions to HIGH and the
PWM_LS signal can pass through to the low−side driver. An
identical sequence exists to ensure that the high−side driver
cannot be turned ON until the low−side driver is OFF.
Programmable VEE Voltage (VEESET)
V
EE
is regulated to the voltage set at V
which is
CH
determined by the internal low dropout regulator (LDO)
voltage, programmable by the VEESET pin. The
NCP51705 offers several convenient pin strapping options
for VEESET. If VEESET is left floating (a 100 pF bypass
capacitor from VEESET to SGND is recommended), then
V
EE
is set to regulate at −3 V. For a −5 V V voltage, the
EE
VEESET pin should be connected directly to V5V (pin 23).
If VEESET is connected to any voltage between 9 V and
V
DD
, then V
is clamped and set to regulate at the
EE
minimum charge pump voltage of −8 V. The charge pump
starts when V > 7.5 V. Additionally, the V voltage rail
DD
EE
includes an internally fixed under−voltage lockout (UVLO)
set to 80% of the programmed V value. Since V and
EE
DD
V
are each monitored by independent UVLO circuits, the
EE
Signal Ground (SGND) and Power Ground (PGND)
Signal ground connection (SGND) is the GND for all
control logic biased from the 5 V rail (V5V). Internally, the
SGND and PGND pins are tied together by two anti−parallel
diodes to limit ground bounce difference due to bond wire
inductances during the switching actions of the high−current
gate drive circuits. It is recommended to connect the SGND
and PGND pins together with a short, low−impedance trace
on the PCB.
NCP51705 is smart enough to realize when both voltage
rails are within limits deemed safe for switching a given SiC
MOSFET.
Some SiC MOSFETs can operate between 0 V and VDD.
For these applications, 0 V<OUT<V switching can be
DD
achieved by disabling the charge pump entirely. When
VEESET is connected to SGND and VEE is connected to
PGND, the charge pump is disabled. With the charge pump
disabled and V tied directly to PGND, the output switches
between 0 V<OUT<V . During this mode of operation the
EE
PGND is the reference potential (0 V) for the high−current
gate−drive circuit. Two bypass capacitors should be
connected between the VDD pin and the PGND pin. One is
DD
internal V UVLO function is also disabled accordingly.
EE
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15
NCP51705
Another configuration is to disable the charge pump but
allow the use of an external negative V voltage rail. This
The VEE voltage can programmed from −3.4
V<VEE<−7.6 V for a range of VEESET bias voltage
between 1.5 V<VEESET<10.5 V. The absolute minimum
programmable VEE voltage is −3 V and can be set by
applying 1 V to VEESET, or by simply leaving the VEESET
pin floating. For any VEESET voltage greater than 10.5 V,
up to VDD, the VEE voltage rail is clamped to an absolute
maximum programmable voltage of −7.6 V. The range of
programmable VEE negative voltage versus VEESET bias
voltage is shown graphically in Figure 36.
EE
option permits –V <OUT<V
switching with a slight
EE
DD
savings in IC power dissipation, since the charge pump is not
switching. With VEESET connected to SGND, an external
negative voltage rail, V
, can be connected directly
EE(EXT)
between VEE and PGND as shown in (bold highlight)
Figure 34. V can be supplied from a dedicated bias
EE(EXT)
winding, LDO or an external negative DC power converter.
When using an external V bias, be mindful that since
EE(EXT)
VEESET is 0 V, the internal V UVLO is disabled and
EE
-3
- 3.5
-4
therefore the NCP51705 is unaware if the V voltage level
EE
is within or outside of the expected range.
NCP51705
VEE Charge
Pump
- 4.5
-5
VEESET
5
- 5.5
-6
VDD
- 6.5
-7
GLDO
LDO
9 V
VCH
- 7.5
-8
6
CCH
P
N
P
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
19.5
21
VEESET (V)
SiC
Drive
(SINK)
14
13
Q1
N
Figure 36. VEE versus VEESET bias voltage
OUTSNK
The configurability of the VEESET pin is summarized in
Table 3
C
C
VEE
12
7
8
11
CF
CVEE
Table 3. Summary of VEESET Pin Configuration
VEE(EXT)
VEESET
COMMENT
V
V
EE(UVLO)
EE
Figure 34. Supplying VEE with negative external
voltage bias
V
DD
10.5 V<VEESET<V
−8 V
−5 V
−6.4 V
DD
V5V
−4 V
If none of the pin strapping options provide the desired
negative bias voltage, the VEESET pin can be
V
EE
OPEN
Add C
from VEESET to
SGND
≤100 pF
−3.4 V
−2.72 V
VEE
programmed using an external voltage bias. An external
LDO from VDD or a simple resistive divider connected
between VDD and SGND can be used as shown in (bold
highlight) Figure 35.
SGND
SGND
Remove C
and
0 V
NA
NA
VEE
connect V to PGND
EE
Connect V to ex-
−V
EXT
EE
ternal negative volt-
age supply
19
VDD
NCP51705
VEE Charge
Pump
RSET1
Resistor
divider
Resistor divider from
Variable
NA
VEESET
5
V
DD
to SGND
RSET2
GLDO
LDO
9 V
VCH
6
CCH
P
P
SiC
Drive
(SINK)
14
13
Q1
N
N
OUTSNK
C
C
VEE
12
7
8
11
CF
CVEE
Figure 35. Applying bias voltage to VEESET
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16
NCP51705
Charge Pump Configuration (VCH, C+, C− and VEE)
As can be seen from the charge pump functional block
diagram shown in Figure 37, only three external capacitors
be detrimental for one SiC MOSFET but may be acceptable
for another depending on heat−sinking, cooling and V
start−up time. The optimal UVLO turn−on threshold can
DD
(C , C and C ) are required to establish the negative
also vary depending on how the V voltage rail is derived.
CH
F
VEE
DD
V
EE
voltage rail. The charge pump power stage essentially
Some power systems may have a dedicated, housekeeping,
consists of two PMOS and two NMOS switches arranged in
a bridge configuration.
bias supply while others might rely on a V bootstrapping
technique.
DD
The NCP51705 addresses this need through
a
NCP51705
VEE Charge
Pump
programmable UVLO turn−on threshold that can be set with
a single resistor between UVSET and SGND. As shown in
Figure 38, the UVSET pin is internally driven by a 25 mA
ADJUST
VEESET
5
VDD
current source. The UVSET resistor, R
according to a desired UVLO turn−on voltage, V , as
defined by:
, is chosen
UVSET
GLDO
LDO
ON
9 V
VCH
6
VON
6 25 mA
ID
CCH
RUVSET
+
(eq. 1)
P
N
P
SiC
Drive
(SINK)
VDS
14
13
Q1
N
NCP51705
UVSET Function
OUTSNK
C
C
VEE
7
8
11
12
VDD V5V
CF
CVEE
μA
25
Figure 37. NCP51705 VEE Charge Pump
An external flying capacitor, C , is connected between the
midpoints of each leg of the bridge as shown. The switching
÷ 6
F
frequency is internally set at 390 kHz. The V output is
EE
seen at the VEE pin and is released after V >7 V. Once V
UVSET
DD
EE
24
exceeds 80% of the set amplitude, the VEE power rail is
deemed sufficient and the VEE Under Voltage Lock Out no
longer prevents switching.
CUVF RUVSET
Figure 38. NCP51705 UVSET Programmable UVLO
Output (OUTSNK and OUTSRC)
The value for V is typically determined by referencing
ON
The NCP51705 output is driven by a pure MOS,
low−impedance totem pole output stage to ensure full VEE
to VDD, rail−to−rail switching. The output slew rate is
the SiC MOSFET voltage versus current, output
characteristic curves. Because the on−resistance of a SiC
MOSFET dramatically increases even for a slight decrease
determined primarily by V , V and the C of the SiC
DD
EE
iss
in V , the allowable UVLO hysteresis must be small. For
GS
MOSFET. The turn−on (OUTSRC) and turn−off
(OUTSNK) functions each have dual dedicated pins. This
allows a single resistor between each pin and the SiC
MOSFET gate to independently control gate ringing as well
this reason, the NCP51705 has a fixed 1 V hysteresis so that
the turn−off voltage, V , is always 1 V less than the set
OFF
V
. Due to the narrow, 1 V hysteresis band, a small filter
ON
capacitor, C , is recommended to prevent any periodic or
UVF
as fine tuning dV /dT turn−on and turn−off transitions
DS
random noise disturbances on the UVSET pin. A ceramic
present on the SiC drain−source voltage. The driver
provides the high peak currents necessary for high−speed
switching, even at the higher Miller plateau voltage typical
of SiC MOSFETs. The outputs of the NCP51705
(OUTSRC, OUTSNK) are rated to 6 A peak current
capability.
capacitor in the range of 10 nF<C <100 nF should be
UVF
placed between UVSET and SGND as close as possible to
the IC.
Positive Bias Voltage (VDD and SVDD)
The positive bias voltage for the driver OUTSRC is
provided through VDD. The input bias voltage to the
internal 5 V regulator is provided through SVDD. VDD and
SVDD should be the same value coming from the same
voltage source but they are seperated to allow a small RC
filter to be used at the input to SVDD. A small resistor (few
W’s) can be inserted between VDD and SVDD to help
prevent any switching noise that might be present on VDD
from coupling into the control logic biased by the internal
Programmable Under−Voltage Lockout (UVSET)
UVLO for a gate driver IC is important for protecting the
MOSFET by disabling the output until V
known threshold. This not only protects the load but verifies
to the controller that the applied V voltage is above the
turn−on threshold. Because the on−resistance of a SiC
MOSFET has a strong dependency on V (and therefore
is above a
DD
DD
GS
V
DD
), allowing the driver output to switch at low V can
DD
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17
NCP51705
5 V regulator. In many cases this resistor may not be
The 400 mA current source is sufficient to ensure a
predictable forward voltage drop across D while also
necessary and VDD can be connected directly to SVDD.
However, it is recommended to allow a placeholder on the
PCB design to accommodate this resistor until it can be
determined if it is needed or not.
1
allowing the voltage drop across R to be independent of
1
V
DS
during the on−time of the SiC MOSFET. If desired,
DESAT protection can be disabled by connecting the
DESAT pin to ground. Conversely, if the DESAT pin is left
For V >7 V, quiescent current ramps up linearly until
DD
the set UVLO threshold, V , is crossed. After V >V
floating, or R fails open, the 400 mA current source flowing
ON
DD
ON
1
and V >V
, the IC is properly biased to allow
through the 12 kW resistor, puts a constant 4.8 V on the
non−inverting input of the DESAT comparator. This
condition essentially disables the gate drive to the SiC
EE
EE(UVLO)
output switching. Except for the case when
VEESET=SGND (VEE=0 V), both VDD and VEE UVLO
conditions must be met before output switching can ensue.
Two bypass capacitors must be used between VDD and
PGND as detailed in Signal Ground (SGND) and Power
Ground (PGND) section.
MOSFET. The voltage on the DESAT pin, V
determined as:
, is
DESAT
ǒ
Ǔ
ǒ
DSǓ
VDESAT + 400 mA R1 ) VD1 ) ID R
(eq. 2)
After assigning the maximum value for I (plus allowing
D
any additional design margin) R and I are selected such
Over−Current Protection (DESAT)
1
D
that V
<7.5 V. Solving for R gives:
The implementation of the NCP51705 DESAT function
can be realized using only two external components. As
shown in Figure 39, the drain−source voltage of the SiC
DESAT
1
ǒ
Ǔ
V
DESAT * VD1 * ID RDS
R1 +
(eq. 3)
400 mA
MOSFET, Q is monitored via the DESAT pin through R
1
1
In addition to setting the maximum allowable V
voltage, R also serves the dual purpose of limiting the
DS
and D .
1
1
instantaneous current through the junction capacitance of
D . Because the drain voltage on the SiC MOSFET sees
1
NCP51705
DESAT Function
VDD
extremely high dV/dt, the current through the p−n junction
mA
400
R1
D1
capacitance of D can become very high if R is not sized
1
1
DESAT
22
appropriately. Therefore, selecting a fast, high−voltage
diode with lowest junction capacitance should be a priority.
3.3 V
Typical values for R will be near the range of
5
60 k
1
ID
5kW<R <10kW but this can vary according to the I and
Q
Q
S
R
1
D
500ns
Timer
R
DS
parameters of the selected SiC MOSFET. If R is much
1
12 k
smaller than 5 kW, the instantaneous current into the DESAT
pin can be hundreds of milliamps, which is problematic to
the 400 mA internal DESAT current source. Conversely, if
1.25 V
IN
18
17
14
13
VDS
R is much larger than 10 kW, a RC delay ensues as a product
1
OUTSRC
OUTSNK
DESAT_FLT
ENABLE
Q1
SiC
Drive
of R and the junction capacitance of D . The delay can be
1
1
on the order of few ms, resulting in an additional delay time
responding to an over current condition.
Figure 39. NCP51705 DESAT Function
5 V Bias (V5V)
During the time that Q is off several hundred volts can
This is the bypass capacitor pin for the internal 5 V bias
rail powering the control circuitry. The recommended
capacitor value is 2.2 mF. At least a 1 mF, good−quality,
high−frequency, ceramic capacitor should be placed in close
proximity to the pin. A smaller ceramic capacitor value such
as 100 nF will assure stability but may result in a 500 mV
overshoot on the 5 V rail during start−up. The 5 V rail starts
1
appear across the drain−source terminals. Once Q is turned
1
on, the drain−source voltage rapidly falls and this transition
from high−voltage to near zero voltage is expected to
happen in less than a few hundred nano−seconds. During the
turn−on transition, the leading edge of the DESAT signal is
blanked by a 500 ns timer, consisting of a 5 W, low
impedance pull−down resistance. This allows sufficient
to rise approximately 30 ms after V is applied. Once the
DD
time for V to fall while at the same time ensuring DESAT
7 V threshold is exceeded at the VDD pin, the 5 V rail is
enabled. The V5V pin can source up to 10 mA making it
suitable for use as a low power bias supply for housekeeping
circuits such as open collector pull−up, optocoupler or
digital isolator bias.
DS
is not inadvertently activated. After 500 ns, the DESAT pin
is released and the 400 mA current source provides a constant
current through R , D and the SiC MOSFET on−resistance.
1
1
During the on−time, if the DESAT pin rises above 7.5 V, the
DESAT comparator output goes HIGH which triggers the
clock input of an RS latch. Such a fault will reduce the
on−time of the Q_NOT output on a cycle−by−cycle basis.
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18
NCP51705
Applications Information – High−Side Gate Drive Example
Many high−voltage switching applications use power
dedicated to the low−side gate drive is not level shifted and
therefore only serves the purpose of electrical safety and
galvanic isolation. In this simplified example, IN+
(non−inverting PWM logic) and IN− (active enable) are the
only two signals sourced from the digital controller and
XEN is read back from the NCP51705. XEN can be used as
the timing information basis for developing gate drive
timing, cross conduction prevention, dead−time adjustment
and fault detection. The V5V from the NCP51705 can be
used to power the secondary side of each digital isolator as
shown Figure 40.
topologies that include high−side, low−side gate drive
schemes. Some well known examples include converter
topologies such as: LLC, half−bridge and full−bidge. The
NCP51705 can be applied in half−bridge (or full−bridge)
power topologies such as the one shown in Figure 40.
High−voltage applications tend to prefer isolated drivers for
both, the high−side and low−side gate drive. This implies the
need for two digital isolators. In addition to providing
electrical safety and galvanic isolation, the digital isolator
assigned to the high−side gate driver, serves the dual purpose
of level shifting the IN+ PWM input signal. Since the
low−side drive is ground referenced, the digital isolator
CONTROLLER BIAS (3.3 V or 5 V)
ISOLATOR BIAS
20 V BIAS (isolated)
PWM_HS
Digital Controller
FAULT_HS
XEN_HS
ENABLE
PWM_LS
Digital
Isolators
ISOLATOR BIAS
20 V BIAS (isolated)
FAULT_LS
XEN_LS
Isolation
Boundary
Figure 40. NCP51705 Half−Bridge Gate Drive
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19
NCP51705
PCB Guideline
IN+
1
2
3
4
5
6
18
17
16
OUTSRC
OUTSRC
IN−
XEN
PGND
NCP51705
(Top View)
SGND
VEESET
VCH
15 PGND
14
OUTSNK
13 OUTSNK
Figure 41. Recommend PCB drawing
First of all, to optimize operation of SiC gate driving
should be minimize influence of the parasitic inductance and
capacitance on the layout. The following should be
considered before beginning a PCB layout using the
NCP51705.
• The SiC driver should be locate as close as possible to
the SiC MOSFET.
• VDD, SVDD, V5V, Charge Pump and VEE capacitor
should be locate as close as possible to the device.
• When the VEESET = GND, the VEE should be as
close as possible to the PGND trace.
• Driver input and DESAT should not going close to the
high dV/dT traces. It can cause abnormal operation by
significant noise.
• If the device operates in the high temperature condition,
use thermal via distribution from exposed pad to the
other layer to make the thermal resistance as low as
possible. In this case, do not connect the thermal pad to
SGND or PGND.
• Use wide traces for OUTSRC, OUTSNK and VEE
related with main gate driving path.
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20
NCP51705
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
CASE 485L
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
L
L
D
A
B
PIN 1
REFEENCE
L1
DETAIL A
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
ALTERNATE
2X
CONSTRUCTIONS
MILLIMETERS
0.15
C
DIM MIN
MAX
1.00
0.05
A3
A
A1
A3
b
0.80
0.00
EXPOSED Cu
MOLD CMPD
2X
0.15
C
TOP VIEW
0.20 REF
0.20
0.30
2.90
D
4.00 BSC
DETAIL B
D2
E
2.70
2.70
A1
0.10
0.08
C
C
4.00 BSC
DETAIL B
E2
e
2.90
A
ALTERNATE TERMINAL
CONSTRUCTIONS
0.50 BSC
L
0.30
0.05
0.50
0.15
A3
L1
SEATING
PLANE
C
NOTE 4
A1
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT
D2
DETAIL A
24X L
4.30
7
24X
0.55
2.90
13
E2
1
1
24
19
24X b
2.90
4.30
e
e/2
0.10 C A B
NOTE 3
0.05 C
BOTTOM VIEW
24X
0.32
0.50
PITCH
DIMENSIONS: MILLIMETERS
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