NCP51820D [ONSEMI]
High Speed Half-Bridge Driver for GaN Power Switches;
| 型号： | NCP51820D |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Half-Bridge Driver for GaN Power Switches |
| 文件： | 总20页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Half-Bridge
Driver for GaN Power
Switches
NCP51820
The NCP51820 high−speed, gate driver is designed to meet the
stringent requirements of driving enhancement mode (e−mode), high
electron mobility transistor (HEMT) and gate injection transistor
(GIT), gallium nitrade (GaN) power switches in off−line, half−bridge
power topologies. The NCP51820 offers short and matched
propagation delays with advanced level shift technology providing
−3.5 V to +650 V (typical) common mode voltage range for the
high−side drive and −3.5 V to +3.5 V common mode voltage range for
the low−side drive. In addition, the device provides stable dV/dt
operation rated up to 200 V/ns for both driver output stages in high
speed switching applications.
To fully protect the gate of the GaN power transistor against
excessive voltage stress, both drive stages employ a dedicated voltage
regulator to accurately maintain the gate−source drive signal
amplitude. The circuit actively regulates the driver’s bias rails and thus
protects against potential gate−source over−voltage under various
operating conditions.
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QFN15 4x4, 0.5P
CASE 485FN
MARKING DIAGRAM
51820A
ALYW G
G
51820A = Specific Device Code
The NCP51820 offers important protection functions such as
independent under−voltage lockout (UVLO), monitoring VDD bias
voltage and VDDH and VDDL driver bias and thermal shutdown
based on die junction temperature of the device. Programmable
dead−time control can be configured to prevent cross−conduction.
A
L
YW
G
= Assembly Site
= Wafer Lot Number
= Assembly Start Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
PIN ASSIGNMENT
• 650 V, Integrated High−Side and Low−Side Gate Drivers
• UVLO Protections for VDD High and Low−Side Drivers
• Dual TTL Compatible Schmitt Trigger Inputs
• Split Output Allows Independent Turn−ON/Turn−OFF Adjustment
• Source Capability: 1 A; Sink Capability: 2 A
VDDH
1
2
3
4
13 EN
12 HIN
11 LIN
HOSRC
HOSNK
SW
• Separated HO and LO Driver Output Stages
NCP51820
(Top View)
• 1 ns Rise and Fall Times Optimized for GaN Devices
• SW and PGND: Negative Voltage Transient up to 3.5 V
• 200 V/ns dV/dt Rating for all SW and PGND Referenced Circuitry
• Maximum Propagation Delay of Less Than 50 ns
• Matched Propagation Delays to Less Than 5 ns
• User Programmable Dead−Time Control
10 SGND
9
DT
• Thermal Shutdown (TSD)
Typical Applications
ORDERING INFORMATION
• Driving GaN Power Transistors used in Full or Half−Bridge, LLC,
Active Clamp Flyback or Forward, Totem Pole PFC and
Synchronous Rectifier Topologies
• Industrial Inverters and Motor Drives
• AC to DC Converters
†
Device
NCP51820AMNTWG
Package
Shipping
QFN15
(Pb−Free)
4000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
August, 2020 − Rev. 2
NCP51820/D
NCP51820
VIN
VDD
VDDH
EN
1
2
3
4
13
12
11
10
9
PWM
mC
or
HOSRC
HOSNK
SW
HIN
LIN
NCP51820
(Top View)
DSP
SGND
DT
POWER
STAGE
Figure 1. Typical Application Schematic
VDDH
REGULATOR
VBST
VDD
VDDH
HOSRC
HOSNK
SW
VDDH
UVLO
S
R
HO
Q
LEVEL SHIFTER
VDD
UVLO
8.5V/8V
(ON/OFF)
SCHMITT
TRIGGER INPUT
EN
HIN
LIN
DT
VDDL
REGULATOR
VDDL
SHOOT THOUGH
PREVENTION
CYCLE−By−
CYCLE EDGE
TRIGGERED
SHUTDOWN
VDDL
UVLO
LOSRC
LOSNK
PGND
LO
DELAY
LEVEL SHIFTER
DEAD−TIME
MODE CONTROL
SGND
Figure 2. Internal Block Diagram
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2
NCP51820
PIN CONNECTIONS
VDDH
HOSRC
HOSNK
SW
1
2
3
4
13
12
11
10
9
EN
HIN
LIN
NCP51820
(Top View)
SGND
DT
Figure 3. Pin Assignments – 15 Lead QFN (Top View)
PIN DESCRIPTION
Pin No.
Name
Description
High−side driver positive bias voltage output
High−side driver sourcing output
1
2
VDDH
HOSRC
HOSNK
SW
3
High−side driver sinking output
4
Switch−node / high−side driver return
Low−side driver positive bias voltage output
Low−side driver sourcing output
5
VDDL
LOSRC
LOSNK
PGND
DT
6
7
Low−side driver sinking output
8
Power ground / low−side driver return
Dead time adjustment / mode select
Logic / signal ground
9
10
11
12
13
14
15
SGND
LIN
Logic input for low−side gate driver output
Logic input for high−side gate driver output
Logic input for disabling the driver (low power mode)
Bias voltage for high current driver
Bootstrap positive bias voltage
HIN
EN
VDD
VBST
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3
NCP51820
ABSOLUTE MAXIMUM RATINGS (All voltages are referenced to SGND pin unless otherwise noted)
Symbol
Rating
Min
−0.3
−0.3
Max
20
Unit
V
V
DD
Low−side and logic−fixed supply voltage (PGND = SGND)
V
DDL
Low−side supply voltage V
(internally regulated; output only, do not
connect to external voltage source, referenced to PGND)
5.5
V
DDL
V
High−side common mode voltage range (SW)
−3.5
−0.3
650
5.5
V
V
SW
V
DDH
High−side floating supply voltage V
(internally regulated; output only,
DDH
do not connect to external voltage source; referenced to SW)
V
High−side floating supply voltage V
High−side floating supply voltage V
−0.3
−0.3
−0.3
670
20
V
V
V
BST_SGND
BST
BST
V
(referenced to SW)
BST_SW
V
,
High−side floating driver sourcing/sinking output voltage (referenced to SW)
V
+0.3
DDH
HOSRC
V
HOSNK
V
PGND voltage
−3.5
−0.3
3.5
+0.3
V
V
PGND
V
,
Low−side driver sourcing/sinking output voltage (referenced to PGND)
V
LOSRC
DDL
V
LOSNK
V
Logic input voltage (HIN, LIN, and EN)
Dead−time control voltage (DT)
Allowable offset voltage slew rate
Operating Junction Temperature
Storage Temperature Range
−0.3
−0.3
−
V
+0.3
+0.3
V
V
IN
DD
V
DT
V
DD
dV /dt
SW
200
V/ns
°C
°C
kV
kV
T
−
150
150
1
J
T
STG
−55
−
Electrostatic Discharge Capability
Human Body Model (Note 3)
Charged Device Model (Note 3)
−
1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. V – PGND voltage must not exceed 20 V
DD
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012
ESD Charged Device Model tested per JESD22−C101.
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 Class I.
THERMAL CHARACTERISTICS
Symbol
Rating
Value
245
Unit
q
Thermal Characteristics,
QFN15 4x4 (Note 5)
IS0P
IS2P
IS0P
IS2P
°C/W
JA
188
Thermal Resistance Junction−Ambient (Note 6)
P
D
Power Dissipation (Note 6)
QFN15 4x4 (Note 5)
0.51
0.665
W
5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
6. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2×114.3×1.6 mm PCB (FR−4 glass epoxy material).
IS0P: one single layer with zero power planes
IS2P: one single layer with two power planes
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4
NCP51820
RECOMMENDED OPERATING CONDITIONS (All voltages are referenced to SGND pin unless otherwise noted)
Symbol
Rating
Min
9
Max
17
Unit
V
V
DD
Low−side and logic−fixed supply voltage
V
SW
−SGND
SW−SGND maximum dc offset voltage (High−Side driver)
−
580
V
V
BST
High−side floating supply voltage V
−
V +17
SW
V
BST
V
, V
, V
High−side floating driver sourcing/sinking output voltage
Low−side driver sourcing/sinking output voltage
Logic input voltage (HIN, LIN, and EN)
−
V
DDH
V
HOSRC
HOSNK
LOSNK
V
−
V
DDL
V
LOSRC
V
IN
−
17
V
PGND−SGND
PGND−SGND maximum dc offset voltage (Low−Side driver)
−3.0
3.0
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (V
(V , V
) = 15 V, DT = SGND = PGND and C
= 330 pF for typical values
BIAS
DD
BST
LOAD
T = 25°C, for min/max values T = −40°C to +125°C, unless otherwise specified.) The V and I parameters are referenced to SGND.
A
A
IN
IN
The V and I parameters are referenced to V
and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC,
O
O
SW
and LOSNK.
Symbol
Parameter
Test Conditions and Description
Min
Typ
Max
Unit
POWER SUPPLY SECTION (VDD)
Quiescent V supply current
I
V
= V = 0 V, EN = 0 V
HIN
−
−
100
1.5
8.5
8.0
0.5
5.3
150
2.5
9.0
8.5
−
mA
mA
V
QDD
DD
LIN
I
Operating V supply current
f
= 500 kHz, average value
PDD
DD
LIN
V
V
V
DD
V
DD
V
DD
V
DD
UVLO positive going threshold
UVLO negative going threshold
UVLO Hysteresis
V
DD
V
DD
V
DD
= Sweep
= Sweep
= Sweep
8.0
7.5
−
DDUV+
DDUV−
DDHYS
V
V
V
t
UVLO Filter Delay Time (Note 7)
−
−
ms
UVDDFLT
BOOTSTRAPPED POWER SUPPLY SECTION
Offset supply leakage current
I
LK
V
V
= V
= 600 V
−
−
−
−
10
100
2.5
mA
mA
BST
SW
I
Quiescent V
supply current
supply current
= V
= 0 V, EN = 5 V
35
1.5
QBST
BST
BST
LIN
HIN
I
Operating V
f
= 500 kHz, average value
mA
PBST
HIN
GATE DRIVER POWER SUPPLY SECTION
V
V
−V
regulated voltage
0 mA < I < 10 mA
4.94
4.94
5.20
5.20
5.46
5.46
V
V
DDH
DDH
SW
O
V
V −PGND regulated voltage
DDL
DDL
INPUT LOGIC SECTION (HIN, LIN and EN)
V
High Level Input Voltage Threshold
Low Level Input Voltage Threshold
Input Logic Voltage Hysteresis
High Level Logic Input Bias Current
Low Level Logic Input Bias Current
Input Pull−down Resistance
−
1.2
−
−
−
2.5
−
V
V
INH
V
INL
V
0.5
15
−
−
V
IN_HYS
I
V
HIN
V
HIN
V
HIN
= V = 5 V
9
21
2.2
−
mA
mA
kW
IN+
LIN
I
= V = 0 V
−
IN−
LIN
R
= V = 5 V
−
333
IN
LIN
DEAD−TIME SECTION
V
Minimum Dead−Time Control Voltage
Maximum Dead−Time Control Voltage
R
R
= 30 kW
0.45
22
3.1
160
−
0.60
30
4.0
200
−
0.75
38
V
DT,MIN
DT,MIN
DT
DT
t
ns
V
V
= 200 kW
4.8
240
5
DT,MAX
DT,MAX
t
ns
ns
ns
Dt
Dead−Time mismatch between
LO → HO and HO → LO
R
R
= 30 kW
DT
DT
DT
= 200 kW
−
−
10
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NCP51820
ELECTRICAL CHARACTERISTICS (V
(V , V
) = 15 V, DT = SGND = PGND and C
= 330 pF for typical values
BIAS
DD
BST
LOAD
T = 25°C, for min/max values T = −40°C to +125°C, unless otherwise specified.) The V and I parameters are referenced to SGND.
A
A
IN
IN
The V and I parameters are referenced to V and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC,
O
O
SW
and LOSNK. (continued)
Symbol
Parameter
Test Conditions and Description
Min
Typ
Max
Unit
DEAD−TIME SECTION
V
Dead−Time Disable Threshold
Cross conduction prevention active
0.35
5.5
0.40
6.0
0.45
6.5
V
V
DT,0
V
High− & Low−Side Overlap Enable
Threshold
Cross conduction prevention
disabled
DT,OLE
PROTECTION SECTION
V
UVLO Threshold on VDDH and VDDL
positive going threshold
4.15
4.0
4.40
4.2
4.70
4.5
V
V
UVTH_VDDX+
V
UVLO Threshold on VDDH and VDDL
negative going threshold
UVTH_VDDX−
TSD
hys
Thermal Shutdown (Note 7)
150
−
−
−
°C
°C
Hysteresis of Thermal Shutdown
(Note 7)
−
50
GATE DRIVE OUTPUT SECTION
V
High−level output voltage,
I
I
= 10 mA
= 10 mA
−
−
10
5
40
20
mV
mV
OH
OSRC
V
−V or V −V
VDDH
HOSRC
VDDL
LOSRC
V
Low−level output voltage,
−V or V
OL
OSNK
V
–PGND
LOSNK
HOSNK
SW
I
Peak source current (Note 7)
Peak sink current (Note 7)
C
C
= 200 pF, R
= 200 pF, R
= 1 W
= 1 W
0.9
1.8
1.0
2.0
−
−
A
A
OSRC
LOAD
LOAD
gate
I
OSNK
gate
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, is not tested in production.
DYNAMIC ELECTRICAL CHARACTERISTICS (V
(V , V
)=15 V, DT=SGND=PGND and C
=330 pF, for typical
LOAD
BIAS
DD
BST
values T =25°C, for min/max values T =−40°C to +125°C, unless otherwise specified.) (Notes 9)
A
A
Symbol
Parameter
Test Conditions
Min
−
Typ
100
25
Max
150
50
Unit
mA
I
Quiescent V supply current
V
LIN
= V = 0 V, EN = 0 V
HIN
QDD
DD
t
LOSRC turn−on propagation delay
LIN rising to LOSRC rising (50% to 10%)
−
ns
PDLON
time
t
LOSNK turn−off propagation delay
LIN falling to LOSNK falling (50% to 90%)
−
−
−
25
25
25
50
50
50
ns
ns
ns
PDLOFF
time
t
HOSRC turn−on propagation delay
time
HIN rising to HOSRC rising (50% to 10%)
SW = PGND
PDHON
t
HOSNK turn−off propagation delay
time
HIN falling to HOSNK falling (50% to 90%)
SW = PGND
PDHOFF
t
LOSRC turn−on rising time
LOSNK turn−off falling time
HOSRC turn−on rising time
HOSNK turn−off falling time
Propagation Delay match
Minimum input pulse width
−
−
−
−
−
−
2
1.5
2
4
3.0
4
ns
ns
ns
ns
ns
ns
RL
t
FL
t
RH
SW = PGND
t
FH
1.5
−
3.0
5
Dt
HIN to HO and LIN to LO, SW = PGND
DEL
PW
t
−
10
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. This parameter, although guaranteed by design, is not tested in production.
9. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C.
J
A
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NCP51820
Timing Diagram
Shown in Figure 4 are the timing waveform definitions matching the specified dynamic electrical characteristics specified
in the gate drive output section.
50%
HIN
(LIN)
90%
10%
HO
(LO)
t
t
t
t
FH
PDHON
RH
PDHOFF
(t
) (t
)
(t ) (t )
PDLOFF FL
PDLON
RL
Figure 4. Input to Output Timing Diagram
60
50
14
12
10
8
CLOAD = 0 pF
CLOAD = 100 pF
CLOAD = 330 pF
CLOAD = 1 nF
40
30
20
10
0
6
4
2
0
10
100
1000
10000
10
100
1000
[kHz]
10000
F
HIN
= F
[kHz]
F
= F
LIN
LIN
HIN
Figure 5. Operating VDD Supply Current (IPDD) vs.
Frequency (VDD = 12 V, SW = PGND, EN = VDD,
Both Outputs Switching)
Figure 6. Operating VDD Supply Current (IPDD) vs.
Frequency (VDD = 12 V, SW = PGND, EN = VDD,
Both Outputs Switching)
4.0
3.0
3.0
2.5
2.0
1.5
140
125
110
95
IQDD, EN = 0 V
IQBST, EN = 5 V
80
65
LIN = 100 kHz
LIN = 500 kHz
LIN = 1 MHz
HIN = 100 kHz
HIN = 500 kHz
HIN = 1 MHz
1.0
0.5
0.0
50
35
20
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 7. Quiescent Current (IQDD, IQBST) vs.
Temperature
Figure 8. Operating Current (IPDD, IPBST) vs.
Temperature
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NCP51820
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.22
5.21
5.20
5.19
5.18
5.17
VDDH, 0 mA
VDDH, 10 mA
VDDUV+
VDDUV−
5.16
5.15
5.14
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 9. VDD UVLO (VDDUVLO+, VDDUVLO−) vs.
Temperature
Figure 10. VDDH (VDDH) Regulated Output Voltage
vs. Temperature
5.22
5.21
5.20
5.19
5.18
5.17
5.16
5.15
5.14
2.2
2.1
2.0
1.9
1.8
1.7
VINH
VINL
1.6
1.5
1.4
1.3
1.2
VDDH, 0 mA
VDDH, 10 mA
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 11. VDDL (VDDL) Regulated Output Voltage
vs. Temperature
Figure 12. Input Logic (HIN, LIN, EN) Threshold vs.
Temperature
400
375
350
325
300
275
250
22
20
18
tPDLON
16
14
12
10
tPDLOFF
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 13. Input Logic (HIN, LIN, EN) Pull−down
Figure 14. LIN to LOSRC Propagation Delay vs.
Temperature
Resistance vs. Temperature
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NCP51820
22
20
18
16
14
12
10
3.0
2.5
2.0
1.5
1.0
tPDHON
tPDHOFF
tRL
tFL
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 16. LOSRC Rise Time and LOSNK Fall Time vs.
Temperature
Figure 15. HIN to HOSRC Propagation Delay vs.
Temperature
3.0
2.5
2.0
1.5
4.5
4.4
4.3
4.2
VUVTH_VDDL+
VUVTH_VDDL−
4.1
tRH
tFH
1.0
−40 −20
4.0
−40 −20
0
20
40
60
80
100 120
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 17. HOSRC Rise Time and HOSNK Fall Time
vs. Temperature
Figure 18. VDDL UVLO vs. Temperature
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
4.5
4.4
4.3
4.2
VUVTH_VDDH+
VUVTH_VDDH−
4.1
4.0
0
−40 −20
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 20. VBST Leakage Current (ILK) vs.
Temperature
Figure 19. VDDH UVLO vs. Temperature
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NCP51820
2.5
2.0
1.5
1.2
1.0
0.8
0.6
0.4
0.2
0.0
tDEL_SRC
tDEL_SNK
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
Delta, tDT (RDT = 30 kW)
Delta, tDT (RDT = 200 kW)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 21. Propagation Delay Matching (HIN to HO,
LIN to LO) vs. Temperature
Figure 22. Dead−time Mismatch vs. Temperature
35
34
33
32
31
30
29
28
27
26
25
0.70
0.69
0.68
0.67
0.66
0.65
0.64
0.63
tDT, MIN; HO−LO
0.62
tDT, MIN; LO−HO
0.61
0.60
VDT, MIN
−40 −20
0
20
40
60
80 100 120
Temperature [°C]
Figure 23. Minimum Dead−time (RDT = 30 kW) vs. Temperature
216
214
212
210
208
206
204
202
200
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
tDT, MIN; HO−LO
tDT, MIN; LO−HO
VDT, MIN
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Figure 24. Maximum Dead−time (RDT = 200 kW) vs. Temperature
www.onsemi.com
10
NCP51820
APPLICATIONS INFORMATION
The NCP51820 can be quickly configured by following the steps outlined in this section. The component references made
throughout this section refer to the schematic diagram and reference designations shown in Figure 25.
C
VBST
D
R
HBST
BST
VIN
VDD
C
VDD
R
EN
C
VDDH
VDDH
EN
1
2
3
4
13
12
11
10
9
PWM
mC
or
C
ENBYP
R
R
HOSRC
HOSRC
HOSNK
SW
HIN
LIN
Q
H
HOSNK
NCP51820
(Top View)
DSP
SGND
C
DTBYP
POWER
STAGE
DT
R
DT
C
VDDL
R
R
LOSRC
Q
L
LOSNK
Figure 25. Application Schematic, Half−Bridge Example (Kelvin Gate Return Connections Shown)
DETAILED PIN FUNCTIONALITY
Bias Supply Voltage (VDD)
A dc voltage applied to VDD provides bias for the digital
inputs, internal logic functions, high−side floating bootstrap
(VBST) bias supplying the internal high−side regulator
(VDDH) as well as providing bias directly to the internal
low−side regulator (VDDL). Because the GaN FETs receive
source current locally through the dedicated internal
is below 6 V. A large value for C
means the bootstrap
VBST
capacitor will take longer to fully charge as also determined
by the on−time of the low−side GaN. Neglecting the effects
of parasitic inductance, the minimum value bootstrap
capacitor can be approximated as:
QG
CBST
+
regulators, a single VDD bypass capacitor, C
, is all
VDD
(eq. 1)
DVBST
that’s required, connected directly between the VDD and
SGND pins. The C capacitor should be a ceramic bypass
Where:
VDD
capacitor > 100 nF, located as close as possible to the VDD
and SGND pins to properly filter out all glitches while
switching. Under voltage lockout (UVLO) is important for
protecting the GaN FETs and power stage. The NCP51820
Q
DV
N
= total gate charge required by GaN
= VDD − V − NxV > 6 V
G
BST
PP
F
= number of series diodes connected
= allowable V droop voltage
V
V
PP
BST
includes UVLO thresholds of V
> 8.5 V, ON and
(typically less than 10% of VDD)
= D forward voltage drop
DDUV+
V
DDUV−
< 8 V, OFF, making it well suited for +12 V bias
F
BST
rails.
Choose a low ESR and ESL ceramic capacitor with a
High−Side Bootstrap Voltage (VBST)
voltage rating of twice the applied voltage (2 x DV ).
BST
Three components make up the high side bootstrap
voltage bias serving as the input to the VDDH regulator. The
Once the bootstrap capacitor is selected, the peak charging
current can be determined by knowing the frequency and
duty cycle of the low−side gate drive.
bootstrap current limiting resistor and diode, R
and
BST
D
, series connected between the VDD and VBST pins
BST
DVBST FSW
dV
IPK + CBST
+ CBST
and the bootstrap capacitor, C
, connected directly
VBST
(eq. 2)
dt
DMAX
Switch node between VBST and (SW) pins. The VBST
voltage is input to an internal LDO which produces the
VDDH voltage. The LDO has a dropout voltage of 6 V. No
high side pulses are produced when the voltage on VBST pin
Where:
D
= Max duty cycle of low−side gate drive
MAX
F
SW
= Switching frequency
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11
NCP51820
Low−Side Linear Regulator (VDDL)
The bootstrap diode, D , needs to have a voltage rating
BST
The NCP51820 includes an internal linear regulator
dedicated to providing a tightly regulated, 5.2 V gate drive
amplitude signal to the low−side GaN FET. The VDDL
regulator is fed directly from VDD, providing the most
direct interface to the low−side GaN FET. This assures the
lowest possible parasitic capacitance, required for meeting
high−speed switching requirements of GaN. The VDDL
regulator is referenced between VDDL and the power
ground (PGND) pins and is capable of operating from
common mode voltage range between −3.5 V to +3.5 V.
Source current for the low−side GaN FET is provided from
greater than VIN, should be high−speed (low reverse
recovery), should be low current and should have very low
junction capacitance. Diode junction capacitance, C , can
J
become more problematic due to the high dV/dt that can
appear across the GaN V . Symptoms of high dV/dt
DS
switching can be mitigated by using a Kelvin source return
to SW, as shown in Figure 25. Another method to reduce C
J
is to use 2 or more diodes in series such that the sum of the
total voltage ratings from each diode is greater than VIN.
Each of the individual C ’s add reciprocally to reduce the
J
total junction capacitance. The additional number of diode
forward voltage drops must also be accounted for when
the charge stored in the C
and PGND. The value of the C
connected between VDDL
capacitor is a function
VDDL
calculating C
.
VDDL
BST
of the gate charge requirement of the low−side GaN FET.
The VDDL regulator also includes dedicated UVLO
The purpose of the bootstrap resistor, R , is to limit
BST
peak C
charging current, I , especially during startup.
BST
PK
thresholds of
V
>
4.5 V, ON and
A small resistor may not limit the peak current enough,
resulting in excessive ringing which can cause jitter in the
high−side gate drive and/or EMI problems. A large resistor
will dissipate more power and create a longer RC time
constant causing a longer start−up time. A bootstrap resistor
UVTH_VDDL+
V
< 4.3 V, OFF.
UVTH_VDDL−
Signal Ground (SGND) and Power Ground (PGND)
SGND is the GND for all internal control logic and digital
inputs. Internally, the SGND and PGND pins are isolated
from each other.
in the range of 1 W < R
< 10 W is usually sufficient.
BST
PGND serves as the low−side, gate drive, return
reference. As shown in Figure 2, the low−side level shifter,
drive logic, PMOS sink and VDDL regulator are referenced
to PGND. For GaN FETs that include a source Kelvin return,
a direct connection should be made from PGND to the GaN
High−Side Linear Regulator (VDDH)
The NCP51820 includes an internal linear regulator
dedicated to providing a tightly regulated, 5.2 V gate drive
amplitude signal to the high−side GaN FET. The VDDH
regulator appears after the bootstrap, providing the most
direct interface to the high−side GaN FET. This assures the
lowest possible parasitic capacitance, required for meeting
high−speed switching requirements of GaN. The VDDH
regulator is referenced between VDDH and the SW pins and
can float between a common mode voltage range of −3.5 V
up to 650 V. Source current for the high−side GaN FET is
FET Kelvin return. C
should then be referenced to the
VDDL
PGND but separate from the power stage ground as shown
in Figure 25. For GaN FETs that do not include a dedicated
source Kelvin pin, best practice PCB layout techniques
should be used to isolate the gate drive return current from
the power stage, ground return current. Please refer to
document AND9932, for NCP51820 and high−speed GaN,
PCB layout tips.
provided from the charge stored in C
between VDDH and SW. The value of the C
connected
VDDH
capacitor
VDDH
For half−bridge power topologies or any applications
using a current sense transformer, SGND and PGND must
be connected together on the PCB. In such applications, it is
recommended to connect the SGND and PGND pins
together with a short, low−impedance trace on the PCB as
close to the NCP51820 as possible. Directly beneath the
NCP51820 is an ideal way to make the SGND to PGND
connection.
is a function of the gate charge requirement of the GaN FET.
The VDDH regulator also includes dedicated UVLO
thresholds of
V
>
4.5 V, ON and
UVTH_VDDH+
V
< 4.3 V, OFF.
UVTH_VDDH−
Switch Node (SW)
The SW pin serves as the high−side, gate drive, return
reference. As shown in Figure 2, the high−side level shifter,
drive logic, PMOS sink and VDDH regulator are referenced
to SW. For GaN FETs that include a source Kelvin return, a
direct connection should be made from SW to the GaN FET
For low−power applications, such as the active−clamp
flyback or forward shown in Figure 26, a current sensing
resistor, R , located in the low−side GaN FET source leg
CS
Kelvin return. C
and C
should then be referenced
VDDH
BST
is commonly used. In such applications, the NCP51820
PGND and SGND pins must not be connected on the PCB
to the SW pin but separate from the power stage switch node
as shown in Figure 25. For GaN FETs that do not include a
dedicated source Kelvin pin, best practice PCB layout
techniques should be used to isolate the gate drive return
current from the power stage, switch node current. Please
refer to document AND9932, for NCP51820 and
high−speed GaN, PCB layout tips.
because R would essentially be shorted through this
CS
connection. The NCP51820 low−side drive circuit is able to
withstand −3.5 V to +3.5 V of common mode voltage. Since
most current sense voltage signals are less than 1 V, the
low−side drive stage can easily “float” above the voltage,
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12
NCP51820
V
, generated by the current sense. For the active clamp
gate−source terminals. A low impedance current sense
resistor is recommended. Please refer to document
AND9932, for NCP51820 and high−speed GaN, PCB
layout tips.
RCS
example in Figure 26, the entire low−side gate drive, shown
in the shaded box, is floating above V . This is important
because it ensures no loss of gate drive amplitude so the full
RCS
5.2 V, VDDL voltage appears at the low−side GaN FET
D
R
HBST
C
BST
VBST
VIN
VDD
C
VDD
R
EN
C
CL
C
VDDH
VDDH
EN
1
2
3
4
13
12
11
10
9
R
R
C
HOSRC
ENBYP
POWER
STAGE
HOSRC
HOSNK
SW
HIN
LIN
PWM
mC
or
Q
H
HOSNK
NCP51820
(Top View)
DSP
SGND
C
DTBYP
DT
R
DT
C
VDDL
R
R
LOSRC
Q
L
LOSNK
R
CS
V
RCS
Figure 26. Application Schematic, Active Clamp, Low−Side, Floating Gate Drive Example
Input (HIN, LIN)
Enable (EN)
Both independent PWM inputs are Schmitt trigger,
Transistor−Transistor Logic (TTL) compatible and are
internally pulled low to SGND such that each corresponding
driver input is defaulted to the inactive (disabled) state. The
TTL input thresholds provide buffer and logic level
translation functions capable of operating from a variety of
PWM signals up to VDD of the NCP51820. TTL levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage greater than 2.5 V
maximum is considered logic high. Both input thresholds
meet industry−standard, TTL−logic defined thresholds and
Enable (EN) is internally pulled low to SGND so the
driver is always defaulted to a disabled output status. Similar
to HIN and LIN, EN is a Schmitt trigger TTL compatible
input. Pulling the EN pin above 2.5 V maximum, enables the
outputs, placing the NCP51820 into an active ready state.
Due to the nature of high−speed switching associated with
GaN power stages, and for improved noise immunity, it is
recommended to connect the EN pin to VDD through a 1 kW
(or less) pull−up resistor. For applications where the EN pin
is actively controlled, the EN pin can be driven direct but
should be bypassed with a 10 nF decoupling capacitor. As
shown in Figure 27, if EN is pulled low during normal
operation, the driver outputs are immediately disabled, even
terminating an active HIN or LIN pulse mid –cycle during
the on−time. When EN is toggled high, during normal
operation, a cycle−by−cycle, edge−triggered logic function
is employed to prevent shortened, erroneous control pulses
from being processed by the output. This behavior is
highlighted in Figure 27, where EN transitions high at the
same time the HIN (or LIN) input pulse is high. In this way,
the NCP51820 is intelligent by waiting until the next rising
edge to process the full input signal to the output driver
stage.
are therefore independent of V
voltage. A typical
DD
hysteresis voltage of 0.5 V is specified for each driver input.
For optimal high−speed switching performance, the driving
signal for the TTL inputs should have fast rising and falling
edges with a slew rate of 6 V/ms or faster, so a rise time from
0 to 3.3 V should be 550 ns or less.
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13
NCP51820
HIN
(LIN)
HO
(LO)
EN
External Shutdown
Figure 27. Timing Chart of Enable Function
Dead−Time Control (DT)
Accurately ensuring some minimal amount of dead−time
between the high−side and low−side gate drive output
signals is critical for safe, reliable optimized operation of
any high−speed, half−bridge power stage. The DT should be
MODE B:
Connect a 25 kW < R < 200 kW Resistor from DT to
DT
SGND; Dead−time is programmable by a single resistor
connected between the DT and SGND pins. The amount of
desired dead−time can be programmed via the dead−time
bypassed with a 100 nF (C ) ceramic capacitor placed
DTBYP
closest to the pin and directly between DT and SGND. If
resistor, R , between the range of 25 kW < R < 200 kW
DT
DT
used, the R resistor should then be placed directly in
to obtain an equivalent dead−time, proportional to R , in
DT
DT
parallel with C
The NCP51820 offers four unique
the range of 25 ns < t < 200 ns. If either edge between HIN
DTBYP.
DT
mode settings to utilize dead−time in such a way to be fully
and LIN result in a dead−time less than the amount set by
compatible with any control algorithm.
R , the set DT value shall be dominant. If either edge
DT
between HIN and LIN result in a dead−time greater than the
amount set by R , the controller dead−time shall be
MODE A:
DT
Connect DT to SGND; When the DT pin voltage, V , is
less than 0.5 V typical (R = 0 W), the DT programmability
DT
dominant. The control voltage range, V , for R is 0.5 V
DT
DT
DT
< V < 4 V. DT programmability is summarized and shown
DT
is disabled and fixed dead−time, anti−cross−conduction
protection is enabled. If HIN and LIN are overlapping by X
ns, then X ns of dead−time is automatically inserted.
Conversely, if HIN and LIN have greater than 0 ns of
dead−time, then the dead−time is not modified by the
NCP51820 and is passed through to the output stage as
defined by the controller. This type of dead−time control is
preferred when the controller will be making the necessary
dead−time adjustments but needs to rely on the NCP51820
dead−time control function for anti−cross−conduction
protection.
graphically in Figure 29.
MODE C:
Connect a 249 kW Resistor from DT to SGND; Connect a
249 kW resistor between DT and SGND to program the
maximum dead−time value of 200 ns. The control voltage
range, V , for assuring t = 200 ns is 4 V < V < 5 V. DT
DT
DT
DT
programmability is summarized and shown graphically in
Figure 29.
MODE D:
Connect DT to VDD; When the DT pin voltage, V , is
DT
greater than 6 V (pulled up to VDD through 10 kW resistor),
anti−cross−conduction protection is disabled, allowing the
output signals to overlap. This operating mode is suitable for
applications where it is desired to have both driver output
stages switching simultaneously. If choosing this operating
mode while driving a half−bridge power stage, extreme
caution should be taken, as cross conduction can potentially
damage power components if not accounted for. This type
of dead−time control is preferred when the controller will be
making extremely accurate dead−time adjustments and can
respond to the potential of over−current faults on a
cycle−by−cycle basis. DT programmability is summarized
and shown graphically in Figure 29.
HIN
50%
50%
LIN
50%
50%
DT
LO
DT
50%
HO
50%
Figure 28. Internal Dead−Time Definitions
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14
NCP51820
VDT [V]
6
t DT [ns]
No dead−time
Mode A: V < 0.5 V
DT
t
DT
= SGND = 0 V
Output ENABLED
MODE D: 6 V < V < VDD (pull−up)
Cross−conduction prevention active
DT
t
DT
= 0 ns
Cross−conduction prevention disabled
5
4
3
2
1
0
Dead−time Control Range
Mode B: 0.5 V < V < 4 V
DT
t
DT
= R x 1 ns/kW
DT
Cross−conduction prevention active
200
150
100
50
Maximum dead−time
MODE C: 4 V<V <5 V
DT
t
=200 ns
DT
Cross−conduction prevention on
0
25
50
100
150
200
[kW]
250
300
R
DT
Figure 29. Dead−Time Control, tDT, VDT vs RDT
High−Side Output (HOSRC and HOSNK)
Q of the low−side GaN FET. The turn−on (LOSRC) and
G
The NCP51820 high−side drive stage is level shifted from
HIN and SGND and referenced to SW and can withstand a
common mode voltage range from −3.5 V to +650 V.
HOSRC and HOSNK outputs are driven by a pure MOS,
low−impedance totem pole output stage to ensure tightly
regulated, low stray capacitance, full VDDH switching. The
output slew rate is determined primarily by VDDH and the
turn−off (LOSNK) functions each have dedicated pins. This
allows a single resistor between each pin and the low−side
GaN FET gate to independently control gate ringing as well
as fine tuning dV /dt turn−on and turn−off transitions
DS
present on the GaN drain−source voltage. The driver
provides the high peak currents necessary for high−speed
switching, even at the Miller plateau voltage. The outputs of
the NCP51820 are rated to 1 A peak current source
(LOSRC) and 2 A sink (LOSNK). The high−side and
low−side drive stage can be thought of as two independent
floating driver channels. Both driver output channels are
perfectly suited for driving the latest generation HEMT GIT
GaN FETs which require constant current into the internal
gate clamp or HEMT GaN FETs which are strictly
unclamped, voltage controlled devices requiring tightly
regulated gate drive signals.
Q of the high−side GaN FET. The turn−on (HOSRC) and
G
turn−off (HOSNK) functions each have dedicated pins. This
allows a single resistor between each pin and the high−side
GaN FET gate to independently control gate ringing as well
as fine tuning dV /dt turn−on and turn−off transitions
DS
present on the GaN drain−source voltage. The driver
provides the high peak currents necessary for high−speed
switching, even at the Miller plateau voltage. The outputs of
the NCP51820 are rated to 1 A peak current source
(HOSRC) and 2 A sink (HOSNK).
Input to Output Protection Functions
Figure 30 graphically summarizes the input to output
protection functions for the following three cases:
Low−Side Output (LOSRC and LOSNK)
The NCP51820 low−side drive stage is level shifted from
LIN and SGND and referenced to PGND and can withstand
a common mode voltage range from −3.5 V to +3.5 V.
LOSRC and LOSNK outputs are driven by a pure MOS,
low−impedance totem pole output stage to ensure tightly
regulated, low stray capacitance, full VDDL switching. The
output slew rate is determined primarily by VDDL and the
Case A:
External shutdown due to EN pulled low. Outputs are
immediately terminated when EN is pulled low. The second
rising edge of either HIN or LIN is processed to the output
when EN is pulled high.
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15
NCP51820
Case B:
UVLO protection event during shutdown and start−up.
Case C:
Anti−cross−conduction, shoot−through protection. As
Crossing the UVLO ON and OFF thresholds has the same
effect as EN, where outputs are immediately terminated
when UVLO OFF is reached. The second rising edge of
either HIN or LIN is processed to the output when UVLO
ON is reached.
described in the DT section MODE A, when the DT pin is
connected SGND, any amount of HIN to LIN overlap is
translated to HO to LO dead−time.
A
B
C
HIN
LIN
EN
Shutdown
VDD
VDDUVL
Cycle−by−Cycle
Shoot−Through
Prevention
Cycle−by−Cycle
Shutdown
Shutdown
UVLO
HO
LO
Disregard
Disregard
DT DT
Figure 30. Protection Functions, Timing Diagram
PCB LAYOUT
5. Move the NCP51820 and associated components
close to the GaN FET source and sink resistors.
6. If possible, arrange the GaN FETs in a “staggered”
pattern with the goal of maintaining the HO and LO
gate drive lengths as closely matched as possible. To
avoid high current and high dV/dt through vias, it is
preferred that both GaN FETs be located on the same
side of the PCB as the NCP51820.
7. The HO and LO gate drives should be considered as
two independent gate drive circuits that are
electrically isolated from each other. HO and LO will
therefore each require dedicated copper land return
planes on layer 2 directly beneath layer 1 gate drive
routing.
When beginning a PCB design using GaN FETs, the best
layout procedure is one that is priority−driven as listed
below. Each of these “summary” comments are highlighted
in more detail with clarifying diagrams in document
AND9932, NCP51820 and high−speed GaN, PCB layout
tips.
1. Multi−layer PCB designs with proper use of
ground/return planes as described in this document
are a must. High frequency, high voltage, high dV/dt
and high di/dt all warrant the need for a multi−layer,
PCB design approach. Inexpensive, single−layer,
PCB designs do not allow for proper routing or
design of ground planes necessary to realize the full
benefits of a GaN based power stage.
2. Begin by placing the most noise sensitive
components near the NCP51820 first. VDD, VDDH,
VDDL, EN and DT bypass capacitors as well as the
VBST capacitor, resistor and diode should be placed
as close to their respective pins as possible.
Proper routing of the power loop, switch−node, gate drive
loops and use of planes are critical for a successful GaN PCB
design. For the gate drives, proper routing and noise
isolation will help reduce additional parasitic loop
inductance, noise injection, ringing, gate oscillations and
inadvertent turn−on. The goal is to design a high frequency,
power PCB that is thoughtful with regard to proper
grounding while maintaining controlled current flow
through direct pathway connections with minimal loop
distances.
3. Place the DT resistor directly next to C
DT and SGND pins.
4. Place the HO and LO, source and sink gate drive
resistors as close to the GaN FETs as possible.
and the
DTBYP
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16
NCP51820
COMPONENT PLACEMENT AND ROUTING
The diagram shown in Figure 31 highlights the critical
component placement around the NCP51820 and the
interface to the HS and LS GaN FETs. The strategic
placement of critical components around the NCP51820,
use of dedicated ground and return planes, Kelvin source
connections and direct gate drive routing are discussed in
detail in document AND9932, NCP51820 and high−speed
GaN, PCB layout tips.
HS GATE RETURN PLANE
(ISOLATED FROM SWITCH NODE)
VBST CAPACITOR
SGND PLANE
VBST DIODE
HS SOURCE
AND SINK
GATE
RESISTORS
VBST
RESISTOR
VDD
CAPACITORS
VBULK
VDDH BYPASS
CAPACITOR
NCP51820
HS GaN FET
DT RESISTOR
POWER
SWITCH
NODE
LS GaN FET
VDDL BYPASS
CAPACITOR
LS SOURCE AND SINK
GATE RESISTORS
LS GATE RETURN
PLANE (ISOLATED
FROM POWER PGND)
POWER PGND
Figure 31. NCP51820 Component Placement
Thermal Guidelines
High−speed, gate drivers used to switch GaN FETs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
the IC is operating within acceptable temperature limits.
The total power dissipation in a gate driver is the sum of
Dynamic Predrive / Shoot−through Current: Power loss
resulting from internal current consumption under dynamic
operating conditions can be obtained using the “I
vs.
PDD
Frequency” graphs in Figure 5 and Figure 6 to determine the
current, I
flowing from V
under actual operating
PDD
DD
conditions.
two components, P
and P
:
GATE
PTOTAL + 2 PGATE ) PDYNAMIC
DYNAMIC
PDYNAMIC + IPDD VDD
(eq. 5)
(eq. 3)
Once the power dissipated in the driver is determined, the
driver junction temperature rise with respect to the PCB can
be evaluated using the thermal equation, given below:
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit time) to
switch the GaN FETs on and off at the switching frequency.
The power dissipation that results from driving a GaN FET
TJ + (PTOTAL qJA) ) TB
(eq. 6)
with a specified gate−source voltage, V , with gate charge,
Where:
GS
Q , at switching frequency, F , is determined by:
T
= driver junction temperature
G
SW
J
ĂĂĂĂĂĂĂĂĂq = thermal characterization parameter relating
PGATE + QG VGS FSW
JA
(eq. 4)
temperature rise to total power dissipation
This needs to be calculated for the high−side and low−side
T
= board temperature in location defined
B
GaN FETs where the Q can possibly be different if the
G
devices are not the same
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17
NCP51820
As an example, consider an application driving two
GaN FETs with a gate charge of 5 nC each with V = 12 V
reliable operation, the maximum junction temperature of the
device must not exceed the absolute maximum rating of
DD
(V
= V
= 5.2 V). At a switching frequency of
150°C; with 80% derating, T would be limited to 120°C.
DDH
DDL
J
500 kHz, the total power dissipation is:
Rearranging Equation 6 determines the board temperature
required to maintain the junction temperature below 120°C:
PGATE + 5 nC 5.2 V 500 kHz 2 + 26 mW
(eq. 7)
(eq. 8)
(eq. 9)
TB + TJ * (PTOTAL qJA
)
(eq. 10)
PDYNAMIC + 4 mA 12 V + 48 mW
PTOTAL + 74 mW
TB ≤ 120°C * (74 mW 245°CńW) + 102°C
(eq. 11)
Similarly, eq. 6 can be used to calculate the junction
temperature (operating near room temperature) as:
The QFN15 4x4 package has a junction−to−ambient
thermal characterization parameter of q = 245°C/W. In a
JA
TJ + (74 mW 245°CńW) ) 25°C
(eq. 12)
system application, the localized temperature around the
device is a function of the layout and construction of the
PCB along with airflow across the surfaces. To ensure
TJ + 43.13°C
(eq. 13)
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18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN15 4x4, 0.5P
CASE 485FN
ISSUE B
DATE 24 JUL 2019
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
XXXXXX = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON81104G
QFN15 4x4, 0.5P
PAGE 1 OF 1
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