NCP5214MNR2G_技术文档

NCP5214

2−in−1 Notebook DDR

Power Controller

The NCP5214 2−in−1 Notebook DDR Power Controller is

specifically designed as a total power solution for notebook DDR

memory system. This IC combines the efficiency of a PWM

controller for the VDDQ supply with the simplicity of linear

regulators for the VTT termination voltage and the buffered low

noise reference. This IC contains a synchronous PWM buck

controller for driving two external NFETs to form the DDR memory

supply voltage (VDDQ). The DDR memory termination regulator

output voltage (VTT) and the buffered VREF are internally set to

track at the half of VDDQ. An internal power good voltage monitor

tracks VDDQ output and notifies the user whether the VDDQ output

is within target range. Protective features include soft−start

circuitries, undervoltage monitoring of supply voltage, VDDQ

overcurrent protection, VDDQ overvoltage and undervoltage

protections, and thermal shutdown. The IC is packaged in DFN−22.

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MARKING

DIAGRAM

1

DFN−22

22

MN SUFFIX

NCP5214

AWLYYWW

G

CASE 506AF

1

NCP5214 = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

Features

• Incorporates VDDQ, VTT Regulator, Buffered VREF

• Adjustable VDDQ Output

• VTT and VREF Track VDDQ/2

• Operates from Single 5.0 V Supply

• Supports VDDQ Conversion Rails from 4.5 V to 24 V

• Power−saving Mode for High Efficiency at Light Load

• Integrated Power FETs with VTT Regulator Sourcing/Sinking 1.5 A

DC and 2.4 A Peak Current

PIN CONNECTIONS

VDDQEN

VTTEN

FPWM

SS

VTTGND

VTT

PGND

BGDDQ

VCCP

SWDDQ

TGDDQ

BOOST

OCDDQ

PGOOD

VTTREF

FBDDQ

COMP

• Requires Only 20 mF Ceramic Output Capacitor for VTT

• Buffered Low Noise 15 mA VREF Output

• All External Power MOSFETs are N−channel

• <5.0 mA Current Consumption During Shutdown

• Fixed Switching Frequency of 400 kHz

• Soft−start Protection for VDDQ and VTT

• Undervoltage Monitor of Supply Voltage

• Overvoltage Protection and Undervoltage Protection for VDDQ

• Short−circuit Protection for VDDQ and VTT

• Thermal Shutdown

VTTI

FBVTT

AGND

DDQREF

VCCA

(Top View)

NOTE: Pin 23 is the thermal pad on

the bottom of the device.

• Housed in DFN−22

• This is a Pb−Free Device

ORDERING INFORMATION

Device

NCP5214MNR2G

Package

Shipping†

2500 Tape & Reel

Typical Applications

DFN−22

• Notebook DDR/DDR2 Memory Supply and Termination Voltage

• Active Termination Busses (SSTL−18, SSTL−2, SSTL−3)

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

©

Semiconductor Components Industries, LLC, 2005

1

Publication Order Number:

December, 2005 − Rev. 0

NCP5214/D

NCP5214

CL1

RL1

VDDQEN

VTTEN

FPWM

VDDQEN

VTTEN

FPWM

OCDDQ

5VCC

VIN

SS

BOOST

VCCP

CSS

5VCC

4.5 V to 24 V

(Battery/

PWRGD

VTT

Adapter)

M1

M2

PGOOD

VDDQ

TGDDQ

L

1.8 V, 10 A

0.9 V, 1.5 A

VTT

1.8 mH

SWDDQ

BGDDQ

COUT2

Ceramic

10 mF x2

NCP5214

COUT1

POSCAP

150 mF x2

FBVTT

PGND1

VTTGND

5VCC

VREF

COMP

CZ1

VCCA

CP1

CZ2

R1

R2

RZ1

RZ2

VTTREF

FBDDQ

0.9 V, 15 mA

DDQREF

AGND

VTTI

Figure 1. Typical Application Diagram

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2

NCP5214

5VCC

VIN

VREF

VOLTAGE &

CURRENT

REFERENCE

VDDQEN

VREFGD

TSD

THERMAL

SHUTDOWN

CBULK

VDDQEN

VTTEN

5VCC

VCCP

VTTEN

FPWM

VCCP

CONTROL

LOGIC

VCCAGD

VCCA

VBOOST

VOCDDQGD

VCCA

BOOST

FAULT

+

−

INREGDDQ

ILIM

RL1

VREF

+

−

IREF

VBOOST

OCDDQ

VOCDDQ

M3

VDDQ

TGDDQ

SWDDQ

PWM

LOGIC

FBDDQ

SWDDQ

+

−

VDDQ

L

VREF

VDDQEN

VTTEN

VCCA

Power−

Saving

Loop

VCCP

NEGATIVE CURRENT

DETECTION

SS

COUT1

M4

Control

BGDDQ

PGND

+

−

PGND

5VCC

VREF

VFBDDQ

OVLO

+

−

+

PWM−

COMP

PGOOD

−

UVLO

VREF

VFBDDQ

VREF

+

−

OSC

COMP

CZ1

PGND

CZ2

CP1

VOCDDQ

R1

R2

RZ1

RZ2

+

−

Adaptive

Ramp

A

FBDDQ

DDQREF

VTTI

Current

Limit &

Soft−Start

VCCA

+

−

M1

VDDQEN

VTTEN

SC2PWR

VTT

VTTI

VTTGND

VCCA

VTT

Regulation

Control

Deadband

Control

VTT

+

−

COUT2

INREGDDQ

VTTREF

M2

SC2GND

PGND

+

−

VTTGND

VTTREF

COUT3

VTTGND

FBVTT

GND

AGND

VTTGND

Figure 2. Detailed Block Diagram

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3

NCP5214

PIN FUNCTION DESCRIPTION

1

Symbol

VDDQEN

VTTEN

FPWM

SS

Description

VDDQ regulator enable input. High to enable.

2

VTT regulator enable input. High to enable.

3

Forced PWM enable input. Low to enable forced PWM mode and disable power−saving mode.

VDDQ Soft−start capacitor connection to ground.

4

5

VTTGND

VTT

Power ground for the VTT regulator.

6

VTT regulator output.

7

VTTI

Power input for VTT regulator which is normally connected to the VDDQ output of the buck regulator.

VTT regulator feedback pin for closed loop regulation.

Analog ground connection and remote ground sense.

External reference input which is used to regulate VTT and VTTREF to 1/2VDDQREF.

8

FBVTT

AGND

DDQREF

VCCA

9

10

11

5.0 V supply input for the IC’s control and logic section, which is monitored by undervoltage lock out

circuitry.

12

13

14

15

16

COMP

FBDDQ

VTTREF

PGOOD

OCDDQ

VDDQ error amplifier compensation node.

VDDQ regulator feedback pin for closed loop regulation.

DDR reference voltage output.

Power good signal open−drain output.

Overcurrent sense and program input for the high−side FET of VDDQ regulator. Also the battery

voltage input for the internal ramp generator to implement the voltage feedforward rejection to the input

voltage variation. This pin must be connected to the VIN through a resistor to perform the current limit

and voltage feedforward functions.

17

18

19

20

BOOST

TGDDQ

SWDDQ

VCCP

Positive supply input for high−side gate driver of VDDQ regulator and boost capacitor connection.

Gate driver output for VDDQ regulator high−side N−Channel power FET.

VDDQ regulator inductor driven node, return for high−side gate driver, and current limit sense input.

Power supply for the VDDQ regulator low−side gate driver and also supply voltage for the bootstrap

capacitor of the VDDQ regulator high−side gate driver supply.

21

22

23

BGDDQ

PGND

Gate driver output for VDDQ regulator low−side N−Channel power FET.

Power ground for the VDDQ regulator.

THPAD

Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane

under the IC.

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4

NCP5214

MAXIMUM RATINGS

Rating

Power Supply Voltage (Pin 11, 20) to AGND (Pin 9)

Symbol

, V

Value

Unit

V

−0.3, 6.0

CCA CCP

High−Side Gate Drive Supply: BOOST (Pin 17) to SWDDQ (Pin 19)

High−Side FET Gate Drive Voltage: TGDDQ (Pin 18) to SWDDQ (Pin 19)

V

−V

V

BOOST SWDDQ,

−V

TGDDQ SWDDQ

Input/Output Pins to AGND (Pin 9)

Pins 1−4, 6−8, 10, 12−15, 21

V

−0.3, 6.0

27

V

IO

Overcurrent Sense Input (Pin 16) to AGND (Pin 9)

Switch Node (Pin 19)

V

OCDDQ

V

−4.0 (<100 ns),

0.3 (dc), 32

SWDDQ

PGND (Pin 22), VTTGND (Pin 5) to AGND (Pin 9)

V

−0.3, 0.3

35

V

GND

Thermal Characteristics

DFN−22 Plastic Package

R

_C/W

q

JA

Thermal Resistance, Junction−to−Ambient

Operating Junction Temperature Range

Operating Ambient Temperature Range

Storage Temperature Range

T

0 to +150

−40 to +85

−55 to +150

2

_C

−

J

A

T

stg

Moisture Sensitivity Level

MSL

Maximumratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values

(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage

may occur and reliability may be affected.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model (HBM) ≤2.0 kV per JEDEC standard: JESD22–A114 except Pin 17 which is ≤500 V.

Machine Model (MM) ≤200 V per JEDEC standard: JESD22–A115 except Pin 17 which is ≤50 V.

2. Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78.

3. Pin 16 (OCDDQ) must be pulled high to VIN through a resistor.

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5

NCP5214

ELECTRICAL CHARACTERISTICS (V = 12 V, T = −40 to 85_C, V

= V

− V

= 5.0 V, L = 1.8 mH,

IN

A

CCA

CCP

BOOST

SWDDQ

C

OUT1

= 150 mF x 2, C

= 22 mF x 2, RL1 = 5.6 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 10 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF,

OUT2

CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at T = 25_C.)

A

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

SUPPLY VOLTAGE

Input Voltage

V

−

4.5

−

24

5.5

V

IN

V

Operating Voltage

V

5.0

CCA

CCP

CCA

CCP

V

SUPPLY CURRENT

V

CCA

V

CCA

V

CCA

Quiescent Supply Current in S0

Quiescent Supply Current in S3

Shutdown Current

I

V

= 5.0 V, V = 5.0 V

TTEN

−

3.5

0.9

1.0

10

5.0

4.0

mA

VCCA_S0

VCCA_S3

VCCA_SD

DDQEN

V

= 5.0 V, V

= 0 V

DDQEN

TTEN

I

V

= 0 V, V

= 0 V,

DDQEN

TTEN

T_A= 25°C

= 5.0 V, V = 5.0 V,

TTEN

V

CCP

V

CCP

V

CCP

Quiescent Supply Current in S0

Quiescent Supply Current in S3

Shutdown Current

I

V

−

20

mA

VCCP_S0

VCCP_S3

VCCP_SD

DDQEN

TGDDQ and BGDDQ Open

V

= 5.0 V, V = 0 V,

DDQEN

TTEN

TGDDQ and BGDDQ Open

I

V = 0 V, V = 0 V

1.0

2.0

DDQEN

TTEN

UNDERVOLTAGE MONITOR

V

UVLO Lower Threshold

UVLO Hysteresis

V

Falling Edge

−

3.7

0.35

3.0

4.1

−

V

CCA

CCAUV−

V

−

CCA

CCAUVHYS

OCDDQUV+

UVLO Upper Threshold

UVLO Hysteresis

V

Rising Edge

−

4.4

−

OCDDQ

V

0.4

OCDDQUVHYS

THERMAL SHUTDOWN

Thermal Trip Point

T

(Note 4)

−

150

25

−

_C

SD

Hysteresis

T

SDHYS

V

DDQ

SWITCHING REGULATOR

FBDDQ Feedback Voltage, Control Loop in

Regulation

V

T_A= 25°C

T_A= −40 to 85°C

0.788

0.784

0.8

0.812

0.816

V

FBDDQ

Feedback Input Current

Oscillator Frequency

I

V

= 0.8 V

−

340

−

1.0

460

−

mA

kHz

V

fb

FBDDQ

F

SW

−

400

1.25

45

Ramp Amplitude Voltage

V

= 5.0 V (Note 4)

−

ramp

IN

Ramp Amplitude to V Ratio

dVRAMP/dVIN

−

mV/V

mA

IN

OCDDQ Pin Current Sink

I

V

= 4.0 V

26

−

31

36

−

OC

OCDDQ

OCDDQ Pin Current Sink Temperature

Coefficient

TC

T_A= −40 to 85°C

3200

ppm/

_C

IOC

Minimum On Time

t

−

150

−

ns

onmin

Maximum Duty Cycle

D

max

V

= 5.0 V

= 15 V

= 24 V

−

90

50

32

−

%

IN

Soft−Start Current

I

V

= 5.0 V, Vss = 0 V

2.8

4.0

5.2

−

mA

ss

DDQEN

Overvoltage Trip Threshold

FBOVPth

With Respect to Error

115

130

%

Comparator Threshold of 0.8 V

Undervoltage Trip Threshold

FBUVPth

With Respect to Error

−

65

75

%

Comparator Threshold of 0.8 V

4. Guaranteed by design, not tested in production.

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6

NCP5214

ELECTRICAL CHARACTERISTICS (continued) (V = 12 V, T = −40 to 85_C, V

= V

− V

= 5.0 V,

IN

A

CCA

CCP

BOOST

SWDDQ

L = 1.8 mH, C

= 150 mF x 2, C

= 22 mF x 2, RL1 = 5.6 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 10 kW, RZ2 = 130 W, CP1 = 100 pF,

OUT1

OUT2

CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at T = 25_C.)

A

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

ERROR AMPLIFIER

DC Gain

GAIN

Ft

(Note 5)

−

70

−

dB

Unity Gain Bandwidth

COMP_GND = 220 nF,

2.0

MHz

1.0 W in Series (Note 5)

Slew Rate

SR

(Note 5)

−

3.0

1.8

−

V/mS

GATE DRIVERS

TGDDQ Gate Pull−HIGH Resistance

R

H_TG

V

− V

SWDDQ

= 5.0 V,

= 4.0 V

4.0

W

BOOST

− V

TGDDQ

SWDDQ

TGDDQ Gate Pull−LOW Resistance

R

L_TG

V

− V

= 5.0 V,

= 1.0 V

−

1.8

4.0

W

BOOST

SWDDQ

TGDDQ

SWDDQ

BGDDQ Gate Pull−HIGH Resistance

BGDDQ Gate Pull−LOW Resistance

R

V

CCP

V

CCP

= 5.0 V, V

= 4.0 V

= 1.0 V

−

1.8

0.9

4.0

3.0

W

H_BG

BGDDQ

R

L_BG

VTT0

V

TT

ACTIVE TERMINATOR

V

TT

with Respect to 1/2V

d

1/2VDDQREF – V ,

TT

mV

DDQREF

VDDQREF = 2.5 V,

I

= 0 to 2.4 A

VTT

(Sink Current)

−30

−

I

= 0 to –2.4 A

VTT

(Source Current)

30

1/2VDDQREF – V

,

TT

mV

VDDQREF = 1.8 V,

I

= 0 to 2.0 A

VTT

(Sink Current)

−30

−

I

= 0 to –2.0 A

VTT

(Source Current)

−

40

2.5

−

30

75

−

DDQREF Input Resistance

Source Current Limit

DDQREF_R

VDDQREF = 2.5 V

55

kW

A

I

−

3.0

1.0

0.32

LIMVTsrc

Sink Current Limit

I

−

A

LIMVTsnk

Soft−Start Source Current Limit

Maximum Soft−Start Time

I

−

A

LIMVTSS

t

−

ms

ssvttmax

V

TTREF

OUTPUT

V

Source Current

I

VDDQREF = 1.8 V or 2.5 V

1/2VDDQREF – V

15

−

mA

mV

TTREF

VTTR

V

Accuracy Referred to 1/2V

d

,

TTR

−25

25

DDQREF

VTTR

VDDQREF = 2.5 V,

= 0 mA to 15 mA

I

VTTR

1/2VDDQREF – V

,

−18

−

18

mV

TTR

VDDQREF = 1.8 V,

= 0 mA to 15 mA

I

VTTR

5. Guaranteed by design, not tested in production.

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7

NCP5214

ELECTRICAL CHARACTERISTICS (continued) (V = 12 V, T = −40 to 85_C, V

= V

− V

= 5.0 V,

IN

A

CCA

CCP

BOOST

SWDDQ

L = 1.8 mH, C

= 150 mF x 2, C

= 22 mF x 2, RL1 = 5.6 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 10 kW, RZ2 = 130 W, CP1 = 100 pF,

OUT1

OUT2

CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at T = 25_C.)

A

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

CONTROL SECTION

VDDQEN Pin Threshold High

VDDQEN Pin Threshold Low

VDDQEN Pin Input Current

V

−

1.4

−

V

DDQEN_H

V

0.5

1.0

DDQEN_L

I

V

= 5.0 V

−

mA

IN_

DDQEN

VDDQEN

VTTEN Pin Threshold High

VTTEN Pin Threshold Low

VTTEN Pin Input Current

V

−

1.4

−

V

TTEN_H

V

−

0.5

1.0

TTEN_L

I

V

= V = 5.0 V

TTEN

−

mA

IN_VTTEN

DDQEN

FPWM Pin Threshold High

FPWM Pin Threshold Low

FPWM Pin Input Current

FPWM_H

FPWM_L

−

1.4

−

V

−

0.5

1.0

I

V

= V

=FPWM

−

mA

IN_FPWM

DDQEN

TTEN

= 5.0 V

PGOOD Pin ON Resistance

PGOOD_R

I

= 5.0 mA

−

70

−

W

mA

ms

_PGOOD

PGOOD Pin OFF Current

PGOOD_LK

−

1.0

200

PGOOD LOW−to−HIGH Hold Time, for S5 to S0

6. Guaranteed by design, not tested in production.

t

(Note 6)

−

hold

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8

NCP5214

TYPICAL OPERATING CHARACTERISTICS

4.0

3.8

3.6

1.0

0.8

0.6

3.4

3.2

0.4

0.2

3.0

0.0

−40

−15

10

35

60

85

−40

−15

10

35

60

85

T , AMBIENT TEMPERATURE (°C)

A

T , AMBIENT TEMPERATURE (°C)

A

Figure 3. VCCA Quiescent Current in S0

vs. Ambient Temperature

Figure 4. VCCA Quiescent Current in S3

vs. Ambient Temperature

10

8

450

425

6

400

375

4

2

0

−40

350

−40

−15

10

35

60

−15

10

35

60

T , AMBIENT TEMPERATURE (°C)

A

T , AMBIENT TEMPERATURE (°C)

A

Figure 5. VCCA Shutdown Current

vs. Ambient Temperature

Figure 6. Switching Frequency in S0

vs. Ambient Temperature

5.0

4.5

0.90

0.85

4.0

3.5

0.80

0.75

0.70

3.0

−40

−15

10

35

60

−15

10

35

60

T , AMBIENT TEMPERATURE (°C)

A

T , AMBIENT TEMPERATURE (°C)

A

Figure 7. VDDQ Feedback Voltage

vs. Ambient Temperature

Figure 8. Soft−Start Current

vs. Ambient Temperature

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9

NCP5214

TYPICAL OPERATING CHARACTERISTICS

1.820

1.815

1.810

1.805

1.800

1.795

1.810

1.805

I

= 100 mA

= 10 A

VDDQ

1.800

1.795

V

IN

= 5 V

I

VDDQ

V

= 24 V

IN

1.790

1.785

V

= 1.8 V

DDQ

V

DDQ

= 1.8 V

S0 Mode

T = 25°C

A

T = 25°C

A

1.780

1.790

0

5

10

15

20

25

3.0

15

0

2

4

6

8

10

V

, INPUT VOLTAGE (V)

I

, VDDQ OUTPUT CURRENT (A)

IN

VDDQ

Figure 9. VDDQ Output Voltage

vs. Input Voltage

Figure 10. VDDQ Output Voltage

vs. VDDQ Output Current

1.29

1.28

1.27

1.26

1.25

1.24

1.23

1.22

1.21

0.94

0.93

0.92

0.91

0.90

0.89

0.88

0.87

0.86

V

IN

= 5 V

V

= 5 V

IN

V

IN

= 24 V

V

IN

= 24 V

1.0

V

= 2.5 V

V

= 1.8 V

T = 25°C

A

DDQ

T = 25°C

A

−3.0

−2.0

−1.0

0.0

2.0

−2.0 −1.5 −1.0 −0.5 0.0

0.5

1.0

1.5 2.0

I

, VTT OUTPUT CURRENT (A)

I , VTT OUTPUT CURRENT (A)

VTT

Figure 11. VTT Output Voltage (DDR)

vs. VTT Output Current

Figure 12. VTT Output Voltage (DDR2)

vs. VTT Output Current

1.260

0.910

0.905

1.255

1.250

1.245

0.900

0.895

V

= 5 V

V

IN

= 5 V

IN

V

IN

= 24 V

V

IN

= 24 V

V

DDQ

= 2.5 V

V

DDQ

= 1.8 V

T = 25°C

A

T = 25°C

A

1.240

0.890

0

5

10

0

5

10

15

I , VTTR OUTPUT CURRENT (mA)

VTTR

I , VTTR OUTPUT CURRENT (mA)

VTTR

Figure 13. VTTR Output Voltage (DDR)

vs. VTTR Output Current

Figure 14. VTTR Output Voltage (DDR2)

vs. VTTR Output Current

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10

NCP5214

TYPICAL OPERATING CHARACTERISTICS

100

90

100

V

= 5 V

= 12 V

= 20 V

V

= 5 V

= 12 V

= 20 V

IN

90

80

V

IN

V

IN

V

IN

V

IN

80

with power−saving

without power−saving

70

60

70

60

V

DDQ

= 2.5 V

V

DDQ

= 1.8 V

Freq = 400 kHz max

T = 25°C

A

50

0.1

50

0.1

1.0

10

100

1.0

10

100

I , VDDQ OUTPUT CURRENT (A)

VDDQ

I , VDDQ OUTPUT CURRENT (A)

VDDQ

Figure 15. VDDQ Efficiency (DDR)

vs. VDDQ Output Current

Figure 16. VDDQ Efficiency (DDR2)

vs. VDDQ Output Current

VIN

20V/div

VIN

20V/div

1V/div

VDDQ

VTT

VDDQ

1V/div

VTT

1V/div

VTTR

VDDQEN = High; VTTEN = High; VIN = 0 V to 20 V

VDDQEN = High; VTTEN = High; VIN =20 V to 0 V

Figure 17. Power−Up Waveforms

Figure 18. Power−Down Waveforms

5V/div

VDDQEN

VDDQ

VDDQEN

VDDQ

1V/div

5V/div

VTTR

1V/div

5V/div

PGOOD

VDDQEN = 0 V to 5 V

VDDQEN = 5 V to 0 V

Figure 19. VDDQ, VTTR Start−Up Waveforms

Figure 20. VDDQ, VTTR Shutdown Waveforms

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11

NCP5214

TYPICAL OPERATING CHARACTERISTICS

VTTEN

VTT

VTTEN

5V/div

1V/div

VTT

1V/div

500mA/div

IVTTI

500mA/div

VDDQEN = High; VTT Loaded with 4.7 W to GND

Figure 21. VTT Start−Up Waveforms

Figure 22. VTT Shutdown Waveforms

100mV/div

VDDQ

100mV/div

VDDQ

VTT

1V/div

VTT

1V/div

50mV/div

VTTR

50mV/div

VTTR

5V/div

FPWM

VTTEN

IVDDQ = 50 mA, IVTT = 100 mA, IVTTR = 5 mA

IVDDQ = 50mA, IVTT = 100mA, IVTTR = 5mA, VTTEN = 0V

Figure 23. S0−S3−S0 Transition Waveforms

Figure 24. PS−FPWM−PS Transition

Waveforms

100mV/div

50mV/div

VDDQ

VTT

100mV/div

50mV/div

VDDQ

VTT

50mV/div

5A/div

VTTR

IVDDQ

5A/div

IVDDQ = 0 A−7 A, IVTT = 1.5 A, IVTTR = 15 mA

IVDDQ = 7 A−0 A, IVTT = 1.5 A, IVTTR = 15 mA

Figure 25. VDDQ Load Transient

Figure 26. VDDQ Load Transient

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12

NCP5214

TYPICAL OPERATING CHARACTERISTICS

VDDQ

100mV/div

VDDQ

VTT

50mV/div

VTTR

IVTT

50mV/div

2A/div

IVTT

2A/div

IVDDQ = 8 A, IVTT = 0 A to −2 A to 0 A, IVTTR = 15 mA

IVDDQ = 8 A, IVTT = 0 A to 2 A to 0 A, IVTTR = 15 mA

Figure 27. VTT Source Current Transient

Figure 28. VTT Sink Current Transient

VDDQ

VTT

100mV/div

50mV/div

10V/div

100mV/div

50mV/div

VDDQ

VTT

50mV/div

10V/div

VTTR

VIN

VTTR

VIN

IVDDQ = 0 A, IVTT = 0 A, IVTTR = 0 mA, VIN = 7 V to 20 V

IVDDQ = 0 A, IVTT = 0 A, IVTTR = 0 mA, VIN = 20 V to 7 V

Figure 29. Line Transient 7V to 20V at No Load

Figure 30. Line Transient 20V to 7V at No Load

100mV/div

VDDQ

100mV/div

VTT

50mV/div

VTT

50mV/div

10V/div

50mV/div

10V/div

VTTR

VIN

VTTR

VIN

IVDDQ = 10A, IVTT = 1.5A, IVTTR = 15mA, VIN = 20V to 7V

IVDDQ = 10A, IVTT = 1.5A, IVTTR = 15mA, VIN = 7V to 20V

Figure 31. Line Transient 7V to 20V at Full

Load

Figure 32. Line Transient 20V to 7V at Full

Load

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13

NCP5214

TYPICAL OPERATING CHARACTERISTICS

100mV/div

VDDQ

100mV/div

VTT

1V/div

50mV/div

5A/div

VTT

1V/div

VTTR

IVTT

VTTR

50mV/div

IVTT

5A/div

IVDDQ = 8 A, VTT shorts to VDDQ, IVTTR = 15 mA

IVDDQ = 8 A, VTT shorts to ground, IVTTR = 15 mA

Figure 33. VTT Short Circuit to Ground and

Recovery

Figure 34. VTT Short Circuit to VDDQ and

Recovery

VDDQ, 1V/div

VSWDDQ, 10V/div

VIN, 20V/div

IL, 10A/div

VIN, 20V/div

IL, 10A/div

Figure 35. VDDQ OCP by Short Circuit to

Ground

Figure 36. VDDQ OCP by Steady IVDDQ

Increase

VDDQ, 1V/div

VSWDDQ, 10V/div

VIN, 20V/div

IL, 10A/div

Figure 37. VDDQ OCP by Start into a Short

Circuit

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14

NCP5214

DETAILED OPERATING DESCRIPTION

General

VDDQ output voltage is divided down and fed back to the

The NCP5214 2−in−1 Notebook DDR Power Controller

inverting input of an internal error amplifier through

FBDDQ pin to close the loop at VDDQ = VFBDDQ ×

(1 + R1/R2). This amplifier compares the feedback voltage

with an internal VREF (= 0.800 V) to generate an error

signal for the PWM comparator. This error signal is further

compared with a fixed frequency RAMP waveform

derived from the internal oscillator to generate a

pulse−width−modulated signal. This PWM signal drives

the external N−Channel Power FETs via the TGDDQ and

BGDDQ pins. External inductor L and capacitor COUT1

filter the output waveform. The VDDQ output voltage

ramps up at a pre−defined soft−start rate when the IC enters

state S0 from S5. When in normal mode, and regulation of

VDDQ is detected, signal INREGDDQ will go HIGH to

notify the control logic block.

combines the efficiency of a PWM controller for the

VDDQ supply, with the simplicity of using a linear

regulator for the VTT termination voltage power supply.

The VDDQ output can be adjusted through the external

potential divider, while the VTT is internally set to track

half VDDQ.

The inclusion of VDDQ power good voltage monitor,

soft−start, VDDQ overcurrent protection, VDDQ

overvoltage and undervoltage protections, supply

undervoltage monitor, and thermal shutdown makes this

device a total power solution for high current DDR memory

system. The IC is packaged in DFN−22.

Control Logic

The internal control logic is powered by VCCA. The IC

is enabled whenever VDDQEN is high (exceed 1.4 V). An

internal bandgap voltage, VREF, is then generated. Once

VREF reaches its regulation voltage, an internal signal

VREFGD will be asserted. This transition wakes up the

supply undervoltage monitor blocks, which will assert

VCCAGD if VCCA voltage is within certain preset levels.

The control logic accepts external signals at VCCA,

OCDDQ, VDDQEN, VTTEN, and FPWM pins to control

the operating state of the VDDQ and VTT regulators in

accordance with Table 1. A timing diagram is shown in

Figure 38.

Input voltage feedforward is implemented to the RAMP

signal generation to reject the effect of wide input voltage

variation. With input voltage feedforward, the amplitude of

the RAMP is proportional to the input voltage.

For enhanced efficiency, an active synchronous switch is

used to eliminate the conduction loss contributed by the

forward voltage of a diode or Schottky diode rectifier.

Adaptive non−overlap timing control of the

complementary gate drive output signals is provided to

reduce large shoot−through current that degrades

efficiency.

Tolerance of VDDQ

VDDQ Switching Regulator in Normal Mode (S0)

The tolerance of VFBDDQ and the ratio of external

resistor divider R1/R2 both impact the precision of VDDQ.

With the control loop in regulation, VDDQ = VFBDDQ ×

(1 + R1/R2). With a worst case (for all valid operating

conditions) VFBDDQ tolerance of "1.5%, a worst case

range of "2.5% for VDDQ = 1.8 V will be assured if the

ratio R1/R2 is specified as 1.2500 "1%.

The VDDQ regulator is a switching synchronous

rectification buck controller directly driving two external

N−Channel power FETs. An external resistor divider sets

the nominal output voltage. The control architecture is

voltage mode fixed frequency PWM with external

compensation and with switching frequency fixed at

400 kHz " 15%. As can be observed from Figure 1, the

Table 1. State, Operation, Input and Output Condition Table

Input Conditions

Operating Conditions

Output Conditions

VCCA VOCDDQ VDDQEN VTTEN FPWM

VDDQ

VTTREF

H−Z

VTT

TGDDQ

BGDDQ

Low

PGOOD

Mode

S5

Low

X

H−Z

Low

H−Z

S5

Low

High

X

H−Z

Low

S0

High

Low

X

Normal

Standby

Normal

H−Z

Normal

Standby

Normal

Standby

S3

High

(Power− (Power−

saving)

S3

S5

High

X

High

X

High

Low

X

Low

X

Normal

H−Z

Normal

H−Z

Normal

H−Z

Low

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NCP5214

VDDQ Regulator in Standby Mode (S3)

current source to charge up the VTT output capacitor. The

current limit is initially 1.0 A during VTT soft−start. It is

then increased to 2.5 A after 128 internal clock cycles

which is typically 0.32 ms.

During state S3, a power−saving mode is activated when

the FPWM pin is pulled to VCCA. In power−saving mode,

the switching frequency is reduced with the VDDQ output

current and the low−side FET is turned off after the

detection of negative inductor current, so as to enhance the

efficiency of the VDDQ regulator at light loads. The

switching frequency can be reduced smoothly until it

reaches the minimum frequency at about 15 kHz.

Therefore, perceptible audible noise can be avoided at light

load condition.

In power−saving mode, the low−side MOSFET is turned

off after the detection of negative inductor current and the

converter cannot sink current. The power−saving mode can

be disabled by pulling the FPWM pin to ground. Then, the

converter operates in forced−PWM mode with fixed

switching frequency and ability to sink current.

VTT Active Terminator in Standby Mode (S3)

VTT output is high−impedance in S3 mode.

Fault Protection of VTT Active Terminator

To provide protection for the internal FETs, bidirectional

current limit is implemented, preset at the minimum of

2.5 A magnitude.

Thermal Consideration of VTT Active Terminator

The VTT terminator is designed to handle large transient

output currents. If large currents are required for very long

duration, then care should be taken to ensure the maximum

junction temperature is not exceeded. The 5x6 DFN−22 has

a thermal resistance of 35_C/W (dependent on air flow,

grade of copper, and number of vias). In order to take full

advantage from this thermal capability of this package, the

thermal pad underneath must be soldered directly onto a

PCB metal substrate to allow good thermal contact. It is

recommended that PCB with 2 oz. copper foil is used and

there should have 6 to 8 vias with 0.6 mm hole size

underneath the package’s thermal pad connecting the top

layer metal to the bottom layer metal and the internal layer

metal substrates of the PCB.

Fault Protection of VDDQ Regulator

During state S0 and S3, external resistor (RL1) between

OCDDQ and VIN sets the current limit for the high−side

switch. An internal 31 mA current sink (IOC) at OCDDQ

pin establishes a voltage drop across this resistor and

develops a voltage at the non−inverting input of the current

limit comparator. The voltage at the non−inverting input is

compared to the voltage at SWDDQ pin when the

high−side gate drive is high after a fixed period of blanking

time (150 ns) to avoid false current limit triggering. When

the voltage at SWDDQ is lower than that at the

non−inverting input for 4 consecutive internal clock

cycles, an overcurrent condition occurs, during which, all

VTTREF Output

The VTTREF output tracks VDDQREF/2 at "2%

accuracy. It has source current capability of up to 15 mA.

VTTREF should be bypassed to analog ground of the

device by 1.0 mF ceramic capacitor for stable operation.

The VTTREF is turned on as long as VDDQEN is pulled

high. In S0 mode, VTTREF soft−starts with VDDQ and

tracks VDDQREF/2. In S3 mode, VTTREF is kept on with

VDDQ. VTTREF is turned off only in S4/S5 like VDDQ

output.

outputs will be latched off to protect against

short−to−ground condition on SWDDQ or VDDQ. The IC

will be reset once VCCA or VDDQEN is cycled.

a

Feedback Compensation of VDDQ Regulator

The compensation network is shown in Figures 2 and 39.

VTT Active Terminator in Normal Mode (S0)

The VTT active terminator is a two−quadrant linear

regulator with two internal N−channel power FETs. It is

capable of sinking and sourcing at least 1.5 A continuous

current and up to 2.4 A transient peak current. It is activated

in normal mode in state S0 when the VTTEN pin is HIGH

and VDDQ is in regulation. Its input power path is from

VDDQ with the internal FETs gate drive power derived

from VCCA. The VTT internal reference voltage is derived

from the DDQREF pin. The VTT output is set to VDDQ/2

when VTT output is connecting to the FBVTT pin directly.

This regulator is stable with only a minimum 20 mF output

capacitor. The VTT regulator will have an internal

soft−start when it is transited from disable to enable.

During the VTT soft−start, a current limit is used as a

Output Voltages Sensing

The VDDQ output voltage is sensed across the FBDDQ

and AGND pins. FBDDQ should be connected through a

feedback resistor divider to the VDDQ point of regulation

which is usually the local VDDQ bypass capacitor for load.

The AGND should be connected directly through a sense

trace to the remote ground sense point which is usually the

ground of local VDDQ bypass capacitor for load.

The VTT output voltage is sensed between the FBVTT

and VTTGND pins. The FBVTT should be connected to

the VTT regulation point, which is usually the VTT local

bypass capacitor, via a direct sense trace. The VTTGND

should be connected via a direct sense trace to the ground

of the VTT local bypass capacitor for load.

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16

NCP5214

Supply Voltage Undervoltage Monitor

MOSFET to discharge the excessive output voltage. When

the VDDQ output voltage goes back down to the nominal

regulation voltage, normal switching cycles are resumed.

When the VDDQ output exceeds 130% (typ) of the

nominal regulation voltage for 4 consecutive internal clock

cycles, the controller sets overvoltage fault, the device is

latched off by turning off both the high−side and low−side

MOSFETs. The overvoltage fault latch can be reset and the

controller can be restarted by toggling VDDQEN, VCCA,

or VIN.

The IC continuously monitors VCCA and VIN through

VCCA pin and OCDDQ pin respectively. VCCAGD is set

HIGH if VCCA is higher than its preset threshold (derived

from VREF with hysteresis). The IC will enter S5 state if

VCCA fails while in S0 and both VDDQEN and VTTEN

remain HIGH.

Thermal Shutdown

When the chip junction temperature exceeds 150_C, the

entire IC is shutdown. The IC resumes normal operation

only after the junction temperature dropping below 125_C.

Undervoltage Protection

In S3 power−saving mode with reduced switching at

lighter loads, when the VDDQ falls below 94% of the

nominal regulation voltage, the reduced switching

frequency is raised up back to the maximum switching

frequency. When VDDQ voltage is back to nominal

regulation voltage, the normal S3 power−saving operation

is resumed. In both S0 and S3 modes, when the VDDQ falls

below 65% (typ) of the nominal regulation voltage for 4

consecutive internal clock cycles, the undervoltage fault is

set, the device is latched off by turning off both the

high−side and low−side MOSFETs. The output is

discharged by the load current. The load current and output

capacitance determine the discharge rate. Cycling

VDDQEN, VCCA, or VIN can reset the undervoltage fault

latch and restart the controller.

Power Good

The PGOOD is an open−drain output of a window

comparator which continuously monitors the VDDQ

output voltage. The PGOOD is pulled low when the VDDQ

rises 12% above or drops 12% below the nominal

regulation point. The PGOOD becomes high impedance

when the VDDQ is within 12% of the preset nominal

regulation voltage. A 100 kW resistor is recommended to

connect between PGOOD and VCCA as pull−up resistor

for logic level output.

Overvoltage Protection

When the VDDQ output is above 106% but below 130%

of the nominal regulation output voltage, the controller

turns off the high−side MOSFET and turns on the low−side

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NCP5214

VCCA

VIN

(VOCDDQ)

VDDQEN

VTTEN

VTTEN is

Don’t Care

in S5

VDDQ

Soft−start

VDDQ

VTT

VTT in H−Z

VTT Soft−start

VTTREF

PGOOD

t

X 200 ms

hold

Operating

Mode

S5

S0

S3

S0

S5

VTTEN goes LOW

to activate S3 mode

and to turn off VTT.

PGOOD

goes HIGH.

Both VDDQEN and

VTTEN go LOW to

trigger S5 mode;

VCCA goes

above 4.0 V to

enable the IC.

VDDQ, VTT, VTTREF

are disabled, then

INREGDDQ and

INREGDDQ goes

HIGH, VTT goes into

normal mode.

VDDQEN goes HIGH,

VDDQ and VTTREF

are enabled but not

activated until VIN

goes above threshold

of 3.0 V. VTTEN goes

HIGH, VTT is enabled

but not activated until

VDDQ is good.

PGOOD goes LOW.

VTTEN goes

HIGH, VTT goes

into normal mode.

VIN goes above the

threshold, the VDDQ

and VTTREF go into

normal mode.

Figure 38. Powerup and Powerdown Timing Diagram

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18

NCP5214

APPLICATION INFORMATION

Input Capacitor Selection for VDDQ Buck Regulator

The input capacitor is important for proper regulation

operation of the buck regulator. It minimizes the input

voltage ripple and current ripple from the power source by

providing a local loop for switching current. The input

capacitor should be placed close to the drain of the

high−side MOSFET and source of the low−side MOSFET

with short, wide traces for connection. The input capacitor

must have large enough rms ripple current rating to

withstand the large current pulses present at the input of the

bulk regulator due to the switching current. The required

input capacitor rms ripple current rating can be estimated

V

+ I

L(ripple)

ESR, for small t

on

and large C

OUT

ripple

(eq. 3)

where I

and C

is the inductor ripple current, t is on−time,

on

L(ripple)

is the output capacitance.

OUT

The inductor ripple current can be calculated by the

equation:

(V −V

IN OUT

) V

OUT

V

(eq. 4)

I

+

L(ripple)

L f

SW

IN

where L is the inductance and f

is the switching

SW

frequency. The output ripple voltage can be reduced by

either using the inductor with larger inductance or the

output capacitor with smaller ESR. Thus, the ESR needed

to meet the ripple voltage requirement can be obtained by:

by the following with minimum V :

IN

2

V

OUT

IN

(eq. 1)

_OUTǸ

_*ǒ Ǔ

I

w I

CIN(RMS)

V

IN

V

ripple

L f

V

IN

SW

(eq. 5)

ESR v

Besides, the voltage rating of the input capacitor should

be at least 1.25 times of the maximum input voltage.

Capacitance of around 20 mF to 50 mF should be sufficient

for most DDR applications. Ceramic capacitors are the

most suitable choice of input capacitor for notebook

applications due to their low ESR, high ripple current, and

high voltage rating. POSCAP or OS−CON capacitors can

also be used since they have good ESR and ripple current

rating, but they are larger in size and more expensive.

Aluminum electrolytic capacitors are also a choice for their

high voltage rating and low cost, but several aluminum

capacitors in parallel should be used for the required ripple

current. If ceramic capacitors are used, X5R and X7R types

are preferred rather than the Y5V type since the X5R and

X7R types are ceramic capacitors and have smaller

tolerance and temperature coefficient.

(V −V

IN OUT

) V

OUT

The inductor ripple current is typically 30% of the

maximum load current and the ripple voltage is typically

2% of the output voltage. Thus, the above inequality can be

simplified to:

0.02 V

OUT

(eq. 6)

ESR v

0.3 I

LOAD(max)

For the load transient, the output capacitor contributes to

both the load−rise and the load−release responses. The

voltage undershoot during step−up load can be calculated

by the equation:

1−^V

OUT

IN

DI

C

LOAD

OUT

V

+ DI

LOAD

ESR )

ǒ Ǔ

(eq. 7)

undershoot

f

SW

Output Capacitor Selection for VDDQ Buck Regulator

The output filter capacitor plays an important role in

steady state output ripple voltage, load transient

requirement, and loop compensation stability. The ESR

and the capacitance of the output capacitor are the most

important parameters needed to be considered. In general,

the output capacitor must have small enough ESR for

output ripple voltage and load transient requirement.

Besides, the capacitance of the output capacitor should be

large enough to meet the overshoot and undershoot during

load transient. Since steady state output ripple voltage,

transient load undershoot and overshoot are the largest at

where DI

is the change in output current. If the second

LOAD

term is ignored, then it becomes the following inequality:

V

undershoot

(eq. 8)

ESR v

DI

LOAD

The maximum ESR requires to meet voltage undershoot

requirement at step−up load transient can be estimated

from the above inequality.

Then, the required output capacitor capacitance can be

obtained by the following:

1−^V

OUT

IN

DI

LOAD

V

C

OUT

w

ǒ Ǔ

(eq. 9)

V

−DI

ESR

f

SW

undershoot LOAD

maximum V , the ESR and capacitance of output

IN

capacitor should be estimated at the maximum V

condition.

IN

The output voltage overshoot during load−release is

because the excessive stored energy in the inductor is

absorbed by the output capacitor. The overshoot voltage

can be calculated by the following equation:

For steady output ripple voltage, both ESR and

capacitance of the output capacitor are the contributing

factors, however, the capacitor ESR is the dominant factor.

The output ripple voltage is calculated as follows:

2

LI

2

V

) C

OUT OUT

OUT

STEP(peak)

C

₊Ǹ

V

overshoot

−V

OUT

I

t

on

L(ripple)

(eq. 2)

V

ripple

+ I ESR )

L(ripple)

(eq. 10)

C

OUT

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19

NCP5214

Then the required output capacitor capacitance can be

estimated by:

current. Therefore, the maximum DC current rating of the

inductor can be obtained by:

(eq. 16)

2

I + 1.2 I

L(rating) L(peak)

L I

STEP(peak)

(eq. 11)

C

w

OUT

2 2

) V ) −V

OUT

(V

overshoot

where I

is the peak inductor current at maximum load

OUT

) V

L(peak)

current which is determined by:

(V −V

IN OUT

OUT

I

+ DI )

LOAD

STEP(peak)

I

L(ripple)

2

2L f

SW

V

IN

I

+ I

)

L(peak)

LOAD(max)

+ I

LOAD(max)

(eq. 12)

(V −V

IN OUT

) V

OUT

where I

is the load current step plus half of the

STEP(peak)

2 L f

SW

V

IN

ripple current at the load release and DI

in the output load current.

is the change

LOAD

(eq. 17)

Besides, the ESR and the capacitance of the output filter

capacitor also contribute to double pole and ESR zero

frequencies of the output filter, and the poles and zeros

frequencies of the compensation network for close loop

stability. The compensation network will be discussed in

more detail in the Loop Compensation section.

Other parameters about output filter capacitor that

needed to be considered are the voltage rating and ripple

current rating. The voltage rating should be at least 1.25

times the output voltage and the rms ripple current rating

should be greater than the inductor ripple current. Thus, the

voltage rating and ripple current rating can be obtained by:

Since the excessive energy stored in the inductor

contributed to the output voltage overshoot during load

release, the following inequality can be used to ensure that

the selected inductance value can meet the voltage

overshoot requirement at load release:

2

C

OUT

((V

) V

OUT

) −V

OUT

)

overshoot

L v

2

I

STEP(peak)

(eq. 18)

In addition, the inductor also needs to have low enough

DCR to obtain good conversion efficiency. In general,

inductors with about 2.0 mW to 3.0 mW per mH of

inductance can be used. Besides, larger inductance value

can be selected to achieve higher efficiency as long as it

still meets the targeted voltage overshoot at load release

and inductor DC current rating.

(eq. 13)

V

rating

w 1.25 V

OUT

(V −V

) V

V

IN OUT

OUT

I

w I +

L(ripple)

COUT(RMS)

L f

SW

IN

(eq. 14)

MOSFET Selection

SP−Cap, POSCAP and OS−CON capacitors are suitable

for the output capacitor since their ESR is low enough to

meet the ripple voltage and load transient requirements.

Usually, two or more capacitors of the same type,

capacitance and ESR can be used in parallel to achieve the

required ESR and capacitance without change the ESR

zero position for maintaining the same loop stability. Other

than the performance point of view, the physical size and

cost are also the concerned factors for output capacitor

selection.

External N−channel MOSFETs are used as the switching

elements of the buck controller. Both high−side and

low−side MOSFETs must be logic−level MOSFETs which

can be fully turned on at 5.0 V gate−drive voltage.

On−resistance (R

), maximum drain−to−source

DS(on)

voltage (V ), maximum drain current rating, and gate

DSS

charges (Q , Q , Q ) are the key parameters to be

G

GD

GS

considered when choosing the MOSFETs.

For on−resistance, it should be the lower; the better is the

performance in terms of efficiency and power dissipation.

Check the MOSFET’s rated R

at V = 4.5 Vwhen

GS

Inductor Selection

DS(on)

selecting the MOSFETs. The low−side MOSFET should

have lower R than the high−side MOSFET since the

turn−on time of the low−side MOSFET is much longer than

The inductor should be chosen according to the inductor

ripple current, inductance, maximum current rating,

transient load release, and DCR.

DS(on)

the high−side MOSFET in high V and low V

converter. Generally, high−side MOSFET with R

buck

In general, the inductor ripple current is 20% to 40% of

the maximum load current. A ripple current of 30% of the

maximum load current can be used as a typical value. The

required inductance can be estimated by:

IN

OUT

DS(on)

about

about 7.0 mW and low−side MOSFET with R

DS(on)

5.0 mW can achieve good efficiency.

The maximum drain current rating of the high−side

MOSFET and low−side MOSFET must be higher than the

peak inductor current at maximum load current. The

low−side MOSFET should have larger maximum drain

current rating than the high−side MOSFET since the

low−side MOSFET have longer turn−on time.

(V −V

IN OUT

0.3 I

LOAD(max)

) V

OUT

V f

IN SW

(eq. 15)

L w

where I

is the maximum load current.

The DC current rating of the inductor should be about 1.2

times of the peak inductor current at maximum output load

LOAD(max)

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20

NCP5214

The maximum drain−to−source voltage rating of the

MOSFETs used in buck converter should be at least 1.2 times

of the maximum input voltage. Generally, V of 30 V

left floating for normal operation. The voltage drop across

RL1 must be less than 1.0 V to allow enough headroom for

the voltage detection at the OCDDQ pin under low VIN

DSS

should be sufficient for both high−side MOSFET and

low−side MOSFET of the buck converter for notebook

application.

condition. In addition, since the MOSFET R

with temperature as current flows through the MOSFET

increases, the OCP trip point also varies with the MOSFET

varies

DS(on)

As a general rule of thumb, the gate charges are the

R

temperature variation.

DS(on)

smaller; the better is the MOSFET while R

is still low

Since the IOC and R

have device variations and

DS(on)

enough. MOSFETs are susceptible to false turn−on under

high dV/dt and high VDS conditions. Under high dV/dt and

MOSFET R

increase with temperature, to avoid false

DS(on)

triggering the overcurrent protection in normal operating

output load range, calculate the RL1 value from the

previous equation with the following conditions such that

minimum value of inductor current limit is set:

1. The minimum IOC value from the specification

table.

high V condition, current will flow through the C of

DS

GD

the capacitor divider formed by C and C , cause the

GD

GS

C

to charge up and the V to rise. If the V rises above

GS GS

GS

the threshold voltage, the MOSFET will turn on.

Therefore, it should be checked that the low−side MOSFET

have low Q to Q ratio. This indicates that the low−side

2. The maximum R

of the MOSFET used at

DS(on)

GD

GS

MOSFET have better immunity to short moment false

turn−on due to high dV/dt during the turn−on of the

high−side MOSFET. Such short moment false turn−on will

cause minor shoot−through current which will degrade

efficiency, especially at high input voltage condition.

the highest junction temperature.

3. Determine I for I > I +

LOAD(max)

LIMIT

I

2, where I

= I

+

L(ripple)/

LOAD(max)

VDDQ(max)

if VTT is powered by VDDQ.

VTT(max)

Besides, a decoupling capacitor C_DCPLshould be added

closed to the lead of the current limit setting resistor RL1

which connected to the drain of the high−side MOSFET.

Overcurrent Protection of VDDQ Buck Regulator

The OCP circuit is configured to set the current limit for

the current flowing through the high−side FET and

inductor during S0 and S3. The overcurrent tripping level

is programmed by an external resistor RL1 connected

between the OCDDQ pin and drain of the high−side FET.

An internal 31 mA current sink (IOC) at pin OCDDQ

establishes a voltage drop across the resistor RL1 at a

magnitude of RL1xIOC and develops a voltage at the

non−inverting input of the current limit comparator.

Another voltage drop is established across the high−side

Loop Compensation

Once the output LC filter components have been

determined, the compensation network components can be

selected. Since NCP5214 is a voltage mode PWM

converter with output LC filter, Type III compensation

network is required to obtain the desired close loop

bandwidth and phase boost with unconditional stability.

The NCP5214 PWM modulator, output LC filter and

Type III compensation network are shown in Figure 39.

The output LC filter has a double pole and a single zero.

The double pole is due to the inductance of the inductor and

capacitance of the output capacitor, while the single zero

is due to the ESR and capacitance of the output capacitor.

The Type III compensation has two RC pole−zero pairs.

The two zeros are used to compensate the LC double pole

and provide 180° phase boost. The two poles are used to

compensate the ESR zero and provide controlled gain

roll−off. For an ideally compensated system, the Bode plot

should have the close−loop gain roll−off with a slope of

−20 dB/decade crossing the 0 dB with the required

bandwidth and the phase margin larger than 45° for all

frequencies below the 0 dB frequency. The closed loop

gain is obtained by adding the modulator and filter gain (in

dB) to the compensation gain (in dB).The bandwidth is the

frequency at which the gain is 0 dB and the phase margin

is the difference between the close loop phase and 180°.

The goal of compensation is to achieve a stable close loop

system with the highest possible bandwidth, the gain

having −20 dB/decade slope at 0 dB gain crossing, and

sufficient phase margin for stability. The bandwidth of

close loop gain should be less than 50% of the switching

frequency and the compensation gain should be bounded

by the error amplifier open loop gain.

MOSFET R

at a magnitude of I_LxR

and a

DS(on)

voltage is developed at SWDDQ when the high−side

MOSFET is turned on and the inductor current flows

through the R

of the MOSFET. The voltage at the

DS(on)

non−inverting input of the current limit comparator is then

compared to the voltage at SWDDQ pin when the

high−side gate drive is high after a fixed period of blanking

time (150 ns) to avoid false current limit triggering. When

the voltage at SWDDQ is lower than the voltage at the

non−inverting input of the current limit comparator for four

consecutive internal clock cycles, an overcurrent condition

occurs, during which, all outputs will be latched off to

protect against a short−to−ground condition on SWDDQ or

VDDQ. i.e., the voltage drop across the R

of

DS(on)

high−side FET developed by the drain current is larger than

the voltage drop across RL1, the OCP is triggered and the

device will be latched off.

The overcurrent protection will trip when a peak inductor

current hit the I

determined by the equation:

LIMIT

RL1 IOC

I

+

(eq. 19)

LIMIT

R

DS(on)

It should be noted that the OCDDQ pin must be pulled

high to VIN through a resistor RL1 and this pin cannot be

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21

NCP5214

VIN

CIN

NCP5214

VBOOST

Q1

Q2

TGDDQ

VDDQ

L

VDDQ

PWM

LOGIC

SWDDQ

BGDDQ

VCCP

PGND

ESR

OUTPUT

FILTER

COUT

PGND

PWM

COMP

OSC

COMP

C2

C3

R4

ERROR

AMP

VIN

C1

VREF

COMPENSATION

NETWORK

R1

R2

VRAMP

R3

ADAPTIVE

RAMP

A

FBDDQ

MODULATOR

Figure 39. Voltage Mode Buck Converter with Modulator, LC filter and Type III Compensation

Modulator DC Gain can be calculated by:

Type III compensation poles and zeros break frequencies

are defined by the below equations:

V

IN

(eq. 20)

G

+ 20 log

MOD(DC)

V

1

RAMP

(eq. 24)

f

+

Z1

2p R C

3

2

LC filter double pole and ESR zero break frequencies are

defined by:

1

ǒ

f

+

P1

(eq. 25)

C

1

C

1

C

)C

2

Ǔ

2p R

1

3

f

+

(eq. 21)

PLC

Ǹ

2p L C

OUT

1

(eq. 26)

(eq. 27)

f

+

Z2

2p (R ) R ) C

1

4

3

(eq. 22)

f

+

ZESR

2p ESR C

OUT

1

f

+

P2

Compensation network DC Gain can be calculated by the

equation:

2p R C

4

3

R

3

R

1

(eq. 23)

G

+ 20 log

COMP(DC)

100

f

Z1

f

Z2

f

80

60

40

20

P1

f

P2

Open Loop Error

Amp Gain

Compensation

Gain

0

R

3

1

20 log

−20

−40

Closed Loop Gain

V

IN

Modulator & Filter Gain

f

ZESR

PLC

V

RAMP

f

−60

10

100

1 k

10 k 100 k 1 M 10 M

FREQUENCY (Hz)

Figure 40. Asymptotic Bode Plot of the Converter Gain

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22

NCP5214

Close loop system bandwidth can be calculated by:

By using the above equations and guidelines, the

compensation components values can be determined by the

equations below:

R

V

3

1

IN

1

BW +

(eq. 28)

Ǹ

V

RAMP

2p L C

OUT

Ǹ

2p BW V

R L C

RAMP

V

1

OUT

Since the ramp amplitude of the PWM modulator has a

voltage feedforward function, the ramp amplitude is a

(eq. 30)

R

+

3

IN

function of V which can be determined by:

IN

Ǹ

2 L C

OUT

(eq. 31)

(eq. 32)

C

+

2

(eq. 29)

V

+ 1.25 V ) 0.045 (V −5.0 V)

IN

RAMP

R

3

Below are some guidelines for setting the compensation

components:

C

2

⁺ǒ

Ǔ_* 1

C

1

R

C

2

3

ESR C

1. Set a value for R between 2.0 kW and 5.0 kW.

OUT

1

2. Set a target for the close loop bandwidth which

should be less than 50% of the switching

frequency.

R

1

(eq. 33)

(eq. 34)

R

4

+

Ǹ

p f

SW

L C

* 1

OUT

1

3. Pick compensation DC gain (R /R ) for desired

3

1

C

3

+

p R f

4

SW

close loop bandwidth.

The modulator and filter gain, compensation gain, and

close loop gain asymptotic Bode plot can be drawn by the

calculated results to check the compensation gain and close

loop gain obtained. An example of asymptotic Bode plot is

shown in Figure 40.

4. Place 1st zero at half filter double pole.

5. Place 1st pole at ESR zero.

6. Place 2nd zero at filter double pole.

7. Place 2nd pole at half the switching frequency.

The phase of the output filter can be calculated by:

2pf ESR ) DCR C

OUT

−1

ǒ

Ǔ

Phase

+ −tan (2pf ESR C

)−tan

(eq. 35)

(Filter)

OUT

2

2pf L C

−1

OUT

where the DCR of the inductor can be neglected if the DCR is small.

The phase of the Type III compensation network can be calculated by:

C C

C ) C

1

2

−1

ǒ_{2pf R}

Ǔ

Phase

+ −90° ) tan (2pf R C )−tan

(TypeIII)

3

2

3

(eq. 36)

(eq. 39)

−1

) tan (2pf (R ) R ) C )−tan (2pf R C )

1

4

3

4

3

The close loop phase can be calculated by summing the

filter phase and compensation phase:

0.8 R

1

R

2

+

V

OUT

−0.8

Phase

+ Phase

) Phase

(Filter) (TypeIII)

It is recommended to adjust the value of R to fine−tune

(CloseLoop)

2

the output voltage when it is necessary. The value of R

1

(eq. 37)

should not be changed since the compensation DC gain and

the 2 zero break frequency of the compensation gain are

Then the close loop phase margin can be estimated by:

nd

Phase

+ Phase

* (*180°)

(Margin)

(CloseLoop)

contributed by R . If the value of R is changed, the

1

(eq. 38)

compensation, the close loop bandwidth and phase margin,

and the system stability will be affected. Besides, it is

recommended to use resistors with at least 1% tolerance for

It should be checked that closed loop gain has a 0 dB gain

crossing with −20 dB/decade slope and a phase margin of

45° or greater. The compensation components values may

require some adjustment to meet these requirements.

Besides, the compensation gain should be checked with the

error amplifier open loop gain to make sure that it is

bounded by the error amplifier open loop gain.

The poles and zeros locations and hence the

compensation network components values may need to be

further fine tuned after actual system testing and analysis.

R and R .

1

2

Soft−Start of Buck Regulator

A VDDQ soft−start feature is incorporated in the device

to prevent surge current from power supply and output

voltage overshoot during power up. When VDDQEN,

VCCA, and VOCDDQ rise above their respective upper

threshold voltages, the external soft−start capacitor C

SS

will be charged up by a constant current source, I . When

ss

Feedback Resistor Divider

The output voltage of the buck regulator can be adjusted

by the feedback resistor divider formed by R and R . Once

the soft−start voltage (Vcss) rises above the SS_EN voltage

(X50 mV), the BGDDQ and TGDDQ will start switching

and VDDQ output will ramp up with VFBDDQ following

the soft−start voltage. When the soft−start voltage reaches

the SS_OK voltage (XVref + 50 mV), the soft−start of

1

2

the value of R is selected when determining the

1

compensation components, the value of R can be obtained

2

by:

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23

NCP5214

VDDQ is finished. The C will continue to charge up until

it reaches about 2.5 V to 3.0 V.

to VTTGND with at least a 10 mF capacitor if external

voltage source is used.

ss

The soft−start time t can be programmed by the

ss

Design Example

soft−start capacitor according to the following equation:

A design example of a VDDQ bulk converter with the

following design parameters is shown below:

0.8 C

ss

(eq. 40)

t

ss

[

I

ss

DDR2 VDDQ bulk converter design parameters:

1. Input voltage range: 7.0 V to 20 V.

Ceramic capacitors with low tolerance and low

temperature coefficient, such as B, X5R, X7R ceramic

capacitors are recommended to be used as the C . Ceramic

capacitors with Y5V temperature characteristic are not

recommended.

2. Nominal V : 1.8 V.

OUT

SS

3. Static tolerance: 2% ("36 mV).

4. Transient tolerance: "100 mV.

5. Maximum output current: 10 A

(I

= 8.0 A, I

= 2.0 A).

Soft−Start of VTT Active Terminator

VDDQ(max)

VTT(max)

6. Load transient step: 1.0 A to 8.0 A.

7. Switching frequency: 400 kHz.

8. Bandwidth: 100 kHz.

The VTT source current limit is used as a constant

current source to charge up the VTT output capacitor

during VTT soft−start. Besides, the VTT source current

limit is reduced to about 1.0 A for 128 internal clock cycles

to minimize the inrush current during VTT soft−start.

9. Soft−start time: 400 ms.

a. Calculate input capacitor rms ripple current rating and

voltage rating:

Therefore, the VTT soft−start time t

by the equation:

can be estimated

SSVTT

2

1.836 V

8.0 V

1.836 V

8.0 V

Ǹ

_*ǒ

Ǔ

I

w 10 A

+ 4.2 A

CIN(RMS)

C

VTT

OUTVTT

I

(eq. 41)

t

[

SSVTT

(eq. 42)

LIMVTSS

(eq. 43)

V

w 20 1.25 V + 25 V

where C

is the capacitance of VTT output capacitor

CIN(rating)

OUTVTT

and I

is the VTT soft−start source current limit.

LIMVTSS

Therefore, two 10 mF 25 V ceramic capacitors with 1210

size in parallel are used.

Boost Supply Diode and Capacitor

b. Calculate inductance, rated current and DCR of

inductor:

First, suppose ripple current is 0.3 times the maximum

output current, such that:

An external diode and capacitor are used to generate the

boost voltage for the supply of the high−side gate driver of

the bulk regulator. Schottky diode with low forward

voltage should be used to ensure higher floating gate drive

voltage can be applied across the gate and the source of the

high−side MOSFET. A Schottky diode with 30 V reverse

voltage and 0.5 A DC current ratings can be used as the

boost supply diode for most applications. A 0.1 mF to

0.22 mF ceramic capacitor should be sufficient as the boost

capacitor.

(20 V−1.836 V) 1.836 V

0.3 10 A 20 V 400 kHz

(eq. 44)

+ 1.39 mH

L w

Second, the overshoot requirement at load release is then

considered and supposes two 220 mF capacitors in parallel

are used as an initially guess, such that:

2

)

(

440 mF (100 mV )1.836 V) −(1.836 V)

Lv

+2.56 mH

0.3 7 A

2

Ǔ

ǒ_{7 A )}

VTTI Input Power Supply for VTT and VTTR

2

(eq. 45)

Both VTT and VTTR are supplied by VTTI for sourcing

current. VTTI is normally connected to the VDDQ output

for optimum performance. If VTTI is connected to VDDQ,

no bypass capacitor is required to add to VTTI since the

bulk capacitor at VDDQ output is sufficiently large.

Besides, the maximum load current of VDDQ is the sum of

Thus, inductors with standard inductance values of

1.5 mH, 1.8 mH and 2.2 mH can be used. As a trade−off

between smaller overshoot and better efficiency, the

average value of 1.8 mH inductor is selected.

Then, the maximum rated DC current is calculated by:

I

and I

when making electrical design

(20 V−1.836 V) 1.836 V

2 1.8 mH 400 kHz 20

VDDQ(max)

VTT(max)

_+ 1.2ǒ_{10 A )}

Ǔ

I

L(rated)

and components selection of the VDDQ buck regulator.

VTTI can also be connected to an external voltage source.

However, extra power dissipation will be generated from

the internal VTT high−side MOSFET and more

heatsinking is required if the external voltage is higher than

+ 13.39 A

(eq. 46)

Therefore, inductor with maximum rated DC current of

14 A or larger can be used.

Finally, the DCR of inductor is 2.0 mW per mH of

inductance as a rule of thumb, then:

VDDQ. Whereas, the headroom will be limit by the R

DS(on)

of the VTT linear regulator high−side MOSFET, and the

maximum VTT output current with VTT within regulation

window will also be reduced if the external voltage is lower

than VDDQ. Besides, the VTTI pin input must be bypassed

2 mW

(eq. 47)

DCR +

1.8 mH + 3.6 mW

1 mH

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24

NCP5214

Thus, inductor with 1.8 mH inductance, 14 A maximum

Second, the ESR required to meet the transient load

undershoot requirement is considered, such that:

rated DC current and 3.5 mW DCR is chosen.

c. Calculate ESR and capacitance of output filter

capacitor:

100 mV

(eq. 49)

ESR v

+ 14.3 mW

7 A

First, the ESR required to achieve the desired output

ripple voltage is considered. Suppose the output ripple

voltage is 2% of the nominal output voltage.

Therefore, the suitable ESR is 12 mW or smaller, and the

value of 7.5 mW is selected for more design margin and

better performance. Then, two same SP−Caps or POSCAPs

each with 15 mW ESR in parallel having a resultant ESR

of 7.5 mW should be good enough to meet the

requirements.

Then, check that whether the previously supposed

capacitance meets the undershoot and overshoot

requirements.

(0.02 1.8 V) 1.8 mH 400 kHz 20 V

ESR v

(20 V−1.8 V) 1.8 V

+ 15.8 mW

(eq. 48)

To ensure that undershoot requirement of less than 100 mV is achieved, the capacitance must be:

1.8 V−36 mV

ǒ₁₋

Ǔ

20 V

7 A

(eq. 50)

(eq. 51)

C

w

+ 335.9 mF

ǒ Ǔ

OUT

100 mV−7 A 7.5 mW

400 kHz

To make sure that overshoot requirement of less than 100 mV is fulfilled, capacitance must be:

(20 V−1.836 V) 1.836 V

_{1.8 mH}ǒ_{7 A )}

(100 mV ) 1.836 V) − (1.836 V)

Ǔ²

2

2 1.8 mH 400 kHz 20 V

C

w

+ 317.6 mF

OUT

2

Therefore, output capacitor with capacitance of 440 mF

should meet both undershoot and overshoot requirements.

Sometimes, it may take several times of iterations between

the process of selecting inductance of the inductor and ESR

and capacitance of the output capacitor.

d. Calculate the resistance value of OCP current limit

setting resistor:

First, the OCP current limit is estimated at maximum

load condition, such that:

(20 V−1.836 V) 1.836 V

2 1.8 mH 400 kHz 20 V

I

u 8 A ) 2 A )

+ 11.16 A

LIMIT

Then, the voltage rating of the output capacitor is

estimated by:

(eq. 54)

(eq. 52)

V

rated

w 1.25 1.836 V + 2.3 V

Thus, I

is set to 11.5 A. Suppose from the high−side

LIMIT

Thus, output capacitor with 2.5 V or larger rated voltage

is used.

Finally, the rated rms ripple current of the output

capacitor is considered:

MOSFET data sheet, the maximum R

is 10 mW.

DS(on)

Then, the value of RL1 is calculated by:

11.5 A 10 mW

(eq. 55)

RL1 +

+ 4.4 kW

26 mA

(20 V−1.836 V) 1.836 V

1.8 mH 400 kHz 20 V

Therefore, the resistor with standard value of 4.7 kW is

selected for RL1.

I

w

+ 2.3 A

COUT(rms)

(eq. 53)

e. Calculate the RC values of the compensation network:

Thus, capacitor with rated rms ripple current of 3.0 A or

larger should be selected. Two capacitors each with 1.5 A

rated ripple current can be connected in parallel to provide

a total of 3.0 A rated rms ripple current.

Therefore, two same capacitors in parallel each with

capacitance of 220 mF, ESR of 15 mW, rated voltage of

2.5 V, and rated rms ripple current of 1.5 A are used.

First, 4.3 kW is chosen as the value of R which is in the

1

range between 2.0 kW and 5.0 kW.

Since the worst case of stability is at the maximum V ,

IN

the close loop compensation should be considered at

maximum V . Then the ramp amplitude can be calculated

IN

as below:

V

+ 1.25 V ) 0.045 (20 V−5 V) + 1.925 V

RAMP

(eq. 56)

Since the L = 1.8 mH, C

= 440 mF, and the target close loop bandwidth is 100 kHz, the value of R can be

3

OUT

calculated as:

Ǹ

2p 100 kHz 1.925 V 4.3 kW 1.8 mH 440 mF

(eq. 57)

R

3

+

+ 7.3 kW

20 V

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25

NCP5214

Thus, standard value of 7.5 kW is selected for R .

Then, if the second zero break frequency is placed at the LC

filter’s double pole and the second pole is placed at half the

3

If the first zero break frequency is placed at half the LC

filter’s double pole, the value of C can be calculated by:

switching frequency, the value of R can be calculated by:

2

4

4.3 kW

Ǹ

2 1.8 mH 440 mF

R

4

+

+ 125 W

(eq. 58)

C

2

+

+ 7.5 nF

Ǹ

p 400 kHz 1.8 mH 440 mF−1

7.5 kW

(eq. 60)

Thus, standard value of 8.2 nF is chosen for C2.

If the 1st pole break frequency is placed at the LC filter’s

Thus, standard value of 130 W is selected for R .

4

Then, C can be calculated by:

3

ESR zero, the value of C can be calculated by:

1

(eq. 61)

+ 6.12 nF

C

3

+

8.2 nF

7.5 kW 8.2 nF

7.5 mW 440 mF

C

1

+

+ 464.9 pF

p 130 W 400 kHz

(eq. 59)

* 1

Therefore, standard value of 5.6 nF is selected for C .

3

Thus, standard value of 470 pF can be chosen for C .

1

However, 180 pF is selected for more phase boost at the

0 dB gain crossing.

Then, the close loop phase margin can be estimated by the following:

−1

+ −tan (2p 100 kHz 7.5 mW 440 mF)

Phase

(Filter)

2p 100 kHz 7.5 mW

−1

ǒ

Ǔ

−tan

2

2p (100 kHz) 1.8 mH 440 mF−1

+ −153.66°

−1

+ −90 ) tan (2p 100 kHz 7.5 kW 8.2 nF)

Phase

(TypeIII)

180 pF 8.2 nF

180 pF ) 8.2 nF

) tan (2p 100 kHz (4.3 kW ) 130 W) 5.6 nF)

−1

ǒ_{2p 100 kHz 7.5 kW}

Ǔ

−tan

(eq. 62)

−1

−tan (2p 100 kHz 130 W 5.6 nF)

+ 20.57°

Phase

+ −153.66° ) 20.57° + −133.09°

(closeloop)

+ Phase

−(−180°) + −133.09°−(−180°) + 46.91°

(closeloop)

(margin)

Therefore, the phase margin is large enough for stability.

f. Calculate the resistance value of feedback resistor

divider:

Therefore, a 3.44 kW resistor is selected for the low−side

feedback resistor R .

2

g. Calculate soft−start capacitor value for the desired

Since a 4.3 kW resistor is chosen as the high−side resistor

400 ms VDDQ soft−start time:

R , the resistance value of low−side resistor R can be

calculated by:

1

2

4.0 mA 400 ms

(eq. 64)

C

SS

+

+ 2.0 nF

0.8 V

0.8 4.3 kW

1.8 V−0.8 V

Therefore, 2.0 nF X5R ceramic capacitor is selected for

the soft−start capacitor.

(eq. 63)

R

2

+

+ 3.44 kW

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26

NCP5214

PCB Layout Guidelines

vias with 0.6 mm hole−diameter to help heat

dissipation and ensure good thermal capability. It

is recommended to use PCB with 1 oz or 2 oz

copper foil. The thermal pad can be connected to

either PGND ground plane or AGND ground

plane but not both.

Cautious PCB layout design is very critical to ensure

high performance and stable operation of the DDR power

controller. The following items must be considered when

preparing PCB layout:

1. All high−current traces must be kept as short and

wide as possible to reduce power loss.

5. The input capacitor ground terminal, the VDDQ

output capacitor ground terminal and the source

of the low−side MOSFET must be connected to

the PGND ground plane through multiple vias.

6. Sensitive traces like trace from FBDDQ, trace

from COMP, trace from OCDDQ, trace from

FBVTT and trace from VTTREF should be

avoided from the high−voltage switching nodes

like SWDDQ, BOOST, TGDDQ and BGDDQ.

7. Separate sense trace should be used to connect

the VDDQ point of regulation, which is usually

the local bypass capacitor for load, to the

feedback resistor divider to ensure accurate

voltage sensing. The feedback resistor divider

should be place close to the FBDDQ pin.

8. Separate sense trace should be used to connect the

VTT point of regulation, which is usually the local

bypass capacitor for load, to the FBVTT pin.

9. Separate sense trace should be used to connect

the VDDQ point of regulation to the DDQREF

pin to ensure that the reference voltage to VTT is

accurately half of the VDDQ voltage.

10. The traces length between the gate driver outputs

and gates of the MOSFETs must be minimized to

avoid parasitic impedance.

11. To ensure normal function of the device, an RC

filter should be placed close to the VCCA pin and

a decoupling capacitor should be placed close to

the VCCP pin.

12. The copper trace area of the switching node which

includes the source of the high−side MOSFET,

drain of the low−side MOSFET and high voltage

side of the inductor should be minimized by using

short wide trace to reduce EMI.

13. A snubber circuit consists of a 3.3 W resistor and

1.0 nF capacitor may need to be connected across

the switching node and PGND to reduce the

high−frequency ringing occurring at the rising

edge of the switching waveform to obtain more

accurate inductor current limit sensing of the

VDDQ buck converter. However, adding this

snubber circuit will slightly reduce the conversion

efficiency.

High−current traces are the trace from the input

voltage terminal to the drain of the high−side

MOSFET, the trace from the source of the

high−side MOSFET to the inductor, the trace

from inductor to the VDDQ output terminal, the

trace from the input ground terminal to the

VDDQ output ground terminal, the trace from

VDDQ output to VTTI pin, the trace from VTT

pin to VTT output terminal, and the trace from

VTT output ground terminal to the VTTGND pin.

Power handling and heaksinking of high−current

traces can be improved by also routing the same

high−current traces in the other layers and joined

together with multiple vias.

2. Power components which include the input

capacitor, high−side MOSFET, low−side

MOSFET and VDDQ output capacitor of the

buck converter section must be positioned close

together to minimize the current loop. The input

capacitor must be placed close to the drain of the

high−side MOSFET and the source of the

low−side MOSFET.

3. To ensure the proper function of the device,

separated ground connections should be used for

different parts of the application circuit according

to their functions. The input capacitor ground, the

low−side MOSFET source, the VDDQ output

capacitor ground, the VCCP decoupling capacitor

ground should be connected to the PGND. The

trace path connecting the source of the low−side

MOSFET and PGND pin should be minimized.

The VTT output capacitor ground should be

connected to the VTTGND first with a short

trace, it is then connected to the ground plane of

PGND. The VCCA decoupling capacitor ground,

the ground of the VDDQ feedback resistor, the

soft−start capacitor ground, the VTTREF output

capacitor ground should be connected to the

AGND. The AGND pin is then connected directly

through a sense trace to the remote ground sense

point of the PGND, which is usually the ground

of the local bypass capacitor for the load. Never

connect the AGND, PGND and VTTGND

together just under the thermal pad.

14. VTTI should be connected to VDDQ output with

wide and short trace if VDDQ is used as the

sourcing supply for VTT. An input capacitor of at

4. The thermal pad of the DFN−22 package should

be connected to the ground planes in the internal

layer and bottom layer from the copper pad at top

layer underneath the package through six to eight

least 10 mF should be added close to the VTTI

pin and bypassed to VTTGND if external voltage

supply is used as the VTT sourcing supply.

http://onsemi.com

27

NCP5214

VCCA

C5

U1

NCP5214

(option)

0.1 mF

16

R1

R2

R3

100 k 100 k 100 k 100 k

R4

1

2

VDDQEN OCDDQ

R6

TP5

5 V

20

17

5.6 kW

VTTEN

VCCP

BIAS SUPPLY

JP1 JP2 JP3

4.7 mF

C6

MBR0530T1

2

3

4

1

BOOST

FPWM

SS

D1

Q1

TP6

TP7

NTMS4700N

VIN

(4.5 V TO 24 V)

C7

C1

1.8 nF

C10

10 mF

C8

C9

10 mF *33 mF

ON Semiconductor

NCP5214

0.1 mF

GND

R7

18

19

TP1

TP4

15

TGDDQ

SWDDQ

(option for Vin < 8 V)

PGOOD

VTTREF

PGOOD

0 W

N−CHANNEL

30 V, 7.3 mW

NTMS4107N

14

1.8 mH, 14 A, 3.4 mW

VREF

0.9 V/15 mA

1.25 V/15 mA

AGND

VDDQ

C13

1 mF

TP8

1.8 V/10 A

2.5 V/12 A

VDDQ

C18

1 mF

TP10

TP2

L1

(option)

6

8

5

Q2

VTT

C12

150 mF

C11

150 mF

R14

3.3 W

VTT

0.9 V/ 1.5 A

1.25 V/ 1.5 A

FBVTT

VTTGND

R8

TP9

C19

C17

10 mF

21

22

12

C2

10 mF

BGDDQ

PGND

(option)

TP3

VDDQGND

0 W

1 nF

N−CHANNEL

VTTGND

5 V

C14

30 V, 4.7 mW

100 pF

R5

COMP

11

VCCA

C16

4.7 nF

C15

R11

4.3 k

C11, C12

(150 mF, 4 V, 15 mW)

R9

10 W

C4

1 mF

10 k

R10

130

LOW ESR SP−CAP UD Series

Panasonic EEFUD0G151R

(150 mF, 4 V, 18 mW)

LOW−ESR POSCAP TPE Series

SANYO 4TPE150MI

2.2 nF

10

13

7

FBDDQ

VTTI

DDQREF

AGND

(option)

C3

10 mF

* Install R12 = 3.44 k for VDDQ = 1.8 V

Install R12 = 2.02 k for VDDQ = 2.5 V

9

*

R12

3.44 k

C20

THPAD

23

10 mF

(option)

VTTGND

JP4

R13

0 W

Figure 41. Schematic Diagram of Evaluation Board

http://onsemi.com

28

NCP5214

PCB Layout of Evaluation Board

Figure 42. Silkscreen of Evaluation Board PCB

Figure 43. Top Layer of Evaluation Board

PCB Layout

Figure 45. Middle Layer2 of Evaluation

Board PCB Layout

Figure 44. Middle Layer1 of Evaluation

Board PCB Layout

Figure 46. Bottom Layer of Evaluation Board

PCB Layout

http://onsemi.com

29

NCP5214

Table 2. Bill of Materials of the Evaluation Board

Item

Qty

1

Designators

C1

Part Description

Mfg. & P/N

Remark

1

2

3

Capacitor, Ceramic, 1.8 nF/50 V 0603

Capacitor, Ceramic, 10 μF/6.3 V 0805

Panasonic ECJ1VB1H182K

Panasonic ECJ2FB0J106M

2

C2, C17

C3, C20

2

C3 & C20 are

optional

4

5

6

7

8

9

3

2

1

2

1

2

C4, C13, C18

C5, C7

C6

Capacitor, Ceramic, 1 μF/10 V 0805

Capacitor, Ceramic, 0.1 μF/25 V 0603

Capacitor, Ceramic, 4.7 μF/10 V 0603

Capacitor, Ceramic, 10 μF/25 V 1210

Capacitor, Electrolytic, 33 μF/35 V Size D

Panasonic ECJ1VB1A105M

Panasonic ECJ1VB1E104K

Panasonic ECJ2FB1C475M

Panasonic ECJ4YB1E106M

Panasonic EEVFK1V330P

C5 is optional

C9 is optional

C8, C10

C9

C11, C12

Capacitor, SP−CAP, 150 μF/4 V Size D /

Capacitor, POSCAP, 150 μF/4 V Size D

Panasonic EEFUD0G151R /

Sanyo 4TPE150MI

10

11

12

13

14

15

16

17

1

3

1

C14

Capacitor, Ceramic, 100 pF/50 V 0603

Capacitor, Ceramic, 2.2 nF/50 V 0603

Capacitor, Ceramic, 4.7 nF/50 V 0603

Capacitor, Ceramic, 1 nF/50 V 0603

Diode, 0.5 A 30 V schottky SOD−123

Header, 3−pin, 100 mil spacing

Panasonic ECJ1VC1H101K

Panasonic ECJ1VB1H222K

Panasonic ECJ1VB1H472K

Panasonic ECJ1VB1H102K

ON Semiconductor MBR0530T1

Any

C15

C16

C19

C19 is optional

D1

JP1, JP2, JP3

JP4

Header, 2−pin, 100 mil spacing

Any

L1

Inductor, SMD, 1.8 μH/14 A /

Inductor, SMD, 1.5 μH/17 A

Panasonic ETQP2H1R8BFA /

TOKO FDA1055−1R5M=P3

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

1

4

1

2

1

8

1

4

1

Q1

MOSFET, N−Channel SO−8, 30 V/14.5 A

MOSFET, N−Channel SO−8, 30 V/19 A

Resistor, 100 kW 5% 0603

Resistor, 10 W 5% 0603

ON Semiconductor NTMS4700N

ON Semiconductor NTMS4107N

Panasonic ERJ3GEYJ104V

Panasonic ERJ3GEYJ100V

Panasonic ERJ3EKF5602V

Panasonic ERJ3GEYJ0R0V

Panasonic ERJ3EKF1002V

Panasonic ERJ3EKF1300V

Panasonic ERJ3EKF4301V

Panasonic ERJ3EKF3441V

Panasonic ERJ3GEYJ3R3V

Any

Q2

R1, R2, R3, R4

R5

R6

Resistor, 5.6 kW 1% 0603

Resistor, 0 W 5% 0603

R7

R8, R13

R9

Resistor, 0 W 5% 0603

Resistor, 10 kW 1% 0603

R10

Resistor, 130 W 1% 0603

R11

Resistor, 4.3 kW 1% 0603

Resistor, 3.44 kW 1% 0603

Resistor, 3.3 W 5% 0603

R12

R14

R14 is optional

TP1 − TP8

U1

Header, single pin

2−in−1 Notebook DDR Power Controller

Shunt, 100 mil jumper

ON Semiconductor NCP5214

Any

Test Pin, 0.7 mm Diameter, 12 mm Height

Any

Place at the

GND between

C11 and C8

34

35

4

1

Bumpon, 4.44 x 0.20 transparent

4−layered PCB 2500 mil x 2000 mil

3M

Any

http://onsemi.com

30

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

DFN22 6*5*0.9 MM, 0.5 P

CASE 506AF−01

ISSUE A

22

DATE 15 AUG 2005

1

A

SCALE 2:1

D

B

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINALS AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN 1 LOCATION

E

0.15

C

MILLIMETERS

DIM MIN

MAX

1.00

0.05

A

A1

A3

b

0.80

0.00

0.20 REF

TOP VIEW

SIDE VIEW

0.15

C

0.18

0.30

0.10

0.08

C

D

D2

E

E2

e

K

6.00 BSC

3.98

4.28

A

5.00 BSC

2.98

3.28

A1

(A3)

0.50 BSC

C

0.20

0.50

−−−

0.60

SEATING

PLANE

L

D2

e

GENERIC

22 X L

1

11

MARKING DIAGRAM*

1

E2

22 X K

XXXXXXXX

AWLYYWW

G

22

12

22 X b

0.10 C A

B

0.05

C

NOTE 3

XXXXX = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

BOTTOM VIEW

WL

YY

WW

G

SOLDERING FOOTPRINT

4.300

0.169

0.980

0.039

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

5.770

0.227

3.130

0.123

0.340

0.013

0.280

0.011

mm

0.500

0.020

22X

20X

ǒ

Ǔ

SCALE 8:1

inches

98AON12565D

ON SEMICONDUCTOR STANDARD

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

NEW STANDARD:

Case Outline Number:

http://onsemi.com

October, 2002 − Rev. 0

DESCRIPTION: DFN22 6*5*0.9 MM, 0.5 P

PAGE 1 OFX2XX

1

DOCUMENT NUMBER:

98AON12565D

PAGE 2 OF 2

ISSUE

REVISION

RELEASED TO PRODUCTION. REQ. BY P. CELAYA.

MODIFIED SOLDERING FOOTPRINT. REQ. BY

DATE

O

A

27 OCT 2004

15 AUG 2005

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

Case Outline Number:

August, 2005 − Rev. 01A

506AF

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCP5214MNR2G
厂家：	ONSEMI
描述：	2-in-1 Notebook DDR Power Controller 双倍数据速率开关光电二极管
文件：	总33页 (文件大小：419K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP5214MNR2G [ONSEMI]

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