NCP5322ADWG [ONSEMI]
Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC; 两相降压控制器，集成了栅极驱动器和5位DAC
| 型号： | NCP5322ADWG |
| 厂家： | 
ONSEMI |
| 描述： | Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
| 文件： | 总31页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5322A
Two−Phase Buck Controller
with Integrated Gate
Drivers and 5−Bit DAC
The NCP5322A is a second−generation, two−phase step down
controller which incorporates all control functions required to power
high performance processors and high current power supplies.
Proprietary multi−phase architecture guarantees balanced load current
distribution and reduces overall solution cost in high current
http://onsemi.com
2
applications. Enhanced V ™ control architecture provides the fastest
28
possible transient response, excellent overall regulation, and ease of
use. The NCP5322A is a second−generation PWM controller because
1
2
it optimizes transient response by combining traditional Enhanced V
SO−28L
DW SUFFIX
CASE 751F
with an internal PWM ramp and fast−feedback directly from V
to
CORE
the internal PWM comparator. These enhancements provide greater
design flexibility, facilitate use and reduce output voltage jitter.
The NCP5322A multi−phase architecture reduces output voltage
and input current ripple, allowing for a significant reduction in filter
size and inductor values with a corresponding increase in inductor
current slew rate. This approach allows a considerable reduction in
input and output capacitor requirements, as well as reducing overall
solution size and cost.
PIN CONNECTIONS AND
MARKING DIAGRAM
1
28
COMP
R
OSC
CCL
V
V
FB
V
V
DRP
CCL1
CS1
GATE(L)1
CS2
GND
GATE(H)1
Features
CS
2
REF
• Enhanced V Control Method with Internal Ramp
PWRGD
V
CCH1
• Internal PWM Ramp
V
V
V
V
V
LGND
SS
ID0
ID1
ID2
ID3
ID4
LIM
• Fast−Feedback Directly from V
CORE
V
CCL2
• 5−Bit DAC with 1.0% Accuracy
GATE(L)2
GND2
GATE(H)2
• Adjustable Output Voltage Positioning
• 4 On−Board Gate Drivers
I
REF
V
CCH2
• 200 kHz to 800 kHz Operation Set by Resistor
• Current Sensed through Buck Inductors or Sense Resistors
• Hiccup Mode Current Limit
A
WL
YY
= Assembly Location
= Wafer Lot
= Year
• Individual Current Limits for Each Phase
• On−Board Current Sense Amplifiers
• 3.3 V, 1.0 mA Reference Output
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
• 5.0 V and/or 12 V Operation
Device
Package
Shipping†
• On/Off Control (through Soft Start Pin)
• Power Good Output with Internal Delay
• Pb−Free Packages are Available
NCP5322ADW
SO−28L
26 Units/Rail
26 Units/Rail
NCP5322ADWG
SO−28L
(Pb−Free)
NCP5322ADWR2
NCP5322ADWR2G
1000 Tape & Reel
1000 Tape & Reel
SO−28L
SO−28L
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
January, 2007 − Rev. 5
NCP5322A/D
NCP5322A
L1 300 nH
C2
D1
+12 V
BAT54SLT1
+
C
D3
INPUT
1.0 mF
D2
Electrolytics
MBRA120LT3
BAT54SLT1
C1
1.0 mF
L
VCC
1.0 mF
ENABLE
R
C
Q1
0.1 mF
R3
C
AMP
FBK1
2.2 nF
6.04 k
330
Q1
Q5
C
VCC
C
2.2 nF
2N3904
1.0 mF
CMP1
C
L2 1.1 mH
FBK2
V
FB
SIG
470 pF
GND
Q2
D4
18 V
SIG
GND
C
R
OUT
DRP1
21 k
R
64.9 k
OSC
Electrolytics
COMP
R
OSC
C
VCCLx
V
V
V
CCL
FB
1.0 mF
C
CER
V
DRP
CCL1
Ceramics
Cs1
CS2
GL1
R
49.9 k
CSREF
GND1
GH1
C
0.1 mF
Q3
CS
REF
CS
REF
PWRGD
PWRGD
V
CCH1
C
CSREF
C
VCCHx
V
V
LGND
SS
ID0
ID0
0.01 mF
1.0 mF
V
V
Q3
ID1
ID1
SIG
GND
V
V
V
ID2
ID2
CCL2
L3 1.1 mH
V
V
GL2
GND2
GH2
ID3
ID3
V
V
ID4
ID4
I
LIM
Q4
SIG
REF
V
GND
CCH2
R
3.57 k
LIM1
C
0.1 mF
C
SS
0.1 mF
NCP5322A
REF
R
1.0 k
LIM2
SIG
SIG
SIG
GND
GND
GND
R
CS1
75 k−142 k
CS1
CS2
SWNODE1
SWNODE2
R
CS2
75 k−142 k
C
CS1
C
CS2
0.01 mF 0.01 mF
Recommended Components:
L1: Coiltronics P/N CTX15−14771 or T30−26 core with 3T of #16 AWG
L2: Coiltronics P/N TBD or T50−52B with 5T of #16 AWG Bifilar
C
C
: 3 × Sanyo Oscon 16SP270M (270 mF, 16 V, 4.4 A
: 10 × Rubycon 16MBZ1500M10x20 (1500 mF, 16 V, 13 mW)
, 18 mW)
RMS
INPUT
OUT
or 8 × Sanyo Oscon 4SP820M (820 mF, 4 V, 12 mW)
: 12 × Panasonic ECJ−3YB0J106K (10 mF, 6.3 V)
C
CERAMICS
Q1−Q4: ON Semiconductor NTB85N03 (28 V, 85 A)
: Murata P/N BLM21P221SG (220 W at 100 MHz)
L
VCC
Figure 1. Application Diagram, 12 V Only to 1.6 V at 45 A, 220 kHz
http://onsemi.com
2
NCP5322A
+12 V
L1 300 nH
+5.0 V
D1
+
MBRA120LT3
C
INPUT
L
VCC
Electrolytics
ENABLE
R
C
Q1
0.1 mF
C
AMP
FBK1
2.2 nF
3.40 k
Q1
C
VCC
C
2.2 nF
1.0 mF
CMP1
C
L2 825 nH
FBK2
V
FB
SIG
470 pF
GND
Q2
SIG
GND
C
R
DRP1
OUT
R
39.2 k
OSC
Electrolytics
10.7 k
COMP
R
OSC
C
VCCLx
V
V
V
CCL
FB
1.0 mF
C
CER
V
DRP
CCL1
Ceramics
Cs1
CS2
GL1
R
CSREF
33 k
GND1
GH1
CS
REF
CS
REF
C
0.1 mF
Q3
PWRGD
PWRGD
V
CCH1
C
CSREF
0.01 mF
C
1.0 mF
V
V
LGND
SS
VCCHx
ID0
ID0
V
V
ID1
Q3
ID1
SIG
GND
V
V
V
ID2
ID2
CCL2
L3 825 nH
V
V
GL2
GND2
GH2
ID3
ID3
V
V
ID4
ID4
I
LIM
Q4
SIG
REF
V
GND
CCH2
R
4.12 k
LIM1
C
0.1 mF
C
SS
0.1 mF
NCP5322A
REF
R
1.0 k
LIM2
SIG
SIG
SIG
GND
GND
GND
R
CS1
50 k−100 k
CS1
CS2
SWNODE1
SWNODE2
R
CS2
50 k−100 k
C
CS1
C
CS2
0.01 mF 0.01 mF
Recommended Components:
L1: Coiltronics P/N CTX15−14771 or T30−26 core with 3T of #16 AWG
L2: Coiltronics P/N CTX22−15401 or T50−52 with 5T of #16 AWG Bifilar
L : Murata P/N BLM21P221SG (220 W at 100 MHz)
VCC
Q1−Q4: ON Semiconductor NTB85N03 (28 V, 85 A)
Figure 2. Alternate Application Diagram, 5.0 V (with 12 V Bias) to 1.6 V at 45 A, 335 kHz
http://onsemi.com
3
NCP5322A
MAXIMUM RATINGS*
Rating
Value
Unit
Operating Junction Temperature
Lead Temperature Soldering:
150
°C
Reflow: (SMD styles only) (Note 1): Pb Devices
(Note 2): Pb−Free Devices
230 peak
260 Peak
°C
Package Thermal Resistance:
Junction−to−Case, R
15
75
°C/W
°C/W
q
JC
Junction−to−Ambient, R
q
JA
Storage Temperature Range
−65 to +150
2.0
°C
ESD Susceptibility (Human Body Model)
JEDEC Moisture Sensitivity
kV
Pb Devices
Pb−Free Devices
Level 1
Level 2
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
2. 60 second maximum above 217°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Name
V
V
I
I
SINK
MAX
MIN
SOURCE
COMP
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
6.0 V
16 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
8.0 mA
1.0 mA
1.0 mA
20 mA
1.0 mA
50 mA
V
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
N/A
FB
V
DRP
CS1, CS2
CS
REF
OSC
R
PWRGD
VID Pins
I
LIM
REF
SS
V
CCL
V
20 V
N/A
1.5 A for 1.0 ms,
CCHx
200 mA DC
V
16 V
20 V
16 V
0.3 V
0 V
−0.3 V
N/A
1.5 A for 1.0 ms,
200 mA DC
CCLx
GATE(H)x
GATE(L)x
GND1, GND2
LGND
−2.0 V for 100 ns,
−0.3 V DC
1.5 A for 1.0 ms,
200 mA DC
1.5 A for 1.0 ms,
200 mA DC
−2.0 V for 100 ns,
−0.3 V DC
1.5 A for 1.0 ms,
200 mA DC
1.5 A for 1.0 ms,
200 mA DC
−0.3 V
2.0 A for 1.0 ms,
200 mA DC
N/A
N/A
0 V
50 mA
http://onsemi.com
4
NCP5322A
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V
= V
< 20 V; 4.5 V <
CCH2
A
J
CCH1
V
= V
= V
< 14 V; C
= 3.3 nF, R
= 32.4 kW, C
= 1.0 nF, C = 0.1 mF, C = 0.1 mF,
REF SS
CCL
CCL1
CCL2
GATE
R(OSC)
COMP
DAC Code 10000 (1.45 V), C
= 1.0 mF; unless otherwise specified.)
VCC
Characteristic
Test Conditions
Min
Typ
Max
Unit
Voltage Identification DAC
Accuracy (all codes)
Measure V = COMP
1.0
%
FB
V
V
V
V
V
ID0
ID4
ID3
ID2
ID1
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Fault Mode − Output Off
1.089 1.111
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
kW
V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.25
1.114
1.139
1.163
1.188
1.213
1.238
1.262
1.287
1.312
1.337
1.361
1.386
1.411
1.436
1.460
1.485
1.510
1.535
1.559
1.584
1.609
1.634
1.658
1.683
1.708
1.733
1.757
1.782
1.807
1.832
1.00
1.136
1.162
1.187
1.212
1.237
1.263
1.288
1.313
1.338
1.364
1.389
1.414
1.439
1.465
1.490
1.515
1.540
1.566
1.591
1.616
1.641
1.667
1.692
1.717
1.742
1.768
1.793
1.818
1.843
1.869
1.50
Input Threshold
V
V
, V , V , V , V
ID3 ID2 ID1
ID4
ID0
ID0
Input Pull−up Resistance
Pull−up Voltage
, V , V , V , V
25
50
100
ID4
ID3
ID2
ID1
−
3.15
3.30
3.45
http://onsemi.com
5
NCP5322A
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V
= V
< 20 V; 4.5 V <
CCH2
A
J
CCH1
V
= V
= V
< 14 V; C
= 3.3 nF, R
= 32.4 kW, C
= 1.0 nF, C = 0.1 mF, C = 0.1 mF,
REF SS
CCL
CCL1
CCL2
GATE
R(OSC)
COMP
DAC Code 10000 (1.45 V), C
= 1.0 mF; unless otherwise specified.)
VCC
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Good Output
Power Good Fault Delay
PWRGD Low Voltage
Output Leakage Current
Lower Threshold
CS
CS
CS
= DAC to DAC 15%
60
−
120
0.25
0.1
240
0.40
10
ms
V
REF
REF
REF
= 1.0 V, I
= 4.0 mA
PWRGD
= 1.45 V, PWRGD = 5.5 V
−
mA
%
%
−
−
−15
9.0
−12
12
−9.0
15
Upper Threshold
Voltage Feedback Error Amplifier
Bias Current
V
9.0
15
10.3
30
11.5
60
mA
mA
1.0 V < V < 1.9 V. Note 3.
FB
FB
COMP Source Current
COMP Sink Current
COMP Clamp Voltage
COMP = 0.5 V to 2.0 V;
V
= 1.8 V; DAC = 00000
FB
15
−
30
−
60
mA
COMP = 0.5 V to 2.0 V;
= 1.9 V; DAC = 00000
V
FB
SS = 0.25 V to 2.5 V; V = LGND;
SS
V
FB
Measure COMP
Voltage
COMP Max Voltage
COMP Min Voltage
Transconductance
2.4
−
2.7
0.1
32
−
0.2
−
V
V
COMP Open; V = 1.8 V; DAC = 00000
FB
COMP Open; V = 1.9 V; DAC = 00000
FB
−
mmho
−10 mA < I
< +10 mA
COMP
Output Impedance
Open Loop DC Gain
Unity Gain Bandwidth
−
−
60
−
2.5
90
−
−
−
MW
dB
Note 4.
400
kHz
0.01 mF COMP Capacitor
−
−
70
−
dB
PSRR @ 1.0 kHz
Soft Start
Soft Start Charge Current
Soft Start Discharge Current
Hiccup Mode Charge/Discharge Ratio
Soft Start Clamp Voltage
Soft Start Discharge Threshold Voltage
PWM Comparators
0.2 V ≤ SS ≤ 3.0 V
15
4.0
30
7.5
50
13
mA
mA
−
0.2 V ≤ SS ≤ 3.0 V
−
−
−
3.0
4.0
−
3.3
4.0
4.2
0.34
V
0.20
0.27
V
Minimum Pulse Width
CS1 = CS2 = CS
−
350
0.4
475
0.5
ns
V
REF
Channel Start Up Offset
0.3
V(CS1) = V(CS2) = V(V ) = V(CS
) = 0 V;
REF
FB
Measure V(COMP) when GATE(H)1,
GATE(H)2, switch high
GATE(H) and GATE(L)
High Voltage (AC)
Measure V
− GATE(L) or
−
0
1.0
V
CCLX
X
V
− GATE(H) . Note 4.
X
CCHX
Low Voltage (AC)
Measure GATE(L)
GATE(H) . Note 4.
−
−
0
0.5
80
V
X or
X
Rise Time GATE(H)
1.0 V < GATE < 8.0 V; V
= 10 V
CCHX
35
ns
X
3. The V Bias Current changes with the value of R
per Figure 5.
OSC
FB
4. Guaranteed by design. Not tested in production.
http://onsemi.com
6
NCP5322A
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V
= V
< 20 V; 4.5 V <
CCH2
A
J
CCH1
V
= V
= V
< 14 V; C
= 3.3 nF, R
= 32.4 kW, C
= 1.0 nF, C = 0.1 mF, C = 0.1 mF,
REF SS
CCL
CCL1
CCL2
GATE
R(OSC)
COMP
DAC Code 10000 (1.45 V), C
= 1.0 mF; unless otherwise specified.)
VCC
Characteristic
Test Conditions
Min
Typ
Max
Unit
GATE(H) and GATE(L)
Rise Time GATE(L)
1.0 V < GATE < 8.0 V; V
8.0 V > GATE > 1.0 V; V
8.0 V > GATE > 1.0 V; V
= 10 V
−
−
35
35
35
65
65
1.2
80
80
ns
ns
ns
ns
ns
V
X
CCLX
CCHX
CCLX
Fall Time GATE(H)
= 10 V
= 10 V
X
Fall Time GATE(L)
−
80
X
GATE(H)x to GATE(L)x Delay
GATE(L)x to GATE(H)x Delay
GATE Pull−Down
GATE(H) < 2.0 V, GATE(L) > 2.0 V
30
30
−
110
110
1.6
X
X
GATE(L) < 2.0 V, GATE(H) > 2.0 V
X
X
Force 100 mA into GATE with no power applied
to V and V = 2.0 V.
CCHX
CCLX
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
Measure any phase (R
Measure any phase (R
Measure any phase (R
= 32.4 k)
340
150
600
−
400
200
800
1.0
460
250
1000
−
kHz
kHz
kHz
V
OSC
OSC
OSC
= 63.4 k). Note 5.
= 16.2 k). Note 5.
R
OSC
Voltage
−
Phase Delay
−
165
180
195
deg
Adaptive Voltage Positioning
V
Output Voltage to DAC
CS1 = CS2 = CS , V = COMP
REF FB
−15
−
15
mV
DRP
OUT
Offset
Measure V
− COMP
DRP
V
Operating Voltage Range
Measure V
− GND, Note 5.
DRP
−
−
2.3
V
DRP
Maximum V
Voltage
(CS1 = CS2) − CS
= 50 mV,
REF
260
330
400
mV
DRP
V
= COMP, Measure V
− COMP
DRP
FB
Current Sense Amp to V
Gain
−
2.6
3.3
4.0
V/V
DRP
Current Sensing and Sharing
CS1−CS2 Input Bias Current
V(CSx) = V(CS
V(CSx) = V(CS
) = 0 V
) = 0 V
−
−
0.1
0.3
3.5
−
2.0
4.0
3.9
5.0
mA
mA
REF
CS
Input Bias Current
−
REF
REF
Current Sense Amplifier Gain
3.15
−5.0
V/V
mV
Current Sense Amp Mismatch (The
Sum of Gain and Offset Errors.)
0 ≤ (CSx − CS
) ≤ 50 mV. Note 5.
REF
Current Sense Input to I
Gain
0.25 V < I
< 1.00 V
LIM
5.5
4.0
−
6.75
10
8.5
26
V/V
mV/ms
V
LIM
Current Limit Filter Slew Rate
−
I
I
Operating Voltage Range
Bias Current
Note 5.
−
1.3
1.0
135
LIM
LIM
0 < I
< 1.0 V
−
0.1
105
mA
LIM
Single Phase Pulse−by−Pulse
Current Limit
Measure V(CSx) − V(CS
Pulse−by−Pulse Limit
) that Trips
REF
90
mV
Current Share Amplifier Bandwidth
Note 5.
1.0
−
−
MHz
General Electrical Specifications
V
V
Operating Current
V
V
= COMP (no switching)
−
−
22
26
mA
mA
CCL
FB
FB
or V
Operating Current
CCL2
= COMP (no switching)
4.5
5.5
CCL1
5. Guaranteed by design. Not tested in production.
http://onsemi.com
7
NCP5322A
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V
= V
< 20 V; 4.5 V <
CCH2
A
J
CCH1
V
= V
= V
< 14 V; C
= 3.3 nF, R
= 32.4 kW, C
= 1.0 nF, C = 0.1 mF, C = 0.1 mF,
REF SS
CCL
CCL1
CCL2
GATE
R(OSC)
COMP
DAC Code 10000 (1.45 V), C
= 1.0 mF; unless otherwise specified.)
VCC
Characteristic
Test Conditions
Min
Typ
Max
Unit
General Electrical Specifications
V
V
V
V
V
V
V
or V
Operating Current
V = COMP (no switching)
FB
−
3.2
4.3
4.5
4.5
mA
V
CCH1
CCH2
Start Threshold
Stop Threshold
Hysteresis
GATEs switching, Soft Start charging
4.05
3.75
100
1.8
CCL
GATEs stop switching, Soft Start discharging
GATEs not switching, Soft Start not charging
GATEs switching, Soft Start charging
4.1
4.35
300
2.2
V
CCL
200
2.0
mV
V
CCL
Start Threshold
Stop Threshold
Hysteresis
CCH1
CCH1
CCH1
GATEs stop switching, Soft Start discharging
GATEs not switching, Soft Start not charging
1.55
100
1.75
200
1.90
300
V
mV
Reference Output
Output Voltage
V
3.2
−
3.3
3.4
−
V
0 mA < I(V
) < 1.0 mA
REF
REF
Internal Ramp
Ramp Height @ 50% PWM
Duty−Cycle
CS1 = CS2 = CS
.
125
mV
REF
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−28L
PIN SYMBOL
FUNCTION
1
COMP
Output of the error amplifier and input for the PWM
comparators.
2
3
V
Voltage Feedback Pin. To use Adaptive Voltage Positioning
(AVP) select an offset voltage at light load and connect a
FB
resistor between V and V
. The input current of the V
FB
OUT
FB
pin and the resistor value determine output voltage offset for
zero output current. Short V to V for no AVP.
FB
OUT
V
Current sense output for AVP. The offset of this pin above the
DAC voltage is proportional to the output current. Connect a
DRP
resistor from this pin to V to set amount AVP or leave this
FB
pin open for no AVP. This pin’s maximum working voltage is
2.3 Vdc.
4−5
6
CS1−CS2
Current sense inputs. Connect current sense network for the
corresponding phase to each input. The input voltages to
these pins must be kept within 105 mV of CS
by−pulse current limit will be tripped.
or pulse−
REF
CS
Reference for Current Sense Amplifiers, input to the Power
Good comparators, and fast feedback connection to the
PWM comparator. To balance input offset voltages between
the inverting and noninverting inputs of the Current Sense
REF
Amplifiers, connect a resistor between CS
and the output
REF
voltage. The value should be 1/3 of the value of the resistors
connected to the CSx pins. The input voltage to this pin must
not exceed the maximum DAC (VID) setting by more than
100 mV or the internal PWM comparator may saturate.
7
PWRGD
Power Good Output. Open collector output goes low when
CS
(V
) is out of regulation.
OUT
REF
8−12
V
−V
Voltage ID DAC inputs. These pins are internally pulled up to
3.3 V if left open.
ID4
ID0
http://onsemi.com
8
NCP5322A
PACKAGE PIN DESCRIPTION (continued)
PACKAGE PIN #
SO−28L
PIN SYMBOL
FUNCTION
13
I
Sets threshold for current limit. Connect to reference through
a resistive divider. This pin’s maximum working voltage is
1.3 Vdc.
LIM
Reference output. Decouple with 0.1 mF to LGND.
Power for GATE(H)2.
14
15
16
17
18
19
20
REF
V
CCH2
GATE(H)2
High side driver #2.
GND2
Return for #2 drivers.
GATE(L)2
Low side driver #2.
V
Power for GATE(L)2.
CCL2
SS
Soft Start capacitor pin. The Soft Start capacitor controls
both Soft Start time and hiccup mode frequency. The COMP
pin is clamped below Soft Start during Start−Up and hiccup
mode.
21
22
LGND
Return for internal control circuits and IC substrate connection.
V
Power for GATE(H)1. UVLO Sense for High Side Driver sup-
ply connects to this pin.
CCH1
23
24
25
26
27
GATE(H)1
GND1
High side driver #1.
Return #1 drivers.
Low side driver #1.
Power for GATE(L)1.
GATE(L)1
V
CCL1
V
Power for internal control circuits. UVLO Sense for Logic
connects to this pin.
CCL
28
R
OSC
A resistor from this pin to ground sets operating frequency
and V bias current.
FB
http://onsemi.com
9
NCP5322A
N o n − O v e r l a p
N o n − O v e r l a p
D A C 5 − B i t
Figure 3. Block Diagram
http://onsemi.com
10
NCP5322A
TYPICAL PERFORMANCE CHARACTERISTICS
900
800
700
600
500
400
25
20
15
10
5
300
200
100
0
10
20
30
40
50
60
70
10
20
30
40
50
60
70
80
R
OSC
Value (kW)
R
OSC
Value, kW
Figure 4. Oscillator Frequency vs. ROSC Value
Figure 5. VFB Bias Current vs. ROSC Value
120
120
100
100
80
60
40
20
0
80
60
40
20
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Load Capacitance, nF
Load Capacitance, nF
Figure 6. GATE(H) Rise Time vs. Load Capacitance
Measured from 1.0 V to 4.0 V with VCC at 5.0 V
Figure 7. GATE(H) Fall Time vs. Load Capacitance
Measured from 4.0 V to 1.0 V with VCC at 5.0 V
120
100
120
100
80
60
40
80
60
40
20
0
20
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Load Capacitance, nF
Load Capacitance, nF
Figure 8. GATE(L) Rise Time vs. Load Capacitance
Measured from 1.0 V to 4.0 V with VCC at 5.0 V
Figure 9. GATE(L) Fall Time vs. Load Capacitance
Measured from 4.0 V to 1.0 V with VCC at 5.0 V
http://onsemi.com
11
NCP5322A
APPLICATIONS INFORMATION
Overview
currents in individual phases. Each phase is delayed 180°
from the previous phase. Normally, GATE(H) transitions to
a high voltage at the beginning of each oscillator cycle.
Inductor current ramps up until the combination of the
current sense signal, the internal ramp and the output voltage
ripple trip the PWM comparator and bring GATE(H) low.
Once GATE(H) goes low, it will remain low until the
beginning of the next oscillator cycle. While GATE(H) is
The NCP5322A DC/DC controller from ON
Semiconductor was developed using the Enhanced V
topology to meet requirements of low voltage, high current
loads with fast transient requirements. Enhanced V combines
the original V topology with peak current−mode control for
fast transient response and current sensing capability. The
addition of an internal PWM ramp and implementation of
2
2
2
2
fast−feedback directly from V
has improved transient
high, the Enhanced V loop will respond to line and load
CORE
response and simplified design. The NCP5322A includes
Power Good (PWRGD) and MOSFET gate drivers to
provide a “fully integrated solution” to simplify design,
minimize circuit board area, and reduce overall system cost.
Two advantages of a multi−phase converter over a
single−phase converter are current sharing and increased
apparent output frequency. Current sharing allows the
designer to use less inductance in each phase than would be
required in a single−phase converter. The smaller inductor
will produce larger ripple currents but the total per phase
power dissipation is reduced because the RMS current is lower.
Transient response is improved because the control loop will
measure and adjust the current faster in a smaller output
inductor. Increased apparent output frequency is desirable
because the off time and the ripple voltage of the two−phase
converter will be less than that of a single−phase converter.
variations. On the other hand, once GATE(H) is low, the loop
can not respond until the beginning of the next PWM cycle.
Therefore, constant frequency Enhanced V will typically
2
respond to disturbances within the off−time of the converter.
2
The Enhanced V architecture measures and adjusts the
output current in each phase. An additional input (CSn) for
2
inductor current information has been added to the V loop
for each phase as shown in Figure 10. The triangular inductor
current is measured differentially across RS, amplified by
CSA and summed with the Channel Startup Offset, the
Internal Ramp, and the Output Voltage at the non−inverting
input of the PWM comparator. The purpose of the Internal
Ramp is to compensate for propagation delays in the
NCP5322A. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation, and PWM duty cycles
above 50% without external slope compensation. As the
sum of the inductor current and the internal ramp increase,
the voltage on the positive pin of the PWM comparator rises
and terminates the PWM cycle. If the inductor starts a cycle
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The NCP5322A provides a
Fixed Frequency Multi−Phase Control
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
CSn input for each phase, but the CS
and COMP inputs
REF
are common to all phases. Current sharing is accomplished
by referencing all phases to the same CS and COMP
REF
pins, so that a phase with a larger current signal will turn off
earlier than a phase with a smaller current signal.
The NCP5322A controller uses two−phase, fixed
2
frequency, Enhanced V architecture to measure and control
http://onsemi.com
12
NCP5322A
n = 1 or 2
CSn
Ln
SWNODE
RLn
+
CSA
COn
RSn
Internal Ramp
CS
V
REF
− +
To F/F
Reset
V
“Fast−Feedback”
Connection
OUT
+
Channel
Start−Up
Offset
(V
)
CORE
+
FB
PWM
COMP
E.A.
+
DAC
Out
COMP
+
Figure 10. Enhanced V2 Control Employing Resistive Current Sensing and Additional Internal Ramp
2
Enhanced V responds to disturbances in V
by
external steady−state ramp at 0 A, G
is the Current Sense
CORE
CSA
employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in 1−2 PWM cycles. Fast voltage feedback is
Amplifier Gain (nominally 3.5 V/V), and the Channel
Startup Offset is typically 0.40 V. The magnitude of the
Ext_Ramp can be calculated from:
Ext_Ramp + D @ (V * V
IN OUT
)ń(R
CSn
@ C )
@ f
CSn SW
For example, if V
at 0 A is set to 1.630 V with AVP
OUT
implemented by a direct connection from V
to the
and the input voltage is 12.0 V, the duty cycle (D) will be
CORE
non−inverting pin of the PWM comparator via the
summation with the inductor current, internal ramp, and
Offset. A rapid increase in load current will produce a
1.630/12.0 or 13.6%. Int_Ramp will be 125 mV • 13.6/50 =
34 mV. Realistic values for R , C
and f are 60 kW,
CSn CSn
SW
0.01 mF, and 220 kHz − using these and the previously
mentioned formula, Ext_Ramp will be 10.6 mV.
negative offset at V
and at the output of the summer.
CORE
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle in 1 PWM cycle.
V
+ 1.630 V ) 0.40 V ) 34 mV
) 3.5 VńV @ 10.6 mVń2
+ 2.083 Vdc.
COMP
As shown in Figure 10, an internal ramp (nominally 125 mV
at a 50% duty cycle) is added to the inductor current ramp
at the positive terminal of the PWM comparator. This
additional ramp compensates for propagation time delays
from the current sense amplifier (CSA), the PWM
comparator, and the MOSFET gate drivers. As a result, the
minimum ON time of the controller is reduced and lower
duty cycles may be achieved at higher frequencies. Also, the
additional ramp reduces the reliance on the inductor current
ramp and allows greater flexibility when choosing the output
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage.
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as:
DV + R @ G
CSA
@ DI .
OUT
S
inductor and the R
C
(n = 1 or 2) time constant of the
The single−phase power stage output impedance is:
CSn CSn
feedback components from V
to the CSn pin.
CORE
Single Stage Impedance+DV +R @ G
ńDI
OUT OUT S CSA
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be:
The multi−phase power stage output impedance is the
single−phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few
microseconds of a transient before the feedback loop has
repositioned the COMP pin.
V
+ V
OUT
@ 0 A ) Channel_Startup_Offset
@ Ext_Rampń2
COMP
) Int_Ramp ) G
CSA
The peak output current can be calculated from:
Int_Ramp is the “partial” internal ramp value at the
corresponding duty cycle, Ext_Ramp is the peak−to−peak
http://onsemi.com
13
NCP5322A
I
OUT,PEAK + (V
COMP
* V
OUT
* Offset)ń(R @ G )
CSA
S
SWNODE
Figure 11 shows the step response of the COMP pin at a
fixed level. Before T1 the converter is in normal steady state
operation. The inductor current provides a portion of the
PWM ramp through the Current Sense Amplifier. The PWM
cycle ends when the sum of the current ramp, the “partial”
internal ramp voltage signal and Offset exceed the level of
the COMP pin. At T1 the output current increases and the
output voltage sags. The next PWM cycle begins and the
cycle continues longer than previously while the current
signal increases enough to make up for the lower voltage at
V
(V
)
OUT
FB
Internal Ramp
CSA Out w/
Exaggerated
Delays
the V pin and the cycle ends at T2. After T2 the output
FB
voltage remains lower than at light load and the average
current signal level (CSn output) is raised so that the sum of
the current and voltage signal is the same as with the original
load. In a closed loop system the COMP pin would move
higher to restore the output voltage to the original level.
COMP−Offset
CSA Out + Ramp + CS
REF
T1
T2
Figure 11. Open Loop Operation
n = 1 or 2
CSn
R
CSn
SWNODE
+
CSA
COn
Ln
C
CSn
Internal Ramp
RLn
CS
V
REF
− +
To F/F
Reset
V
“Fast−Feedback”
Connection
OUT
+
Channel
Start−Up
Offset
(V
)
CORE
+
FB
PWM
COMP
E.A.
+
DAC
Out
COMP
+
Figure 12. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp
Inductive Current Sensing
considered when setting the I
threshold. If a more
LIM
For lossless sensing, current can be sensed across the
inductor as shown in Figure 12. In the diagram, L is the
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 10.
output inductance and R is the inherent inductor resistance.
L
To compensate the current sense signal, the values of R
CSn
Current Sharing Accuracy
and C
are chosen so that L/R = R
• C . If this
CSn CSn
CSn
L
Printed circuit board (PCB) traces that carry inductor
current can be used as part of the current sense resistance
depending on where the current sense signal is picked off.
For accurate current sharing, the current sense inputs should
sense the current at relatively the same point for each phase
criteria is met, the current sense signal will be the same shape
as the inductor current and the voltage signal at CSn will
represent the instantaneous value of inductor current. Also,
the circuit can be analyzed as if a sense resistor of value R
L
was used as a sense resistor (R ).
S
and the connection to the CS
pin should be made so that
REF
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
no phase is favored. In some cases, especially with inductive
sensing, resistance of the PCB can be useful for increasing
the current sense resistance. The total current sense
resistance used for calculations must include any PCB trace
resistance between the CSn input and the CS
carries inductor current.
input that
REF
http://onsemi.com
14
NCP5322A
Current Sense Amplifier (CSA) input mismatch and the
value of the current sense component will determine the
accuracy of the current sharing between phases. The worst
case Current Sense Amplifier input mismatch is 5.0 mV
and will typically be within 3.0 mV. The difference in peak
currents between phases will be the CSA input mismatch
divided by the current sense resistance. If all current sense
components are of equal resistance a 3.0 mV mismatch with
a 2.0 mW sense resistance will produce a 1.5 A difference in
current between phases.
External Ramp Size and Current Sensing
The internal ramp allows flexibility of current sense time
constant. Typically, the current sense R
• C
time
CSn
CSn
constant (n = 1 or 2) should be equal to or slower than the
inductor’s time constant. If RC is chosen to be smaller
(faster) than L/R , the AC or transient portion of the current
L
sensing signal will be scaled larger than the DC portion. This
will provide a larger steady state ramp, but circuit
performance will be affected and must be evaluated
carefully. The current signal will overshoot during transients
Figure 13. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50 ms/div)
and settle at the rate determined by R
• C . It will
CSn
CSn
Current Limit
eventually settle to the correct DC level, but the error will
decay with the time constant of R • C . If this error is
Two levels of overcurrent protection are provided. First,
if the voltage on the Current Sense pins (either CS1 or CS2)
CSn
CSn
excessive it will effect transient response, adaptive
positioning and current limit. During a positive current
transient, the COMP pin will be required to undershoot in
response to the current signal in order to maintain the output
exceeds CS
by more than a fixed threshold (Single Pulse
REF
Current Limit), the PWM comparator is turned off. This
provides fast peak current protection for individual phases.
Second, the individual phase currents are summed and
low−pass filtered to compare an averaged current signal to
voltage. Similarly, the V
signal will overshoot which
DRP
will produce too much transient droop in the output voltage.
Single phase overcurrent will trip earlier than it would if
compensated correctly and hiccup mode current limit will
have a lower threshold for fast rise step loads than for slowly
rising output currents.
a user adjustable voltage on the I
pin. If the I
voltage
LIM
LIM
is exceeded, the fault latch trips and the Soft Start capacitor
is discharged until the Soft−Start pin reaches 0.27 V. Then
Soft Start begins. The converter will continue to operate in
a low current hiccup mode until the fault condition is
corrected.
The waveforms in Figure 13 show a simulation of the
current sense signal and the actual inductor current during a
Overvoltage Protection
positive step in load current with values of L = 500 nH, R
L
Overvoltage protection (OVP) is provided as a result of
the normal operation of the Enhanced V control topology
= 1.6 mW, R
signal compensation the value of R
= 20 k and C
= 0.01 mF. For ideal current
CSn
CSn
2
should be 31 kW. Due
CSn
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 400 ns, causing the top
MOSFET to shut OFF and the synchronous (lower)
MOSFET to turn ON. This results in a “crowbar” action to
clamp the output voltage and prevent damage to the load.
The regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low.
to the faster than ideal RC time constant there is an overshoot
of 50% and the overshoot decays with a 200 ms time
constant. With this compensation the I
pin threshold
LIM
must be set more than 50% above the full load current to
avoid triggering hiccup mode during a large output load
step.
Transient Response and Adaptive Positioning
For applications with fast transient currents the output filter
is frequently sized larger than ripple currents require in order
to reduce voltage excursions during load transients. Adaptive
voltage positioning can reduce peak−to−peak output voltage
deviations during load transients and allow for a smaller
output filter. The output voltage can be set higher than
nominal at light loads to reduce output voltage sag when the
load current is applied. Similarly, the output voltage can be set
lower than nominal during heavy loads to reduce overshoot
http://onsemi.com
15
NCP5322A
when the load current is removed. For low current
error amplifier. Values less than 1 nF may cause oscillations
of the COMP voltage. These oscillations will increase the
output voltage jitter.
applications a droop resistor can provide fast accurate adaptive
positioning. However, at high currents the loss in a droop
resistor becomes excessive. For example; in a 50 A converter
a 1 mW resistor to provide a 50 mV change in output voltage
between no load and full load would dissipate 2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond to changes in load current.
Figure 14 shows how adaptive positioning works. The
waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
The capacitor (C
) between the COMP pin and the
AMP
inverting error amplifier input (the V pin) and the parallel
FB
combination of the resistors R
and R
determine the
FBK1
DRP1
bandwidth of the error amplifier. The gain of the error
amplifier crosses 0 dB at a high enough frequency to give a
quick transient response, but well below the switching
frequency to minimize ripple and noise on the COMP pin.
A capacitor in parallel with the V resistor (C
) adds
FB
FBK2
a zero to boost phase near the crossover frequency to
improve loop stability.
Setting−up and tuning the error amplifier is a three step
process. First, the no−load and full−load adaptive voltage
positioning (AVP) are set using R
and R
,
FBK1
DRP1
respectively. Second, the current sense time constant and
error amplifier gain are adjusted with R and C while
CSn
AMP
monitoring V
during transient loading. Lastly, the
OUT
peak−to−peakvoltage ripple on the COMP pin is examined
when the converter is fully loaded to insure low output
voltage jitter. The details of this process are covered in the
Design Procedure section.
Normal
Undervoltage Lockout (UVLO)
FastAdaptive Positioning
SlowAdaptive Positioning
Limits
The controller has undervoltage lockout functions
connected to two pins. One, intended for the logic and
low−side drivers, with approximately a 4.2 V turn−on
Figure 14. Adaptive Positioning
threshold is connected to the V
pin. A second, for the
CCL
high side drivers, with approximately a 1.875 V threshold,
is connected to the V pin.
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to the application diagram in Figure 1). To set the no−load
positioning, a resistor is placed between the output voltage
CCH1
The UVLO threshold for the high side drivers varies with
the part type. In many applications this function will be
disabled or will only check that the applicable supply is on
− not that is at a high enough voltage to run the converter. See
individual datasheets for more information on UVLO.
and V pin. The V bias current will develop a voltage
FB
FB
across the resistor to adjust the no−load output voltage. The
bias current is dependent on the value of R as shown
V
FB
OSC
in the datasheet.
During no load conditions the V
Soft Start Enable, and Hiccup Mode
pin is at the same
DRP
A capacitor between the Soft Start pin and GND controls
Soft Start and Hiccup mode slopes. A 0.1 mF capacitor with
the 30 mA charge current will allow the output to ramp up at
0.3 V/ms or 1.6 V in 5.3 ms at start−up.
When a fault is detected due to an overcurrent condition
the converter will enter a low duty cycle hiccup mode.
During hiccup mode the converter will not switch from the
time a fault is detected until the Soft Start capacitor has
discharged below the Soft Start Discharge Threshold and
then charged back up above the Channel Start Up Offset.
The Soft Start pin will disable the converter when pulled
below the maximum Soft Start Discharge Threshold
(nominally 0.27 V).
voltage as the V pin, so none of the V bias current flows
FB
FB
through the V
resistor. When output current increases
DRP
the V
pin increases proportionally and the V
pin
DRP
DRP
current offsets the V bias current and causes the output
voltage to decrease.
FB
The response during the first few microseconds of a load
transient are controlled primarily by power stage output
impedance and the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
current signal size is too large or the error amp too slow there
will be a long transition to the final voltage after a transient.
This will be most apparent with lower capacitance output
filters.
Power Good (PWRGD)
The open−collector Power Good (PWRGD) pin is driven
Error Amp Compensation & Tuning
The transconductance error amplifier requires a capacitor
by a “window−comparator” monitoring V
. This
CORE
comparator will transition HIGH if V
is within 12%
CORE
(C
CMP1
in the Applications Diagram) between the COMP
of the nominal VID setting. After a 120 ms delay, the
pin and GND. This capacitor stabilizes the transconductance
http://onsemi.com
16
NCP5322A
comparators output will saturate the open−collector output
transistor and the PWRGD pin will be pulled LOW.
and GATE traces, away from the R
resistor.
pin and
OSC
6. Place the Soft Start capacitor (C ) near the Soft
SS
Layout Guidelines
Start pin.
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multi−layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to route the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
The current sense signals are typically tens of milli−volts.
Noise pick−up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as the switch node and gate drive signals. If the
current signals are taken from a location other than directly
at the inductor any additional resistance between the
pick−off point and the inductor appears as part of the
inherent inductor resistances and should be considered in
design calculations. The capacitors for the current feedback
networks should be placed as close to the current sense pins
as practical. After placing the NCP5322A control IC, follow
these guidelines to optimize the layout and routing:
1. Place the 1 mF power supply bypass (ceramic)
7. Place the MOSFETs and output inductors to reduce
the size of the noisy SWNODEs. There is a trade−
off between reducing the size of the SWNODEs
for noise reduction and providing adequate
heat−sinking for the synchronous MOSFETs.
8. Place the input inductor and input capacitor(s) near
the Drain of the control (upper) MOSFETs. There
is a trade−off between reducing the size of this
node to save board area and providing adequate
heat−sinking for the control MOSFETs.
9. Place the output capacitors (electrolytic and ceramic)
close to the processor socket or output connector.
10. The trace from the SWNODEs to the current sense
components (R , R ) will be very noisy.
CS1 CS2
Route this away from more sensitive, low−level
traces. The Ground layer can be used to help
isolate this trace.
11. The Gate traces are very noisy. Route these away
from more sensitive, low−level traces. Keep each
Gate signal on one layer and insure that there is an
uninterrupted return path directly below the Gate
trace. The Ground layer can be used to help isolate
these traces.
12. Don’t “daisy chain” connections to Ground from
one via. Allow each connection to Ground to have
its own via as close to the component as possible.
13. Use a slot in the ground plane from the bulk output
capacitors back to the input power connector to
prevent high currents from flowing beneath the
control IC. This slot should extend length−wise
under the control IC and separate the connections
to “signal ground” and “power ground.” Examples
of signal ground include the capacitors at COMP,
CS , Soft−Start (SS), V
, and REF, the
REF
CCL
resistors at R
and I , and the LGND pin to
OSC
LIM
capacitors close to their associated pins: V
,
).
the controller. Examples of power ground include
the capacitors to V (and/or V ) and
CCL
V
CCH1
(and/or V
), V
(and/or V
CCH2
CCL1
CCL2
CCH1
CCH2
2. Place the MOSFETs to minimize the length of the
Gate traces. Orient the MOSFETs such that the
Drain connections are away from the controller and
the Gate connections are closest to the controller.
3. Place the components associated with the internal
V
(and/or V
), the Source of the
CCL1
CCL2
synchronous MOSFET, and the GND1 and GND2
pins of the controller.
14. The CS
sense point should be equidistant
REF
between the output inductors to equalize the PCB
resistance added to the current sense paths. This
will insure acceptable current sharing. Also, route
error amplifier (R
, C
, C
, R
,
FBK1 FBK2 AMP CMP1
C
, R
) to minimize the trace lengths to
CMP1 DRP1
the pins V , V
and COMP.
the CS
connection away from noisy traces such
FB
DRP
REF
4. Place the current sense components (R , R
,
as the SWNODEs and GATE traces. If noise from
the SWNODEs or GATE signals capacitively
CS1 CS2
C
, C , R
, C
) near the CS1, CS2,
CS1 CS2 CSREF CSREF
and CS
pins.
couples to the CS
trace the external ramps will
REF
REF
5. Place the frequency setting resistor (R
) close to
be very noisy and voltage jitter will result.
OSC
the R
pin. The R
pin is very sensitive to
15. Ideally, the SWNODEs are exactly the same shape
OSC
OSC
noise. Route noisy traces, such as the SWNODEs
and the current sense points (connections to R
CS1
http://onsemi.com
17
NCP5322A
and R ) are made at identical locations to
value will result in very large ripple currents in the power
components (MOSFETs, capacitors, etc) resulting in
increased dissipation and lower converter efficiency. Also,
increased ripple currents will force the designer to use
higher rated MOSFETs, oversize the thermal solution, and
use more, higher rated input and output capacitors − the
converter cost will be adversely effected.
CS2
equalize the PCB resistance added to the current
sense paths. This will help to insure acceptable
current sharing.
16. Place the 0.1 mF ceramic capacitors, C and C
,
Q1
Q2
close to the drains of the MOSFETs Q1 and Q2,
respectively.
One method of calculating an output inductor value is to
size the inductor to produce a specified maximum ripple
current in the inductor. Lower ripple currents will result in
less core and MOSFET losses and higher converter
efficiency. Equation 3 may be used to calculate the minimum
inductor value to produce a given maximum ripple current
(α) per phase. The inductor value calculated by this equation
is a minimum because values less than this will produce more
ripple current than desired. Conversely, higher inductor
values will result in less than the maximum ripple current.
Design Procedure
1. Output Capacitor Selection
The output capacitors filter the current from the output
inductor and provide a low impedance for transient load
current changes. Typically, microprocessor applications
will require both bulk (electrolytic, tantalum) and low
impedance, high frequency (ceramic) types of capacitors.
The bulk capacitors provide “hold up” during transient
loading. The low impedance capacitors reduce steady−state
ripple and bypass the bulk capacitance when the output
current changes very quickly. The microprocessor
manufacturers usually specify a minimum number of
ceramic capacitors. The designer must determine the
number of bulk capacitors.
(3)
(V * V
) @ V
@ V @ f )
IN SW
IN
OUT OUT
Lo
MIN
+
(a @ I
O,MAX
α is the ripple current as a percentage of the maximum
output current per phase (α = 0.15 for 15%, α = 0.25 for
25%, etc). If the minimum inductor value is used, the
inductor current will swing α% about its value at the center
(1/2 the DC output current for a two−phase converter).
Therefore, for a two−phase converter, the inductor must be
designed or selected such that it will not saturate with a peak
Choose the number of bulk output capacitors to meet the
peak transient requirements. The formula below can be used
to provide a starting point for the minimum number of bulk
capacitors (N
):
OUT,MIN
(1)
current of (1 + α) • I
/2.
DI
O,MAX
O,MAX
DV
N
+ ESR per capacitor @
OUT,MIN
The maximum inductor value is limited by the transient
response of the converter. If the converter is to have a fast
transient response then the inductor should be made as small
as possible. If the inductor is too large its current will change
too slowly, the output voltage will droop excessively, more
bulk capacitors will be required, and the converter cost will
be increased. For a given inductor value, its interesting to
determine the times required to increase or decrease the
current.
O,MAX
In reality, both the ESR and ESL of the bulk capacitors
determine the voltage change during a load transient
according to:
(2)
@ ESR
O,MAX
DV
+ (DI
ńDt) @ ESL ) DI
O,MAX
O,MAX
Unfortunately, capacitor manufacturers do not specify the
ESL of their components and the inductance added by the
PCB traces is highly dependent on the layout and routing.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk capacitors and perform
transient testing or careful modeling/simulation to
determine the final number of bulk capacitors.
For increasing current:
(3.1)
Dt
+ Lo @ DI ń(V * V )
IN OUT
INC
O
For decreasing current:
(3.2)
Dt
+ Lo @ DI ń(V )
OUT
DEC
O
2. Output Inductor Selection
For typical processor applications with output voltages
less than half the input voltage, the current will be increased
much more quickly than it can be decreased. It may be more
difficult for the converter to stay within the regulation limits
when the load is removed than when it is applied − excessive
overshoot may result.
The output inductor may be the most critical component
in the converter because it will directly effect the choice of
other components and dictate both the steady−state and
transient performance of the converter. When selecting an
inductor the designer must consider factors such as DC
current, peak current, output voltage ripple, core material,
magnetic saturation, temperature, physical size, and cost
(usually the primary concern).
In general, the output inductance value should be as low
and physically small as possible to provide the best transient
response and minimum cost. If a large inductance value is
used, the converter will not respond quickly to rapid changes
in the load current. On the other hand, too low an inductance
The output voltage ripple can be calculated using the
output inductor value derived in this Section (Lo
), the
MIN
number of output capacitors (N ) and the per
OUT,MIN
capacitor ESR determined in the previous Section:
V
+ (ESR per cap ń N
) @
OUT,MIN
(4)
OUT,P−P
NJ
Nj
@ f )
MIN SW
(V * #Phases @ V
) @ D ń (Lo
OUT
IN
http://onsemi.com
18
NCP5322A
This formula assumes steady−state conditions with no
more than one phase on at any time. The second term in
Equation 4 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the two individual phase currents that are
180 degrees out−of−phase. As the inductor current in one
phase ramps upward, current in the other phase ramps
downward and provides a canceling of currents during part
of the switching cycle. Therefore, the total output ripple
current and voltage are reduced in a multi−phase converter.
DI is the peak−to−peak ripple current in the output
Lo
inductor of value Lo:
(10)
DI + (V * V ) @ Dń(Lo @ f
Lo IN OUT
)
SW
For the two−phase converter, the input capacitor(s) RMS
current is then:
(11)
2
I
+ [2D @ (I
) I @ DI
C,MIN C,IN
CIN,RMS
C,MIN
2
2
1ń2
@ (1 * 2D)]
) DI
ń3) ) I
C,IN
IN,AVG
Select the number of input capacitors (N ) to provide the
IN
3. Input Capacitor Selection
RMS input current (I ) based on the RMS ripple
CIN,RMS
The choice and number of input capacitors is primarily
determined by their voltage and ripple current ratings. The
designer must choose capacitors that will support the worst
case input voltage with adequate margin. To calculate the
number of input capacitors one must first determine the total
RMS input ripple current. To this end, begin by calculating
the average input current to the converter:
current rating per capacitor (I
):
RMS,RATED
(12)
N
IN
+ I
ńI
CIN,RMS RMS,RATED
For a two−phase converter with perfect efficiency (η = 1),
the worst case input ripple−current will occur when the
converter is operating at a 25% duty cycle. At this operating
point, the parallel combination of input capacitors must
support an RMS ripple current equal to 25% of the
converter’s DC output current. At other duty cycles, the
ripple−current will be less. For example, at a duty cycle of
either 10% or 40%, the two−phase input ripple−current will
be approximately 20% of the converter’s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple−current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should be cognizant of the ESR of the
input capacitors. The input capacitor power loss can be
calculated from:
(5)
I
+ I
@ Dńh
O,MAX
IN,AVG
where:
D is the duty cycle of the converter, D = V
/V .
OUT IN
η is the specified minimum efficiency.
I
is the maximum converter output current.
O,MAX
The input capacitors will discharge when the control FET
is ON and charge when the control FET is OFF as shown in
Figure 15.
DI
= I
− I
C,MAX C,MIN
C,IN
I
C,MAX
2
(13)
P
CIN
+ I
@ ESR_per_capacitorńN
CIN,RMS IN
I
C,MIN
t
T/2
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10°C rise in the
capacitor’s temperature.
ON
0 A
FET Off,
Caps Charging
−I
IN,AVG
4. Input Inductor Selection
FET On,
Caps Discharging
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents will reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step−load
change is applied as shown in Figure 16. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
Figure 15. Input Capacitor Current for a
Two−Phase Converter
The following equations will determine the maximum and
minimum currents delivered by the input capacitors:
(6)
(7)
I
+ I
+ I
ńh * I
C,MAX
Lo,MAX
ńh * I
IN,AVG
I
C,MIN
Lo,MIN
IN,AVG
I
I
is the maximum output inductor current:
Lo,MAX
Lo,MIN
(8)
(9)
I
+ I
ń2 ) DI ń2
O,MAX Lo
Lo,MAX
is the minimum output inductor current:
I
+ I
ń2 * DI ń2
O,MAX Lo
Lo,MIN
http://onsemi.com
19
NCP5322A
(14)
current (I ), the per capacitor ESR of the output
O,MAX
V
+
OUT,FULL−LOAD
capacitors (ESR
), and the number of the output
) as shown in Figure 16. Assuming the load
OUT
V
* (I
ń2) @ ESR
ńN
OUT,NO−LOAD
O,MAX
OUT OUT
capacitors (N
OUT
current is shared equally between the two phases, the output
voltage at full, transient load will be:
V
OUT
MAX dI/dt occurs in
first few PWM cycles.
I
I
Lo
Li
Vi(t = 0) = 12 V
Q1
SWNODE
Vo(t = 0) = 1.630 V
Li
TBD
Lo
700 nH
V
+
Ci
+
Co
Ci
3 × 16SP270
7 × 16MBZ1500M10X20
Q2
+
−
Vi
12 V
22.5 u(t)
ESR
ESR
Co
Ci
18 m/3 = 6.0 m
13 m/7 = 1.9 m
Figure 16. Calculating the Input Inductance
(18)
When the control MOSFET (Q1 in Figure 16) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
+ V ń dI ńdt
Li IN MAX
Li
MIN
+ DV ń dI ńdt
Ci IN MAX
dI /dt
IN
is the maximum allowable input current slew
MAX
rate.
(15)
DV + V * V
Lo
IN
OUT,FULL−LOAD
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
V
* V
+
IN
OUT,NO−LOAD
) (I
ń2) @ ESR
ńN
O,MAX
OUT OUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
dI ńdt + DV ńLo
Lo Lo
(16)
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the −26 or −52 from Micrometals, the inductance “swing”
with DC bias must be taken into account − inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (DV ) is determined by the number of input
Ci
capacitors (N ), their per capacitor ESR (ESR ), and the
IN
IN
current in the output inductor according to:
(17)
+ ESR ńN @ dI ńdt @ t
IN IN Lo
DV
ON
Ci
+ ESR ńN @ dI ńdt @ Dńf
IN IN Lo
5. MOSFET & Heatsink Selection
SW
Power dissipation, package size, and thermal solution
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
Before the load is applied, the voltage across the input
inductor (V ) is very small − the input capacitors charge to
Li
the input voltage, V . After the load is applied the voltage
IN
drop across the input capacitors, DV , appears across the
Ci
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
http://onsemi.com
20
NCP5322A
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
non−overlap time of the gate drivers.
I
D
V
GATE
V
For the upper or control MOSFET, the power dissipation
can be approximated from:
GS_TH
(19)
2
P
+ (I
@ R )
DS(on)
D,CONTROL
RMS,CNTL
Q
Q
Q
V
DRAIN
GS1
GS2
GD
) (I
@ Q ńI @ V @ f )
switch g IN SW
Lo,MAX
Figure 17. MOSFET Switching Characteristics
) (Q
ń2 @ V @ f
) ) (V @ Q
@ f
)
oss
IN SW IN RR SW
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
I is the output current from the gate driver IC.
g
V
IN
is the input voltage to the converter.
f
Q
is the switching frequency of the converter.
is the MOSFET total gate charge to obtain R
sw
.
DS(on)
G
Commonly specified in the data sheet.
V is the gate drive voltage.
g
Q
Q
is the reverse recovery charge of the lower MOSFET.
is the MOSFET output charge specified in the data
RR
oss
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
Where I
is the RMS value of the trapezoidal
RMS,CNTL
current in the control MOSFET:
2
P
+ (I
@ R
)
DS(on)
D,SYNCH
RMS,SYNCH
@ I
(20)
2
(26)
I
+ [D @ (I
) I
@ I
RMS,CNTL
Lo,MAX
Lo,MAX Lo,MIN
) (Vf
ń2 @ t_nonoverlap @ f
diode O,MAX SW
)
2
1ń2
)ń3]
) I
Lo,MIN
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non−overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
I
is the maximum output inductor current:
Lo,MAX
(21)
(22)
I
+ I
ń2 ) DI ń2
O,MAX Lo
Lo,MAX
I
I
is the minimum output inductor current:
Lo,MIN
O,MAX
I
+ I
ń2 * DI ń2
O,MAX Lo
Lo,MIN
(27)
I
+ [(1 * D)
RMS,SYNCH
is the maximum converter output current.
2
2
1ń2
)ń3]
D is the duty cycle of the converter:
@ (I
Lo,MAX
) I
@ I
Lo,MAX Lo,MIN
) I
Lo,MIN
(23)
D + V
ńV
where:
Vf
OUT IN
is the forward voltage of the MOSFET’s intrinsic
diode
DI is the peak−to−peak ripple current in the output
Lo
diode at the converter output current.
inductor of value Lo:
t_nonoverlap is the non−overlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
(24)
DI + (V * V
Lo IN OUT
) @ Dń(Lo @ f
)
SW
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
is the post gate threshold portion of the
Q
switch
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 17.
(28)
q
T
t (T * T )ńP
J A D
(25)
Q
+ Q
) Q
gs2 gd
switch
http://onsemi.com
21
NCP5322A
where;
maximum input voltage, maximum loading, and component
variations (i.e. worst case MOSFET R ). Also, the
q is the total thermal impedance (q + q ).
T
JC
SA
DS(on)
q
is the junction−to−case thermal impedance of the
MOSFET.
is the sink−to−ambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used).
is the specified maximum allowed junction
temperature.
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, its advisable to have as
much heatsink area as possible – all too often new designs
are found to be too hot and require re−design to add
heatsinking.
JC
q
SA
T
J
6. Adaptive Voltage Positioning
There are two resistors that determine the Adaptive
T is the worst case ambient operating temperature.
For TO−220 and TO−263 packages, standard FR−4
copper clad circuit boards will have approximate thermal
A
Voltage Positioning: R
no−load “high” voltage position and R
full−load “droop” voltage.
and R . R
establishes the
determines the
FBK1
DRP FBK1
DRP
resistances (q ) as shown below:
SA
Resistor R
is connected between V
and the V
FBK1
CORE FB
Pad Size
(in /mm )
Single−Sided
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V pin and develop a voltage
2
2
1 oz. Copper
60−65°C/W
55−60°C/W
50−55°C/W
45−50°C/W
38−42°C/W
33−37°C/W
FB
0.5/323
drop from V
regulates V
to the V pin. Because the error amplifier
CORE
FB
to the DAC setting, the output voltage,
0.75/484
1.0/645
FB
V
, will be higher by the amount IBIAS
• R
.
CORE
VFB
FBK1
This condition is shown in Figure 18.
To calculate R the designer must specify the no−load
voltage increase above the VID setting (DV
1.5/968
FBK1
2.0/1290
2.5/1612
) and
NO−LOAD
determine the V bias current. Usually, the no−load voltage
FB
increase is specified in the design guide for the processor
that is available from the manufacturer. The V bias current
FB
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
is determined by the value of the resistor from R
to
OSC
ground (see Figure 5 in the data sheet for a graph of
IBIAS versus R ). The value of R can then be
VFB
OSC
FBK1
calculated:
+ −
VID Setting
R
CS1
CS1
+
−
G
COMP
+
−
Σ
L1
0 A
VDRP
C
CS1
Error
Amp
IBIAS
VFB
R
R
VFBK
DRP
R
CS2
CS2
+
−
V
= VID
V
= VID
V
CORE
DRP
FB
L2
0 A
G
VDRP
C
CS2
I
= 0
I
= IBIAS
VFB
DRP
FBK
CS
REF
V
= VID + IBIAS
w R
CORE
VFB
VFBk
Figure 18. AVP Circuitry at No−Load
(29)
R
FBK1
+ DV ńIBIAS
NO−LOAD VFB
a voltage drop from V to Vcore across R
– the
FBK
FB
converter’s output voltage will be reduced. This condition is
shown in Figure 19.
Resistor R
is connected between the V
and the
DRP
DRP
V
pins. At no−load, the V
and the V pins will both
DRP FB
FB
To determine the value of R
the designer must specify
DRP
be at the DAC voltage so this resistor will conduct zero
current. However, at full−load, the voltage at the V pin
the full−load voltage reduction from the VID (DAC) setting
(DV ) and predict the voltage increase at the
DRP
OUT,FULL−LOAD
will increase proportional to the output inductor’s current
while V will still be regulated to the DAC voltage. Current
V
DRP
pin at full−load. Usually, the full−load voltage
FB
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the
will be conducted from V
will be large enough to supply the V bias current and cause
to V by R . This current
DRP
FB DRP
FB
http://onsemi.com
22
NCP5322A
voltage increase at the V
pin at full−load (DV ), the
DRP
DV
is the full−load voltage reduction
DRP
OUT,FULL−LOAD
designer must consider the output inductor’s resistance
(R ), the PCB trace resistance between the current sense
from the VID (DAC) setting. DV
voltage change from the no−load AVP setting.
is not the
OUT,FULL−LOAD
L
points (R
), and the controller IC’s gain from the current
PCB
sense to the V
pin (G ):
VDRP
DRP
7. Current Sensing
For inductive current sensing, choose the current sense
network (R , C , n = 1 or 2) to satisfy
(30)
(31)
DV
+ I
@ (R ) R ) @ G
PCB VDRP
DRP
O,MAX
L
CSn CSn
The value of R
can then be calculated:
DRP
(32)
R
CSn
@ C
+ Loń(R ) R )
PCB
CSn
L
DV
DRP
OUT,FULL−LOAD FBK1
R
+
DRP
(IBIAS
) DV )
ńR
VFB
+ −
R
CS1
CS1
+
−
G
COMP
+
−
VID Setting
Σ
L1
I
VDRP
Error
Amp
/2
MAX
IBIAS
VFB
C
CS1
R
R
VFBK
DRP
R
CS2
CS2
CS
+
−
G
V
I
= VID +
• R • G
V
= VID
V
CORE
DRP
FB
MAX
L
VDRP
L2
I
VDRP
/2
MAX
C
CS2
I
I
FBK
DRP
I
I
= I
• R • G /R
VDRP DRP
DRP
FBK
MAX
L
REF
= I
− IBIAS
DRP
VFB
V
= VID − (I
= VID − I
− IBIAS
) w R
CORE
DRP
VFB
VFBK
w R w G
w R
/R
+ IBIAS
w R
MAX
L
VDRP
FBK DRP
VFB
FBK
Figure 19. AVP Circuitry at Full−Load
Figure 20. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Long
(Slow): VDRP and VOUT Respond Too Slowly.
Figure 21. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Short
(Fast): VDRP and VOUT Both Overshoot.
http://onsemi.com
23
NCP5322A
For resistive current sensing, choose the current sense
network (R , C , n = 1 or 2) to satisfy
CSn CSn
(33)
R
CSn
@ C
CSn
+ Loń(R
)
sense
This will provide an adequate starting point for R
and
CSn
C
CSn
. After the converter is constructed, the value of R
CSn
(and/or C ) should be fine−tuned in the lab by observing
CSn
the V
signal during a step change in load current. The
DRP
R
• C
network should be tuned to provide a
CSn
CSn
“square−wave” at the V
output pin with maximum rise
DRP
time and minimal overshoot as shown in Figure 22.
Equation 32 will be most accurate for better iron powder
core material (such as the −8 from Micrometals). This
material is very consistent with DC current and frequency.
Less expensive core materials (such as the −52 from
Micrometals) change their characteristics with DC current,
AC flux density, and frequency. This material will yield
acceptable converter performance if the current sense time
constant is set lower (longer) than anticipated. As a rule of
Figure 22. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Optimal:
VDRP and VOUT Respond to the Load Current Quickly
Without Overshooting.
thumb, use approximately twice the resistance (R ) or
CSn
twice the capacitance (C ) when using the less expensive
CSn
core material.
8. Error Amplifier Tuning
After the steady−state (static) AVP has been set and the
current sense network has been optimized the Error
Amplifier must be tuned. Basically, the gain of the Error
Amplifier should be adjusted to provide an acceptable
transient response by increasing or decreasing the Error
Amplifier’s feedback capacitor (C
in the Applications
AMP
Diagram). The bandwidth of the control loop will vary
directly with the gain of the error amplifier.
Figure 23. The Value of CAMP Is Too High and the
Loop Gain/Bandwidth Too Low. COMP Slews Too
Slowly Which Results in Overshoot in VOUT
.
If C
is too large the loop gain/bandwidth will be low,
AMP
the COMP pin will slew too slowly, and the output voltage
will overshoot as shown in Figure 23. On the other hand, if
C
AMP
is too small the loop gain/bandwidth will be high, the
COMP pin will slew very quickly and overshoot. Integrator
http://onsemi.com
24
NCP5322A
“wind up” is the cause of the overshoot. In this case the
output voltage will transition more slowly because COMP
spikes upward as shown in Figure 24. Too much loop
gain/bandwidth increase the risk of instability. In general,
one should use the lowest loop gain/bandwidth as possible
to achieve acceptable transient response − this will insure
good stability. If C
is optimal the COMP pin will slew
AMP
quickly but not overshoot and the output voltage will
monotonically settle as shown in Figure 25.
After the control loop is tuned to provide an acceptable
transient response the steady−state voltage ripple on the
COMP pin should be examined. When the converter is
operating at full, steady−state load, the peak−to−peak
voltage ripple on the COMP pin should be less than 20 mV
PP
as shown in Figure 26. Less than 10 mV is ideal. Excessive
ripple on the COMP pin will contribute to output voltage
jitter.
Figure 26. At Full−Load (28 A) the Peak−to−Peak
Voltage Ripple on the COMP Pin Should Be Less
than 20 mV for a Well−Tuned/Stable Controller.
Higher COMP Voltage Ripple Will Contribute to
Output Voltage Jitter.
PP
9. Current Limit Setting
When the output of the current sense amplifier (CO1 or
CO2 in the block diagram) exceeds the voltage on the I
LIM
pin the part will enter hiccup mode. For inductive sensing,
the I pin voltage should be set based on the inductor’s
LIM
maximum resistance (R
). The design must consider
LMAX
the inductor’s resistance increase due to current heating and
ambient temperature rise. Also, depending on the current
sense points, the circuit board may add additional resistance.
In general, the temperature coefficient of copper is +0.393%
per °C. If using a current sense resistor (R
), the I
SENSE
LIM
pin voltage should be set based on the maximum value of the
sense resistor. To set the level of the I pin:
Figure 24. The Value of CAMP Is Too Low and the
Loop Gain/Bandwidth Too High. COMP Moves Too
Quickly, Which Is Evident from the Small Spike in Its
Voltage When the Load Is Applied or Removed. The
Output Voltage Transitions More Slowly Because of
the COMP Spike.
LIM
(34)
V
ILIM
+ (I
) DI ń2) @ R @ G
Lo ILIM
OUT,LIM
where:
I
is the current limit threshold of the converter;
OUT,LIM
DI /2 is half the inductor ripple current;
Lo
R is either (R
+ R ) or R
PCB SENSE;
LMAX
G
ILIM
is the current sense to I
gain.
LIM
For the overcurrent protection to work properly, the
current sense time constant (RC) should be slightly larger
than the RL time constant. If the RC time constant is too fast,
during step load changes the sensed current waveform will
appear larger than the actual inductor current and will
probably trip the current limit at a lower level than expected.
10. PWM Comparator Input Voltage
The voltage at the positive input terminal of the PWM
comparator (see Figure 10 or 12) is limited by the internal
voltage supply of the controller (3.3 V), the size of the
internal ramp, and the magnitude of the channel startup
offset voltage. To prevent the PWM comparator from
Figure 25. The Value of CAMP Is Optimal. COMP Slews
Quickly Without Spiking or Ringing. VOUT Does Not
Overshoot and Monotonically Settles to Its Final Value.
saturating, the differential input voltage from CS
to CSn
REF
(n = 1 or 2) must satisfy the following equation:
http://onsemi.com
25
NCP5322A
(1)
V
) V ) 310 mV @ D v 2.45 V
COn,MAX
DI
O,MAX
CSREF,MAX
N
+ ESR per capacitor @
OUT,MIN
(35)
DV
O,MAX
where:
+ 13 mW @ 45 Ań(1.630 V * 1.540 V)
+ 6.5 or 7 capacitors minimum (10, 500 mF)
V
+ Max VID Setting wń AVP @ Full Load
CSREF,MAX
V
+ [V
* V
CSREF
] @ G
CSA,MAX
COn,MAX
CSn
2. Output Inductor Selection
Calculate the minimum output inductance at I
according to Equation 4 with 20% inductor ripple current
(I
ń2 ) DI ń2) @ R
+
O,MAX
Lo
MAX
O,MAX
@ G
CSA,MAX
(α = 0.20):
R
+ R
or (R
L,MAX
) R
)
PCB,MAX
MAX
SENSE
(3)
(V * V
) @ V
OUT
IN OUT
Lo
MIN
+
+
(a @ I @ V @ f
)
O,MAX
IN SW
11. Soft Start Time
(12 V * 1.565 V) @ 1.565 V
(0.2 @ 45 A @ 12 V @ 220 kHz)
If the Soft Start time is defined from the instant the Soft
Start pin is released (i.e. the converter is enabled) to when
the output reaches the VID setting with AVP then the Soft
+ 687 nH
Start time (t ) can be calculated from:
SS
To save cost, we choose the inexpensive T50−52B core
2
from Micrometals: 43.5 nH/N , 3.19 cm/turn. According to
T
+ V
COMP
@ C ńI
SS SS
SS
(36)
the Micrometals catalog, at 22.5 A (per phase) the
permeability of this core will be approximately 70% of the
permeability at 0 A. Therefore, at 0 A we must achieve at
least 687 nH/0.7 or 981 nH. Using five turns of #16AWG
bifilar (2 mW/ft) will produce 1.1 mH.
where:
V
+ V
OUT
@ 0 A ) Channel_Startup_Offset
@ Ext_Rampń2
COMP
) Int_Ramp ) G
CSA
Use Equation 4 to insure the output voltage ripple will
satisfy the design goal with the minimum number of
capacitors and the nominal output inductance:
C
is the capacitor from the Soft−Start pin to LGND;
SS
Ext_Ramp = D • (V − V
) / (R
• C • f );
CSn SW
IN
OUT
CSn
I
is the Soft−Start charge current from the data sheet.
SS
V
+ (ESR per cap ń N
) @
OUT,MIN
(4)
OUT,P−P
NJ
Nj
@ f )
MIN SW
Design Example
(V * #Phases @ V
) @ D ń (Lo
OUT
IN
+
(13 mWń7) @
Typical Design Requirements:
NJ
Nj
(5.0 V * 2 @ 1.6 V) @ (1.6 Vń5.0 V)ń(1.1 mH @ 220 kHz)
V
V
V
= 12.0 Vdc
IN
= 1.60Vdc (nominal)
OUT
{
}
+ (1.86 mW) @ 2.38 A
< 10 mV max
OUT,RIPPLE
PP
+ 4.43 mV
VID Range: 1.100 Vdc − 1.850 Vdc
I
I
= 45 A at full−load
The output voltage ripple will be decreased when output
capacitors are added to satisfy transient loading
requirements.
O,MAX
= 52 A min at 55°C (shutdown threshold)
OUT,LIM
dI /dt = 0.50 A/ms max
IN
f
= 220 kHz
We will need the nominal and worst case inductor
resistances for subsequent calculations:
SW
η = 81% min at full−load
T
T
= 60°C
A,MAX
R + 5 turns @ 3.19 cmńturn @ 0.03218 ftńcm @ 2 mWńft
L
= 125°C
J,MAX
+ 1.03 mW
t
SS
< 10.0 ms (Soft Start time)
DV
at no−load (static) =
OUT
The inductor resistance will be maximized when the
inductor is “hot” due to the load current and the ambient
temperature is high. Assuming a 40°C temperature rise of
the inductor at full−load and a 35°C ambient temperature
rise we can calculate:
+30 mV from VID setting = 1.630 Vdc
DV at full−load (static) =
OUT
–35 mV from VID setting = 1.565 Vdc
DV at full−load (transient) =
OUT
−65 mV from VID setting = 1.540 Vdc
R
+ 1.03 mW @ [1 ) 0.39%ń°C @ (40°C ) 35°C)]
+ 1.33 mW
L,MAX
1. Output Capacitor Selection
First, choose a low−cost, low−ESR output capacitor
such as the Rubycon 16MBZ1500M10X20: 16 V, 1500 mF,
The output inductance at full−load will be:
2.55 A
, 13 mW, 10 × 20mm. Calculate the minimum
RMS
Lo + 0.70 1.1 mH + 770 nH
number of output capacitors:
http://onsemi.com
26
NCP5322A
3. Input Capacitor Selection
Use Equation 5 to determine the average input current to
the converter at full−load;
the input and output capacitors, and a maximum duty cycle
(D = (1.850 V + 30 mV )/12.0 V = 0.157).
AVP
IN
(5)
+ I
@ Dńh
I
O,MAX
IN,AVG
+ 45 A @ (1.565 Vń12 V)ń0.81 + 5.87 A
Next, use Equations 6 to 10 with the full−load inductance
value of 770 nH:
+ (V * V
IN OUT
) @ Dń(Lo @ f
)
SW
DI
Lo
(10)
(1.565 Vń12 V)
(770 nH @ 220 kHz)
+ (12 V * 1.565 V) @
+ 8.03 App
(8)
+ I ń2 ) DI ń2
O,MAX Lo
I
Lo,MAX
+ 45 Ań2 ) 8.03 Appń2 + 26.5 A
Figure 27. Actual DC/DC Converter Circuitry With the
Calculated Input Inductor and Minimum Filtering
Components. The Measured Slew−Rate (dIIN/dt) of
the Input Current (0.064 A/ms) Is Much Lower Than
Expected (0.1 A/ms) Because of Input Voltage Drop,
Parasitic Inductance, and Lower Real ESRs Than
Specified in the Capacitors’ Data Sheets.
+ I
ń2 * DI ń2
Lo
I
O,MAX
Lo,MIN
(9)
(6)
+ 45 Ań2 * 8.03 Appń2 + 18.5 A
+ I
ńh * I
IN,AVG
I
Lo,MAX
C,MAX
+ 26.5 Ań0.81 * 5.87 A + 20.63 A
First, use Equation 15 to calculate the voltage across the
output inductor due to the 45 A load current being shared
equally between the two phases:
(7)
+ I
ńh * I
Lo,MIN
I
IN,AVG
C,MIN
+ 18.5 Ań0.81 * 5.87 A + 12.63 A
(15)
DV + V * V
For the two−phase converter, the input capacitor(s) RMS
current at full−load is then (Note: D = 1.565 V/12 V = 0.13):
Lo
IN
OUT,NO−LOAD
ń2) @ ESR
) (I
ńN
OUT OUT
O,MAX
(11)
2
+ 12 V * 1.85 V ) 45 Ań2 @ 13 mWń7
+ 10.19 V
I
+ [2D @ (I
) I
@ DI
CIN,RMS
C,MIN
C,MIN C,IN
2
2
1ń2
@ (1 * 2D)]
) DI
ń3) ) I
C,IN
IN,AVG
Second, use Equation 16 to determine the rate of current
increase in the output inductor when the load is first applied
(i.e. Lo has not changed much due to the DC current):
2
2
+ [0.26 @ (12.63 ) 12.63 @ 8.00 ) 8.00 ń3)
2
1ń2
) 5.87 @ (1 * 0.26)]
(16)
+ DV ńLo
dI ńdt
Lo
Lo
+ 9.69 A
RMS
+ 10.19 Vń1.1 mH + 9.26 Vńms
At this point, the designer must decide between saving
Finally, use Equations 17 and 18 to calculate the minimum
input inductance value:
board space by using higher−rated/more costly capacitors or
saving cost by using more lower−rated/less costly
capacitors. To save board space, we choose the SP (Oscon)
series capacitors by Sanyo. Part number 16SP270: 270 mF,
(17)
+ ESR ńN @ dI ńdt @ Dńf
IN IN Lo
DV
SW
Ci
+ 18 mWń3 @ 9.26 Vńms @ 0.157ń220 kHz
+ 39.7 mV
16 V, 4.4 A
, 18 mW, 10 × 10.5 mm. This design will
RMS
require 9.69 A/4.4 A = 2.2 or N = 3 capacitors on the input
IN
for a conservative design.
(18)
+ DV ń dI ńdt
Li
MIN
Ci
IN MAX
4. Input Inductor Selection
+ 39.7 mVń0.50 Ańms + 80 nH
The input inductor must limit the input current slew rate
to less than 0.5 A/ms during a load transient from 0 to 45 A.
A conservative value will be calculated assuming the
Next, choose the small, cost effective T30−26 core from
Micrometals (33.5 nH/N ) with #16 AWG. The design
requires only 1.54 turns to achieve the minimum inductance
2
minimum number of output capacitors (N
= 7), three
OUT
input capacitors (N = 3), worst case ESR values for both
IN
http://onsemi.com
27
NCP5322A
(27)
value. Allow for inductance “swing” at full−load by using
three turns. The input inductor’s value will be:
I
+ [(1 * D) @
RMS,SYNCH
2
2
1ń2
(I
) I
@ I ) I
Lo,MAX Lo,MIN Lo,MIN
)ń3]
Lo,MAX
+ [(1 * 0.13) @ (26.5 ) 26.5 @ 18.5 ) 18.5 )ń3]
+ 21.1 A
2
2
L + 3 @ 33.5 nHńN + 301 nH
i
2
2
1ń2
This inductor is available as part number CTX15−14771
from Coiltronics.
RMS
Equation 26 is used to calculate the power dissipation of
the synchronous MOSFET:
5. MOSFET & Heatsink Selection
The IPB05N03L from Infineon is chosen for both the
control and synchronous MOSFET due to its low R
and low gate−charge requirements. The following
parameters are derived from the IPB05N03L data sheet:
(26)
2
P
+ (I
@ R )
DS(on)
D,SYNCH
RMS,SYNCH
@ I ń2 @ t_nonoverlap @ f
DS(on)
) (Vf
)
SW
diode O,MAX
2
(21.1 A
@ 3.9 mW)
+
RMS
) (0.86 V @ 45 Ań2 @ 65 ns @ 220 kHz)
+ 1.74 W ) 0.28 W + 2.02 W
Rds = 3.9 mW @ 10 V
ON
Q
Q
Q
= 25 nC
= 45 nC
= 35 nC
SWITCH
RR
OSS
Equation 28 is used to calculate the heat sink thermal
impedances necessary to maintain less than the specified
maximum junction temperatures at 60°C ambient:
Vf
= 0.86 V @ 25 A
= 1.0°C/W
diode
q
JC
NCP5322A Parameters:
i = 1.5 A
q
t (125 * 60°C)ń1.6 W * 1.0°CńW + 40°CńW
t (125 * 60°C)2.02 W * 1.0°CW + 31°CW
G
CNTL
V = 10 V
G
q
SYNCH
t_nonoverlap = 65 ns
If board area permits, a cost effective heatsink could be
The RMS value of the current in the control MOSFET is
calculated from Equation 20 and the previously derived
values for D, I
2
formed by using a TO−263 mounting pad of at least 1.5 in
for the upper MOSFET and 2.5 in for the lower MOSFET
2
, and I
at the converter’s maximum
LMAX
LMIN
on a single−sided, 1 oz. copper PCB. The total required pad
area would be slightly less if the area were divided evenly
between top and bottom layers with multiple thermal vias
joining the two areas. To conserve board space, AAVID
offers clip−on heatsinks for TO−220 thru−hole packages.
Examples of these heatsinks include #577002 (1″ × 0.75″ ×
0.25″, 33°C/W at 2 W) and #591302 (0.75″ ×0.5″ × 0.5″,
29°C/W at 2 W).
output current:
(20)
2
I
+ [D @ (I
) I
@ I
RMS,CNTL
Lo,MAX
Lo,MAX Lo,MIN
2
1ń2
)ń3]
) I
Lo,MIN
2
2
1ń2
+ 0.36 @ [(26.5 ) 26.5 @ 18.5 ) 18.5 )ń3]
+ 8.15 A
RMS
Equation 19 is used to calculate the power dissipation of
the control MOSFET:
6. Adaptive Voltage Positioning
First, to achieve the 220 kHz switching frequency, use
Figure 4 to determine that a 65 kW resistor is needed for
(19)
2
P
+ (I
@ R )
DS(on)
D,CONTROL
RMS,CNTL
@ Q
) (I
ńI @ V @ f )
switch g IN SW
R
OSC
. Then, use Figure 5 to find the V bias current at the
Lo,MAX
FB
corresponding value of R
. In this example, the 65 kW
OSC
) (Q
ń2 @ V @ f
) ) (V @ Q
@ f
RR SW
)
oss
IN SW IN
R
OSC
resistor results in a V bias current of approximately
FB
2
+ (8.15 A
@ 3.9 mW)
RMS
5.0 mA. Knowing the V bias current, one can calculate the
FB
required values for R
through 31.
The no−load position is easily set using Equation 29:
and R
using Equations 29
DRP
FBK1
) (26.5 A @ 25 nCń1.5 A @ 12 V @ 220 kHz)
) (35 nCń2 @ 12 V @ 220 kHz)
) (12 V @ 45 nC @ 220 kHz)
(29)
R
FBK1
+ DV ńIBIAS
NO−LOAD VFB
+ 0.26 W ) 1.17 W ) 0.05 W ) 0.12 W
+ 1.60 W
+ +30 mVń5.0 mA
+ 6.04 kW
The RMS value of the current in the synchronous
MOSFET is calculated from Equation 27 and the previously
For inductive current sensing, the designer must calculate
the inductor’s resistance (R ) and approximate any
L
derived values for D, I
, and I
at the converter’s
Lo,MAX
Lo,MIN
resistance added by the circuit board (R
). We found the
PCB
maximum output current:
http://onsemi.com
28
NCP5322A
inductor’s nominal resistance in Section 2 (0.82 mW). In this
example, we approximate 0.50 mW for the circuit board
with minimal overshoot and fast rise time due to a step
change in load current as shown in Figures 20−22.
resistance (R
be used to calculate the increase at the V
). With this information, Equation 30 can
PCB
8. Error Amplifier Tuning
The error amplifier is tuned by adjusting C
an acceptable full−load transient response as shown in
Figures 23−25. After a value for C is chosen, the
peak−to−peakvoltage ripple on the COMP pin is examined
pin at full load:
DRP
to provide
AMP
(30)
DV
+ I
@ (R ) R
PCB
) @ G
DRP
O,MAX
L
VDRP
AMP
+ 45 A @ (1.03 mW ) 0.50 mW) @ 3.3 VńV
+ 227 mV
under full−load to insure less than 20 mV as shown in
PP
Figure 26.
R
DRP1
can then be calculated from Equation 31:
(31)
DV
9. Current Limit Setting
DRP
R
DRP
+
(IBIAS
) DV
ńR
)
VFB
OUT,FULL−LOAD FBK1
The maximum inductor resistance, the maximum PCB
resistance, and the maximum current−sense gain as shown
in Equation 34 determine the current limit. The maximum
+ 227 mVń(5.0 mA ) 35 mVń6.04 kW)
+ 21.0 kW
current, I
, was specified in the design requirements.
OUT,LIM
The maximum inductor resistance occurs at full−load and
the highest ambient temperature. This value was found in the
“Output Inductor Section” (1.06 mW). This analysis
assumes the PCB resistance only increases due to the change
in ambient temperature. Component heating will also
increase the PCB temperature but quantifying this effect is
difficult. Lab testing should be used to “fine tune” the
overcurrent threshold.
7. Current Sensing
Choose the current sense network (R , C , n = 1 or 2)
to satisfy:
CSn CSn
(32)
R
CSn
@ C
CSn
+ Loń(R ) R )
PCB
L
Equation 32 will be most accurate for better iron powder
core material (such as the −8 from Micrometals). This
material is very consistent with DC current and frequency.
Less expensive core materials (such as the −52 from
Micrometals) change their characteristics with DC current,
AC flux density, and frequency. This material will yield
acceptable converter performance if the current sense time
constant is set lower (longer) than anticipated. As a rule of
R
+ 0.50 mW @ (1 ) 0.39%ń°C @ (60 * 25)°C)
PCB,MAX
+ 0.57 mW
+ (I
) DI ń2) @ (R
Lo LMAX
) R
)
V
ILIM
OUT,LIM
PCB,MAX
@ G
ILIM
thumb, use approximately twice the resistance (R ) or
CSn
twice the capacitance (C ) when using the less expensive
core material.
The component values determined thus far are Lo = 1.1mH,
(52 A ) 8.03 Ań2) @ (1.33 mW ) 0.57 mW)
@ 6.75 VńV
CSn
+
R = 1.03 mW, and R
= 0.50mW. We choose a convenient
+ 0.718 Vdc
L
PCB
value for C
(0.01 mF) and solve for R
;
CS1
CS1
Set the voltage at the I
the 3.3 V reference output as shown in Figure 28. If the
pin using a resistor divider from
LIM
R
CSn
+ 1.1 mHń(1.03 mW ) 0.50 mW)ń0.01 mF
+ 71 kW
resistor from I
resistor from I
to GND is chosen as 1 k (R
to 3.3 V can be calculated from:
), the
LIM
LIM
LIM2
Equation 32 will be most accurate for higher quality iron
powder core materials such as the −2 or −8 from
Micrometals. The permeability of these more expensive
cores is relatively constant versus DC current, AC flux
density and frequency. Less expensive core materials (such
as the −52 from Micrometals) change their characteristics
versus DC current, AC flux density, and frequency. The less
expensive materials may yield acceptable converter
performance if the current sense time constant is set
approximately 1×−2× longer than anticipated. For example,
R
LIM1
+ (V
REF
* V
)ń(V )
ńR
ILIM
ILIM LIM2
+ (3.3 V * 0.718 V)ń(0.718 Vń1 kW)
+ 3596 W or 3.57 kW
3.3 V
REF
To I
Pin
R
LIM1
LIM
V
LIM
R
LIM2
1 k
use up to twice the resistance (R ) or twice the capacitance
CSn
(C ) when using the less expensive core material. If we
CSn
use −52 material for this design, the value of R
to be increased to 2 × 71 kW or 142 kW.
After the circuit is constructed, the values of R
may need
CSn
Figure 28. Setting the Current Limit
and/or
CSn
C
CSn
should be tuned to provide a “square−wave” at V
DRP
http://onsemi.com
29
NCP5322A
10. PWM Comparator Input Voltage
(V * V
IN OUT
)
Ext_Ramp + D @
Use Equation 35 to check the voltage level to the positive
pin of the internal PWM comparators. The design should not
saturate the PWM comparator at maximum DAC output
voltage (+1% error), AVP at full−load, 100% duty cycle (D
= 1), and worst−case maximum internal ramp (310 mV at
100% duty cycle):
(R
@ C @ f
)
CSn
CSn SW
(12 V * 1.630 V)
60 kW @ 0.01 F @ 220 kHz)
+ 0.135 @
+ 11 mV
Then calculate the steady−state COMP voltage:
V
+ Max VID Setting wń AVP @ Full−Load
+ 1.01 @ 1.850 V * 30 mV + 1.834 V
CSREF,MAX
+
V
V
@ 0 A ) Channel_Startup_Offset
COMP
OUT
) Int_Ramp ) G
@ Ext_Rampń2
CSA
V
+ 1.630 V ) 0.40 V ) 0.135 @ 250 mV
) 3.5 VńV @ 11 mVń2
COn,MAX
+ (I
ń2 ) DI ń2) @ R
O,MAX Lo MAX
@ G
CSA,MAX
+
+ 2.083 V
(52 Ań2 ) 8.03 Ań2) @ (1.33 mW ) 0.57 mW)
@ 3.90 VńV
Then choose a convenient value for the Soft−Start time
(7.5 ms) and solve Equation 37 for the Soft−Start capacitor,
+ 0.222 V
C
SS
:
(37)
(35)
V
) V
COn,MAX
) 310 mV @ D
+ t
@ I ńV
SS SS COMP
C
SS
CSREF,MAX
+ 1.834 V ) 0.222 V ) 310 mV
+ 2.366 V
+ 7.5 ms @ 30 mAń2.083 V
+ 0.108 mF or 0.1 mF
This value is acceptable because it below the specified
maximum of 2.45 V.
I
is the Soft−Start charge current from the data sheet.
SS
11. Soft Start Time
To set the Soft Start time, first calculate the external ramp
size at a duty−cycle of D = 1.630 V/12 V = 0.135:
http://onsemi.com
30
NCP5322A
PACKAGE DIMENSIONS
SOIC
DW SUFFIX
CASE 751F−05
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBER
PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN
EXCESS OF B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
−X−
E
D
28
15
H
M
M
Y
0.25
MILLIMETERS
DIM MIN
MAX
2.65
0.29
0.49
0.32
18.05
7.60
−Y−
A
A1
B
2.35
0.13
0.35
0.23
17.80
7.40
1
14
PIN 1 IDENT
C
D
E
G
H
1.27 BSC
10.05
0.41
0
10.55
0.90
8
A
L
L
M
_
_
0.10
−T−
SEATING
PLANE
G
A1
C
B
M
M
S
S
Y
0.025
T X
2
V
is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP5322A/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明