NCP5331_技术文档

NCP5331

Two−Phase PWM

Controller with Integrated

Gate Drivers

The NCP5331 is a second-generation, two-phase, buck controller

that incorporates advanced control functions to power 64-bit AMD

Athlont processors and low voltage, high current power supplies.

Proprietary multiphase architecture guarantees balanced load-current

sharing, reduces output voltage and input current ripple, decreases

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MARKING

DIAGRAMS

filter requirements and inductor values, and increases output current

2

slew rate. Traditional Enhanced V

t

has been combined with an

to the

internal PWM ramp and voltage feedback directly from V

CORE

internal PWM comparator. These features and enhancements deliver

the fastest transient response, reduce output voltage jitter, provide

greater design flexibility and portability, and minimize overall

solution cost.

NCP5331

AWLYYWW

LQFP-32

FT SUFFIX

CASE 873A

32

1

Advanced features include adjustable power- good delay,

programmable overcurrent shutdown timer, superior overvoltage

protection (OVP), and differential remote sensing. An innovative

overvoltage protection (OVP) scheme safeguards the CPU during

extreme situations including power up with a shorted upper MOSFET,

shorting of an upper MOSFET during normal operation, and loss of

the voltage feedback signal, COREFB+.

A

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

ORDERING INFORMATION

Features

Device

Package

Shipping

• Reduced SMT Package Size (7 mm × 7 mm)

• Enhanced V Control Method

2

NCP5331FTR2

LQFP-32

2000 Tape & Reel

• Four On-Board Gate Drivers

• Internal PWM Ramps

• Differential Remote Voltage Sense

• Fast Feedback Pin (V

)

FFB

• 5-Bit DAC with 0.8% System Tolerance

• Timed Hiccup Mode Current Limit

• Power Good Output with Programmable Delay

• Advanced Overvoltage Protection (OVP)

• Adjustable Output Voltage Positioning

• 150 kHz to 600 kHz Operation Set by Resistor

• “Lossless” Current Sensing through Output Inductors

• Independent Current Sense Amplifiers

• 5.0 V, 2 mA Reference Output

Semiconductor Components Industries, LLC, 2003

1

Publication Order Number:

June, 2003 - Rev. 11

NCP5331/D

NCP5331

PIN CONNECTIONS

LQFP-32

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

V

FB

GL1

23

22

21

20

19

18

17

V

GND1

GH1

DRP

LGND

CS1

CB

OUT

CS

V

CCH

REF

CS2

GH2

GND2

GL2

V

FFB

REF

5 V

9

10 11 12 13 14 15 16

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2

NCP5331

+

C C L 1

C C L 2

V

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

1 6

1 5

1 4

1 3

1 2

1 1

C C L

V

O V

C

P G

C

I D 4

V

I D 3

V

I D 2

V

I D 1

V

C

D

P G D

S B

I D 0

V

5 V

L I M

I

- S E N

1 0

C

O S

R

C O M P

9

Recommended Components:

Q1, Q4: ON Semiconductor NTD60N03 (60 A, 28 V, 6.1 mΩ)

Q5−Q9: ON Semiconductor NTD80N02 (80 A, 24 V, 5.0 mΩ)

L1, L2: Coiltronics CTX22-15274 or T50-8B/90 w/ 6 T of #16

AWG Bifilar (1 mΩ)

C

: 5 × Rubycon 16MBZ1500M10X20 (1500 µF, 16 V, 2.55 A

)

IN

RMS

CO1: 10 × Rubycon 16MBZ1000M10X16 (1000 µF, 16 V, 19 mΩ)

CO2: 24 × TDK C2012X5R0J106M (10 µF, 6.3 V, 0805)

CO3: 16 × TDK C1608X5R1A224KT (0.22 F, 10 V, 0603)

L3: Coiltronics CTX15-14771 or T30-26 w/ 3 T of #16 AWG

CO4: 2 × Sanyo PosCAP 6TPD330M (330 µF, 6.3 V, 10 mΩ, 4.4 A

)

RMS

Figure 1. Application Diagram, 12 V to 1.2 V at 52 A, 200 kHz for 64-Bit AMD Athlon Processor

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3

NCP5331

MAXIMUM RATINGS*

Rating

Value

Unit

Operating Junction Temperature

150

°C

Lead Temperature Soldering

SMD Reflow Profile (60 seconds maximum)

230

183

°C peak

°C

Storage Temperature Range

-65 to 150

52

°C

°C/W

kV

Package Thermal Resistance:

Junction-to-Ambient, R

θ

JA

ESD Susceptibility (Human Body Model)

2.0

JEDEC Moisture Sensitivity

TBD

-

*The maximum package power dissipation must be observed.

MAXIMUM RATINGS

Pin Symbol

V

MAX

V

MIN

I

SINK

SOURCE

COMP

6.0 V

13.2 V

6.0 V

16 V

-0.3 V

1.0 mA

8.0 mA

1.0 mA

20 mA

4.0 mA

1.0 mA

50 mA

V

FB

1.0 mA

N/A

V

DRP

CS1, CS2

CS

REF

OSC

R

PGD

VID Pins

I

LIM

5 V

REF

OUT

PGD

OVC

CCL

CCH

CB

C

V

20 V

N/A

1.5 A for 1.0 µs,

200 mA dc

V

16 V

-0.3 V

N/A

1.5 A for 1.0 µs,

200 mA dc

CCLx

5 V

6.0 V

20 V

1.0 mA

SB

GHx

-2.0 V for 100 ns,

-0.3 V dc

1.5 A for 1.0 µs,

200 mA dc

1.5 A for 1.0 µs,

200 mA dc

GLx

16 V

-2.0 V for 100 ns,

-0.3 V dc

1.5 A for 1.0 µs,

200 mA dc

1.5 A for 1.0 µs,

200 mA dc

GND1, GND2

0.3 V

-0.3 V

2.0 A for 1.0 µs,

N/A

200 mA dc

LGND

-SEN

0 V

50 mA

1.0 mA

N/A

0.3 V

-0.3 V

1.0 mA

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4

NCP5331

ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V

< 16 V; 9.0 V < V

< 20 V;

CCH

A

J

CCL

9.0 V < V

= V

< 14 V; C

= 3.3 nF, R

= 32.4 kΩ, C

= 1.0 nF, C

= 0.1 µF, DAC Code 01110 (1.2 V),

CCL1

CCL2

GATE

ROSC

COMP

5V(REF)

C

= 1.0 µF, 0.25 V ≤ I

≤ 1.0 V; unless otherwise noted)

VCC

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Voltage Identification DAC

Voltage Identification (VID) Codes

Measure V = COMP, -SEN = LGND

FB

V

ID3

V

ID2

V

ID1

V

ID0

ID4

0

-

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

Shutdown

-

V

%

µs

V

µA

V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

System Accuracy

Percent deviation from programmed VID codes

VID = 11111

-0.8

5.0

1.00

12

0.8

15

Shutdown Time Delay

Input Threshold

10

V

-V

1.25

1.50

40

ID0

ID4

VID Pin Bias Current

VID Pin Clamp Voltage

V

25

-

2.3

2.6

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5

NCP5331

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V

< 16 V; 9.0 V < V < 20 V;

CCH

A

J

CCL

9.0 V < V

= V

< 14 V; C

= 3.3 nF, R

= 32.4 kΩ, C

= 1.0 nF, C

= 0.1 µF, DAC Code 01110 (1.2 V),

CCL1

CCL2

GATE

ROSC

COMP

5V(REF)

C

= 1.0 µF, 0.25 V ≤ I

≤ 1.0 V; unless otherwise noted)

VCC

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Voltage Identification DAC (continued)

-SEN Bias Current

LGND < 55 mV, All DAC Codes

-

40

80

-

120

200

µA

-SEN Offset from GND

Power Good Output

Internal Delay Time

-150

mV

-

175

290

250

425

400

µs

mV

µA

%

PWRGD Low Output Voltage

Output Leakage Current

I

= 4.0 mA

-

PGD

V

PGD

= 5.5 V

0.1

2.0

V

CORE

/CS

Comparator

Tolerance from DAC Setting

-15%

-12.5%

-10%

REF

Threshold Voltage

C

Charge Current

R

= 32.4 kΩ

14.5

2.8

16

17.5

3.2

µA

PGD

OSC

PGD

Comparator Threshold

Voltage

-

3.0

V

PGD

C

External Delay Time

C

= 0.033 µF. Note 1.

4.8

6.0

7.8

ms

PGD

Voltage Feedback Error Amplifier

Bias Current

V

FB

9.4

15

10.3

30

11.1

60

µA

V

0.7 V < V < 1.6 V. Note 2.

FB

COMP Source Current

COMP Sink Current

COMP = 0.5 V to 2.0 V; V = 0.8 V

FB

15

30

60

COMP = 0.5 V to 2.0 V; V = 1.5 V

FB

COMP Discharge Threshold

Voltage

-

0.20

0.33

0.40

Transconductance

-

32

-

mmho

-10 µA < I

< +10 µA

COMP

Output Impedance

Open Loop Dc Gain

Unity Gain Bandwidth

-

2.5

90

-

MΩ

dB

Note 1.

60

-

400

kHz

C

= 0.01 µF

COMP

-

70

-

dB

PSRR @ 1.0 kHz

COMP Max Voltage

V

= 0.8 V, COMP Open

= 1.5 V, COMP Open

4.1

-

4.4

0.1

7.5

4.0

-

V

FB

COMP Min Voltage

0.2

13

-

FB

Hiccup Latch Discharge Current

-

4.0

-

µA

-

Hiccup Latch Charge/Discharge

Ratio

PWM Comparators

Minimum Pulse Width

Channel Start-Up Offset

CS1 = CS2 = CS

-

235

280

ns

V

REF

0.45

0.60

0.80

CS1 = CS2 = V = CS

= 0 V;

FB

REF

Measure COMP when GHx switch High

Overcurrent Shutdown Timer

Overcurrent Shutdown Voltage

Threshold

-

2.8

3.0

3.2

V

C

Low Output Voltage

Source Current

-

250

5.0

400

8.0

mV

OVC

3.0

µA

1. Guaranteed by design. Not tested in production.

2. The V Bias Current changes with the value of R

per Figure 5.

OSC

FB

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6

NCP5331

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V

< 16 V; 9.0 V < V < 20 V;

CCH

A

J

CCL

9.0 V < V

= V

< 14 V; C

= 3.3 nF, R

= 32.4 kΩ, C

= 1.0 nF, C

= 0.1 µF, DAC Code 01110 (1.2 V),

CCL1

CCL2

GATE

ROSC

COMP

5V(REF)

C

= 1.0 µF, 0.25 V ≤ I

≤ 1.0 V; unless otherwise noted)

VCC

LIM

Characteristic

Test Conditions

Min

65

Typ

120

2.1

Max

230

2.2

Unit

ms

V

Overcurrent Shutdown Timer (continued)

Overcurrent Shutdown Time = 0.22 µF. Note 3.

Internal Overvoltage Protection (OVP)

Overvoltage Threshold LGND = 0 V, V = 0 V, CS

C

OVC

= 0 V,

REF

2.0

FB

Increase CS

until GL1 and GL2 switch High.

REF

External Overvoltage Protection (CB

)

OUT

Overvoltage Positive Threshold

5 V = 5.0 V, LGND = 0 V, CS

= 0 V,

= High.

2.0

0.8

-

2.1

0.9

-

2.2

1.0

2.0

0.4

V

SB

REF

Increase CS

until CB

REF

OUT

Overvoltage Negative Threshold

5 V = 5.0 V, LGND = 0 V, CS

= 3.0 V,

SB

REF

Decrease CS

until CB

= Low.

OUT

REF

CB

Maximum Allowable

-

mA

V

OUT

Sink Current

CB

Low Voltage

6.6 kΩ Pull-Up to 13.2 V

-

OUT

GATE DRIVERS

High Voltage (AC)

Low Voltage (AC)

Rise Time GHx

Rise Time GLx

Measure V

- GLx or V

- GHx. Note 3.

-

0

1.0

0.5

80

V

CCLx

CCHx

Measure GLx GHx. Note 3.

V

or

1.0 V < GHx < 8.0 V; V

= 10 V

-

35

65

1.2

ns

V

CCH

1.0 V < GLx < 8.0 V; V

= 10 V

-

80

CCLx

Fall Time GHx

8.0 V > GHx > 1.0 V; V

-

80

CCH

Fall Time GLx

8.0 V > GLx > 1.0 V; V

-

80

CCLx

GHx to GLx Delay

GLx to GHx Delay

GATE Pull-Down

GHx < 2.0 V, GLx > 2.0 V

GLx < 2.0 V, GHx > 2.0 V

30

-

110

1.6

Force 100 µA into GATE with no power applied to

V

CCH

and V

= 2.0 V.

CCLx

Oscillator

Switching Frequency

R

= 32.4 k

255

110

450

-

300

150

600

1.0

345

190

750

-

kHz

V

OSC

= 63.4 k; Note 3.

= 16.2 k; Note 3.

R

Voltage

-

OSC

Phase Delay

165

180

195

deg

Adaptive Voltage Positioning

V

Output Voltage to

CS1 = CS2 = CS

, V = COMP,

- COMP

6

mV

V/V

DRP

REF FB

DAC

Offset

Measure V

OUT

DRP

Maximum V

Voltage

10 mV ≤ (CS1 = CS2) - CS

≤ 50 mV,

- COMP

300

3.9

400

4.2

500

DRP

REF

DRP

V

FB

= COMP, Measure V

Current Sense Amp to V

Gain

10 mV ≤ (CS1 = CS2) - CS

≤ 50 mV

- COMP

4.75

DRP

REF

DRP

V

FB

= COMP, Measure V

3. Guaranteed by design. Not tested in production.

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7

NCP5331

ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 9.0 V < V

< 16 V; 9.0 V < V < 20 V;

CCH

A

J

CCL

9.0 V < V

= V

< 14 V; C

= 3.3 nF, R

= 32.4 kΩ, C

= 1.0 nF, C

= 0.1 µF, DAC Code 01110 (1.2 V),

CCL1

CCL2

GATE

ROSC

COMP

5V(REF)

C

= 1.0 µF, 0.25 V ≤ I

≤ 1.0 V; unless otherwise noted)

VCC

LIM

Characteristic

Test Conditions

Min

Typ

Max

Unit

Current Sensing

CS1-CS2 Input Bias Current

CS Input Bias Current

CSx = CS

CSx - CS

= 0 V

-

0.1

0.35

110

2.1

0.5

1.5

µA

REF

= 50 mV

-

REF

V

FFB

Pull-Up Resistor

-

80

1.85

9.5

145

2.35

14

kW

Current Sense Amplifier Gain

CSx - CS

= 40 mV

V/V

REF

Current Sense Input to I

Gain

I

= 1.00 V

12

LIM

Current Limit Filter Slew Rate

4.0

-

7.0

-

13

3.0

1.0

-

mV/µs

V

I

Operating Voltage Range

Bias Current

Note 4.

0 < I

LIM

< 1.0 V

-

0.1

-

µA

LIM

Current Sense Amplifier

Bandwidth

Note 4.

1.0

MHz

General Electrical Specifications

V

Operating Current

V

= COMP (no switching)

-

22

26

10

mA

CCL

FB

V

CCL1

or V

Operating

5.0

CCL2

FB

Current

V

Operating Current

V

= COMP (no switching)

-

6.4

-

9.0

400

8.9

mA

µA

V

CCH

FB

5 V Quiescent Current

CB

= Low

OUT

-

SB

V

CCL

V

CCL

V

CCL

V

CCH

V

CCH

V

CCH

Start Threshold

Stop Threshold

Hysteresis

GATEs switching, COMP charging

8.1

5.75

2.05

8.1

6.35

1.45

8.5

GATEs stop switching, COMP discharging

GATEs not switching, COMP not charging

GATEs switching, COMP charging

6.15

2.35

8.5

6.55

2.65

8.9

V

Start Threshold

Stop Threshold

Hysteresis

V

GATEs stop switching, COMP discharging

GATEs not switching, COMP not charging

6.75

1.75

7.15

2.05

V

Reference Output

5 V Output Voltage

4.85

-

5.0

5.15

-

V

0 mA < I(5 V

) < 1.0 mA

REF

Internal Ramp

Ramp Height @ 50% PWM

Duty Cycle

CS1 = CS2 = CS

125

mV

REF

4. Guaranteed by design. Not tested in production.

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8

NCP5331

PACKAGE PIN DESCRIPTION

Pin No.

Symbol

Description

Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP), set the light load offset voltage

1

V

FB

by connecting a resistor between V and V . The resistor and the V bias current determine

FB

CORE

FB

the offset. For no adaptive positioning connect V directly to V

.

FB

CORE

2

V

DRP

Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC

voltage is proportional to the output current. Connect a resistor from this pin to V to set the

FB

amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 4.1 Vdc.

3

LGND

Return for the internal control circuits and the IC substrate connection.

4, 6

CS1, CS2

Current sense inputs. Connect the current sense network for the corresponding phase to each in-

put. The input voltages to these pins must be kept within 125 mV of CS

.

REF

5

CS

Reference for both differential current sense amplifiers. To balance input offset voltages between

the inverting and non-inverting inputs of the Current Sense Amplifiers, connect this pin to the output

voltage through a resistor equal to one third of the value of the current sense resistors.

REF

7

8

V

Fast Feedback connection to the PWM comparators and input to the Power Good comparator.

FFB

5 V

Reference output. Decouple to LGND with 0.1 µF.

REF

OSC

9

R

A resistor from this pin to ground sets the operating frequency and V bias current.

FB

10

11-15

16

17

18

19

20

21

-SEN

Ground connection for the DAC. Provides remote sensing of ground at the load.

VID pins

Voltage ID DAC inputs. These pins are internally pulled up and clamped at 2.3 V if left unconnected.

V

CCL2

Power for GL2.

GL2

GND2

GH2

Low side driver #2.

Return for driver #2.

High side driver #2.

V

CCH

Power for GH1 and GH2.

CB

Open-collector crowbar output pin. This pin is high impedance when an overvoltage condition is

OUT

detected at CS

. Connect this pin to the gate of a MOSFET or SCR to crowbar either V

REF

or

CORE

V

IN

to GND. To prevent failure of the crowbar device, this pin should be used in conjunction with

logic on the motherboard to disable the ATX supply via PS and/or a relatively fast fuse should be

ON

placed upstream to disconnect the input voltage.

22

23

24

25

26

27

GH1

High side driver #1.

GND1

GL1

Return for driver #1.

Low side driver #1.

V

CCL1

Power for GL1.

V

Power for the internal control circuits. UVLO sense for Logic connects to this pin.

CCL

OVC

C

A capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit.

This timer is started by the first overcurrent condition (set by the I

voltage). Once timed out, volt-

LIM

age at the V

pin must be cycled to reset this fault. Connecting this pin to LGND ±200 mV will

CCL

disable this function and hiccup mode current limit will operate indefinitely.

28

C

A capacitor from this pin to ground sets the programmable time between when V

crosses the

CORE

PGD

PWRGD threshold and when the open-collector PWRGD pin transitions from a logic Low to a logic

High. The minimum delay is internally set to 200 µs. Connecting this pin to 5 V

will disable the

REF

programmable timer and the delay will be set to the internal delay.

29

30

PGD

Power Good output. Open collector output that will transition Low when CS

regulation.

(V

) is out of

REF

CORE

5 V

Input power for the CB

circuitry. To provide maximum overvoltage protection to the CPU, this pin

OUT

SB

should be connected to 5 V from the ATX supply (ATX, pin 9). If the CB

function is not used,

SB

OUT

this pin must be connected to the NCP5331 controller’s internal voltage reference (5 V

, pin 8).

REF

31

32

I

Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maxi-

mum working voltage is 3.0 Vdc.

LIM

COMP

Output of the error amplifier and input for the PWM comparators.

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9

NCP5331

N o n - O v e r l a p

Figure 2. Block Diagram, Control Functions

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10

NCP5331

Figure 3. Block Diagram, Protection

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11

NCP5331

Controller

5.0 V

25 µA

V

ID0

-V

ID4

Hi or Lo

0.65 V

1.65 V

+

-

Figure 4. Simplified VID Pin Input Circuitry

TYPICAL PERFORMANCE CHARACTERISTICS

600

550

500

450

400

350

300

250

200

150

100

25

20

15

10

5

0

10

20

30

40

50

60

70

10

20

30

40

50

60

70

80

R

(k)

R

Value, kΩ

OSC

Figure 5. Oscillator Frequency vs. R_OSCValue

Figure 6. V_FBCurrent vs. R_OSCValue

650

V

= 5 V

SOURCE

600

550

500

450

400

350

300

250

200

Minimum NCP5331

Pulse Width = 280 ns

V

= 12 V

SOURCE

V

CORE

(V)

Figure 7. Maximum Frequency vs. V_CORE

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12

NCP5331

TYPICAL PERFORMANCE CHARACTERISTICS

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4.0

3.9

5.15

5.10

5.05

5.00

4.95

4.90

4.85

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

Temperature (°C)

Figure 8. CSA to V_DRPGain vs. Temperature

Figure 9. 5.0 V_REFOutput Voltage vs.

Temperature

25

14.0

13.5

13.0

12.5

12.0

11.5

11.0

20

15

10

5

10.5

10.0

9.5

0

-5

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

Temperature (°C)

Figure 10. CSA to I_LIMGain vs. Temperature

Figure 11. V_DRPOutput to DAC_OUTOffset vs.

Temperature

11.0

15

14

13

12

11

10

10.8

10.6

10.4

10.2

10.0

9.8

9.6

9.4

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

Temperature (°C)

Figure 12. V_FBBias Current vs. Temperature

Figure 13. PGD Threshold vs. Temperature

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13

NCP5331

APPLICATIONS INFORMATION

Overview

converters are connected in parallel, output current can ramp

2

The NCP5331 dc/dc controller utilizes an Enhanced V

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

topology to meet requirements of low voltage, high current

loads with fast transient requirements. Transient response

has been improved and voltage jitter virtually eliminated by

including an internal PWM ramp, connecting fast-feedback

The NCP5331 controller uses a two-phase, fixed

2

frequency, Enhanced V architecture to measure and control

from V

directly to the internal PWM comparator, and

currents in individual phases. Each phase is delayed 180°

from the previous phase. Normally, GHx (x = 1 or 2)

transitions to a high voltage at the beginning of each

oscillator cycle. Inductor current ramps up until the

combination of the current sense signal, the internal ramp

and the output voltage ripple trip the PWM comparator and

bring GHx low. Once GHx goes low, it will remain low until

the beginning of the next oscillator cycle. While GHx is

CORE

precise routing and grounding inside the controller.

Advanced features such as adjustable power-good delay,

programmable overcurrent shutdown time, superior

overvoltage protection (OVP), and differential remote

voltage sensing make it easy to obtain AMD certification.

An innovative overvoltage protection (OVP) scheme

safeguards the CPU during extreme situations including

power up with a shorted upper MOSFET, shorting of an

upper MOSFET during normal operation, and loss of the

voltage feedback signal, COREFB+. The NCP5331

provides a “fully integrated solution” to simplify design,

minimize circuit board area, and reduce overall system cost.

Two advantages of a multiphase converter over a

single-phase converter are current sharing and increased

apparent output frequency. Current sharing allows the

designer to use less inductance in each phase than would be

required in a single-phase converter. The smaller inductor

produces larger ripple currents but the total per phase power

dissipation is reduced because the rms current is lower.

Transient response is improved because the control loop will

measure and adjust the current faster in a smaller output

inductor. Increased apparent output frequency is desirable

because the off-time and the ripple voltage of the two-phase

converter will be less than that of a single-phase converter.

2

high, the Enhanced V loop will respond to line and load

variations (i.e. the upper gate on-time will be increased or

reduced as required). On the other hand, once GHx is low,

the loop can not respond until the beginning of the next

2

PWM cycle. Therefore, constant frequency Enhanced V

will typically respond to disturbances within the off-time of

the converter.

2

The Enhanced V architecture measures and adjusts the

output current in each phase. An additional input, CSx (x =

1 or 2), for inductor current information has been added to the

2

V loop for each phase as shown in Figure 14. The triangular

inductor current is measured differentially across RS,

amplified by CSA and summed with the Channel Startup

Offset, the Internal Ramp, and the Output Voltage at the

noninverting input of the PWM comparator. The purpose of

the Internal Ramp is to compensate for propagation delays in

the NCP5331. This provides greater design flexibility by

allowing smaller external ramps, lower minimum pulse

widths, higher frequency operation, and PWM duty cycles

above 50% without external slope compensation. As the sum

of the inductor current and the internal ramp increase, the

voltage on the positive pin of the PWM comparator rises and

terminates the PWM cycle. If the inductor starts a cycle

Fixed Frequency Multiphase Control

In a multiphase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

SWNODE

CSx

+

CSA

-

COn

Lx

RLx

RSx

x = 1 or 2

Internal Ramp

CS

REF

- +

To F/F

Reset

V

“Fast-Feedback”

Connection

OUT

FFB

+

-

Channel

Start-Up

Offset

(V

)

CORE

V

FB

PWM

COMP

-

+

DAC

Out

+

Error

Amp

COMP

Figure 14. Enhanced V²Control Employing Resistive Current Sensing and Additional Internal Ramp

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14

NCP5331

RSx

CSx

SWNODE

CSx

x = 1 or 2

+

CSA

-

COn

Lx

Internal Ramp

RLx

CS

V

REF

To F/F

Reset

- +

+

-

V

“Fast-Feedback”

Connection

OUT

FFB

Channel

Start-Up

Offset

(V

)

CORE

V

FB

PWM

COMP

-

+

DAC

Out

+

Error

Amp

COMP

Figure 15. Enhanced V²Control Employing Lossless Inductive Current Sensing and Internal Ramp

with higher current, the PWM cycle will terminate earlier

providing negative feedback. The NCP5331 provides a CSx

V

+

V

COMP

@ 0 A ) Channel_Startup_Offset

CORE

) Int_Ramp ) G

@ Ext_Rampń2

CSA

input for each phase, but the CS

and COMP inputs are

REF

common to all phases. Current sharing is accomplished by

referencing all phases to the same CS and COMP pins,

Int_Ramp is the internal ramp value at the corresponding

duty cycle, Ext_Ramp is the peak-to-peak external

REF

so that a phase with a larger current signal will turn off earlier

steady-state ramp at 0 A, G

is the Current Sense

CSA

than a phase with a smaller current signal.

Enhanced V responds to disturbances in V

Amplifier Gain (nominally 2.0 V/V), and the Startup Offset

is typically 0.60 V. The magnitude of the Ext_Ramp can be

calculated from

2

by

CORE

employing both “slow” and “fast” voltage regulation. The

internal error amplifier performs the slow regulation.

Depending on the gain and frequency compensation set by

the amplifier’s external components, the error amplifier will

typically begin to ramp its output to react to changes in the

output voltage in 1-2 PWM cycles. Fast voltage feedback is

Ext_Ramp + D @ (V * V

IN

)ń(RSx @ CSx @ f )

SW

CORE

For example, if V

at 0 A is set to 1.225 V with AVP

CORE

and the input voltage is 12.0 V, the duty cycle (D) will be

1.225/12.0 or 10.2%. Int_Ramp will be 125 mV 10.2/50 =

implemented by a direct connection from V

to the

25.5 mV. Realistic values for RSx, CSx and f are 5.6 kΩ,

CORE

SW

noninverting pin of the PWM comparator via the summation

with the inductor current, internal ramp, and the Startup

OFFSET. A rapid increase in load current will produce a

0.1 µF, and 200 kHz − using these and the previously

mentioned formula, Ext_Ramp will be 9.8 mV.

V

+ 1.225 V ) 0.60 V ) 25.5 mV

) 2.0 VńV @ 9.8 mVń2

+ 1.855 Vdc.

COMP

negative offset at V

and at the output of the summer.

CORE

This will cause the PWM duty cycle to increase almost

instantly. Fast feedback will typically adjust the PWM duty

cycle within 1 PWM cycle.

If the COMP pin is held steady and the inductor current

changes, there must also be a change in the output voltage.

Or, in a closed loop configuration when the output current

changes, the COMP pin must move to keep the same output

voltage. The required change in the output voltage or COMP

pin depends on the scaling of the current feedback signal and

is calculated as

As shown in Figure 14, an internal ramp (nominally 125 mV

at a 50% duty cycle) is added to the inductor current ramp at

the positive terminal of the PWM comparator. This additional

ramp compensates for propagation time delays from the

current sense amplifier (CSA), the PWM comparator, and the

MOSFET gate drivers. As a result, the minimum ON time of

the controller is reduced and lower duty cycles may be

achieved at higher frequencies. Also, the additional ramp

reduces the reliance on the inductor current ramp and allows

greater flexibility when choosing the output inductor and the

RSxCSx (x = 1 or 2) time constant (see Figure 15) of the

DV + RSx @ G

@ DI .

OUT

CSA

The single-phase power stage output impedance is

Single Stage Impedance+DV

ńDI +R @ G

OUT OUT S CSA

feedback components from V

to the CSx pin.

The multiphase power stage output impedance is the

single-phase output impedance divided by the number of

phases. The output impedance of the power stage determines

how the converter will respond during the first few

CORE

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. When the average output

current is zero, the COMP pin will be

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15

NCP5331

be considered. Cores with a low permeability material or a

large gap will usually have minimal inductance change with

temperature and load. Copper magnet wire has a

temperature coefficient of 0.39% per °C. The increase in

winding resistance at higher temperatures should be

SWNODE

V

FB

(V

OUT

)

considered when setting the overcurrent (I )threshold. If

LIM

a more accurate current sense is required than inductive

sensing can provide, current can be sensed through a resistor

as shown in Figure 14.

Internal Ramp

Current Sharing Accuracy

CSA Out w/

Exaggerated

Delays

Printed circuit board (PCB) traces that carry inductor

current can be used as part of the current sense resistance

depending on where the current sense signal is connected.

For accurate current sharing, the current sense inputs should

sense the current at relatively the same point for each phase

COMP-Of fset

CSA Out + Ramp + CS

REF

T1

T2

and the connection to the CS

pin should be made so that

REF

Figure 16. Open Loop Operation

no phase is favored. In some cases, especially with inductive

sensing, resistance of the PCB can be useful for increasing

the current sense resistance. The total current sense

resistance used for calculations must include any PCB trace

microseconds of a transient before the feedback loop has

repositioned the COMP pin.

resistance between the CSx input and the CS

carries inductor current.

input that

The peak output current can be calculated from

REF

(V

* V

* Offset)

CORE

COMP

(RSx @ G

Current Sense Amplifier (CSA) input mismatch and the

value of the current sense component will determine the

accuracy of the current sharing between phases. The worst

case Current Sense Amplifier input mismatch is ±5.0 mV

and will typically be within ±3.0 mV. The difference in peak

currents between phases will be the CSA input mismatch

divided by the current sense resistance. If all current sense

components are of equal resistance a 3.0 mV mismatch with

a 2.0 mΩ total sense resistance will produce a 1.5 A

difference in current between phases.

I

OUT,PEAK +

)

CSA

Figure 16 shows the step response of the COMP pin at a

fixed level. Before time T1 the converter is in normal steady

state operation. The inductor current provides a portion of

the PWM ramp through the Current Sense Amplifier. The

PWM cycle ends when the sum of the current ramp, the

internal ramp voltage and Startup OFFSET exceed the

voltage level of the COMP pin. At T1 the output current

increases and the output voltage sags. The next PWM cycle

begins and this PWM cycle continues longer than

previously. As a result, the current signal increases enough

External Ramp Size and Current Sensing

The internal ramp allows flexibility of current sense time

constant. Typically, the current sense RSxCSx time constant

should be equal to or slower than the inductor’s time

constant. If the RC time constant is chosen to be smaller

to make up for the lower voltage at the V pin and the cycle

FB

ends at T2. After T2 the output voltage remains lower than

at light load and the average current signal level (CSx

output) is raised so that the sum of the current and voltage

signal is the same as with the original load. In a closed loop

system the COMP pin would move higher to restore the

output voltage to the original level.

(faster) than L/R , the ac or transient portion of the current

L

sensing signal will be scaled larger than the dc portion. This

will provide a larger steady state ramp, but circuit

performance (i.e. transient response) will be affected and

must be evaluated carefully. The current signal will

overshoot during transients and settle at the rate determined

by RSx CSx. It will eventually settle to the correct dc level,

but the error will decay with the time constant of RSx CSx.

If this error is excessive it will effect transient response,

adaptive positioning and current limit. During a positive

current transient, the COMP pin will be required to

undershoot in response to the current signal in order to

Inductive Current Sensing

For lossless sensing, current can be sensed across the

output inductor as shown in Figure 15. In the diagram, Lx is

the output inductance and RLx is the inherent inductor

resistance. To compensate the current sense signal, the

values of RSx and CSx are chosen so that Lx/RLx = RSx

CSx. If this criteria is met, the current sense signal will be the

same shape as the inductor current and the voltage signal at

CSx will represent the instantaneous value of inductor

current. Also, the circuit can be analyzed as if a sense resistor

of value RLx was used as a sense resistor (RSx).

maintain the output voltage. Similarly, the V

signal will

DRP

overshoot and will produce too much transient droop in the

output voltage. Also, the hiccup mode current limit will have

a lower threshold for fast rise step loads than for slowly

rising output currents.

When choosing or designing inductors for use with

inductive sensing, tolerances and temperature effects should

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16

NCP5331

The waveforms in Figure 17 show a simulation of the

current sense signal and the actual inductor current during

a positive step in load current with values of L = 500 nH,

R = 1.6 mΩ, RSx = 20 k and CSx = 0.01 µF. For ideal current

L

signal compensation the value of RSx should be 31 kΩ. Due

to the faster than ideal RC time constant there is an overshoot

of 50% and the overshoot decays with a 200 µs time

constant. With this compensation the I

pin threshold

LIM

must be set more than 50% above the full load current to

avoid triggering hiccup mode during a large output load

step.

Current Limit, Hiccup Mode and Overcurrent Timer

The individual phase currents are summed and low-pass

filtered to create an average current signal. The average

current is then compared to a user adjustable voltage at the

I

pin. If the I

voltage is exceeded, the fault latch is set,

LIM

switching stops, and the COMP pin is discharged until it

decreases to 0.27 V. At this point, the fault latch is reset, the

COMP voltage will begin to rise and a new startup cycle

begins. During startup, the output voltage and load current

Figure 17. Inductive Sensing Waveform During a

Load Step with Fast RC Time Constant (50 µs/div)

will increase until either regulation is achieved or the I

LIM

voltage is again exceeded. The converter will continue to

operate in “hiccup mode” until the fault condition is

corrected or the overcurrent timer expires.

When an overcurrent fault occurs the converter will enter

a low duty cycle hiccup mode. During hiccup mode the

converter will not switch from the time a fault is detected

until the soft start capacitor (C ) has discharged below the

C2

COMP Discharge Threshold and then charged back up

above the Channel Start Up Offset. Figure 18 shows the

NCP5331 operating in hiccup mode with the converter

output shorted to GND. Hiccup mode will continue until the

overcurrent timer terminates operation.

The overcurrent timer sets a limit to how long the

converter will operate in hiccup mode. Placing a capacitor

from the C

pin to GND sets the length of time - a larger

OVC

Figure 18. Hiccup Mode Operation

capacitor sets a longer time. The first hiccup pulse starts the

timer by turning on a current source that charges the

capacitor at the C

pin. If the voltage at the C

pin rises

OVC

to 3 V before the output voltage exceeds the PGD threshold,

then the overcurrent latch is set, COMP is discharged, and

PGD is latched Low. Once set, the overcurrent latch will

hold the converter in this state until the input voltage, either

V

CCL

or V

, is cycled. Conversely, if the timer starts and

CCH

either the output short circuit is removed or the load is

decreased before the overcurrent timer expires, PGD will

transition High after its programmed delay time and the

timer will be reset. The nominal overcurrent time can be

calculated using the following equation.

t

+ C

@ (OVC * OVC

THRESH

)ńI

MIN OVC

OVC

@ (3.0 V * 0.25 V)ń5.0 mA

5

@ 5.5 10

Figure 19 shows the overcurrent timer terminating hiccup

mode when C charges up to 3.0 V.

Figure 19. Overcurrent Timer Operation

OVC

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NCP5331

NOTE: Using the lower MOSFETs to prevent overvoltage

is not adequate if the MOSFETs are turned OFF at

NOTE: Even if the lower MOSFETs remain ON after

UVLO, there is not enough gate drive voltage to

prevent V from reaching 4.0 V.

the UVLO threshold - V

reaches 4.0 V within

CORE

100 µs.

Figure 20. Overvoltage Occurs with UVLO Enabled

Figure 21. Overvoltage Occurs with UVLO Disabled

Overvoltage Protection

the CB

pin. This additional MOSFET will clamp V

CORE

OUT

The NCP5331 provides a comprehensive level of

overvoltage protection. Overvoltage protection (OVP)

addresses the following five cases (in decreasing level of

difficulty):

and dissipate the remainder of the energy in the system. The

CB circuitry is powered by 5 V and is not disabled

OUT

SB

during UVLO. Also, the CB

pin will always have

OUT

adequate gate drive to enhance the lower MOSFET. The

OVP circuits in the NCP5331 are not effected when the ATX

1. Normal operation, upper MOSFET shorts

2. Upper MOSFET shorted, turn on the ATX power

3. Normal operation, open the voltage feedback signal

4. Normal operation, ground the voltage feedback

signal

supply current limits and V is removed. Figure 22 and

IN

Figure 23 document successful operation of the CB

OUT

circuitry when an upper MOSFET is shorted during normal

operation with 0 A and 45 A loading.

5. Open the voltage feedback signal, apply ATX power

By far the most difficult overvoltage scenario is when the

upper MOSFET shorts during normal operation. The energy

stored in the output filters of both the ATX supply and the

dc/dc converter must be dissipated very quickly or an

overvoltage condition will occur. When the upper MOSFET

The second most difficult overvoltage scenario is when an

upper MOSFET is shorted and the ATX power is applied. In

this case, V

is equal to V due to the shorted upper

CORE

IN

MOSFET. When V reaches the maximum rating for the

IN

CPU (2.2 V) adequate gate drive voltage is not available to

enhance the lower MOSFETs or crowbar device enough to

protect the CPU. A typical “Logic Level” MOSFET will

conduct only 100-300 µA for a gate drive of 2.0-2.5 V

shorts, V

rises and the error amplifier, due to the closed

CORE

loop control, will within approximately 400 ns, command

the upper MOSFETs (those that aren’t shorted) to turn OFF

and all the lower MOSFETs to turn ON. This will cause two

(R

DS(on)

= 6 kΩ to 25 kΩ). The R

of the crowbar

DS(on)

device must be lower than 15 mΩ during startup to prevent

things to occur: V

will stop increasing, and a very high

damage to the CPU. The NCP5331 avoids this problem by

CORE

current will be drawn from the ATX supply. The current

limit in the ATX supply should become active and the input

voltage to the converter will be removed. Now, when the

input voltage drops below the NCP5331’s UVLO threshold

the lower MOSFETs will be turned OFF. At this point, a fair

amount of the energy in the system will have been

dissipated, however, the converter’s output voltage will

begin to rise again as shown in Figure 20. Even if the lower

MOSFETs are not turned OFF at the UVLO threshold, as

taking advantage of the 5 V voltage from the ATX supply.

SB

If V is less than 5 V , then 5 V will be used to enhance

IN

SB

the crowbar device. Most modern MOSFETs will be less

than 10 mΩ for a V greater than 4.5 V. Figure 24 shows

GS

the NCP5331 preventing V

from exceeding 2.0 V with

CORE

a shorted upper MOSFET during startup.

If the voltage feedback signal (COREFB+) is broken, a

high value internal pull-up resistor will cause V

(and

FFB

V ) to float higher in voltage. As V

FB

(and V ) are

FFB FB

V

IN

decays, adequate gate drive voltage will not exist to

pulled higher, the error amplifier will “think” V

is too

CORE

fully enhance the devices and the CPU may be damaged.

This case is shown in Figure 21.

high and command a lower and lower duty cycle until

is driven to 0 V. Without the internal pull-up resistor

V

CORE

The NCP5331 avoids the problems with UVLO and the

the error amplifier would command 100% duty cycle and

would be driven very high, damaging the CPU.

gate drive voltage. When V

exceeds 2.05 V, the

V

CORE

NCP5331 will activate an external crowbar MOSFET via

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NCP5331

NOTE: The NCP5331 maintains V

< 2.2 V when an

NOTE: The NCP5331 maintains V

< 2.2 V when an

CORE

upper MOSFET shorts with 45 A loading.

upper MOSFET shorts during no-load operation.

Figure 23. NCP5331 Prevents Overvoltage at 45 A

Figure 22. NCP5331 Prevents Overvoltage at 0 A

If the voltage feedback signal (COREFB+) is accidentally

grounded (but V

is not), the error amplifier will respond

CORE

by increasing the duty cycle. Of course, this will cause V

CORE

to rise. When V

reaches 2.0 V, the internal crowbar

CORE

circuit will be activated and the overcurrent/overvoltage latch

will be set. This latch will discharge COMP, turn OFF the

upper MOSFETs, and turn ON the lower MOSFETs. The

overcurrent/overvoltage latch will hold the controller in this

state until the input power is cycled.

Transient Response and Adaptive Positioning

For applications with fast transient currents the output

filter is frequently sized larger than ripple currents require in

order to reduce voltage excursions during load transients.

Adaptive voltage positioning can reduce peak-to-peak

output voltage deviations during load transients and allow

for a smaller output filter. The output voltage can be set

higher than nominal at light loads to reduce output voltage

sag when the load current is applied. Similarly, the output

voltage can be set lower than nominal during heavy loads to

reduce overshoot when the load current is removed. For low

current applications a droop resistor can provide fast

accurate adaptive positioning. However, at high currents the

loss in a droop resistor becomes excessive. For example; in

a 50 A converter a 1 mΩ resistor to provide a 50 mV change

in output voltage between no load and full load would

dissipate 2.5 W.

NOTE: The NCP5331 maintains V

< 2.2 V when an

CORE

upper MOSFET is shorted and ATX power is applied.

Figure 24. NCP5331 Prevents Overvoltage at Startup

Normal

Fast Adaptive Positioning

SlowAdaptive Positioning

Limits

Lossless adaptive positioning is an alternative to using a

droop resistor, but must respond to changes in load current.

Figure 25 shows how adaptive positioning works. The

waveform labeled “Normal” shows a converter without

adaptive positioning. On the left, the output voltage sags

when the output current is stepped up and later overshoots

when current is stepped back down. With fast (ideal)

adaptive positioning the peak to peak excursions are cut in

half. In the slow adaptive positioning waveform the output

voltage is not repositioned quickly enough after current is

stepped up and the upper limit is exceeded.

Figure 25. Adaptive Positioning

The controller can be configured to adjust the output

voltage based on the output current of the converter. (Refer

to the application schematic in Figure 1). To set the no-load

positioning, a resistor is placed between the output voltage

and V pin. The V bias current will develop a voltage

FB

across the resistor to adjust the no-load output voltage. The

bias current is dependent on the value of R as shown

in the data sheets.

V

FB

OSC

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19

NCP5331

During no load conditions the V

pin is at the same

DRP

voltage as the V pin, so none of the V bias current flows

FB

through the V

resistor. When output current increases

DRP

the V

pin increases proportionally and the V

DRP

current offsets the V bias current and causes the output

FB

voltage to decrease.

The response during the first few microseconds of a load

transient are controlled primarily by power stage output

impedance and the ESR and ESL of the output filter. The

transition between fast and slow positioning is controlled by

the total ramp size and the error amp compensation. If the

current signal (external ramp) size is too large or the error

amp too slow there will be a long transition to the final

voltage after a transient. This will be most apparent with

lower capacitance output filters.

NOTE: The PGD timer insures that PGD will transition high

when V is in regulation.

CORE

Error Amp Compensation, Tuning, and Soft Start

Figure 26. Power Good Delay Operation

The transconductance error amplifier requires

a

capacitance (C + C in the Applications Diagram)

C1

C2

between the COMP pin and GND for two reasons. First, this

capacitance stabilizes the transconductance error amplifier.

Values less than a few nF may cause oscillations of the

COMP voltage and increase the output voltage jitter.

Second, this capacitance sets the soft start and hiccup mode

slopes. The internal error amplifier will source

approximately 30 µA during soft start and hiccup mode. No

switching will occur until the COMP voltage exceeds the

Setting up and tuning the error amplifier is a three step

process. First, the no-load and full-load adaptive voltage

positioning (AVP) are set using R and R , respectively.

F1

DRP

Second, the current sense time constant and error amplifier

gain are adjusted with RSx and C while monitoring

A1

V

CORE

during transient loading. Lastly, the peak-to-peak

voltage ripple on the COMP pin is examined when the

converter is fully loaded to insure low output voltage jitter.

The exact details of this process are covered in the Design

Procedure section.

Channel Startup Offset (nominally 0.6 V). If C is set to

C2

0.1 µF the 30 µA from the error amplifier will allow the

output to ramp up or down at approximately 30µ A/0.1 µF

or 0.3 V/ms or 1.2 V in 4 ms.

Undervoltage Lockout (UVLO)

The controller has undervoltage lockout comparators

monitoring two pins. One, intended for the logic and

The COMP voltage will ramp up to the following value.

low- side drivers, is connected to the V

pin with an 8.5 V

V

+

V

@ 0 A ) Channel_Startup_Offset

CCL

COMP

CORE

turn-on and 6.15 V turn-off threshold. A second, for the

high side drivers, is connected to the V pin with an 8.5 V

) Int_Ramp ) G

@ Ext_Rampń2

CSA

CCH

turn-on and 6.75 V turn-off threshold. A UVLO fault sets

the fault latch which forces switching to stop and the upper

and lower gate drivers produce a logic low (i.e., all the

MOSFETs are turned OFF). Power good (PGD) is pulled

low when UVLO occurs. The overcurrent/overvoltage latch

is reset by the UVLO signal.

The COMP pin will disable the converter when pulled

below the COMP Discharge Threshold (nominally 0.27 V).

The RC network between the COMP pin and the soft start

capacitor (R , C ) allows the COMP voltage to slew

C1

quickly during transient loading of the converter. Without

this network the error amplifier would have to drive the large

soft start capacitor (C ) directly, which would drastically

C2

Power Good (PGD) Delay Time

limit the slew rate of the COMP voltage. The R /C

C1 C1

When V

is less than the power good threshold,

CORE

network allows the COMP voltage to undergo a step change

of approximately R

87.5% DAC, or greater than 2.0 V the open-collector

power good pin (PGD) will be pulled low by the NCP5331.

I

.

C1 COMP

The capacitor (C ) between the COMP pin and the error

A1

When V

is in regulation PGD will become high

CORE

amplifier’s inverting input (the V pin) and the parallel

FB

impedance. An external pull-up resistor is required on PGD.

During soft start, when V reaches the power good

combination of the resistors R and R

determine the

F1

DRP

CORE

bandwidth of the error amplifier. The gain of the error

amplifier crosses 0 dB at a high enough frequency to give a

quick transient response, but well below the switching

frequency to minimize ripple and noise on the COMP pin.

threshold, 87.5% DAC, then the “longer” of two timers will

dictate when PGD becomes high impedance. One timer is

internally set to 200 µs and can not be changed. Placing a

capacitor from the C

pin to GND sets the second

PGD

A capacitor in parallel with the R resistor (C ) adds a zero

F1

programmable timer. When V

crosses the PGD

CORE

to boost phase near the crossover frequency to improve loop

stability.

threshold, a current source will charge C

starting at

PGD

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20

NCP5331

0.25 V and “timing out” at 3 V. The current delivered to the

capacitor (I ) is a function of the R resistor

kept low at turn-off, preventing V

below ground.

from being pulled

CORE

C

PGD

OSC

according to the following equation.

However, if using the “Timed Hiccup Mode Current

Limit” feature with Method A, the Covc pin will time out

when the Ilim pin is pulled low, and the NCP5331 will not

turn back on (after time out) unless the power is recycled.

This can be avoided by adding another transistor to the Covc

pin, thereby keeping it low while the part is disabled.

The second method (Method B in Figure 28) is to pull low

on the NCP5331’s comp pin. With this method, GHx will be

low and GLx will be high while the part is disabled.

However, under Method B, if the part is disabled at

turn-on, and if using the “Timed Hiccup Mode Current

Limit” feature, the Covc pin will again time out and the

NCP5331 will not be able to be turned on after the time out

has occurred. This too can be avoided by the use of a

transistor at the Covc pin keeping it low while the part is

disabled.

I

+ 0.52 VńR

OSC

PGD

The programmed delay time can be calculated from

t

+ C

@ (PGD

THRESH

@ (3.0 V * 0.25 V)ńI

* PGD

)ńI

MIN PGD

PGD

The programmable timer may be disabled (set to 0) by

connecting the C pin to 5 V . This will set the PGD

PGD

REF

delay time to the internal delay of 200 µs. Figure 26

demonstrates the use of the programmable PGD timer (set

to 6.0 ms) to allow PGD to transition high when V

safely within the regulation limits for the processor (DAC

is

CORE

±50 mV).

Implementing an Enable Function

An Enable function may be implemented on the NCP5331

in one of two ways. The first method (Method A in

Figure 27) is to pull low on the Ilim pin. This method is the

preferred method, as both the GHx and the GLx pins will be

If using Method B but not with a transistor at the Covc pin,

a 1.0 K resistor must be added between the drain of the

transistor and the Comp pin to prevent the current limit from

being tripped when the Comp pin is quickly pulled low.

COMP

I

*R

LIM

1.0 k

3

QCOMP

BSS123

QI

BSS123

LIM

Hi to Disable

Lo to Enable

Hi to Disable

Lo to Enable

1

2

C

OVC

3

2

3

2

**QC

BSS123

*QC

BSS123

OVC

1

*Needed if not using QCovc

**Allows Disabling at Turn-On

*Needed if using ‘Timed

Hiccup Mode Current Limit’

(when using ‘Timed Hiccup Mode Current Limit’)

Figure 27. Enable Method A

Figure 28. Enable Method B

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21

NCP5331

Power Dissipation

I

, I

are typical device quiescent currents and

CCL CCLx CCH

NCP5331 power dissipation may be approximated by the

following equation:

can be found under the General Electrical Specifications.

Q

is the sum of the High-Side MOSFets total gate

THighFETs

P

+ F

· (V

· Q

THighFETs

loss

SW

CCH

charge

) V

· Q

) ) P

CCLx

TLowFETs Quiescent

Q

is the sum of the Low-Side MOSFets total gate

TLowFETs

where:

charge

Figure 29 shows device temperature rise versus switching

frequency at various gate drive voltage combinations using

ON Semiconductor’s NTD60N03 (Qt = 31nC at 5.0 V) as

the high-side MOSFet and NTD80N02 (Qt = 39nC at 7.0 V)

as the low-side MOSFet. Using other MOSFets will of

course result in different losses, but the general conclusion

will be the same.

P

+ V

· I

CCL CCL

) 2 · V

·I

CCLx CCLx

Quiescent

) (V ) V ) · I

CCH

in CCH

F

is the switching frequency

SW

V

is 12 V

CCL

V

is the low-side gate drive voltage and may be varied

CCLx

between 5.0 and 12 V

If trying to drive 2 lower MOSFets at frequencies higher

than 200 KHz, it may be necessary to reduce the low-side

gate drive voltage.

V

is the high-side gate drive voltage and is between 4.5

CCH

and 7.0 V

V is the input voltage to the converter and is either 5.0 or

in

12 V

84

81

78

V

= 7.0 V;

= 12 V;

CCH

75

72

69

66

63

60

57

54

51

48

45

42

39

36

33

30

27

24

CCLx

2 Low-Side FETS

V

= 4.5 V;

= 12 V;

V

= 7.0 V;

= 12 V;

CCH

CCLx

2 Low-Side FETS

1 Low-Side FETS

V

= 4.5 V;

= 12 V;

CCH

CCLx

1 Low-Side FETS

V

= 7.0 V;

= 12 V;

CCH

CCLx

2 Low-Side FETS

V

4.5 V;

= 12 V;

CCH

CCLx

2 Low-Side FETS

100

150

200

250

300 350

FREQUENCY (kHz)

Figure 29. Calculated NCP5331 temperature rise (LQFP-32 package)

versus frequency at various typical gate drive voltage combinations

with typical ON Semiconductor MOSFets.

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22

NCP5331

Layout Guidelines

5. Place the frequency setting resistor (R

) close to

OSC

With the fast rise, high output currents of microprocessor

applications, parasitic inductance and resistance should be

considered when laying out the power, filter and feedback

signal sections of the board. Typically, a multilayer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to route the currents away from the

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Gate drives experience high di/dt during switching and the

inductance of gate drive traces should be minimized. Gate

drive traces should be kept as short and wide as practical and

should have a return path directly below the gate trace.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

The current sense signals are typically tens of millivolts.

Noise pick-up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as the switch node and gate drive signals. If the

current signals are taken from a location other than directly

at the inductor any additional resistance between the

pick-off point and the inductor appears as part of the

inherent inductor resistances and should be considered in

design calculations. The capacitors for the current feedback

networks should be placed as close to the current sense pins

as practical. After placing the NCP5331 control IC, follow

these guidelines to optimize the layout and routing:

the R

pin. The R

pin is very sensitive to

OSC

noise. Route noisy traces, such as the SWNODEs

and GATE traces, away from the R

resistor.

pin and

OSC

6. Place the MOSFETs and output inductors to

reduce the size of the noisy SWNODEs. However,

there is a trade-off between reducing the size of

the SWNODEs for noise reduction and providing

adequate heat-sinking for the synchronous

MOSFETs.

7. Place the input inductor and input capacitor(s) near

the Drain of the control (upper) MOSFETs. There

is a trade-off between reducing the size of this

node to save board area and providing adequate

heat-sinking for the control (upper) MOSFETs.

8. Place the output capacitors (electrolytic and

ceramic) close to the processor socket or output

connector.

9. The trace from the SWNODEs to the current sense

components (R , R ) will be very noisy. Route

S1 S2

this away from more sensitive, low-level traces.

The Ground layer can be used to help isolate this

trace.

10. The Gate traces are very noisy. Route these away

from more sensitive, low-level traces. Try to keep

each Gate signal on one layer and insure that there

is an uninterrupted return path directly below the

Gate trace. The Ground layer can be used to help

isolate these traces.

11. Gate driver returns, GND1 and GND2, should not

be connected to LGND, but instead directly to the

ground plane.

12. Try not to “daisy chain” connections to Ground

from one via. Ideally, each connection to Ground

will have its own via located as close to the

component as possible.

1. Place the 1 µF ceramic power-supply bypass

capacitors close to their associated pins: V

,

CCL

V

, V

and V .

13. Use a slot in the ground plane to prevent high

currents from flowing beneath the control IC. This

slot should form an “island” for signal ground

under the control IC. “Signal ground” and “power

ground” must be separated. Examples of signal

CCH

CCL1

CCL2

2. Place the MOSFETs to minimize the length of the

Gate traces. Orient the MOSFETs such that the

Drain connections are away from the controller and

the Gate connections are closest to the controller.

3. Place the components associated with the internal

ground include the capacitors at COMP, CS

,

REF

error amplifier (R , C , C , C , R , C

,

and 5V , the resistors at R

and I , and the

OSC LIM

F1 F1 C1 C2 C1 A1

REF

R

V

) to minimize the trace lengths to the pins

LGND pin to the controller. Examples of power

ground include the capacitors to V and V

CCL1

DRP

, V

and COMP.

FB

DRP

CCH

4. Place the current sense components (R , R ,

and V

, the Source of the synchronous

S1 S2

CCL2

C , C , R , C , C ) near the CS1, CS2, and

MOSFETs, and the GND1 and GND2 pins of the

controller.

S1 S2

S

SA SB

CS

pins.

REF

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23

NCP5331

2. Output Inductor Selection

14. The CS

sense point should be equidistant

REF

The output inductor may be the most critical component

in the converter because it will directly effect the choice of

other components and dictate both the steady-state and

transient performance of the converter. When selecting an

inductor the designer must consider factors such as dc

current, peak current, output voltage ripple, core material,

magnetic saturation, temperature, physical size, and cost

(usually the primary concern).

In general, the output inductance value should be as low

and physically small as possible to provide the best transient

response and minimum cost. If a large inductance value is

used, the converter will not respond quickly to rapid changes

in the load current. On the other hand, too low an inductance

value will result in very large ripple currents in the power

components (MOSFETs, capacitors, etc) resulting in

increased dissipation and lower converter efficiency. Also,

increased ripple currents will force the designer to use

higher rated MOSFETs, oversize the thermal solution, and

use more, higher rated input and output capacitors - the

converter cost will be adversely effected.

between the output inductors to equalize the PCB

resistance added to the current sense paths. This

will insure acceptable current sharing. Also, route

the CS

connection away from noisy traces such

REF

as the SWNODEs and GATE traces. If noise from

the SWNODEs or GATE signals capacitively

couples to the CSREF trace the external ramps

will be very noisy and voltage jitter will result.

15. Ideally, the SWNODEs are exactly the same shape

and the current sense points (connections to R

S1

and R ) are made at identical locations to equalize

S2

the PCB resistance added to the current sense paths.

This will help to insure acceptable current sharing.

16. Place the 1 µF ceramic capacitors, C and C ,

P1

P2

close to the drains of the MOSFETs Q1 and Q2,

respectively.

17. If snubbers are used, they must be placed very

close to their associated MOSFETs and

SWNODE. The connections to the snubber

components should be as short as possible.

One method of calculating an output inductor value is to

size the inductor to produce a specified maximum ripple

current in the inductor. Lower ripple currents will result in

less core and MOSFET losses and higher converter

efficiency. Equation 3 may be used to calculate the

minimum inductor value to produce a given maximum

ripple current (α) per phase. The inductor value calculated

by this equation is a minimum because values less than this

will produce more ripple current than desired. Conversely,

higher inductor values will result in less than the maximum

ripple current.

Design Procedure

1. Output Capacitor Selection

The output capacitors filter the current from the output

inductor and provide a low impedance for transient load

current changes. Typically, microprocessor applications

will require both bulk (electrolytic, tantalum) and low

impedance, high frequency (ceramic) types of capacitors.

The bulk capacitors provide “hold up” during transient

loading. The low impedance capacitors reduce steady-state

ripple and bypass the bulk capacitance when the output

current changes very quickly. The microprocessor

manufacturers usually specify a minimum number of

ceramic capacitors. The designer must determine the

number of bulk capacitors.

(3)

(V * V

IN

(a @ I

O,MAX

) @ V

CORE

@ V @ f

Lo

MIN

+

)

IN SW

α is the ripple current as a percentage of the maximum

output current per phase (α = 0.15 for ±15%, α = 0.25 for

±25%, etc). If the minimum inductor value is used, the

inductor current will swing ±α% about its value at the center

(half the dc output current for a two-phase converter).

Therefore, for a two-phase converter, the inductor must be

designed or selected such that it will not saturate with a peak

Choose the number of bulk output capacitors to meet the

peak transient requirements. The following formula can be

used to provide a starting point for the minimum number of

bulk capacitors (N

).

OUT,MIN

(1)

DI

O,MAX

N

+ ESR per capacitor @

OUT,MIN

current of (1 + α) I

/2.

DV

O,MAX

The maximum inductor value is limited by the transient

response of the converter. If the converter is to have a fast

transient response then the inductor should be made as small

as possible. If the inductor is too large its current will change

too slowly, the output voltage will droop excessively, more

bulk capacitors will be required, and the converter cost will

be increased. For a given inductor value, its interesting to

determine the time required to increase or decrease the

current.

In reality, both the ESR and ESL of the bulk capacitors

determine the voltage change during a load transient

according to

(2)

ńDt) @ ESL ) DI @ ESR

O,MAX

DV

+ (DI

O,MAX

Unfortunately, capacitor manufacturers do not specify the

ESL of their components and the inductance added by the

PCB traces is highly dependent on the layout and routing.

Therefore, it is necessary to start a design with slightly more

than the minimum number of bulk capacitors and perform

transient testing or careful modeling/simulation to

determine the final number of bulk capacitors.

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24

NCP5331

For increasing current

(8)

I

+ I

O,MAX

ń2 ) DI ń2

Lo

Lo,MAX

(3.1)

Dt

INC

+ Lo @ DI ń(V * V

IN

)

CORE

O

∆I

C,IN

= I

- I

C,MAX C,MIN

I

For decreasing current

C,MAX

(3.2)

Dt

DEC

+ Lo @ DI ń(V

)

CORE

O

I

C,MIN

t

T/2

ON

For typical processor applications with output voltages

less than half the input voltage, the current will be increased

much more quickly than it can be decreased. It may be more

difficult for the converter to stay within the regulation limits

when the load is removed than when it is applied - excessive

overshoot may result.

0 A

FET Off,

Caps Charging

-I

IN,AVG

FET On,

Caps Discharging

The output voltage ripple can be calculated using the

output inductor value derived in this Section (Lo

), the

MIN

number of output capacitors (N

capacitor ESR determined in the previous Section.

) and the per

Figure 30. Input Capacitor Current for a

Two-Phase Converter

OUT,MIN

V

+ (ESR per cap ń N

) @

(4)

OUT,P- P

OUT,MIN

) @ D ń (Lo

I

is the minimum output inductor current.

Lo,MIN

Ǌ

ǋ

@ f )

MIN SW

(V * #Phases @ V

IN

CORE

(9)

I

+ I

ń2 * DI ń2

Lo

Lo,MIN

O,MAX

This formula assumes steady-state conditions with no

∆I is the peak-to-peak ripple current in the output

Lo

more than one phase on at any time. The second term in

Equation 4 is the total ripple current seen by the output

capacitors. The total output ripple current is the “time

summation” of the two individual phase currents that are

180 degrees out-of-phase. As the inductor current in one

phase ramps upward, current in the other phase ramps

downward and provides a canceling of currents during part

of the switching cycle. Therefore, the total output ripple

current and voltage are reduced in a multiphase converter.

inductor of value L .

o

(10)

DI + (V * V

Lo IN

) @ Dń(Lo @ f )

SW

CORE

For the two-phase converter, the input capacitor(s) rms

current is then

(11)

2

I

+ [2D @ (I

) I

@ DI

C,IN

CIN,RMS

C,MIN

2

1ń2

@ (1 * 2D)]

) DI

ń3) ) I

IN,AVG

C,IN

Select the number of input capacitors (N ) to provide the

3. Input Capacitor Selection

IN

rms input current (I

rating per capacitor (I

) based on the rms ripple current

).

The choice and number of input capacitors is primarily

determined by their voltage and ripple current ratings. The

designer must choose capacitors that will support the worst

case input voltage with adequate margin. To calculate the

number of input capacitors one must first determine the total

rms input ripple current. To this end, begin by calculating the

average input current to the converter.

CIN,RMS

RMS,RATED

(12)

N

+ I

ńI

IN

CIN,RMS RMS,RATED

For a two-phase converter with perfect efficiency (η = 1),

the worst case input ripple current will occur when the

converter is operating at a 25% duty cycle. At this operating

point, the parallel combination of input capacitors must

support an rms ripple current equal to 25% of the converter’s

dc output current. At other duty cycles, the ripple current

will be less. For example, at a duty cycle of either 10% or

40%, the two-phase input ripple current will be

approximately 20% of the converter’s dc output current.

In general, capacitor manufacturers require derating to the

specified ripple current based on the ambient temperature.

More capacitors will be required because of the current

derating. The designer should be cognizant of the ESR of the

input capacitors. The input capacitor power loss can be

calculated from

(5)

I

+ I @ Dńh

O,MAX

IN,AVG

where

D

is the duty cycle of the converter,

D = V /V ,

CORE IN

η

is the specified minimum efficiency,

I

is the maximum converter output current.

O,MAX

The input capacitors will discharge when the control FET

is ON and charge when the control FET is OFF as shown in

Figure 30.

The following equations will determine the maximum and

minimum currents delivered by the input capacitors.

2

+ I @ ESR_per_capacitorńN

CIN,RMS IN

(13)

P

CIN

(6)

(7)

I

+ I

ńh * I

C,MAX

Lo,MAX

ńh * I

Lo,MIN

IN,AVG

Low ESR capacitors are recommended to minimize losses

and reduce capacitor heating. The life of an electrolytic

capacitor is reduced 50% for every 10°C rise in the

capacitor’s temperature.

I

+ I

C,MIN

IN,AVG

I

is the maximum output inductor current.

Lo,MAX

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25

NCP5331

V

OUT

MAX dI/dt occurs in

first few PWM cycles.

I

Li

I

Lo

Vi(t = 0) = 12 V

Q1

SWNODE

Vo(t = 0) = 1.225 V

Li

TBD

Lo

729 nH

V

Ci

+

Co

Ci

5 × 16MBZ1500M10X20

6 × 16MBZ1000M10X16

Q2

Vi

+

-

26 u(t)

12 V

ESR

Ci

Co

13 m/5 = 2.6 m

19 m/6 = 3.2 m

Figure 31. Calculating the Input Inductance

4. Input Inductor Selection

Current changes slowly in the input inductor so the input

capacitors must initially deliver the vast majority of the

input current. The amount of voltage drop across the input

The use of an inductor between the input capacitors and

the power source will accomplish two objectives. First, it

will isolate the voltage source and the system from the noise

generated in the switching supply. Second, it will limit the

inrush current into the input capacitors at power up. Large

inrush currents will reduce the expected life of the input

capacitors. The inductor’s limiting effect on the input

current slew rate becomes increasingly beneficial during

load transients.

The worst case input current slew rate will occur during

the first few PWM cycles immediately after a step-load

change is applied as shown in Figure 31. When the load is

applied, the output voltage is pulled down very quickly.

Current through the output inductors will not change

instantaneously so the initial transient load current must be

conducted by the output capacitors. The output voltage will

step downward depending on the magnitude of the output

capacitors (∆V ) is determined by the number of input

Ci

capacitors (N ), their per capacitor ESR (ESR ), and the

IN

current in the output inductor according to

(17)

+ ESR ńN @ dI ńdt @ t

IN IN Lo ON

DV

Ci

+ ESR ńN @ dI ńdt @ Dńf

IN IN Lo

SW

Before the load is applied, the voltage across the input

inductor (V ) is very small - the input capacitors charge to

Li

the input voltage, V . After the load is applied the voltage

IN

drop across the input capacitors, ∆V , appears across the

Ci

input inductor as well. Knowing this, the minimum value of

the input inductor can be calculated from

(18)

+ V ń dI ńdt

Li IN MAX

Li

MIN

+ DV ń dI ńdt

Ci IN MAX

current (I

capacitors (ESR

capacitors (N

), the per capacitor ESR of the output

O,MAX

where dI /dt

slew rate.

is the maximum allowable input current

IN

MAX

), and the number of the output

OUT

) as shown in Figure 31. Assuming the load

OUT

The input inductance value calculated from Equation 18

is relatively conservative. It assumes the supply voltage is

very “stiff” and does not account for any parasitic elements

that will limit dI/dt such as stray inductance. Also, the ESR

values of the capacitors specified by the manufacturer’s data

sheets are worst case high limits. In reality input voltage

“sag,” lower capacitor ESRs, and stray inductance will help

reduce the slew rate of the input current.

As with the output inductor, the input inductor must

support the maximum current without saturating the

magnetic. Also, for an inexpensive iron powder core, such

as the -26 or -52 from Micrometals, the inductance “swing”

with dc bias must be taken into account - inductance will

decrease as the dc input current increases. At the maximum

input current, the inductance must not decrease below the

minimum value or the dI/dt will be higher than expected.

current is shared equally between the two phases, the output

voltage at full, transient load will be

(14)

V

+

CORE,FULL- LOAD

V

* (I

O,MAX

ń2) @ ESR

ńN

OUT OUT

CORE,NO- LOAD

When the control MOSFET (Q1 in Figure 31) turns ON,

the input voltage will be applied to the opposite terminal of

the output inductor (the SWNODE). At that instant, the

voltage across the output inductor can be calculated as

(15)

DV + V * V

Lo

IN

CORE,FULL- LOAD

CORE,NO- LOAD

V

* V

+

IN

) (I

ń2) @ ESR

ńN

OUT OUT

O,MAX

The differential voltage across the output inductor will

cause its current to increase linearly with time. The slew rate

of this current can be calculated from

dI ńdt + DV ńLo

Lo Lo

(16)

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NCP5331

5. MOSFET and Heatsink Selection

Power dissipation, package size, and thermal solution drive

MOSFET selection. To adequately size the heat sink, the

design must first predict the MOSFET power dissipation.

Once the dissipation is known, the heat sink thermal

impedance can be calculated to prevent the specified

maximum case or junction temperatures from being exceeded

at the highest ambient temperature. Power dissipation has two

primary contributors: conduction losses and switching losses.

The control or upper MOSFET will display both switching

and conduction losses. The synchronous or lower MOSFET

will exhibit only conduction losses because it switches into

nearly zero voltage. However, the body diode in the

synchronous MOSFET will suffer diode losses during the

nonoverlap time of the gate drivers.

I

D

V

GATE

V

GS_TH

Q

V

DRAIN

GS1

GS2

GD

Figure 32. MOSFET Switching Characteristics

For the upper or control MOSFET, the power dissipation

can be approximated from

(25)

Q

+ Q

) Q

gs2 gd

switch

I is the output current from the gate driver IC.

g

(19)

2

P

+ (I

@ R

)

DS(on)

D,CONTROL

RMS,CNTL

@ Q ńI @ V @ f

V

IN

is the input voltage to the converter.

) (I

)

Lo,MAX

switch g IN SW

f

is the switching frequency of the converter.

sw

Q

is the reverse recovery charge of the lower MOSFET.

is the sum of all the MOSFET output charges.

RR

oss

) (Q

ń2 @ V @ f

) ) (V @ Q

@ f )

RR SW

oss

IN SW IN

The first term represents the conduction or IR losses when

the MOSFET is ON, while the second term represents the

switching losses. The third term is the losses associated with

the control and synchronous MOSFET output charge when

the control MOSFET turns ON. The output losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control FET. The fourth term is the loss

due to the reverse recovery time of the body diode in the

synchronous MOSFET. The first two terms are usually

adequate to predict the majority of the losses.

For the lower or synchronous MOSFET, the power

dissipation can be approximated from

2

P

+ (I

RMS,SYNCH

@ R

)

DS(on)

D,SYNCH

) (Vf

(26)

@ I

diode O,MAX

ń2 @ t_nonoverlap @ f )

SW

The first term represents the conduction or IR losses when

the MOSFET is ON, and the second term represents the

diode losses that occur during the gate nonoverlap time.

All terms were defined in the previous discussion for the

control MOSFET with the exception of

I

is the rms value of the trapezoidal current in the

RMS,CNTL

(27)

control MOSFET.

I

+ [(1 * D)

RMS,SYNCH

(20)

2

I

+ [D @ (I

Lo,MAX

) I

@ I

2

)ń3]

1ń2

RMS,CNTL

Lo,MAX Lo,MIN

@ (I

Lo,MAX

) I

@ I

) I

Lo,MIN

Lo,MAX Lo,MIN

2 1ń2

)ń3]

) I

Lo,MIN

Vf

is the forward voltage of the MOSFET’s intrinsic

diode

diode at the converter output current.

I

is the maximum output inductor current.

Lo,MAX

Lo,MIN

O,MAX

t_nonoverlap is the nonoverlap time between the upper

and lower gate drivers to prevent cross conduction. This

time is usually specified in the data sheet for the control IC.

When the MOSFET power dissipations are known, the

designer can calculate the required thermal impedance to

maintain a specified junction temperature at the worst case

ambient operating temperature.

(21)

(22)

I

+ I

O,MAX

ń2 ) DI ń2

Lo

Lo,MAX

is the minimum output inductor current.

I

+ I

O,MAX

ń2 * DI ń2

Lo

Lo,MIN

is the maximum converter output current.

D is the duty cycle of the converter.

(23)

(28)

D + V

ńV

CORE IN

q

T

t (T * T )ńP

J A D

∆I is the peak-to-peak ripple current in the output

Lo

where

inductor of value L .

θ

is the total thermal impedance (θ + θ ),

JC SA

o

T

θ

is the junction-to-case thermal impedance of

the MOSFET,

JC

(24)

DI + (V * V

Lo IN

) @ Dń(Lo @ f )

SW

CORE

R

is the ON resistance of the MOSFET at the

applied gate drive voltage.

is the post gate threshold portion of the

gate-to-source charge plus the gate-to-drain charge. This

may be specified in the data sheet or approximated from the

gate-charge curve as shown in the Figure 32.

DS(on)

θ

is the sink-to-ambient thermal impedance of

the heatsink assuming direct mounting of the

MOSFET (no thermal “pad” is used),

is the specified maximum allowed junction

temperature,

SA

Q

switch

T

J

T

is the worst case ambient operating temperature.

A

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27

NCP5331

For TO-220 and TO-263 packages, standard FR-4

copper clad circuit boards will have approximate thermal

determine the V bias current. Usually, the no-load voltage

FB

increase is specified in the design guide for the processor

resistances (θ ) as shown in the following table.

that is available from the manufacturer. The V bias current

SA

FB

is determined by the value of the resistor from R

to

OSC

Pad Size

(in /mm )

Single-Sided

1 oz. Copper

ground (see Figure TBD for a graph of IBIAS

versus

VFB

2

R

OSC

). The value of R can then be calculated.

F1

0.5/323

60-65 °C/W

55-60 °C/W

50-55 °C/W

45-50 °C/W

38-42 °C/W

33-37 °C/W

(29)

R

+ DV

ńIBIAS

NO- LOAD VFB

F1

0.75/484

1.0/645

Resistor R

is connected between the V

and the

DRP

and the V pins will both

DRP

V

FB

pins. At no-load, the V

DRP

FB

be at the DAC voltage so this resistor will conduct zero

current. However, at full-load, the voltage at the V pin

will increase proportional to the output inductor’s current

while V will still be regulated to the DAC voltage. Current

1.5/968

DRP

2.0/1290

2.5/1612

FB

will be conducted from V

will be large enough to supply the V bias current and cause

to V by R . This current

DRP

FB DRP

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow, maximum

input voltage, maximum loading, and component variations

FB

a voltage drop from V to V

across R - the

FB

CORE

F1

converter’s output voltage will be reduced. This condition is

shown in Figure 34.

To determine the value of R

the designer must specify

DRP

the full-load voltage reduction from the VID (DAC) setting

(i.e., worst case MOSFET R ). Also, the inductors and

DS(on)

(∆V

) and predict the voltage increase at

CORE,FULL- LOAD

capacitors share the MOSFET’s heatsinks and will add heat

and raise the temperature of the circuit board and MOSFET.

For any new design, its advisable to have as much heatsink

area as possible - all too often new designs are found to be

too hot and require redesign to add heatsinking.

the V

pin at full-load. Usually, the full-load voltage

DRP

reduction is specified in the design guide for the processor

that is available from the manufacturer. To predict the

voltage increase at the V

pin at full-load (∆V ), the

DRP

designer must consider the output inductor’s resistance

(R ), the PCB trace resistance between the current sense

6. Adaptive Voltage Positioning

L

There are two resistors that determine the Adaptive

Voltage Positioning, R and R . R establishes the

points (R ), and the controller IC’s gain from the current

PCB

sense to the V

pin (G

).

VDRP

F1

DRP

F1

DRP

no-load “high” voltage position and R

full-load “droop” voltage.

determines the

DRP

(30)

(31)

DV

+ I

@ (R ) R

) @ G

PCB VDRP

DRP

O,MAX

L

The value of R

can then be calculated.

Resistor R is connected between V

and the V

DRP

F1

CORE

FB

pin of the controller. At no load, this resistor will conduct the

internal bias current of the V pin and develop a voltage

DV

DRP

)

CORE,FULL- LOAD F1

R

+

DRP

FB

(IBIAS

) DV

ńR

VFB

drop from V

to the V pin. Because the error amplifier

CORE

FB

∆V

is the full-load voltage reduction

CORE,FULL- LOAD

from the VID (DAC) setting. ∆V

voltage change from the no-load AVP setting.

regulates V to the DAC setting, the output voltage,

FB

is not the

CORE,FULL- LOAD

V

CORE

, will be higher by the amount IBIAS

R . This

VFB F1

condition is shown in Figure 33.

To calculate R the designer must specify the no-load

F1

voltage increase above the VID setting (∆V ) and

NO- LOAD

+ -

R

S1

CS1

+

-

G

+

-

COMP

VID Setting

Σ

L1

0 A

VDRP

C

S1

Error

Amp

IBIAS

VFB

R

F1

DRP

S2

CS2

+

-

G

V

DRP

= VID

V

= VID

V

CORE

FB

L2

0 A

VDRP

S2

I

= 0

I = IBIAS

FBK VFB

DRP

CS

REF

V

CORE

= VID + IBIAS

w R

VFB

F1

Figure 33. AVP Circuitry at No-Load

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28

NCP5331

+ -

R

S1

CS1

+

-

G

+

-

COMP

VID Setting

Σ

L1

VDRP

Error

Amp

I

/2

R

IBIAS

MAX

VFB

C

S1

R

F1

DRP

S2

CS2

CS

+

-

G

V

I

= VID +

• R • G

L VDRP

V

= VID

V

CORE

DRP

MAX

FB

L2

VDRP

I

/2

MAX

S2

I

FBK

DRP

I

= I

MAX

• R • G /R

VDRP DRP

DRP

L

REF

= I

DRP

- IBIAS

VFB

FBK

V

CORE

= VID - (I

- IBIAS

) w R

DRP

VFB

F1

Figure 34. AVP Circuitry at Full-Load

7. Current Sensing

For inductive current sensing, choose the current sense

network (RSx, CSx) to satisfy

(32)

RSx @ CSx + Loń(R ) R

)

PCB

L

For resistive current sensing, choose the current sense

network (RSx, CSx) to satisfy

(33)

RSx @ CSx + Loń(R

)

sense

This will provide an adequate starting point for RSx and

CSx. After the converter is constructed, the value of RSx

(and/or LSx) should be fine-tuned in the lab by observing

the V

signal during a step change in load current. Tune

DRP

the RSx CSx network to provide a “square-wave” at the

output pin with maximum rise time and minimal

V

DRP

NOTE: The RC time constant of the current sense network is

too long (slow); V and V respond too slowly.

overshoot as shown in Figures 34 - 36.

DRP

CORE

Figure 35. V_DRPTuning, RC Time Too Long

NOTE: The RC time constant of the current sense network is

optimal; V

and V

respond to the load current

NOTE: The RC time constant of the current sense network is

DRP

CORE

quickly without overshooting.

too short (fast); V

and V

both overshoot.

DRP

CORE

Figure 37. V_DRPTuning, RC Time Optimal

Figure 36. V_DRPtuning, RC Time Too Short

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29

NCP5331

8. Error Amplifier Tuning

After the steady-state (static) AVP has been set and the

current sense network has been optimized the Error

Amplifier must be tuned. Basically, the gain of the Error

Amplifier should be adjusted to provide an acceptable

transient response by increasing or decreasing the Error

Amplifier’s feedback capacitor (C in the Applications

A1

Diagram). The bandwidth of the control loop will vary

directly with the gain of the error amplifier.

If C is too large the loop gain/bandwidth will be low, the

A1

COMP pin will slew too slowly, and the output voltage will

overshoot as shown in Figure 38. On the other hand, if C

A1

is too small the loop gain/bandwidth will be high, the COMP

pin will slew very quickly and overshoot. Integrator “wind

up” is the cause of the overshoot. In this case the output

voltage will transition more slowly because COMP spikes

upward as shown in Figure 39. Too much loop

gain/bandwidth increase the risk of instability. In general,

one should use the lowest loop gain/bandwidth as possible

to achieve acceptable transient response - this will insure

NOTE: The value of C is too high and the loop gain/

A1

bandwidth too low. COMP slews too slowly which

results in overshoot in V

.

CORE

Figure 38. COMP Tuning, Bandwidth Too Low

good stability. If C is optimal the COMP pin will slew

A1

quickly but not overshoot and the output voltage will

monotonically settle as shown in Figure 40.

After the control loop is tuned to provide an acceptable

transient response the steady- state voltage ripple on the COMP

pin should be examined. When the converter is operating at

full, steady-state load, the peak-to-peak voltage ripple on

the COMP pin should be less than 20 mVpp as shown in

Figure 41. Less than 10 mVpp is ideal. Excessive ripple on

the COMP pin will contribute to output voltage jitter.

9. Current Limit Setting

When the output of the current sense amplifier (CO1 or

CO2 in the block diagram) exceeds the voltage on the I

LIM

NOTE: The value of C is too low and the loop gain/

A1

pin the part will enter hiccup mode. For inductive sensing,

the I pin voltage should be set based on the inductor’s

bandwidth too high. COMP moves too quickly, which is

evident from the small spike in its voltage when the

load is applied or removed. The output voltage

LIM

maximum resistance (R ). The design must consider

LMAX

transitions more slowly because of the COMP spike.

Figure 39. COMP Tuning, Bandwidth Too High

NOTE: At full load the peak-to-peak voltage ripple on the

COMP pin should be less than 20 mV for a

well-tuned/stable controller. Higher COMP voltage

ripple will contribute to output voltage jitter.

NOTE: The value of C is optimal. COMP slews quickly

A1

without spiking or ringing. V

does not overshoot

CORE

and monotonically settles to its final value.

Figure 41. COMP Ripple for a Stable System

Figure 40. COMP Tuning, Bandwidth Optimal

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30

NCP5331

the inductor’s resistance increase due to current heating and

G

is the Current Sense Amplifier Gain

(nominally 2.0 V/V),

CSA

ambient temperature rise. Also, depending on the current

sense points, the circuit board may add additional resistance.

In general, the temperature coefficient of copper is +0.393%

Startup Offset is typically 0.60V.

12. Power Good Delay Time

The power good timer sets the delay time between when

per °C. If using a current sense resistor (R

), the I

SENSE

LIM

pin voltage should be set based on the maximum value of the

sense resistor. To set the level of the I pin,

V

exceeds the C

comparator’s threshold voltage

CORE

PGD

LIM

and when PGD will actually transition high. The PGD delay

time can be calculated from

(34)

V

+ (I

OUT,LIM

) DI ń2) @ R @ G

Lo

ILIM

where

(37)

t

+ C

@ (PGD

* PGD

)ńI

MIN PGD

PGD

THRESH

I

is the current limit threshold of the converter,

is half the inductor ripple current,

OUT,LIM

@ (3.0 V * 0.25V)ńI

PGD

∆I /2

Lo

R

G

is either (R

is the current sense to I

+ R

) or R

,

LMAX

PCB

SENSE

where

PGD

gain.

ILIM

LIM

is the PGD comparator’s threshold

voltage, nominally 3 V,

is the PGD timer’s starting voltage,

nominally 0.25 V,

THRESH

MIN

For the overcurrent protection to work properly, the

current sense time constant (RC) should be slightly larger

than the RL time constant. If the RC time constant is too fast,

during step load changes the sensed current waveform will

appear larger than the actual inductor current and will

probably trip the current limit at a lower level than expected.

PGD

I

is the charge current supplied to the

PGD

capacitor at the C

pin. This current

PGD

is a function of the R

resistor

OSC

according to I

= 0.52 V/R

.

10. Overcurrent Timer

PGD

OSC

The overcurrent timer sets the time the converter will

allow hiccup mode operation. Given the capacitance from

Design Example

the C

pin to GND, the nominal overcurrent time (t

)

OVC

Typical Design Requirements:

can be calculated from the following equation.

V

= 12.0 Vdc

IN

(35)

t

+ C

@ (OVC * OVC

THRESH

)ńI

MIN OVC

OVC

= 1.20 Vdc (nominal)

CORE

< 20 mV max

OUT,RIPPLE

PP

+ C

@ (3.0 V * 0.25 V)ń5.0 mA

OVC

VID Range: 0.800 Vdc - 1.550 Vdc

5

@ 5.5 10

I

= 52 A at full-load

= 72 Adc

O,MAX

where

OUT,LIM

dI /dt = 0.50 A/µs max

OVC

is the overcurrent timer’s shutdown

voltage, nominally 3 V,

is the overcurrent timer’s starting

voltage, nominally 0.25 V,

IN

THRESH

MIN

f

= 200 kHz

SW

η = 80% min at full-load

OVC

T

= 55°C

A,MAX

T

t

= 120°C

= 6.0 ms (Soft Start time)

I

is the charge current supplied to the

J,MAX

OVC

capacitor at the C

pin, nominally

SS

OVC

t

= 120 ms (Overcurrent time)

= 6.0 ms (PGD Delay time)

5 µA.

OVC

PGD

11. Soft Start Time

∆V

at no-load (static) =

CORE

The Soft Start time (t ) can be calculated from

SS

-25 mV from VID setting = 1.225 Vdc

∆V at full-load (static) =

–37 mV from VID setting = 1.163 Vdc

∆V transient loading from 3.0 A to 25 A =

(36)

CORE

t

+ (V

* R

@ I

C1 COMP

) @ C ńI

C2 COMP

SS

COMP

where

CORE

-50 mV from VID setting = 1.150 Vdc

V

+

V

@ 0 A ) Channel_Startup_Offset

COMP

CORE

) Int_Ramp ) G

@ Ext_Rampń2

CSA

1. Output Capacitor Selection

First, choose a low-cost, low-ESR output capacitor such

as the Rubycon 16MBZ1000M10X16: 16 V, 1000 µF,

Ext_Ramp + D @ (V * V

IN

)ń(R

@ C

CSx

@ f )

CSx SW

CORE

2.55 A

, 19 mΩ, 10 × 16 mm. Calculate the minimum

RMS

Int_Ramp + 125 mV @ Dń0.50

number of output capacitors.

I

is the COMP source current from the

data sheet,

is the internal ramp value at the

corresponding duty cycle,

is the peak-to-peak external

steady-state ramp at 0 A,

COMP

(1)

DI

O,MAX

N

+ ESR per capacitor @

OUT,MIN

DV

O,MAX

Int_Ramp

Ext_Ramp

+ 19 mW @ 22 Ań(1.225 V * 1.150 V)

+ 5.6 or 6 capacitors minimum (6000 mF)

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31

NCP5331

2. Output Inductor Selection

Calculate the minimum output inductance at I

Next, use Equation 6 to Equation 10 with the full-load

inductance value of 729 nH.

O,MAX

according to Equation 3 with ±20% inductor ripple current

(α = 0.15).

+ (V * V

IN

) @ Dń(Lo @ f )

OUT SW

DI

Lo

(10)

(1.163 Vń12 V)

(729 nH @ 200 kHz)

(3)

(V * V

IN

(a @ I

O,MAX

) @ V

OUT

@ V @ f )

IN SW

OUT

+ (12 V * 1.163 V) @

+ 7.20 App

Lo

MIN

+

(12 V * 1.163 V) @ 1.163 V

(0.15 @ 52 A @ 12 V @ 200 kHz)

(8)

+ I

O,MAX

ń2 ) DI ń2

Lo

I

Lo,MAX

+ 673 nH

+ 52 Ań2 ) 7.20 Appń2 + 29.6 A

To minimize core losses, we choose the T50−8B/90 core

2

from Micrometals: 23.0 nH/N , 2.50 cm/turn. According to

+ I

O,MAX

ń2 * DI ń2

Lo

I

Lo,MIN

the Micrometals catalog, at 26 A (per phase) the

permeability of this core will be approximately 88% of the

permeability at 0 A. Therefore, at 0 A we must achieve at

least 673 nH/0.88 or 765 nH. Using 6 turns of #16 AWG

bifilar (2 mΩ/ft) will produce 828 nH.

(9)

(6)

+ 52 Ań2 * 7.20 Appń2 + 22.4 A

+ I

Lo,MAX

ńh * I

IN,AVG

I

C,MAX

+ 29.6 Ań0.80 * 6.30 A + 30.7 A

We will need the nominal and worst case inductor

resistances for subsequent calculations.

(7)

+ I

Lo,MIN

ńh * I

IN,AVG

I

C,MIN

R + 6 turns @ 2.5 cmńturn @ 0.03218 ftńcm @ 2 mWńft

L

+ 22.4 Ań0.80 * 6.30 A + 21.7 A

+ 0.965 mW

For the two-phase converter, the input capacitor(s) rms

current at full-load is as follows. (Note: D = 1.163 V/12 V

= 0.097.)

The inductor resistance will be maximized when the

inductor is “hot” due to the load current and the ambient

temperature is high. Assuming a 50°C temperature rise of

the inductor at full-load and a 35°C ambient temperature

rise we can calculate

(11)

2

I

+ [2D @ (I

C,MIN

) I

@ DI

CIN,RMS

C,MIN

C,IN

@ (1 * 2D)]

2

1ń2

) DI

C,IN

ń3) ) I

IN,AVG

R

+ 0.965 mW @ [1 ) 0.39%ń°C @ (50°C ) 35°C)]

+ 1.28 mW

L,MAX

2

+ [0.19 @ (21.7 ) 21.7 @ 9.0 ) 9.0 ń3)

2

1ń2

) 6.30 @ (1 * 0.19)]

The output inductance at full-load will be reduced due to

the saturation characteristic of the core material.

+ 12.9 A

RMS

At this point, the designer must decide between saving

Lo

52 A

+ 0.88 828 nH + 729 nH at full load

board space by using higher- rated/more costly capacitors

or saving cost by using more lower-rated/less costly

capacitors. To save cost, we choose the MBZ series

capacitors by Rubycon. Part number 16MBZ1500M10X20:

Next, use Equation 4 to insure the output voltage ripple

will satisfy the design goal with the minimum number of

output capacitors and the full load output inductance.

1500 µF, 16 V, 2.55 A

, 13 mΩ, 10 × 20 mm. This design

RMS

V

+ (ESR per cap ń N

)

(4)

)}

OUT,P- P

OUT,MIN

will require N = 12.8 A/2.55 A = 5 capacitors on the input

IN

@ {(V * #Phases @ V

) @ D ń (Lo

@ f

for a cost sensitive design or 6 capacitors for a conservative

design.

IN

CORE

52 A SW

+ (19 mWń6) @ {(12 V * 2 @ 1.163 V)

@ (1.163 Vń12 V)ń(729 nH @ 200 kHz)}

4. Input Inductor Selection

For the Claw Hammper CPU, the input inductor must

limit the input current slew rate to less than 0.5 A/µs during

a load transient from 0 to 52 A. A conservative value will be

calculated assuming the minimum number of output

+ 20 mV

So, the ripple requirement will be satisfied if the minimum

number of output capacitors is used. More output capacitors

will probably be required to satisfy the transient

requirement, which will result in a lower ripple voltage.

capacitors (N

= 6), five input capacitors (N = 5), worst

OUT

IN

case ESR values for both the input and output capacitors,

and a maximum duty cycle at the maximum DAC setting

with 25 mV of no-load AVP.

3. Input Capacitor Selection

Use Equation 5 to determine the average input current to

the converter at full-load.

D

+ (1.550 V ) 25 mV

)ń10.8 V + 0.146

AVP IN

MAX

(5)

+ I

@ Dńh

+ 52 A @ (1.163 Vń12 V)ń0.80 + 6.30 A

I

O,MAX

IN,AVG

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32

NCP5331

First, use Equation 15 to calculate the voltage across the

output inductor due to the 52 A load current being shared

equally between the two phases.

The rms value of the current in the control MOSFET is

calculated from Equation 20 and the previously derived

values for D, I

, and I

at the converter’s maximum

LMAX

LMIN

output current.

(15)

DV + V * V

Lo

IN

CORE,NO- LOAD

ń2) @ ESR ńN

(20)

2

I

+ [D @ (I

Lo,MAX

) I

@ I

) (I

RMS,CNTL

Lo,MAX Lo,MIN

O,MAX

OUT OUT

2

1ń2

) I

)ń3]

+ 12 V * 1.575 V ) 52 Ań2 @ 19 mWń6

+ 10.51 V

Lo,MIN

2

1ń2

+ 0.097 @ [(29.6 ) 29.6 @ 22.4 ) 22.4 )ń3]

Second, use Equation 16 to determine the rate of current

increase in the output inductor when the load is applied (i.e.,

Lo has decreased to 88% due to the dc current).

+ 2.53 A

RMS

Equation 19 is used to calculate the power dissipation of

the control MOSFET but has been modified for one upper

and two lower MOSFETs.

(16)

+ DV ńLo

dI ńdt

Lo

+ 10.51 Vń729 nH + 14.4 Vńms

(19)

2

+ (I ) @ R

RMS,CNTL DS(on)

{

}

P

D,CONTROL

) (I

@ Q

ńI @ V @ f

)

Finally, use Equation 17 and Equation 18 to calculate the

minimum input inductance value.

Lo,MAX

switch g IN SW

) (3 @ Q

ń2 @ V @ f

) ) (V @ Q

IN SW IN

@ f )

RR SW

oss

(17)

+ ESR ńN @ dI ńdt @ Dńf

IN IN Lo SW

DV

Ci

2

{

}

@ 8.0 mW

+ 2.53 A

RMS

+ 13 mWń5 @ 14.4 Vńms @ 0.146ń200 kHz

+ 28 mV

) (29.6 A @ 27 nCń1.5 A @ 12 V @ 200 kHz)

) (3 @ 12 nCń2 @ 12 V @ 200 kHz)

) (12 V @ 43 nC @ 200 kHz)

(18)

+ DV ń dI ńdt

Li

MIN

Ci

IN MAX

+ 28 mVń0.50 Ańms + 55 nH

+ 0.051 W ) 1.28 W ) 0.043 W ) 0.10 W

+ 1.48 W per FET

Next, choose the small, cost effective T30-26 core from

2

Micrometals (33.5 nH/N ) with #16 AWG. The design

The rms value of the current in the synchronous MOSFET

is calculated from Equation 27 and the previously derived

requires only 1.28 turns to achieve the minimum inductance

value. We allow for inductance “swing” at full-load by

using three turns. The input inductor’s value will be

values for D, I , and I

Lo,MAX

at the converter’s

Lo,MIN

maximum output current.

2

L + 3 @ 33.5 nHńN + 301 nH

i

(27)

I

+ [(1 * D) @

RMS,SYNCH

This inductor is available as part number CTX15-14771

from Coiltronics.

2

1ń2

(I

Lo,MAX

) I

@ I

) I

Lo,MIN

)ń3]

Lo,MAX Lo,MIN

2

1ń2

+ (1 * 0.097) @ [(29.6 ) 29.6 @ 22.4 ) 22.4 )ń3]

+ 23.5 A (shared by two synchronous MOSFETs)

5. MOSFET & Heatsink Selection

RMS

For the upper MOSFET we choose two (1) NTD60N03

and for the lower MOSFETs we choose two (2) NTD80N02,

both are from ON Semiconductor. The following parameters

are derived from the data sheets.

Equation 26 is used to calculate the power dissipation of

each synchronous MOSFET. Note: The rms current is

shared by the two lower MOSFETs so the total rms current

is divided by two in the following equation. Also, during the

nonoverlap time, the per-phase current is shared by two

body diodes so the full load current is divided between two

phases and two forward body diodes per phase.

NCP5331 Parameter

Gate Drive Current

Value

1.5 A for 1.0 µs

6.5 V

Upper Gate Voltage

Lower Gate Voltage

Gate Nonoverlap Time

11.5 V

(26)

2

P

+ (I

RMS,SYNCH

@ R

)

DS(on)

D,SYNCH

65 ns

) (Vf

@ I

ń2 @ t_nonoverlap @ f

diode O,MAX SW

)

Ǌ

2

ǋ

@ 5.0 mW

(23.5ń2) A

+

RMS

) 0.92 V @ (52 Ań2ń2) @ 65 ns @ 200 kHz

+ 0.69 W ) 0.16 W + 0.85 W per FET

Parameter

NTD60N03

NTD80N02

Ǌ

ǋ

R

8.0 mΩ @ 6.5 V

27 nC

5.0 mΩ @ 10 V

26 nC

DS(on)

Q

SWITCH

Q

43 nC

36 nC

RR

Q

12 nC

OSS

V

0.75 V @ 2.3 A

1.65°C/W

0.92 V @ 20 A

1.65°C/W

F,diode

θ

JC

http://onsemi.com

33

NCP5331

7. Current Sensing

Choose the current sense network (R , C , x = 1 or 2) to

satisfy

Equation 28 is used to calculate the heat sink thermal

impedances necessary to maintain less than the specified

maximum junction temperatures at 55°C ambient.

Sx Sx

(32)

q

t (120 * 55°C)ń1.48 W * 1.65°CńW

R

@ C + Loń(R ) R

Sx

)

PCB

CNTRL

SA

Sx

L

Equation 32 will be most accurate for better iron powder

core material (such as the -8 from Micrometals). This

material is very consistent with dc current and frequency.

Less expensive core materials (such as the -52 from

Micrometals) change their characteristics with dc current,

ac flux density, and frequency. This material will yield

acceptable converter performance if the current sense time

constant is set lower (longer) than anticipated. As a rule of

+ 42.3°CńW

q

t (120 * 55°C)ń0.85 W * 1.65°CńW

SYNCH

SA

+ 74.8°CńW per MOSFET

or 37.4°CńW per phase for two MOSFETsńphase

If board area permits, a cost effective heatsink could be

2

formed by using a TO-263 mounting pad of at least 2.0 in

2

(1282 mm ) for the upper and lower MOSFETs on a

thumb, start with approximately twice the resistance (R )

Sx

single-sided, 1 oz copper PCB. The total required pad area

would be slightly less if the area were divided evenly

between top and bottom layers with multiple thermal vias

joining the two areas. To conserve board space, AAVID

offers clip-on heatsinks for TO-220 thru-hole packages.

Examples of these heatsinks include #577002 (1″ × 0.75″ ×

0.25″, 33°C/W at 2 W) and #591302 (0.75″ × 0.5″ × 0.5″,

29°C/W at 2 W).

or twice the capacitance (C ) when using the less expensive

core material.

Sx

The component values determined thus far are L = 828 nH,

o

R = 0.965 mΩ, and R

= 0.2 mΩ. We choose a convenient

L

PCB

value for C (0.1 µF) and solve for R .

S1

Sx

R

+ 828 nHń(0.965 mW ) 0.2 mW) @ 0.1 mF

+ 7.10 kW

Sn

After the circuit is constructed, the values of R and/or

6. Adaptive Voltage Positioning

Sx

C

should be tuned to provide a “square-wave” at the V

First, to achieve the 200 kHz switching frequency, use

Figure 5 to determine that a 51 kW resistor is needed for

Sx

DRP

pin with minimal overshoot and fast rise time due to a step

change in load current as shown in Figure 35, Figure 36 and

Figure 37. This testing has shown that for a 3 to 25 A

transient, a value of 10.0 kW will produce the desired square

R

OSC

. Then, use Figure 6 to find the V bias current at the

FB

corresponding value of R

. In this example, the 51 kΩ

OSC

R

OSC

resistor results in a V bias current of approximately

FB

wave at V

7.0 µA. Knowing the V bias current, one can calculate the

DRP.

FB

required values for R and R

Equation 31.

The no-load position is easily set using Equation 29.

using Equation 29 through

F1

DRP

8. Error Amplifier Tuning

The error amplifier is tuned by adjusting C to provide

an acceptable full-load transient response as shown in

Figure 38, Figure 39 and Figure 40. After a value for C is

A1

(29)

R

+ DV

ńIBIAS

NO- LOAD VFB

VFBK

A1

chosen, the peak-to-peak voltage ripple on the COMP pin

is examined under full-load to insure less than 20 mVpp as

shown in Figure 41.

+ +25 mVń7.0 mA

+ 3.6 kW

For inductive current sensing, the designer must calculate

the inductor’s resistance (R ) and approximate any

9. Current Limit Setting

L

The maximum inductor resistance, the maximum PCB

resistance, and the maximum current-sense gain determine

the current limit as shown in Equation 34. The maximum

resistance added by the circuit board (R ). We found the

PCB

inductor’s nominal resistance in Section 2 (0.965 mΩ). In

this example, we assume 0.2 mW for the circuit board

current,

I

,

was specified in the design

OUT,LIMIT

resistance (R ). With this information, Equation 30 can

PCB

requirements. The maximum inductor resistance occurs at

full load and the highest ambient temperature. This value

was found in the “Output Inductor Section” (1.28 mΩ). This

analysis assumes the PCB resistance only increases due to

the change in ambient temperature. Component heating will

also increase the PCB temperature but quantifying this

effect is difficult. Lab testing should be used to “fine tune”

the overcurrent threshold.

be used to calculate the increase at the V

pin at full load.

DRP

(30)

DV

+ I

@ (R ) R

) @ G

DRP

O,MAX

L

PCB

VDRP

+ 52 A @ (0.965 mW ) 0.2 mW) @ 4.2 VńV

+ 0.254 mV

R

DRP

can then be calculated from Equation 31.

DV

(31)

DRP

)

CORE,FULL- LOAD F1

R

+

R

+ 0.2 mW @ {1 ) 0.39%ń°C

@ (100°C * 25°C)}

+ 0.26 mW

DRP

PCB,MAX

(IBIAS

) DV

ńR

VFB

+ 254 mVń(7.0 mA ) 37 mVń3.6 kW)

+ 14.7 kW

http://onsemi.com

34

NCP5331

5 V

REF

+ (I

OUT,LIM

) DI ń2) @ (R

Lo

) R

)

V

LMAX

PCB,MAX

ILIM

To I

R

LIM

LIM1

V

LIM

@ G

ILIM

(72 A ) 7.20 Ań2) @ (1.28 mW ) 0.26 mW)

@ 12 VńV

+

R

910

LIM2

+ 1.4 Vdc

Figure 42. Setting the Current Limit

Set the voltage at the I

pin using a resistor divider from

LIM

the 5.0 V reference output as shown in Figure 42. If the

resistor from I to GND is chosen to be 910 Ω (R ),

Then calculate the steady-state COMP voltage.

LIM

LIM2

+

V

@ 0 A ) Channel_Startup_Offset

then the resistor from I

from

to 5.0 V

can be calculated

COMP

OUT

LIM

REF

) Int_Ramp ) G

@ Ext_Rampń2

CSA

R

+ (V

* V

REF

)ń(V

ILIM

ńR )

ILIM LIM2

LIM1

+ 1.225 V ) 0.60 V ) 0.102 @ 250 mV

) 4.0 VńV @ 5.3 mVń2

+ (5.0 V * 1.4 V)ń(1.4 Vń910 W)

+ 2340 W or 2.37 kW

+ 1.86 V

Finally, solve Equation 35 for the soft-start capacitor,

10. Overcurrent Timer

To set the overcurrent timer, solve Equation 35 for C

C

, and substitute as required.

C2

OVC

(36)

C

+ (t

@ I

)ń(V

* R

COMP

@ I

C1 COMP

)

and substitute t

= 120 ms.

C2

SS COMP

OVC

+ (6 ms @ 30 mA)ń(1.86 V * 7.5 kW @ 30 mA)

+ 0.11 mF or 0.1 mF

5

+ t ń(5.5 10 )

OVC

(35)

C

OVC

5

+ 120 msń(5.5 10 )

+ 0.218 mF or 0.22 mF

12. Power Good Delay Time

First, use the previously derived value for R

calculate the current that will be supplied to the C

capacitor.

to

OSC

11. Soft Start Time

To set the Soft Start time, first calculate the external ramp

size at a duty-cycle of D = 1.225 V/12 V = 0.102.

PGD

I

+ 0.52 VńR

OSC

PGD

(V * V

IN

(R @ C @ f

Sx Sx SW

)

OUT

+ 0.52 Vń51 kW

+ 10.2 mA

Ext_Ramp + D @

)

(12 V * 1.225 V)

(10.0 kW @ 0.1 mF @ 200 kHz)

Next, solve equation 37 for C

required.

and substitute as

+ 0.102 @

+ 5.5 mV

PGD

(37)

C

+ t

@ I

ń(PGD

* PGD

)

MIN

PGD

PGD PGD

THRESH

+ 6 ms @ 10.2 mAń(3.0 V * 0.25 V)

+ 0.022 mF

http://onsemi.com

35

NCP5331

PACKAGE DIMENSIONS

LQFP-32

FT SUFFIX

CASE 873A-02

ISSUE A

4X

A

A1

0.20 (0.008) AB T−U

Z

32

25

1

AE

-U-

-T-

P

B

V

B1

DETAIL Y

-Z-

BASE

METAL

DETAIL Y

V1

17

8

N

9

4X

0.20 (0.008) AC T−U

Z

9

F

D

S1

S

_

8X M

J

R

DETAIL AD

G

SECTION AE-AE

-AB-

-AC-

E

C

SEATING

PLANE

0.10 (0.004) AC

W

_

Q

H

K

X

DETAIL AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED

AT DATUM PLANE −AB−.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE −AC−.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE −AB−.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

MILLIMETERS

DIM MIN MAX

7.000 BSC

INCHES

MIN MAX

0.276 BSC

A

A1

B

3.500 BSC

7.000 BSC

3.500 BSC

0.138 BSC

0.276 BSC

0.138 BSC

B1

C

1.400

1.600

0.450

1.450

0.400

0.055

0.063

0.018

0.057

0.016

D

0.300

1.350

0.300

0.012

0.053

0.012

E

F

G

H

0.800 BSC

0.031 BSC

0.050

0.090

0.500

0.150

0.200

0.700

0.002

0.004

0.020

0.006

0.008

0.028

J

K

_

M

N

12 REF

0.090 0.160

0.400 BSC

12 REF

0.004 0.006

0.016 BSC

P

Q

R

1_

0.150

5_

0.250

1_

0.006

5_

0.010

S

9.000 BSC

0.354 BSC

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

S1

V

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.177 BSC

0.354 BSC

0.177 BSC

0.008 REF

0.039 REF

V1

W

X

http://onsemi.com

36

NCP5331

Notes

http://onsemi.com

37

NCP5331

2

V is a trademark of Switch Power, Inc.

AMD Athlon is a trademark of Advanced Micro Devices, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

JAPAN: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051

Phone: 81-3-5773-3850

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada

Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

NCP5331/D

http://onsemi.com

38


型号：	NCP5331
厂家：	ONSEMI
描述：	Two-Phase PWM Controller with Integrated Gate Drivers 双相PWM控制器，集成门极驱动器驱动器栅控制器
文件：	总38页 (文件大小：426K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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