NCP5360RMNR2G [ONSEMI]

Integrated Driver and MOSFET;


型号：	NCP5360RMNR2G
厂家：	ONSEMI
描述：	Integrated Driver and MOSFET
文件：	总8页 (文件大小：174K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP5360R

Integrated Driver and

MOSFET

The NCP5360R integrates a MOSFET driver, high-side MOSFET

and low-side MOSFET into a 8mm x 8mm 56-pin QFN package. The

driver and MOSFETs have been optimized for high-current DC-DC

buck power conversion applications. The NCP5360R integrated

solution greatly reduces package parasitics and board space compared

to a discrete component solution.

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MARKING

DIAGRAM

Features

• Capable of Switching Frequencies up to 1 MHz

• Capable of Output Currents up to 40 A

• Integrated Bootstrap Diode

• Output Disable Control turns off both MOSFETs

• Anti Cross-Conduction Protection Circuitry

• Undervoltage Lockout

• Internal Thermal Shutdown for System Protection

• These are Pb-free Devices

NCP5360R

AWLYYWWG

QFN56

MN SUFFIX

CASE 485AY

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

+12V

ORDERING INFORMATION

VCIN

VIN

†

Device

Package

Shipping

BST

NCP5360RMNR2G QFN56

2500/Tape & Reel

Output

(Pb−Free)

DISB#

PWM

CGND

Disable

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

PWM

VSWH

PGND

Vout

Figure 1. Application Schematic

Publication Order Number:

June, 2010 − Rev. 0

NCP5360R/D

NCP5360R

BOOT

VIN

VCIN

PWM

Logic

VSWH

PGND

Anti−Cross

Conduction

VCIN

DISB#

UVLO

Pre−OV

TSD

Fault

Figure 2. Simplified Block Diagram

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NCP5360R

PIN CONNECTIONS

PWM

VIN

DISB#

CGND

FLAG 57

VIN

FLAG 58

VIN

CGND

VSWH

PGND

VSWH

PGND

VSWH

FLAG 59

(Top View)

Figure 3. Pin Connections

Table 1. PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

Description

2, 3, 8, 53, 54

No Connect

VCIN

CGND

VSWH

Control Input Voltage

Control Signal Ground

Switch Node Output

Low Side FET Gate Access Pin

Power Ground

1, 6, 51, Flag 57

21, 40−50, Flag 59

22−39

PGND

VIN

9−20, Flag 58

Input Voltage

High Side FET Gate Access Pin

Bootstrap Voltage Pin

Output Disable Pin

BOOT

DISB#

PWM

PWM Drive Logic

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NCP5360R

Table 2. ABSOLUTE MAXIMUM RATINGS

Pin Symbol

VCIN

Pin Name

Control Input Voltage

Min

−0.3 V

Max

15 V

30 V

VIN

Power Input Voltage

Bootstrap Voltage

−0.3 V

BOOT

−0.3 V wrt/VSWH

35 V wrt/PGND

40 V < 50 ns wrt/PGND

15 V wrt/VSWH

VSWH

Switch Node Output

−5 V

30 V

−10 V < 200 ns

PWM

DISB#

PGND

PWM Drive Logic

Output Disable

Ground

−0.3 V

0 V

6.5 V

0 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 3. THERMAL CHARACTERISTICS

Rating

Thermal Resistance, High−Side FET

Thermal Resistance, Low−Side FET

Operating Junction Temperature

Storage Temperature

Symbol

Value

Unit

°C/W

°C

JPCB

5.0

JPCB

0 to 150

−55 to 150

°C

1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.

Table 4. OPERATING RANGES (Note 2)

Rating

Symbol

Min

4.5

Typ

Max

13.2

Unit

Control Input Voltage

Input Voltage

CIN

2. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.

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NCP5360R

ELECTRICAL CHARACTERISTICS (Notes 3, 4) (VCIN = 12 V, VIN = 12 V, T = −10°C to +100°C, unless otherwise noted)

Parameter

SUPPLY CURRENT

Symbol

Condition

Min

Typ

Max

Unit

VCIN Current (Normal Mode)

VCIN Current (Shutdown Mode)

UNDERVOLTAGE LOCKOUT

UVLO Startup

−

DISB# = 5 V, PWM = OSC, Fsw = 400 kHz

DISB# = GND

0.5

1.7

−

3.8

4.35

200

4.5

UVLO Hysteresis

150

250

BOOTSTRAP DIODE

Bootstrap Diode Forward Voltage

PWM INPUT

−

VCIN = 12 V, Forward Bias Current = 2 mA

0.1

0.4

0.6

PWM Input Voltage High

PWM Input Voltage Mid−State

PWM Input Voltage Low

3.3

1.3

PWM_HI

2.7

0.7

PWM_MID

PWM_LO

Tri−State Shutdown Holdoff Time

OUTPUT DISABLE

−

200

Output Disable Input Voltage High

Output Disable Input Voltage Low

Output Disable Hysteresis

Output Disable Propagation Delay

2.0

DISB_HI

1.0

DISB_LO

−

500

3. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.

4. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C. Low

duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

PWM

GH−VSWH

Figure 4. Timing Diagram

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NCP5360R

APPLICATION INFORMATION

Theory of Operation

MOSFETs, and even a small amount of cross−conduction

will cause a decrease in the power conversion efficiency.

The NCP5360R prevents cross conduction by monitoring

the status of the MOSFETs and applying the appropriate

amount of “dead−time” or the time between the turn off of

one MOSFET and the turn on of the other MOSFET.

When the PWM input pin goes high, the gate of the

low-side MOSFET (GL pin) will go low after a propagation

delay (tpdlDRVL). The time it takes for the low−side

MOSFET to turn off (tfDRVL) is dependent on the total

charge on the low−side MOSFET gate. The NCP5360R

monitors the gate voltage of both MOSFETs and the

switchnode voltage to determine the conduction status of the

MOSFETs. Once the low−side MOSFET is turned off an

internal timer will delay (tpdhDRVH) the turn on of the

high−side MOSFET.

Likewise, when the PWM input pin goes low, the gate of

the high-side MOSFET (GH pin) will go low after the

propagation delay (tpdlDRVH). The time to turn off the

high−side MOSFET (tfDRVH) is dependent on the total gate

charge of the high−side MOSFET. A timer will be triggered

once the high−side MOSFET has stopped conducting, to

delay (tpdhDRVL) the turn on of the low−side MOSFET.

The NCP5360R is an integrated driver and MOSFET

module designed for use in a synchronous buck converter

topology. A single PWM input signal is all that is required

to properly drive the high−side and low−side MOSFETs.

Undervoltage Lockout

GH and GL are held low until VCIN reaches 4.5 V during

startup. The PWM signals will control the gate status when

the VCIN threshold is exceeded.

Power-On Reset

Power-On Reset feature is used to protect against an

abnormal status during startup. When the initial soft-start

voltage is greater than 2.75 V, the switch node pin is

monitored. If VSWH is higher than 2.25 V, the low-side FET

is turned on to discharge the output capacitors. The fault

mode will latch and DISB# will be forced low until the part

is recycled. When the input voltage is higher than 4.5 V and

DISB# is high, the part will enter normal operation.

Bi-Directional DISB# Signal

Fault modes such as Power-On Reset, Overtemperature

and Undervoltage Lockout will assert the DISB# pin. This

will pull down the DRON of the controller as well, thus

shutting the controller down.

When the PWM input is between V

and

PWM_LO

for longer than 200 ns, both the high-side and

PWM_HI

low-side MOSFETs will be turned off. The PWM input will

Low−Side Driver

need to exceed V

MOSFETs.

to resume normal switching of the

PWM_HI

The low−side driver is designed to drive a ground

referenced low RDS(on) N−Channel MOSFET. The voltage

rail for the low−side driver is internally connected to VCIN

and CGND.

Power Supply Decoupling

The NCP5360R can source and sink relatively large

currents to the gate pins of the MOSFETs. In order to

maintain a constant and stable supply voltage (VCIN) a low

ESR capacitor should be placed near the power and ground

pins. A1mF to 4.7 mF multi layer ceramic capacitor (MLCC)

is usually sufficient.

High−Side Driver

The high−side driver is designed to drive a floating low

RDS(on) N−channel MOSFET. The gate voltage for the

high-side driver is developed by a bootstrap circuit

referenced to Switch Node (VSWH) pin.

The bootstrap circuit is comprised of the internal

bootstrap diode, and an external bootstrap capacitor. When

the NCP5360R is starting up, the VSWH pin is at ground, so

the bootstrap capacitor will charge up to VCIN through the

bootstrap diode. When the PWM input goes high, the

high−side driver will begin to turn on the high−side

MOSFET using the stored charge of the bootstrap capacitor.

As the high−side MOSFET turns on, the VSWH pin will

rise. When the high−side MOSFET is fully on, the switch

node will be at 12 V, and the BST pin will be at 12 V plus the

charge of the bootstrap capacitor (approaching 24 V).

The bootstrap capacitor is recharged when the switch

node goes low during the next cycle.

Input Pins

The PWM input and the Output Disable pins of the

NCP5360R have internal protection for Electro Static

Discharge (ESD), but in normal operation they present a

relatively high input impedance. If the PWM controller does

not have internal pull−down resistors, they should be added

externally to ensure that the driver outputs do not go high

before the controller has reached its undervoltage lockout

threshold.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

(CBST) and the internal diode. The bootstrap capacitor must

have a voltage rating that is able to withstand twice the

maximum supply voltage. A minimum 50 V rating is

recommended. A bootstrap capacitance greater than 100 nF

is recommended. A good quality ceramic capacitor should

be used.

Safety Timer and Overlap Protection Circuit

It is very important that MOSFETs in a synchronous buck

regulator do not both conduct at the same time. Excessive

shoot−through or cross−conduction can damage the

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN56 8x8, 0.5P

CASE 485AY−01

ISSUE O

DATE 12 FEB 2009

A B

NOTES:

SCALE 2:1

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. POSITIONAL TOLERANCE APPLIES TO ALL

THREE EXPOSED PADS.

PIN ONE

LOCATION

DETAIL A

ALTERNATE

CONSTRUCTIONS

MILLIMETERS

DIM MIN

MAX

1.00

0.05

EXPOSED Cu

MOLD CMPD

0.15

0.80

−−−

0.20 REF

0.18

0.15

0.30

TOP VIEW

DETAIL B

8.00 BSC

DETAIL B

(A3)

3.35

2.10

8.00 BSC

6.10

2.05

3.40

0.50 BSC

3.10

0.20

3.55

2.30

0.10

ALTERNATE

CONSTRUCTION

56X

6.30

2.25

3.60

0.08

SEATING

PLANE

NOTE 4

SIDE VIEW

−−−

0.50

0.15

0.10

C A B

0.30

−−−

NOTE 5

DETAIL A

56X L

GENERIC

MARKING DIAGRAM*

XXXXXXXX

AWLYYWWG

XXXXX = Specific Device Code

56X b

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

e/2

0.10

A B

NOTE 3

0.05

BOTTOM VIEW

8.30

6.36

56X

*This information is generic. Please refer

to device data sheet for actual part

marking.

0.63

8.30

2.36

3.61

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

2.31

6.33

3.66

56X

0.30

PKG

OUTLINE

SOLDERING FOOTPRINT

0.50

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON38216E

QFN56 8x8, 0.5P

PAGE 1 OF 1

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NCP5360RMNR2G [ONSEMI]

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