NCP5393_技术文档

NCP5393

2/3/4-Phase Controller for

CPU Applications

The NCP5393 controls up to four V

phases and one V

DDNB

DD

phase to provide a buck regulator solution for current and

next-generation AMD processors. The NCP5393 incorporates

differential voltage sensing, differential phase current sensing,

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optional load-line voltage positioning, and programmable V and

V

DD

offsets to provide accurately regulated power parallel- and

DDNB

MARKING

DIAGRAM

serial-VID AMD processors. Dual-edge multiphase modulation

provides the fastest initial response to dynamic load events. This

reduces system cost by requiring less bulk and ceramic output

capacitance to meet transient regulation specifications.

1

High performance operational error amplifiers are provided to

regulators. Dynamic

NCP5393

AWLYYWWG

simplify compensation of the V and V

DD

DDNB

1

48

Reference Injection further simplifies loop compensation by

eliminating the need to compromise between response to load

transients and response to VID code changes.

QFN48, 7x7

CASE 485AJ

A

= Assembly Location

= Wafer Lot

= Year

Features

WL

YY

WW

G

•ꢀMeets AMD's Parallel, Serial (SVI) and Hybrid VR Specifications

= Work Week

= Pb-Free Package

•ꢀUp to Four V Phases

DD

•ꢀSingle-Phase V

Controller

DDNB

•ꢀDual-Edge PWM for Fastest Initial Response to Transient Loading

•ꢀHigh Performance Operational Error Amplifiers

•ꢀInternal Soft Start and Slew Rate Limiting

ORDERING INFORMATION

†

Device

NCP5393MNR2G

Package

Shipping

•ꢀDynamic Reference Injection (Patent #US07057381)

•ꢀDAC Range from 12.5 mV to 1.55 V

QFN48

(Pb-Free)

2500 / Tape & Reel

•ꢀ$0.5% DAC Accuracy fro 0.8 V to 1.55 V

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

•ꢀV and V Offset Ranges 0 mV - 800 mV

DD

•ꢀTrue Differential Remote Voltage Sense Amplifiers

•ꢀPhase-to-Phase I Current Balancing

DD

•ꢀDifferential Current Sense Amplifiers for Each Phase of Each Output

•ꢀ“Lossless” Inductor Current Sensing for V and V

Outputs

DD

DDNB

•ꢀSupports Load Lines (Droop) for V and V

Outputs

DD

DDNB

•ꢀOscillator Range of 100 kHz - 1 MHz

•ꢀTracking Over Voltage Protection

•ꢀOutput Inductor DCR-Based Over Current Protection for V and

DD

V

DDNB

Outputs

•ꢀGuaranteed Startup into Precharged Loads

•ꢀTemperature Range: 0°C to 70°C

•ꢀThis is a Pb-Free Device*

Applications

•ꢀDesktop Processors

•ꢀServer Processors

•ꢀHigh-End Notebook PCs

*For additional information on our Pb-Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

©ꢀ Semiconductor Components Industries, LLC, 2008

February, 2008 - Rev. 0

1

Publication Order Number:

NCP5393/D

NCP5393

48

1

VCCA

GND

VID1

VID0

NB_COMP

NB_FB

COMP

FB

DROOP

VS+

VS-

NB_DROOP

NB_VS+

NB_VS-

NB_OFFSET

NB_DIFFOUT

ROSC

OFFSET

DIFFOUT

VFIX

12VMON

PSI_L

VID5

VID4

Figure 1. Pinout

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2

NCP5393

NB_VS+

NB_VS-

-

+

-

NB_G

HI-Z

MID

Diff Amp

NB_DIFFOUT

PWM_NB

OVP

FAULT VDD PSI_L

1.3 V

+

-

NB_FB

+

-

Error Amp

ILIMIT_NB

NB_DRVON

NB_COMP

NB_DROOP

NB REGULATOR

Fault Logic

and

ILIMIT_NB =

ILIMIT_VDD/N

(N = VDD

NB_SRL

NB_DAC

NB_VS+

Monitor Circuits

Gain = 1

Droop Amplifier

phase count) NB_VS-

1.3 V

+

NB OFFSET

SCALING

X

NB_CS

NB_CSN

+

-

Gain

= 6

NORMAL OPERATION

NB_OFFSET

BOOT_VID & VFIX MODES

NB

NB_DAC OUT

Oscillator

PWRGOOD

PWROK

NB_SRL

OUT

+

NB

NB Slew

Rate Lim‐

it

VID0

f

= 1.27 x f

NB

VDD

PVI/SVI

HYBRID

VID1

VID2/SVD

VID3/SVC

VID4

INTERFACE

VDD Slew

Rate Limit

VID5

VDD_DAC OUT

+

VDD_SRL OUT

VS-

VS+

-

+

VDD

PSI_L

DIFFOUT

Diff Amp

NORMAL OPERATION

X

OFFSET

BOOT_VID & VFIX MODES

VDD OFFSET

SCALING

1.3 V

+

FB

FLAG

-

Error Amp

COMP

GND

DROOP

Gain = 1

1.3 V

VDD PSI_L

Droop Amplifier

+

CS1

CS1N

+

G1

+

-

PWM1

-

Gain = 6

HI-Z

MID

+

CS2

CS2N

+

G2

G3

G4

+

-

PWM2

-

Gain = 6

+

CS3

CS3N

+

-

PMW3

-

Gain = 6

MID

+

CS4

CS4N

+

-

+

-

PWM4

HI-Z

Gain = 6

VDD

SHED

FAULT

4OFF

Oscillator

OVP

ROSC

ILIM

+

-

ILIMIT_VDD

DRVON

V

REGULATOR

DD

ENABLE

VCCA

Fault Logic

3-Phase

+

-

Detection

and

5V UVLO

4.25V/4.05V

VDD_SRL

Monitor Circuits

VDD_DAC

VS+

VS-

12VMON

+

-

12V UVLO

NCP5393

8.5V/7.5V

Figure 2. NCP5393 Block Diagram

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3

NCP5393

Figure 3. NCP5393 Configured for 3 + 1 Phases, with Optional Droop

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4

NCP5393

NCP5393 PIN DESCRIPTIONS

Pin No.

Symbol

Description

1

VCCA

5 V supply pin for the NCP5393. The V bypassing capacitance must be connected between this

CC

pin and GND (preferably returned to the package flag).

2

3

4

5

GND

COMP

FB

Small-signal power supply return. This pin should be tied directly to the package flag (exposed pad).

Output of the voltage error amplifier for the V regulator.

DD

Voltage error amplifier inverting input for the V regulator.

DD

DROOP

Voltage output signal proportional to total current drawn from the V regulator. Used when load line

DD

operation (“droop”) is desired.

6

7

8

VS+

VS-

Non-inverting input to the differential remote sense amplifier for the V regulator.

DD

Inverting input to the differential remote sense amplifier for the V regulator.

DD

OFFSET

Input for offset voltage to be added to the V DAC's output voltage. Ground this pin for zero V

DD

offset.

9

DIFFOUT

VFIX

Output of the differential remote sense amplifier for the V regulator.

DD

10

When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded

as a two-bit DAC code, which controls the V and VDDNB outputs.

DD

11

12

12VMON

PSI_L

UVLO monitor input for the 12 V power rail.

Power Saving Control. Low = single phase operation, High = normal operation. This pin is not used in

SVI mode.

13

14

15

16

17

18

19

20

21

CS1

CS1N

CS2

Non-inverting input to current sense amplifier #1 for the V regulator. See Table: “Pin Connections

DD

vs. Phase Count”

Inverting input to current sense amplifier #1 for the V regulator. See Table: “Pin Connections vs.

DD

Phase Count”

Non-inverting input to current sense amplifier #2 for the V regulator. See Table: “Pin Connections

DD

vs. Phase Count”

CS2N

CS3

Inverting input to current sense amplifier #2 for the V regulator. See Table: “Pin Connections vs.

DD

Phase Count”

Non-inverting input to current sense amplifier #3 for the V regulator. See Table: “Pin Connections

DD

vs. Phase Count”

CS3N

CS4

Inverting input to current sense amplifier #3 for the V regulator. See Table: “Pin Connections vs.

DD

Phase Count”

Non-inverting input to current sense amplifier #4 for the V regulator. See Table: “Pin Connections

DD

vs. Phase Count”

CS4N

ILIM

Inverting input to current sense amplifier #4 for the V regulator. See Table: “Pin Connections vs.

DD

Phase Count”

Overcurrent shutdown threshold for V and VDDNB. A resistor divider from ROSC to GND is typic‐

DD

ally used to develop an appropriate voltage on ILIM.

22

23

24

25

26

27

VCCB

NB_CS

NB_CSN

VID4

5 V supply pin. Tie this pin to VCCA (Pin 1).

Non-inverting input to the current sense amplifier for the VDDNB regulator

Inverting input to the current sense amplifier for the VDDNB regulator

Parallel Voltage ID DAC Input 4. Not used in SVI mode.

Parallel Voltage ID DAC Input 5. Not used in SVI mode.

VID5

ROSC

A resistance from this pin to ground programs the V and VDDNB oscillator frequencies. This pin

DD

supplies a trimmed output voltage of 2 V.

28

29

NB_DIFFOUT

NB_OFFSET

Output of the differential remote sense amplifier for the VDDNB regulator.

Input for offset voltage to be added to the VDDNB DAC's output voltage. Ground this pin for zero

VDDNB offset.

30

31

NB_VS-

NB_VS+

Inverting input to the differential remote sense amplifier for the VDDNB regulator.

Non-inverting input to the differential remote sense amplifier for the VDDNB regulator.

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5

NCP5393

NCP5393 PIN DESCRIPTIONS

Pin No.

Symbol

Description

32

NB_DROOP

Voltage output signal proportional to total current drawn from the VDDNB regulator. Used when load

line operation (“droop”) is desired.

33

34

NB_FB

NB_COMP

VID0

Voltage error amplifier inverting input for the V

regulator.

DDNB

Output of the voltage error amplifier for the V

regulator.

DDNB

35

Parallel Voltage ID DAC Input 0. Not used in SVI mode.

Parallel Voltage ID DAC Input 1. Also used for PVI or SVI mode selection.

System power supplies status input. Used in SVI mode only.

High = Run, Low = Standby/Reset.

36

VID1

37

PWROK

ENABLE

VID3/SVC

VID2/SVD

PWRGOOD

NB_DRVON

DRVON

NB_G

38

39

Parallel Voltage ID DAC Input 1. Also used in SVI mode.

Open drain output. High indicates that the active output(s) are within specification.

40

41

42

Bidirectional Gate Drive Enable to the gate driver for the V

regulator.

DDNB

43

Bidirectional Gate Drive Enable to gate drivers for the V regulator.

DD

44

PWM output to the V

gate driver.

DDNB

45

G4

PWM output #4. See Table: “Pin Connections vs. Phase Count”

PWM output #3. See Table: “Pin Connections vs. Phase Count”

PWM output #2. See Table: “Pin Connections vs. Phase Count”

PWM output #1. See Table: “Pin Connections vs. Phase Count”

46

G3

47

G2

48

G1

FLAG

PGND

High-current power supply return via metal pad (flag) underneath package. The package flag should

be tied directly to Pin 2.

PIN CONNECTIONS VS. PHASE COUNT

Number of

Phases

CS4 &

CS4N

CS3 &

CS3N

CS2 &

CS2N

CS1 &

CS1N

G4

G3

G2

G1

4

Phase 4

Out

Phase 3

Out

Phase 2

Out

Phase 1

Out

Phase 4 CS

Input

Phase 3 CS

Input

Phase 2 CS

Input

Phase 1 CS

Input

3

2

Tie to

GND

Phase 3

Out

Phase 2

Out

Phase 1

Out

Tie to GND

Phase 3 CS

Input

Phase 2 CS

Input

Phase 1 CS

Input

Tie to

GND

Phase 2

Out

Tie to

GND

Phase 1

Out

Tie to GND

Phase 2 CS

input

Tie to GND

Phase 1 CS

Input

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6

NCP5393

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL INFORMATION

Pin Symbol

12VMON

V

I

SINK

MAX

MIN

SOURCE

13.2 V

7.0 V

5.5 V

3 V

-0.3 V

N/A

50 mA

10 mA

5 mA

20 mA

10 mA

20 mA

1 mA

N/A

VCC

N/A

10 mA

5 mA

20 mA

5 mA

N/A

COMP, NB_COMP

DROOP, NB_DROOP

DIFFOUT, NB_DIFFOUT

DRVON, NB_DRVON

PWRGOOD

VS+, NB_VS+

VS-, NB_VS-

ROSC

1 mA

N/A

0.3 V

5.5 V

All Other Pins

N/A

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

NOTE: All signals are referenced to GND unless noted otherwise.

THERMAL INFORMATION

Rating

Symbol

Value

30.5

Unit

°C/W

°C

Thermal Characteristic, QFN Package (Note 1)

Operating Junction Temperature Range (Note 2)

Operating Ambient Temperature Range

Maximum Storage Temperature Range

Moisture Sensitivity Level, QFN Package

R

q

JA

T

0 to 125

0 to 70

-55 to +150

1

J

T

A

°C

T

°C

STG

MSL

* The maximum package power dissipation must be observed.

1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM.

2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM.

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7

NCP5393

ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvT v70°C; 4.75 VvV v5.25 V; All DAC Codes; C

= 0.1 mF)

A

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

ERROR AMPLIFIERS (V & V

DD

)

DDNB

Input Bias Current

-200

-1.0

-

200

1.0

-

nA

mV

Input Offset Voltage (Note 3)

Open Loop DC Gain

V+ = V- = 1.3V

C = 60 pF to GND, R = 10 kW to GND

-

80

15

70

dB

L

Open Loop Unity Gain Bandwidth

Open Loop Phase Margin

Slew Rate

C = 60 pF to GND, R = 10 kW to GND

L L

-

MHz

deg

V/ms

C = 60 pF to GND, R = 10 kW to GND

L L

-

DV = 100 mV, AV = -10 V/V,

< 2.5 V,

IN

1.5 V < V

-

5

-

COMP

C = 60 pF, DC Loading = $125 mA

L

Maximum Output Voltage

Minimum Output Voltage

10 mV of Overdrive, I

= 2.0 mA

3.5

-

2

-

1.0

-

V

SOURCE

= 2.0 mA

SINK

Output Source Current (Note 3)

Output Sink Current (Note 3)

10 mV of Overdrive, V

= 3.5 V

-

mA

OUT

10 mV of Overdrive, V

= 1.0 V

-

DIFFERENTIAL SUMMING AMPLIFIERS (V & V

DD

)

DDNB

VS- Input Bias Current

VS+ Input Resistance

VS- Voltage at 0 V

DRVON = Low

DRVON = High

DRVON = Low

DRVON = High

33

1.0

7

mA

kW

VS+ Input Bias Voltage

0.37

0.05

-

V

VS+ Input Voltage Range (Note 3)

VS- Input Voltage Range (Note 3)

-3dB Bandwidth (Note 3)

-0.3

3.0

0.3

V

-

C = 80 pF to GND, R = 10 kW to GND

L L

15

1.0

MHz

V/V

DC gain, VS+ to DIFFOUT

VS+ to VS- = 0.5 V to 2.35 V

0.982

1.022

DAC Accuracy (Measured at VS+)

Closed Loop Measurement, Error Amplifier Inside the

Loop.

1.0125 V v VDAC v 1.5500 V

0.8000 V v VDAC v 1.0000 V

12.5 mV v VDAC v 0.8000 V

-0.5

-5

-8

-

0.5

5

8

%

mV

Slew Rate

DV = 100 mV, DV

IN

= 1.3 V-1.2 V

10

V/ms

V

OUT

Maximum Output Voltage

Minimum Output Voltage

Output source current (Note 3)

Output sink current (Note 3)

I

= 2 mA

2.0

SOURCE

0.5

6.3

V

SINK

V

= 3 V

2.0

mA

OUT

V

= 0.5 V

DROOP AMPLIFIERS (V & V

DD

)

DDNB

Gain from Current Sense Input to

Droop Amplifier Output

0 mV < (CSx - CSxN) < 60 mV

CSx = CSxN = 1.3 V

5.7

6.0

V/V

Droop Amplifier DC Output Voltage

Slew Rate

1.3

5.0

-

V

V/ms

V

C = 20 pF to GND, R = 1 kW to GND

L L

-

3.0

-

Maximum Output Voltage

Minimum Output Voltage

Output Source Current (Note 3)

Output Sink Current (Note 3)

I = 4.0 mA

SOURCE

I

= 1.0 mA

-

1.0

-

V

SINK

V

OUT

V

OUT

= 3.0 V

-

4.0

1.0

mA

= 1.0 V

-

3. Guaranteed by design. Not production tested.

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8

NCP5393

ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvT v70°C; 4.75 VvV v5.25 V; All DAC Codes; C

= 0.1 mF)

A

CC

VCC

Parameter

CURRENT SENSE AMPLIFIERS (V & V

Test Conditions

Min

Typ

Max

Unit

)

DDNB

DD

Input Bias Current

CSx = CSxN = 1.4 V

-50

-0.3

-120

-

50

2.6

120

nA

V

Common Mode Input Voltage Range

Differential Mode Input Voltage

Range (Note 3)

mV

Input Offset Voltage (Note 3)

CSx = CSxN = 1.00 V

-1.0

5.0

-

1.0

7.0

mV

V/V

Gain from Current Sense Input to

PWM Comparator

0 mV < (CSx - CSxN) < 60 mV

6.0

INTERNAL OFFSET VOLTAGE

Voltage at Error Amplifier Non-In‐

verting Inputs

-

1.3

-

V

DRVON & NB_DRVON

Output Voltage (High)

Output Voltage (Low)

Delay Time

Sourcing 500 mA

Sinking 500 mA

Propagation Delays

Sourcing 500 mA

Sinking 500 mA

3.0

-

0.7

-

V

-

10

ns

kW

W

Active Internal Pull-up Resistance

Active Internal Pull-down Resistance

Rise Time

-

2.0

150

130

15

-

C (PCB) = 20 pF, DV

L

= 10% to 90%

-

ns

OUT

Fall Time

C (PCB) = 20 pF, DV

L

-

OUT

V

DD

PWM OSCILLATOR

Switching Frequency Range

100

-

900

kHz

Switching Frequency Accuracy

2- or 4-phase

ROSC = 49.9 kW

ROSC = 24.9 kW

ROSC = 10 kW

196

380

803

-

226

420

981

Switching Frequency Accuracy

3-phase

ROSC = 49.9 kW

ROSC = 24.9 kW

ROSC = 10 kW

196

380

803

-

226

420

981

kHz

V

ROSC Output Voltage

10 mA ≤ IROSC ≤ 200 mA

1.94

2.0

2.06

V

DDNB

PWM OSCILLATOR

Switching Frequency

-

1.25

-

x f

VDD

PWM COMPARATORS (V & V

DD

)

DDNB

Minimum Pulse Width (Note 3)

Propagation Delay (Note 3)

Magnitude of the PWM Ramp

0% Duty Cycle

F

= 800 kHz

-

30

10

-

ns

V

SW

$20 mV of Overdrive

1.0

0.2

COMP Voltage at which the PWM Outputs Remain

LOW

V

100% Duty Cycle

COMP Voltage at which the PWM Outputs Remain

HIGH

-

1.2

-

V

PWM Phase Angle Error

Between Adjacent Phases

-15

+15

°

PWRGOOD OUTPUT

PWRGOOD Output Voltage (Low)

PWRGOOD Rise Time

I

= 5 mA

-

0.4

-

V

PGD

External Pullup of 1 kW to 5 V C

= 10% to 90%

= 45 pF, DV

125

ns

TOTAL

OUT

PWRGOOD High-State Leakage

V

= 5.25 V

-

1

mA

PWRGOOD

3. Guaranteed by design. Not production tested.

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9

NCP5393

ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvT v70°C; 4.75 VvV v5.25 V; All DAC Codes; C

= 0.1 mF)

A

CC

VCC

Parameter

PWRGOOD OUTPUT

Test Conditions

Min

Typ

Max

Unit

PWRGOOD Upper Threshold

PWRGOOD Lower Threshold

V

Increasing, DAC = 1.3 V (Wrt DAC)

Decreasing, DAC = 1.3 V

-

300

350

-

mV

OUT

PWM OUTPUTS (V & V

DD

)

DDNB

Output Voltage (High)

Output Voltage (Mid)

Output Voltage (Low)

Rise and Fall Times

Tri-State Output Leakage

Sourcing 500 mA

3.0

1.3

-

1.5

-

V

CC

R = 4 kW to GND

L

1.7

0.15

-

Sinking 500 mA

V

C = 50 pF, 0.7 V to 3.0 V or 3.0 V to 0.7 V

L

-

15

-

ns

mA

W

Gx = 2.5 V (x = 1-4 or NB)

-1.5

-

1.5

-

Output Impedance - HIGH or LOW

State

Resistance to V or GND

CC

50

VDD REGULATOR 2/3/4 PHASE DETECTION

Gate Pin Source Current

-

80

250

20

-

mA

mV

ms

Gate Pin Threshold Voltage

Phase Detect Timer

SLEW RATE LIMITERS

Soft Start Ramp Time

Slew Rate Limit

DAC = 0 to DAC = BOOT_VID

In Any Mode after Soft-Start Completes

-

2

-

ms

3.25

mV/ms

VID INPUTS (Note: In SVI Mode, VID[2] = Bidirectional “SVD' Line and VID[3] = “SVC” Clock Input)

VID Input Voltage (High)

VID Input Voltage (Low)

VID Hysteresis

V

0.9

-

0.6

-

V

HIGH

LOW

HIGH

- V

or V

- V

HIGH

-

100

15

-

mV

mA

V

LOW

Input Pulldown Current

SVD Output Voltage (Low)

ENABLE INPUT

= 0.6 V - 1.9 V

-

IN

In SVI Mode, I

= 5 mA

0

0.25

SINK

ENABLE Input Voltage (High)

ENABLE Input Voltage (Low)

Enable Hysteresis

V

2.0

-

0.8

-

V

HIGH

LOW

Low - High or High - Low

Internal Pullup to V

-

200

15

mV

mA

Enable Input Pull-Up Current

VFIXEN INPUT (Active-Low Input)

VFIXEN Input Voltage (High)

VFIXEN Input Voltage (Low)

VFIXEN Hysteresis

-

CC

V

0.9

-

V

HIGH

0.6

LOW

Low - High or High - Low

Internal Pullup to V

100

15

mV

mA

VFIXEN Input Pull-Up Current

-

CC

3. Guaranteed by design. Not production tested.

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10

NCP5393

ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvT v70°C; 4.75 VvV v5.25 V; All DAC Codes; C

= 0.1 mF)

A

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

PSI_L (Power Saving Control, Active Low) (This pin is used in PVI mode only)

PSI_L Input Voltage (High)

PSI_L Input Voltage (Low)

PSI_L Hysteresis

V

HIGH

V

LOW

V

HIGH

0.9

-

V

0.6

- V

or V

- V

HIGH

100

mV

LOW

CURRENT LIMIT

Current Sense Amp to ILIM Gain

ILIM Pin Input Bias Current

20 mV < (CSx - CSxN) < 60 mV (CS inputs tied)

5.7

-

6.0

-

6.3

0.5

2.0

V/V

mA

V

ILIM Pin Working Voltage Range

(Noteꢀ3)

0.2

-

ILIM Offset Voltage

Offset extrapolated to CSx-CSxN = 0 V, and referred

to the ILIM pin

-

30

-

mV

Delay

600

1.0

ns

V

VDDNB Current Limit Coefficient

= N x V

/V

, where N = number of VDD

NBILIM ILIM

is the equivalent voltage

phases, and V

NBILIM

threshold for NB Current Limit resulting from V

.

ILIM

OFFSET INPUTS (V & V

DD

)

DDNB

Output Offset Voltage Above VDAC

OUTPUT OVERVOLTAGE PROTECTION (V & V

0

-

800

mV

)

DDNB

DD

Over Voltage Threshold

In normal operation, with no VID changes

V

DAC

+ 250

VCCA UNDERVOLTAGE PROTECTION

VCCA UVLO Start Threshold

VCCA UVLO Stop Threshold

VCCA UVLO Hysteresis

INPUT SUPPLY CURRENT

VCC Operating Current

12VMON

4.0

3.8

4.25

4.05

200

4.5

4.3

V

mV

ENABLE held Low, No PWM operation

-

25

35

mA

12VMON (High Threshold)

12VMON (Low Threshold)

12VMON Hysteresis

8

7

8.5

7.5

1.0

9

8

V

Low - High or High - Low

3. Guaranteed by design. Not production tested.

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11

NCP5393

TYPICAL CHARACTERISTICS

2.03

2.01

1.99

1.5

1.4

Enable Increasing Voltage

1.3

1.2

1.97

1.95

Enable Decreasing Voltage

1.1

1.0

0

25

50

75

0

25

50

75

T , JUNCTION TEMPERATURE (°C)

J

Figure 1. SS Time vs. Temperature

Figure 2. Enable Threshold Voltage vs.

Temperature

26.1

25.8

25.5

25.2

24.9

24.6

231.1

230.8

230.5

230.2

229.9

229.6

24.3

24.0

229.3

229.0

25

50

25

50

T , JUNCTION TEMPERATURE (°C)

J

Figure 3. I_CCCurrent vs. Temperature

Figure 4. 2/3/4 Phase Detection Threshold vs.

Temperature

4.5

4.0

2.009

2.008

2.007

2.006

2.005

V

Increasing Voltage

CCP

V

Decreasing Voltage

CCP

3.5

3.0

2.004

2.003

25

50

25

50

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 5. V_CCPUndervoltage Lockout

Threshold Voltage vs. Temperature

Figure 6. ROSC Voltage vs. Temperature

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12

NCP5393

TYPICAL CHARACTERISTICS

10

370

PWRGOOD Upper Voltage

9.5

360

350

340

330

9.0

8.5

8.0

V

CC

Increasing Voltage

V

CC

Decreasing Voltage

7.5

7.0

320

310

PWRGOOD Lower Voltage

25

0

25

50

75

0

50

75

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 7. 12VMON Undervoltage Lockout

Threshold Voltage vs. Temperature

Figure 8. PWRGOOD Voltage vs. Temperature

Functional Description

General

NCP5393 is an universal CPU Power Supply Controller

compatible with both Parallel (PVI) and Serial (SVI)

protocols for AMD Processors. The device provides

and the Vcore ground reference point to VSN. This

configuration keeps ground potential differences between the

local controller ground and the Vcore ground reference point

from affecting regulation of Vcore between Vcore and Vcore

ground reference points. The RSA also subtracts the DAC

(minus VID offset) voltage, thereby producing an unamplified

output error voltage at the DIFFOUT pin. This output also has

a 1.3 V bias voltage as the floating ground to allow both

positive and negative error voltages.

complete control logic and protections for

a

high-performance step-down DC-DC voltage regulator,

optimized for advanced microprocessor power supply

supporting both PVI and SVI communication. It embeds two

independent controllers for CPU CORE and the integrated

NB, each one with its set of protections. The Controller

performs a single-phase control for the NB Section and a

programmable 2- to-4 phase control for the CORE Section

featuring Dual-Edge multiphase architecture.

Precision Programmable DAC

A precision programmable DAC is provided and system

trimmed. This DAC has 0.5% accuracy over the entire

operating temperature range of the part. The DAC can be

programmed to support both PVI and SVI VID code

specifications.

NCP5393 also supports V_FIX mode for board debug: in

this particular configuration the SVI bus is used as a static

bus configuring 4 operative voltages for both the sections

and ignoring any serial-VID command. It can be used for

the board debug before plugging-in the CPU.

High Performance Voltage Error Amplifier

The NCP5393 incorporates differential voltage sensing,

differential phase current sensing, optional load-line

voltage positioning, and programmable VDD and VDDNB

offsets to provide accurately regulated power parallel- and

serial-VID AMD processors. Dual-edge multiphase

modulation provides the fastest initial response to dynamic

load events.

NCP5393 is able to detect which kind of CPU is connected

in order to configure itself to work as a Single-Plane PVI

controller or Dual-Plane SVI controller. The NCP5393

manages On the Fly VID transitions and maintains the slew

rates as defined when the transitions take place. NCP5393

is available in TQFN48 Package.

The error amplifier is designed to provide high slew rate

and bandwidth. Although not required when operating as the

controller of a voltage regulator, a capacitor from COMP to

VFB is required for stable unity gain test configurations.

Gate Driver Outputs and 2/3/4 Phase Operation

The part can be configured to run in 2-, 3-, or 4-phase

mode. In 2-phase mode, phases 1 and 3 should be used to

drive the external gate drivers, G2 and G4 must be grounded.

In 3-phase mode, gate output G4 must be grounded. In

4-phase mode all 4 gate outputs are used as shown in the

4-phase Applications Schematic. The Current Sense inputs

of unused channels should be connected to GND. Please

refer to table “PIN CONNECTIONS vs. PHASE COUNTS”

for details.

Remote Output Sensing Amplifier (RSA)

A true differential amplifier allows the NCP5393 to measure

Vcore voltage feedback with respect to the Vcore ground

reference point by connecting the Vcore reference point to VSP,

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13

NCP5393

Differential Current Sense Amplifiers and Summing

Amplifier

oscillator generates up to 4 symmetrical triangle waveforms

with amplitude between 1.3_V and 2.3_V. The triangle

waves have a phase delay between them such that for 2-, 3-

and 4-phase operation the PWM outputs are separated by

180, 120, and 90 angular degrees, respectively.

Four differential amplifiers are provided to sense the

output current of each phase. The inputs of each current

sense amplifier must be connected across the current sensing

element of the phase controlled by the corresponding gate

output (G1, G2, G3, or G4). If a phase is unused, the

differential inputs to that phase's current sense amplifier

must be shorted together and connected to the GND.

The current signals sensed from inductor DCR are fed into

a summing amplifier to have a summed-up output. The

outputs of current sense amplifiers control three functions.

First, the summing current signal of all phases will go

through DROOP amplifier and join the voltage feedback

loop for output voltage positioning. Second, the output

signal from DROOP amplifier also goes to ILIM amplifier

to monitor the output current limit. Finally, the individual

phase current contributes to the current balance of all phases

by offsetting their ramp signals of PWM comparators.

When the NB phase is enabled, in order to ensure that the

VDDNB oscillator does not accidentally lock to the VDD

oscillator, the VDDNB oscillator will free-run at a

frequency which is nominally 1.25 ratio of f

.

VDD

CPU Support

NCP5393 is able to detect the CPU it is going to supply

and configure itself accordingly. At system Start-up, on the

rising-edge of the EN signal, the device monitors the status

of VID1 and switches in PVI mode (VID1 = 1) or SVI mode

(VID1 = 0). When in PVI mode, NCP5393 uses the

information available on the VID[0:5] bus to address the

CORE Section output voltage. NB Section is kept in HiZ

mode. When in SVI mode, NCP5393 discards the

information available on VID0, VID4 and VID5 and uses

VID2 and VID3 for SVC and SVD respectively.

Oscillator and Triangle Wave Generator

The controller embeds a programmable precision

dual-Oscillator: one section is used for the CORE and it is

a multiphase programmable oscillator managing equal

phase-shift among all phases and the other section is used

for the NB section. The oscillator's frequency is

programmed by the resistance connected from the ROSC

pin to ground. The user will usually form this resistance

from two resistors in order to create a voltage divider that

uses the ROSC output voltage as the reference for creating

the current limit setpoint voltage. The oscillator frequency

range is 100_kHz per phase to 1.0_MHz per phase. The

PVI - Parallel Interface

PVI is a 6-bit-wide parallel interface used to address the

CORE Section reference. According to the selected code,

the device sets the CORE Section reference and regulates its

output voltage. NB Section is kept in HiZ; no activity is

performed on this section. furthermore, PWROK

information is ignored as well since the signal is propietary

of the SVI protocol. Start-up sequences before soft start and

after soft start are given in Figure 9. Voltage identifications

for the 6Bit AMD mode is given in Table 1.

Figure 9. Power Up Sequences Before and After Soft Start in PVI Mode

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14

NCP5393

Table 1. SIX-BIT PARALLEL VID CODES in PVI Modes

SVID[5:0]

00_0000

00_0001

00_0010

00_0011

00_0100

00_0101

00_0110

10_0111

00_1000

00_1001

00_1010

00_1011

00_1100

00_1101

00_1110

00_1111

V

(V)

SVID[5:0]

01_0000

01_0001

01_0010

01_0011

01_0100

01_0101

01_0110

01_0111

01_1000

01_1001

01_1010

01_1011

01_1100

10_1101

01_1110

01_1111

V

(V)

SVID[5:0]

10_0000

10_0001

10_0010

10_0011

10_0100

10_0101

10_0110

10_0111

10_1000

10_1001

10_1010

10_1011

10_1100

10_1101

10_1110

10_1111

V

(V)

SVID[5:0]

11_0000

11_0001

11_0010

11_0011

11_0100

11_0101

11_0110

11_0111

11_1000

11_1001

11_1010

11_1011

11_1100

11_1101

11_1110

11_1111

V

(V)

OUT

1.5500

1.5250

1.5000

1.4750

1.4500

1.4250

1.4000

1.3750

1.3500

1.3250

1.3000

1.2750

1.2500

1.2250

1.2000

1.1750

1.1500

1.1250

1.1000

1.0750

1.0500

1.0250

1.0000

0.9750

0.9500

0.9250

0.9000

0.8750

0.8500

0.8250

0.8000

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6325

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

SVI - Serial Interface

SVI is a two wire, Clock and Data, bus that connects a

single master (AMD processor) to one NCP5393. The

master initiates and terminates SVI transactions and drives

the clock, SVC, and the data SVD, during a transaction. The

slave receives the SVI transactions and acts accordingly.

SVI wire protocol is based on fast-mode I2C. The SVI

communications are given in Figure 10.

SVI interface also considers EN and PWROK signals for

start-up. The device returns a PWRGOOD signal if the

output voltages are in regulation. The VID codes for SVI are

given in Table 2.

Figure 10. SVI Communication - Send Byte

The start-up sequences before and after soft start are

given in Figure 11.

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15

NCP5393

Table 2. SEVEN-BIT SERIAL VID CODES for SVI Mode

SVID[6:0]

000_0000

000_0001

000_0010

000_0011

000_0100

000_0101

000_0110

000_0111

000_1000

000_1001

000_1010

000_1011

000_1100

000_1101

000_1110

000_1111

001_0000

001_0001

001_0010

001_0011

001_0100

001_0101

001_0110

001_0111

001_1000

001_1001

001_1010

001_1011

001_1100

001_1101

001_1110

001_1111

V

(V)

SVID[6:0]

010_0000

010_0001

010_0010

010_0011

010_0100

010_0101

010_0110

010_0111

010_1000

010_1001

010_1010

010_1011

010_1100

010_1101

010_1110

010_1111

011_0000

011_0001

011_0010

011_0011

011_0100

011_0101

011_0110

011_0111

011_1000

011_1001

011_1010

011_1011

011_1100

011_1101

011_1110

011_1111

V

(V)

SVID[6:0]

100_0000

100_0001

100_0010

100_0011

100_0100

100_0101

100_0110

100_0111

100_1000

100_1001

100_1010

100_1011

100_1100

100_1101

100_1110

100_1111

101_0000

101_0001

101_0010

101_0011

101_0100

101_0101

101_0110

101_0111

101_1000

101_1001

101_1010

101_1011

101_1100

110_1101

101_1110

101_1111

V

(V)

SVID[6:0]

110_0000

110_0001

110_0010

110_0011

110_0100

110_0101

110_0110

110_0111

110_1000

110_1001

110_1010

110_1011

110_1100

110_1101

110_1110

110_1111

111_0000

111_0001

111_0010

111_0011

111_0100

111_0101

111_0110

111_0111

111_1000

111_1001

111_1010

111_1011

111_1100

111_1101

111_1110

111_1111

V

(V)

OUT

1.5500

1.5375

1.5250

1.5125

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6325

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

OFF

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16

NCP5393

Figure 11. Power Up Sequences Before and After Soft Start in SVI Mode

Hardware Jumper Override - V_FIX

VFIX is an active low pin and when it is pulled low, the

controller enters V_FIX mode.The voltage regulator can be

powered when an external SVI bus master is not present.

When in VFIX mode, all of the voltage regulator's output

voltages will be governed by the information shown in

Tableꢁ3, regardless of the state of PWROK. VFIX mode is

for debug and bring-up only. If VFIX mode is necessary for

processor bring-up, VFIXEN, SVC, and SVD should be

connected with jumpers to either ground or VDDIO through

suitable pull-up resistors. SVC and SVD are considered as

static VID and the output voltage will change according to

their status.

• This capture is INDEPENDENT of any other signal.

SVI/PVI is determined by sampling VID[1] during

rising edge of ENABLE (SVI: VID[1]=0, PVI:

VID[1]=1). Once SVI/PVI is determined, the VID

controller is enabled and increments to the Boot VID at

the Soft Start rate. VFIXEN mode is entered once

VFIXEN is asserted.

• If VFIXEN is asserted prior to the VID controller

reaching the Boot VID, the VID controller will move to

the VFIXEN VID. Once the first VID value is reached

(either BOOT VID or VFIXEN VID), the VID will

now increment at the Normal rate. Once the VID

controller is enabled, the VID controller can receive

VFIXEN VIDs, independent of PWROK which is

ignored in VFIXEN mode.

Table 3. SVI VFIX VID CODES (TWO-BIT PARALLEL)

SVC

SVD

V

OUT

(V)

• If VFIXEN is de-asserted, the device PORs. This

0

1

0

1

0

1

1.4

occurs independent of ENABLE

1.2

1.0

0.8

PWROK De-assertion

Anytime PWROK de-asserts while EN is asserted, the

controller uses the previously stored BOOT VID and

regulates all planes to that level performing an on-the-Fly

transition to that level. PWRGOOD remains asserted in this

process.

Start-up sequences are presented below:

• Boot VID is captured from SVC and SVD pins on

rising edge of ENABLE.

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17

NCP5393

Protection Features:

voltage, the PWRGOOD goes low, the DRVON signal

remains high, the PWM outputs are set low. The outputs will

remain disabled until the VCC voltage is removed and

reapplied. Every time the OV is triggered it will increment

the OV counter. If the counter reaches a count of 16 then the

OV condition will latch into a permanent OV state. It will

require POR or disable/enable to restart. Prior to latching if

the OV condition goes away then normal operation will

resume. An OV decrement counter is also incorporated. It

consists of a free-running clock which runs at 8x the PWM

frequency. So essentially every 4096 PWM cycles the OV

counter will decrement. For example, for a max PWM

frequency of 1 MHz, the counter decrements roughly every

4ꢁms and for a PWM frequency of 400 kHz, it would be

about every 10 ms. During normal operation, if the output

voltage falls more than 350_mV below the DAC setting, the

PWRGOOD pin will be set low until the output voltage

rises.

Undervoltage Lockout

An undervoltage lockout (UVLO) senses the VCC and

VCCP input. During powerup, the input voltage to the

controller is monitored, and the PWM outputs and the

soft-start circuit are disabled until the input voltage exceeds

the threshold voltage of the UVLO comparator. The UVLO

comparator incorporates hysteresis to avoid chattering,

since VCC is likely to decrease as soon as the converter

initiates soft-start.

Overcurrent Shutdown

A programmable overcurrent function is incorporated

within the IC. A comparator and latch make up this function.

The inverting input of the comparator is connected to the

ILIM pin. The voltage at this pin sets the maximum output

current the converter can produce. The ROSC pin provides

a convenient and accurate reference voltage from which a

resistor divider can create the overcurrent setpoint voltage.

Although not actually disabled, tying the ILIM pin directly

to the ROSC pin sets the limit above useful levels -

effectively disabling overcurrent shutdown. The

comparator noninverting input is the summed current

information from the VDRP minus offset voltage. The

overcurrent latch is set when the current information

exceeds the voltage at the ILIM pin. The outputs are pulled

low, and the soft-start is pulled low. The outputs will remain

disabled until the VCCvoltage is removed and re-applied, or

the ENABLE input is brought low and then high.

Soft-Start

The NCP5393 simply ramps Vcore to boot voltage at a

fixed rate of 2 ms (0.8ꢁmV/uS), and then reads the VID pins

to determine the DAC setting. Then ramps Vcore to the final

DAC setting at the Dynamic VID slew rate of up to

3.25ꢁmV/mS. In SVI mode, SoftStart Time is intended as the

time required by the device to set the output voltages to the

Pre-PWROK Metal VID. In PVI mode, VID[0:5] or V_FIX

VID in V_FIX mode are the set output voltages. Typical soft

start sequence timing in SVI mode is given in Figure 12.

Output Overvoltage and Undervoltage Protection and

Power Good Monitor

An output voltage monitor is incorporated. Duringnormal

operation, if the output voltage is 250 mV over the DAC

Figure 12. Soft-Start Sequence to Vcore = 1.3 V

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18

NCP5393

Programming the Current Limit and the Oscillator Frequency

The demo board is set for an operating frequency of

approximately 330 kHz. The ROSC pin provides a 2.0 V

reference voltage which is divided down with a resistor

divider and fed into the current limit pin ILIM. Calculate the

total series resistance to set the frequency and then calculate

the individual RLIM1 and RLIM2 values for the divider.

The series resistors RLIM1 and RLIM2 sink current from

the ILIM pin to ground. This current is internally mirrored

into a capacitor to create an oscillator. The period is

proportional to the resistance and frequency is inversely

proportional to the total resistance. The total resistance may

be estimated by Equation 2. This equation is valid for the

individual phase frequency in both three and four phase

mode.

-1.1549

R

^ 24686 Fsw

TOTAL

(eq. 1)

-1.1549

30.5ꢀ·ꢀkW ^ 24686 330

Figure 13. ROSC vs. Frequency

The current limit function is based on the total sensed

current of all phases multiplied by a gain of 6. DCR sensed

inductor current is function of the winding temperature. The

best approach is to set the maximum current limit based on

the expected average maximum temperature of the inductor

windings.

DCR

+ DCR ꢀ·ꢀ

25C

Tmax

(eq. 2)

(1 ) 0.00393ꢀ(T

-25))

max

Calculate the current limit voltage:

DCR

Tmax

2ꢀ·ꢀVinꢀ·ꢀF

ꢀ·ꢀVout

Vin-Vout

L

Vout

L

(eq. 3)

_{ꢀ ·ꢀ}ǒ

Ǔ

_^ 6ꢀ·ꢀǒ_{IMIN_OCP}

Ǔ

V

ꢀ·ꢀDCR

Tmax

)

* (N-1)ꢀ·ꢀ

ILIMIT

sw

Solve for the individual resistors:

V

ꢀ·ꢀR

ILIMIT TOTAL

RLIM1 + R

-R

TOTAL LIM2

(eq. 4)

(eq. 5)

(eq. 6)

RLIM2 +

2ꢀ·ꢀV

Final Equation for the Current Limit Threshold

2ꢀ·ꢀVꢀ·ꢀRLIM2

RLIM1)RLIM2

ǒ

Ǔ

Vout

2ꢀ·ꢀVinꢀ·ꢀF

sw

Vin-Vout

L

Vout

L

_{ꢀ ·ꢀ}ǒ

Ǔ

I

(T

LIMIT inductor

) ^

*

* (N-1)ꢀ·ꢀ

6ꢀ·ꢀ(DCR

ꢀ·ꢀ(1 ) 0.00393(T

25C

-25)))

Inductor

The inductors on the demo board have a DCR at 25°C of

limit of 152 A at 100°C. The total sensed current can be

observed as a scaled voltage at the VDRP pin added to a

positive, no-load offset of approximately 1.3 V.

0.75 mW. Selecting the closest available values of 16.9 kW

for RLIM1 and 13.7 kW for RLIM2 yield a nominal

operating frequency of 330 kHz and an approximate current

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19

NCP5393

OUTPUT OFFSET VOLTAGES

External offset voltages from 0 mv to 800 mV `above the DAC' can be added for the V and V independently.

Offset is set by a resistor divider from V to GND. Output offsets are ratiometric to V . As V changes, the on-chip scaling

DD

DD_NB

CC

factors change by the same amount:

Offset = 0.8 V x V

/V

OFFSET CC

For example: For 0 V offset: pin voltage = GND; For 800 mV offset: pin voltage = V

CC

Minimum Voffset_IN

(as Vin/Vcc)

Typical Voffset_IN

(as Vin/Vcc)

Maximum Voffset_IN

(as Vin/Vcc)

Resulting Output Offset

Units

mV

0

0.046875

0.078125

0.109375

0.140625

0.171875

0.203125

0.234375

0.265625

0.296875

0.328125

0.359375

0.390625

0.421875

0.453125

0.484375

0.515625

0.546875

0.578125

0.609375

0.640625

0.671875

0.703125

0.734375

0.765625

0.796875

0.828125

0.859375

0.890625

0.921875

0.953125

0.984375

Vcc+0.3V

0

0.046875

0.078125

0.109375

0.140625

0.171875

0.203125

0.234375

0.265625

0.296875

0.328125

0.359375

0.390625

0.421875

0.453125

0.484375

0.515625

0.546875

0.578125

0.609375

0.640625

0.671875

0.703125

0.734375

0.765625

0.796875

0.828125

0.859375

0.890625

0.921875

0.953125

0.984375

0.06250

0.09375

0.12500

0.15625

0.18750

0.21875

0.25000

0.28125

0.31250

0.34375

0.37500

0.40625

0.43750

0.46875

0.50000

0.53125

0.56250

0.59375

0.62500

0.65625

0.68750

0.71875

0.75000

0.78125

0.81250

0.84375

0.87500

0.90625

0.93750

0.96875

1.00000

25

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

425

450

475

500

525

550

575

600

625

650

675

700

725

750

800

The input to the OFFSET pin for the VDD output is encoded by an internal ADC.

The input to the NB_OFFSET pin for the VDDNB output is encoded by the same ADC.

The reference for this ADC is VCC. The ADC's output is ratiometric to VCC.

Voffset IN represents the voltage applied to the OFFSET or NB_OFFSET pin.

It is intended that these voltages be derived by a resistive divider from Vcc.

The recommended total driving impedance is <10 kilohms.

http://onsemi.com

20

NCP5393

PACKAGE DIMENSIONS

QFN48 7x7, 0.5P

CASE 485AJ-01

ISSUE O

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

D

A B

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO THE PLATED

TERMINAL AND IS MEASURED ABETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN 1

LOCATION

MILLIMETERS

E

DIM MIN

0.80

A1 0.00

MAX

1.00

0.05

A

2X

L

A3

b

0.20 REF

0.15

C

0.20

0.30

D

D2 5.00

E 7.00 BSC

E2 5.00

7.00 BSC

DETAIL A

OPTIONAL CONSTRUCTION

2X SCALE

5.20

2X

0.15

C

TOP VIEW

e

K

L

0.50 BSC

0.20

0.30

---

0.50

(A3)

0.05

0.08

A

SOLDERING FOOTPRINT*

2X

C

A1

NOTE 4

SEATING

PLANE

5.20

C

SIDE VIEW

D2

DETAIL A

1

K

13

25

12

2X

7.30

48X

0.63

E2

48X

0.50 PITCH

0.30

1

36

DIMENSIONS: MILLIMETERS

48

37

48X

b

e

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

^48XL

0.10 C A B

e/2

NOTE 3

C

0.05

BOTTOM VIEW

The products described herein (NCP5393), may be covered by one or more of the following U.S. patents, #US07057381. There may be other patents

pending.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

ꢁLiterature Distribution Center for ON Semiconductor

ꢁP.O. Box 5163, Denver, Colorado 80217 USA

N. American Technical Support: 800-282-9855 Toll Free

ꢁUSA/Canada

Europe, Middle East and Africa Technical Support:

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

ꢁPhone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada ꢁPhone: 421 33 790 2910

ꢁFax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada

ꢁEmail: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

Japan Customer Focus Center

ꢁPhone: 81-3-5773-3850

NCP5393/D

http://onsemi.com

21


型号：	NCP5393
厂家：	ONSEMI
描述：	2/3/4-Phase Controller for CPU Applications 2/3/ 4相位控制器的CPU应用控制器
文件：	总21页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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