NCP5395T_技术文档

NCP5395T

2/3/4-Phase Controller with

On Board Gate Drivers for

CPU Applications

The NCP5395T provides up to a four−phase buck solution which

combines differential voltage sensing, differential phase current

sensing, and adaptive voltage positioning to provide accurately

regulated power for both Intel and AMD processors. It also receives

power saving command (PSI) from CPU, and operates in a single

phase emulation diode mode to obtain a high efficiency at light load.

Dual−edge pulse−width modulation (PWM) combined with precise

inductor current sensing provides the fastest initial response to

dynamic load events both in power saving and normal modes.

Dual−edge multiphase modulation reduces the total bulk and ceramic

output capacitance required therefore reducing the system cost to meet

transient regulation specifications.

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QFN48, 7x7

CASE 485AJ

1

48

MARKING DIAGRAM

48

1

The on board gate drivers includes adaptive non overlap and power

saving operation. A high performance operational error amplifier is

provided to simplify compensation of the system. Patented Dynamic

Reference Injection further simplifies loop compensation by

eliminating the need to compromise between closed−loop transient

NCP5395T

AWLYYWWG

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

WL

YY

WW

G

response and Dynamic V performance.

ID

Features

• Meets Intel’s VR11.1 and AMD’s 6 Bit Code Specifications

• Enhanced Power Saving Function

• Internal Soft Start

• Dual−edge PWM for Fastest Initial Response to Transient Loading

• High Performance Operational Error Amplifier

• Dynamic Reference Injection (Patent #US07057381)

• DAC Range from 0.5 V to 1.6 V

48

1

BG1

BG3

PSI

G4

VRRDY

EN

VID0

VID1

CS1N

CS1P

CS2N

CS2P

CS3N

CS3P

CS4N

CS4P

VID2

AGND

Down−bonded to

Exposed Flag

• DAC Feed Forward Function (Patient Pending)

VID3

VID4

•

0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V

VID5

VID6

• True Differential Remote Voltage Sensing Amplifier

• Phase−to−Phase Current Balancing

VID7/AMD

ROSC

ILIM

• “Lossless” Differential Inductor Current Sensing

• Accurate Current Monitoring (IMON)

• Differential Current Sense Amplifiers for Each Phase

• Adaptive Voltage Positioning (AVP)

ORDERING INFORMATION

• Oscillator Frequency Range of 125 kHz − 1 MHz

• Latched Over Voltage Protection (OVP)

†

Device

NCP5395TMNR2G

Package

Shipping

• Guaranteed Startup into Pre−Charged Loads

• Threshold Sensitive Enable Pin for VTT Sensing

• Power Good Output with Internal Delays

QFN48

(Pb−Free)

2500/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• Output Disable Control Turn Off of Both Phase Pair MOSFETs

• Thermally Compensated Current Monitoring

• Adaptive−Non−Overlap Gate Drive Circuit

Applications

• Thermal Shutdown Protection

• This is a Pb−Free Device

• Desktop Processors

1

Publication Order Number:

June, 2009 − Rev. 0

NCP5395T/D

NCP5395T

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7/AMD

Flexible DAC

VCCP

Overvoltage

Protection

-

+

PSI

BST1

TG1

+

-

DAC

Phase 1

Gate Driver

with

Adaptive

Non−overlap

VSN

VSP

-

+

SWN1

BG1

Diff Amp

DIFFOUT

1.3 V

Error Amp

+

-

BST2

TG2

VFB

Phase 2

Gate Driver

with

Adaptive

Non−overlap

+

-

COMP

VDRP

SWN2

BG2

+

-

VDFB

−2/3

CSSUM

+

CS1P

CS1N

+

-

+

Gain = 6

BST3

TG3

CS2P

CS2N

+

-

+

Phase 3

Gate Driver

with

Adaptive

Non−overlap

+

-

SWN3

CS3P

CS3N

+

-

+

BG3

G4

Gain = 6

+

-

CS4P

CS4N

+

-

Oscillator

IMON

ROSC

ILIM

DRVON

Control,

Fault Logic

and

Monitor

Circuits

+

-

12VMON

VR_RDY

I

Limit

EN

VCC

+

-

4.25 V

UVLO

GND (FLAG)

Figure 1. NCP5395T Functional Block Diagram

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2

NCP5395T

VTT

PSI#_CPU

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

12V_FILTER

D

1

2

12V_FILTER

G

S

IMON

D

S

D

G

PWM3_SENSE_N

PWM3_SENSE_P

G

S

VCCP

48

VBST3

13

14

IMON

VSP

CFB

RFB

47

46

45

44

43

42

TG3

SWN3

DRVON

BST2

15

16

17

18

19

VSN

DIFFOUT

COMP

VFB

RF

CF

RFB

RDRP

R

DRVON

CH

NCP5395T

48L 7x7 QFN

FLAG = GND

TG2

SWN2

VDRP

VDFB

12V_FILTER

CDFB

RDFB

12V_FILTER

20

21

22

BG2 41

40

39

38

37

VCCP

SWN1

TG1

CSSUM

DAC

2

1

RISO

RT

D

G

23

24

12V_FILTER

12VMON

VCC

S

BST1

D

S

D

S

PWM1_SENSE_N

PWM1_SENSE_P

C17

G

+5.0V

VTT

VCCP

PWM1_SENSE_P

PWM1_SENSE_N

ENABLE

PWM3_SENSE_P

PWM3_SENSE_N

Figure 2. Typical 2 Phase Application

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3

NCP5395T

VTT

R236

PSI#_CPU

12V_FILTER

D

2

1

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

12V_FILTER

G

S

D

S

D

PWM3_SENSE_N

PWM3_SENSE_P

G

S

VCCP

12V_FILTER

48

VBST3

IMON

13

14

CFB

RFB

2

1

RFB

47

46

45

44

43

42

41

VSP

TG3

SWN3

DRVON

BST2

TG2

D

15

16

17

18

19

20

VSN

G

S

DIFFOUT

COMP

VFB

DRVON

RF

CH

NCP5395T

48L 7x7 QFN

FLAG = GND

D

S

D

CF

PWM2_SENSE_N

PWM2_SENSE_P

RDRP

R

G

S

G

VDRP

VDFB

CSSUM

DAC

SWN2

BG2

CDFB

RDFB

RT

12V_FILTER

21

22

VCCP

SWN1

TG1

40

39

12V_FILTER

RISO

38

37

23

24

12VMON

VCC

12V_FILTER

2

1

D

G

BST1

S

C37

VCCP

+5.0V

VTT

D

S

D

S

PWM1_SENSE_N

PWM1_SENSE_P

G

PWM1_SENSE_P

PWM1_SENSE_N

PWM2_SENSE_P

12V_FILTER

ENABLE

PWM2_SENSE_N

PWM3_SENSE_P

PWM3_SENSE_N

Figure 3. Typical 3 Phase Application

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4

NCP5395T

VTT

PSI#_CPU

1

2

12V_FILTER

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

12V_FILTER

D

G

S

D

S

D

G

PWM3_SENSE_N

PWM3_SENSE_P

S

IMON

VCCP

12V_FILTER

48

47

46

45

VBST3

TG3

13

14

IMON

VSP

2

1

CFB

RFB

CH

D

G

15

16

17

18

19

20

21

22

VSN

SWN3

DRVON

BST2

TG2

DRVON

S

DIFFOUT

COMP

VFB

RF

CF

NCP5395T

48L 7x7 QFN

FLAG = GND

44

43

D

S

D

G

PWM2_SENSE_N

PWM2_SENSE_P

RDRP

G

42

VDRP

VDFB

CSSUM

DAC

SWN2

BG2

S

CDFB

41

12V_FILTER

40

RDFB

RT

VCCP

SWN1

TG1

12V_FILTER

39

38

37

RISO

23

24

2

1

12VMON

VCC

12V_FILTER

D

G

BST1

S

VCCP

D

S

D

+5.0V

VTT

PWM1_SENSE_N

PWM1_SENSE_P

PWM4_GATE

G

S

PWM1_SENSE_P

PWM1_SENSE_N

12V_FILTER

PWM2_SENSE_P

2

1

ENABLE

D

S

PWM2_SENSE_N

PWM3_SENSE_P

G

BST

1

VCC

4

DRH

SW

PWM3_SENSE_N

DRVON

PWM4_GATE

PWM4_SENSE_P

8

7

5

6

OD

IN

3

2

DRL

PGND

D

S

D

S

PWM4_SENSE_N

PWM4_SENSE_P

NCP5359

G

PWM4_SENSE_N

Figure 4. Typical 4 Phase Application

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5

NCP5395T

Table 1. Pin Descriptions

Pin No.

Symbol

Description

1

2

BG3

PSI

Low side gate drive #3

Power Saving Control. Low = single phase operation; High = normal operation

3

VID0

Voltage ID DAC input

4

VID1

5

VID2

6

VID3

7

VID4

8

VID5

9

VID6

10

11

VID7/AMD

ROSC

Voltage ID DAC input. Pull to V (5 V) to enable AMD 6−bit DAC code.

CC

A resistance from this pin to ground programs the oscillator frequency and provides a 2 V reference

for programming the ILIM voltage.

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

FLAG

ILIM

Over current shutdown threshold setting. ILIM = VDRP − 1.3 V. Resistor divide ROSC to set threshold

0 to 1.1 V analog signal proportional to the output load current. VSN referenced Clamped to 1.1 Vmax

Non−inverting input to the internal differential remote sense amplifier

Inverting input to the internal differential remote sense amplifier

Output of the differential remote sense amplifier

Output of the compensation amplifier

IMON

VSP

VSN

DIFFOUT

COMP

VFB

Compensation amplifier voltage feedback

VDRP

VDFB

CSSUM

DAC

Voltage output signal proportional to current used for current limit and output voltage droop

Droop Amplifier Voltage Feedback

Inverted Sum of the Differential Current Sense inputs

DAC output used to provide feed forward for dynamic VID

Monitor a 12 V input through a resistor divider

12VMON

VCC

Power for the internal control circuits with UVLO monitor

Non−inverting input to current sense amplifier #4

Inverting input to current sense amplifier #4

CS4P

CS4N

CS3P

CS3N

CS2P

CS2N

CS1P

CS1N

EN

Non−inverting input to current sense amplifier #3

Inverting input to current sense amplifier #3

Non−inverting input to current sense amplifier #2

Inverting input to current sense amplifier #2

Non−inverting input to current sense amplifier #1

Inverting input to current sense amplifier #1

Threshold sensitive input. High = startup, Low =shutdown.

Open collector output. High indicates that the output is regulating

PWM output pulse to gate driver.

VR_RDY

G4

BG1

Low side gate drive #1

BST1

TG1

Upper MOSFET floating bootstrap supply for driver#1

High side gate drive #1

SWN1

VCCP

BG2

Switch Node #1

Power V for gate drivers with UVLO monitor

CC

Low side gate drive #2

SWN2

TG2

Switch Node #2

High side gate drive #2

BST2

DRVON

SWN3

TG3

Upper MOSFET floating bootstrap supply for driver#2

Bidirectional Gate Drive Enable

Switch Node #3

High side gate drive #3

BST3

GND

Upper MOSFET floating bootstrap supply for driver#3

Power supply return (QFN Flag)

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6

NCP5395T

ABSOLUTE MAXIMUM RATINGS

Rating

Symbol

Value

Unit

ELECTRICAL INFORMATION

Controller Power Supply Voltages to GND

Driver Power Supply Voltages to GND

High−Side Gate Driver Supplies: BSTx to SWNx

V

−0.3, 7

V

CC

V

CCP

−0.3, 15

V

− V

35 V wrt/GND

40 V ≤ 50 ns wrt/GND

−0.3, 15 wrt/SWN

BST

SWN

High−Side FET Gate Driver Voltages: TGx to SWNx

Switch Node: SWNx

V

− V

BOOT + 0.3 V

35 V ≤ 50 ns wrt/GND

−0.3, 15 wrt/SWN

−5 V (200 ns)

V

TG

SWN

V

SWN

35

40 V ≤ 50 ns wrt/GND

−5 VDC

−10 V (200 ns)

Low−Side Gate Drive: BGx

V

BG

− AGND

V

CC

+ 0.3 V

−5 V (200 ns)

−0.3, 6

0

Logic Inputs

V

LOGIC

GND

V

GND

V−

GND 300

1.1

mV

V

Imon Out

V

IMON

All Other Pins

−0.3, 5.5

V

THERMAL INFORMATION

Thermal Characteristic

QFN Package (Note 1)

R

30.5

°C/W

q

JA

Operating Junction Temperature Range (Note 2)

Operating Ambient Temperature Range

Maximum Storage Temperature Range

T

0 to 125

0 to +70

−55 to +150

1

°C

J

T

AMB

T

STG

Moisture Sensitivity Level

QFN Package

MSL

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

*All signals referenced to GND unless noted otherwise.

*The maximum package power dissipation must be observed.

1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM

2. Operation at −40°C to 0°C guaranteed by design, not production tested.

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7

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

ERROR AMPLIFIER

Open Loop DC Gain

C = 60 pF to GND,

L

−

100

18

−

dB

MHz

°

L

R = 10 kW to GND

Open Loop Unity Gain Bandwidth

Open Loop Phase Margin

Slew Rate

C = 60 pF to GND,

L

R = 10 kW to GND

L

C = 60 pF to GND,

70

L

R = 10 kW to GND

L

DV = 100 mV, G = −10V/V,

10

V/ms

in

DV = 1.5 V − 2.5 V,

out

C = 60 pF to GND,

L

DC Load = 125 mA to GND

Maximum Output Voltage

Minimum Output Voltage

Output Source Current

Output Sink Current

10 mV of Overdrive,

SOURCE

3.0

−

75

−

V

I

= 2.0 mA

10 mV of Overdrive,

= 500 mA

mV

mA

I

SINK

10 mV of Overdrive,

= 3.5 V

1.5

0.65

2.0

1.0

V

out

10 mV of Overdrive,

= 0.1 V

−

V

out

DIFFERENTIAL SUMMING AMPLIFIER

V+ Input Pull down Resistance

DRVON = low

DRVON = high

−

0.6

6.0

−

kW

V+ Input Bias Voltage

DRVON = low

DRVON = high

−

0.8

0.05

0.88

0.1

0.95

V

Input Voltage Range (Note 3)

−0.3

−

3.0

V

−3 dB Bandwidth

C = 80 pF to GND,

L

−

15

−

MHz

L

R = 10 kW to GND

Closed Loop DC gain VS to Diffout

Maximum Output Voltage

VS+ to VS− = 0.5 V to 1.6 V

0.98

3.0

1.0

1.02

V/V

V

10 mV of Overdrive,

−

I

= 2 mA

SOURCE

Minimum Output Voltage

Output Source Current

10 mV of Overdrive,

= 1 mA

−

0.5

−

V

I

SINK

10 mV of Overdrive,

= 3 V

1.5

1.0

2.0

1.5

mA

V

out

Output Sink Current

10 mV of Overdrive,

= 0.2 V

−

V

out

INTERNAL OFFSET VOLTAGE

Offset Voltage to the (+) Pin of the Error Amp & the

VDRP Pin

−2

0

+2

mV

3. Design guaranteed.

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8

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

VDROOP AMPLIFIER

Inverting Voltage Range

Open Loop DC Gain

0

1.3

3.0

V

C = 20 pF to GND including ESD

L

−

100

−

dB

L

R = 1 kW to GND

Open Loop Unity Gain Bandwidth

Open Loop Phase Margin

Slew Rate

C = 20 pF to GND including ESD

L

−

18

70

10

−

MHz

°

L

R = 1 kW to GND

C = 20 pF to GND including ESD

L

R = 1 kW to GND

L

C = 20 pF to GND including ESD

−

V/ms

V

L

R = 1 kW to GND

L

Maximum Output Voltage

Minimum Output Voltage

Output Source Current

Output Sink Current

10 mV of Overdrive,

3.0

−

I

= 4.0 mA

SOURCE

10 mV of Overdrive,

= 1.0 mA

−

1.0

−

V

I

SINK

10 mV of Overdrive,

= 3.0 V

4.0

1.0

−

mA

V

out

10 mV of Overdrive,

= 1.0 V

−

V

out

CSSUM AMPLIFIER

Current Sense Input to V

−3 dB Bandwidth

C = 10 pF to GND,

L

−

12

−

MHz

DRP

L

R = 10 kW to GND

Current Summing Amp Output Offset Voltage

Maximum CSSUM Output Voltage

CSx − CSNx = 0, CSx = 1.1 V

CSx − CSxN = −0.2 V

−13

−

8.0

mV

V

3.0

−

(all phases) I

= 1 mA

SOURCE

Minimum CSSUM Output Voltage

CSx − CSxN = 0.7 V

(all phases) I = 1 mA

−

0.3

V

SINK

Output Source Current

Output Sink Current

PSI

V

= 3.0 V

= 0.3 V

1.0

4.0

−

mA

out

V

out

Enable High Input Leakage Current

Threshold

External 1k Pull−up to 3.3 V

−

450

−

1.0

770

−

mA

mV

ns

600

100

Delay

DRVON

Output High Voltage

Output Low Voltage

Delay Time

Sourcing 500 mA

Sinking 500 mA

3.0

−

0.7

−

V

Propagation delays

−

10

ns

Rise Time

C (PCB) = 20 pF,

−

L

DVo = 10% to 90%

Fall Time

C (PCB) = 20 pF,

−

10

−

ns

L

DVo = 10% to 90%

Internal Pull−Down Resistance

35

70

140

2.0

kW

V

CC

Voltage when DRVON Output Valid

−

V

CURRENT SENSE AMPLIFIERS

Input Bias Current

CSx = CSxN = 1.4 V

all VIOS

−50

−0.3

−120

−2.5

−

50

2.0

120

2.5

nA

V

Common Mode Input Voltage Range

Differential Mode Input Voltage Range

Current Sharing Offset CS1 to CSx (Note 3)

mV

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9

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

CURRENT SENSE AMPLIFIERS

Current Sense Input to PWM Gain

Current Sense Input to CSSUM Gain

IMON

0 V < CSx − CSxN < 0.1 V,

0 V < CSx − CSxN < 0.1 V

5.45

5.75

6.05

V/V

−3.834

−3.7

−3.574

V

DRP

to IMON Gain

1.325 V > V

> 1.75 V

1.965

−

2.02

V/V

DRP

Current Sense Input to V

−3 dB Bandwidth

C = 30 pF to GND,

L

−

4.0

−

MHz

DRP

L

R = 100 kW to GND

Output Referred Offset Voltage

Minimum Output Voltage

Maximum Output Voltage

Output Sink Current

V

= 1.5 V, I

= 0 mA

SOURCE

0

25

−

50

0.1

−

mV

V

DRP

= 1.3 V, I

= 25 mA

−

SINK

I

= 300 mA

1.0

175

1.1

−

V

out

V

out

= 0.3 V

−

mA

V

Maximum Clamp Voltage

IMON − VSN V

R

= HIGH

−

1.2

DRP

= Open

LOAD

OSCILLATOR

Switching Frequency Range

Switching Frequency Accuracy

Switching Frequency Accuracy (2ph or 4ph)

Switching Frequency Accuracy (3ph)

ROSC Output Voltage

100

−

1100

5.0

kHz

%

200 kHz < F

100 kHz < F

< 600 kHz

< 1 MHz

SW

−

10

%

SW

R

= 16.2k

454

468

1.93

−

502

518

2.05

kHz

V

OSC

= 16.2k

−

2.00

MODULATORS (PWM Comparators)

Minimum Pulse Width

Fsw = 800 kHz

−

30

1.1

250

−

ns

V

Magnitude of the PWM Ramp

0% Duty Cycle

COMP Voltage when the PWM

Outputs Remain LO

50

400

mV

100% Duty Cycle

COMP Voltage when the PWM

Outputs Remain HI

1.1

1.35

1.6

15

V

PWM Phase Angle Error

Between Adjacent Phases

−15

−

°

VR_RDY (Power Good) OUTPUT

VR_RDY Output Saturation Voltage

VR_RDY Rise Time (Note 3)

I

= 10 mA

−

0.4

V

PGD

External pull−up of 1 KW to 1.25 V,

= 45 pF, DVo = 10% to 90%

100

150

ns

C

TOT

VR_RDY Output Voltage at Power−up

VR_RDY pulled up to 5 V via 2 kW,

≤ 3 x t

−

1.0

V

t

R(VCC)

R(5V)

100 ms ≤ t

≤ 20 ms

R(VCC)

VR_RDY High − Output Leakage Current

VR_RDY = 5.5 V via 1 K

−

0.1

mA

VR_RDY Upper Threshold Voltage (INTEL)

VCore Increasing, DAC = 1.3 V

300

250

mV

(below

DAC)

VR_RDY Lower Threshold Voltage (INTEL)

VR_RDY Upper Threshold Voltage (AMD)

VR_RDY Lower Threshold Voltage (AMD)

VCore Decreasing, DAC = 1.3 V

VCore Increasing, DAC = 1.3 V

VCore Decreasing, DAC = 1.3 V

390

−

350

−

300

142

192

mV

(below

DAC)

mV

(below

DAC)

282

−

mV

(below

DAC)

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10

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

VR_RDY (Power Good) OUTPUT

VR_RDY Rising Delay

VR_RDY Falling Delay

PWM G4 OUTPUT

VCore Increasing

−

250

5.0

−

ms

VCore Decreasing

Sourcing 500 mA

Sinking 500 mA

Output High Voltage

3.0

1.4

−

1.5

−

1.6

0.7

−

V

Mid Output Voltage

Output Low Voltage

V

Delay + Rise Time (Note 3)

C (PCB) = 50 pF,

−

10

ns

L

DVo = V to GND

CC

Delay + Fall Time (Note 3)

C (PCB) = 50 pF,

−

10

−

ns

L

DVo = GND to V

CC

Tri−State Output Leakage (Note 3)

Gx = 2.5 V, x = 1−4

−

1.5

mA

Output Impedance −

HI or LO State

Max Resistance to V (HI) or

GND (LO)

75

150

W

CC

Minimum V for Valid PWM Output Level

−

2.0

V

CC

PWM 4 2/3/4 Phase Detection

2 Phase Mode

Note Gate 4 tied to V

3.2

1.2

0

−

V

CC

4 Phase Mode

Note Gate Driver will pull to 1.5 V

Note Gate 4 tied to GND

2.8

0.8

3 Phase Mode

DIGITAL SOFT−START

Soft−Start Ramp Time

DAC = 0 to DAC = 1.1 V

1.0

−

1.3

ms

VR11 V

time

Not used in Legacy Startup

400

500

600

ms

boot

VID7/VR11/AMD/LEGACY INPUT

VID Threshold

450

−100

200

600

−

770

100

300

mV

nA

ns

VR11 Input Bias Current

Delay Before Latching VID Change (VID Deskewing)

(Note 3)

Measured from the Edge of the 1st

VID Change

−

AMD Upper Threshold

Note: When above this threshold

the controller will ramp directly to

−

4.8

V

VID without stopping at V

boot

AMD Lower Threshold

3.33

−

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11

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

ENABLE INPUT

Enable High Input Leakage Current

VR11.1 Threshold

Pull−up to 1.3 V

−

450

−

200

770

1.5

−

nA

mV

V

600

1.3

1.1

200

3.5

AMD Upper Threshold

AMD Lower Threshold

AMD Total Hysteresis

Enable Delay Time

0.9

−

V

Rising− Falling Threshold

−

mV

ms

Measure time from Enable

transitioning HI to when SS begins

−

CURRENT LIMIT

ILIM to VDRP Gain

0.97

−

1.00

0.25

0.333

0.5

0.1

−

1.03

−

V/V

mA

ILIM to VRDP Gain in PSI 4 Phase

ILIM to VDRP Gain in PSI 3 Phase

ILIM to VDRP Gain in PSI 2 Phase

ILIM Pin Input Bias Current

ILIM Pin Working Voltage Range

ILIM accuracy

−

1.0

2.0

25

0.1

−25

V

Measured with respect to the ILIM

setting

−

mV

Delay

−

120

ns

OVERVOLTAGE PROTECTION

VR11 Over Voltage Threshold

DAC+

160

DAC+

190

DAC+

210

mV

ns

AMD Over Voltage Threshold

DAC+

210

DAC+

235

DAC+

260

Delay

−

100

UNDERVOLTAGE PROTECTION

V

CC

V

CC

V

CC

UVLO Start Threshold

UVLO Stop Threshold

UVLO Hysteresis

4.0

3.8

4.25

4.05

200

4.5

4.3

−

V

150

mV

12VMON UVLO

12VMON (High Threshold)

12VMON (Low Threshold)

DAC OUTPUT

V

Valid

−

0.6

0.5

0.8

v

CC

0.4

−

CC

Output Source Current

Output Sink Current

VID INPUTS

V

= 1.6 V

= 0.3 V

0

−

5.0

16

mA

out

V

out

5.0

Threshold

450

−100

10

600

−

770

100

25

mV

nA

mA

ns

VR11 Mode Leakage

AMD Mode Input Bias Current

−

st

Delay before Latching VID Change

(VID Deskewing) (Note 3)

Measured from the edge of the 1

VID change

200

−

300

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12

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

DIGITAL DAC SLEW RATE LIMITER

Slew Rate Limit (Intel Mode)

Slew Rate Limit (AMD Mode)

Soft−Start Slew Rate

12.5

3.125

−

15

3.75

−

mV/ms

0.84

INPUT SUPPLY CURRENT

V

CC

Operating Current

EN Low, No PWM

20

−

42

mA

V

SUPPLY VOLTAGE

UVLO Start Threshold

UVLO Stop Threshold

UVLO Hysteresis

POR

CCP

V

8.2

7.2

1.0

3.0

9.0

8.0

−

9.5

8.5

−

V

CCP

Voltage at which the Driver OVP

becomes active

3.17

−

BOOST PIN UVLO

BOOST V UVLO Start Threshold

3.45

3.3

50

4.15

3.85

−

V

CC

BOOST V UVLO Stop Threshold

CC

BOOST V UVLO Hysteresis

200

mV

CC

BOOST SUPPLY CURRENT

I

Standby Current

EN = V , V

CCP

= 12 V

−

2.5

mA

VCCP_NORM

CC

Standby Current

IN = V , V

CCP CCP

0.25

BST1_SD

BST2_SD

BST3_SD

IN = GND, V

CCP

IN = GND, V

CCP

st

STARTUP HIGH SIDE SHORT TRIP (Active only during 1 power on)

V

swx

Output Overvoltage Trip Threshold at Startup

Power Startup time, V > 9 V

1.7

−

2.03

V

CC

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13

NCP5395T

ELECTRICAL CHARACTERISTICS

0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C

= 0.1 mF unless otherwise noted.

A

J

CC

VCC

Parameter

Test Conditions

Min

Typ

Max

Unit

HIGH SIDE DRIVER

W

R

Output Resistance, Sourcing

Output Resistance, Sinking

Transition Time

V

− V

= 12 V

−

1.8

1.0

25

20

15

5.0

2.5

−

H_TG

BST

SW

BST

SW

Tr

C

= 3 nF, V

− V

= 12 V

ns

DRVH

LOAD

BST

SW

Tf

Transition Time

= 3 nF, V

−

SW

Tpdh

Propagation Delay (Note 4)

Driving High, C

= 3 nF,

−

DRVH

LOAD

V

CCP

= 12 V

LOW SIDE DRIVER

R

Output Resistance, Sourcing

Output Resistance, Sinking

Transition Time

SW = GND

SW = V

−

1.6

1.0

20

15

5.0

2.5

−

W

H_BG

L_BG

CC

Tr

Tf

C

= 3 nF

ns

DRVL

LOAD

Transition Time

−

DRVL

Tpdh

Propagation Delay (Note 4)

Driving High, C

= 3 nF,

−

DRVL

LOAD

V

CCP

= 12 V

V

NCDT

Negative Current Detector Threshold (Note 3)

−

−1.0

−

mV

THERMAL SHUTDOWN

Tsd Thermal Shutdown (Note 3)

Tsdhys Thermal Shutdown Hysteresis (Note 3)

VRM 11 DAC

150

170

20

−

°C

−

System Voltage Accuracy

1.0 V < DAC < 1.6 V

0.8 V < DAC < 1.0 V

0.5 V < DAC < 0.8 V

−

0.5

5.0

8.0

%

mV

4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.

IN

tpdl

tf

DRVL

90%

2V

10%

tpdh

10%

th

DRVH

tpdl

tf

tr

DRVL

DRVH

90%

10%

2V

10%

tpdh

DRVH−SW

DRVL

SW

Figure 5. Timing Diagram

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14

NCP5395T

Table 2. VRM11 V_IDCODES

V

ID7

V

ID6

V

ID5

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

800 mV

400 mV

200 mV

100 mV

50 mV

25 mV

12.5 mV

6.25 mV

Voltage (V)

HEX

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

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15

NCP5395T

Table 2. VRM11 V_IDCODES

V

ID7

V

ID6

V

ID5

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

800 mV

400 mV

200 mV

100 mV

50 mV

25 mV

12.5 mV

6.25 mV

Voltage (V)

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

HEX

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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16

NCP5395T

Table 2. VRM11 V_IDCODES

V

ID7

V

ID6

V

ID5

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

800 mV

400 mV

200 mV

100 mV

50 mV

25 mV

12.5 mV

6.25 mV

Voltage (V)

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

HEX

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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17

NCP5395T

Table 2. VRM11 V_IDCODES

V

ID7

V

ID6

V

ID5

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

800 mV

400 mV

200 mV

100 mV

50 mV

25 mV

12.5 mV

6.25 mV

Voltage (V)

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

HEX

8A

8B

8C

8D

8E

8F

90

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

FE

FF

OFF

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18

NCP5395T

Parameter

Test Condition

MIN

TYP

MAX

Units

AMD DAC

System Voltage Accuracy

1.0 V < DAC < 1.55V

0.6 V ≤ DAC < 1.0V

0.375 V < DAC < 0.6V

−

0.5

1.0

−2.0, +3.0

%

5. NOTE: Internal DAC voltage is centered 19 mV below the listed voltage for VR11.1. No DAC offset is implemented for AMD operation.

DAC should be equal to the Nominal V shown in the table.

out

Table 3. AMD PROCESSOR 6−BIT V_IDCODE

(V ) Codes

ID

Nominal

V

ID0

V

Units

V

ID5

ID4

ID3

ID2

ID1

out

0

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

0.775

0.7625

0.7500

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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19

NCP5395T

Table 3. AMD PROCESSOR 6−BIT V_IDCODE

(V ) Codes

ID

Nominal

V

ID0

V

Units

V

ID5

ID4

ID3

ID2

ID1

out

1

0

1

0

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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20

NCP5395T

FUNCTIONAL DESCRIPTIONS

General

sums the remote output voltage with a 1.3 V reference. The

resulting voltage at the output of the remote sense amplifier is:

The NCP5395T dual edge modulated multiphase PWM

controller is specifically designed with the necessary

features for a high current CPU system. The IC consists of

the following blocks: Precision Flexible DAC, Differential

Remote Voltage Sense Amplifier, High Performance

Voltage Error Amplifier, Differential Current Feedback

Amplifiers, Precision Oscillator and Saw−tooth Generator,

and PWM Comparators with Hysteresis. The controller also

supports power saving mode as per Intel VR11.1 by

accurately monitoring the current and switching between

multi−phase and single phase operations as requested by the

microprocessor system. Protection features include:

Undervoltage Lockout, Soft−Start, Overcurrent Protection,

Overvoltage Protection, and Power Good Monitor.

V_Diffout+ V_out) 1.3 V * V_dac* V_outreturn

This signal then goes through a standard compensation

circuit and into the inverting input of the error amplifier. The

non−inverting input of the error amplifier is also connected

to the 1.3 V reference. The 1.3 V reference then is subtracted

out and the error signal at the comp pin of the error amplifier

is as normally expected:

V

_comp+ V_dac* V_out

The non−inverting input of the remote sense amplifier is

pulled low through a small current sink during a fault condition

to prevent accidental charging of the regulator output.

2/3/4 Phase Operation

Precision Programmable DAC

The part can be configured to 2−, 3−, or 4−phase mode. In

2− or 3−phase mode, the internal drivers will be used. In

4−phase mode, an external driver must be used to drive

phase 4. The NCP5359 driver is suggested to be used with

the controller. The input to G4 pin will decide which phase

mode the system is in operation. Please refer to the

Application Schematics for more information.

A precision flexible DAC is provided. The DAC will

conform to 2 different specifications: AMD or VR11.1. The

VID7/AMD pin is provided to determine which DAC

specification will be used and which soft−start mode the part

will use for power up. There are two soft−start modes. If

VID7/AMD is above it’s threshold the device will soft−start

and ramp directly to the DAC code present on the VID

inputs. The following truth table describes the functionality:

High Performance Voltage Error Amplifier

A high performance voltage error amplifier is provided.

The error amplifier’s inverting input is VFB and its output

is COMP. A standard type 3 compensation circuit is used

compensate the system. This involves a 3 pole, 2 zero

compensation network. The comp pin is pulled to ground

before soft−start for smooth start up.

VID7/AMD Pin

VID7

Not active

Active

Enable Pin

Mode

Soft−Start

Mode

Above AMD

Threshold

AMD

Thresholds

Ramp to

VID

Below AMD

Threshold

VR11.1

Thresholds

Ramp to

Vboot

Differential Current Sense

Four differential amplifiers are provided to sense the

output current of each phase. These current sense amplifiers

sense the current through the corresponding phase. A

voltage is generated across a current sense element such as

an inductor or sense resistor. The sense element should be

between 0.3 mW and 1.5 mW. It is possible to sense both

negative and positive going current. The information is used

to create the signal CSSUM and provide feedback for

current sharing.

VID Inputs

VID0−VID7 control the target regulation voltage during

normal operation. In AMD mode the VID capture is enabled

just before soft−start. In VR11 mode the VID capture is

enabled at the end of the V

is valid the DAC will track to it. If an invalid VID occurs it

waiting period. If the VID

BOOT

will be ignored for 10 ms before the controller shuts down.

Remote Sense Amplifier

A high performance differential amplifier is provided to

accurately sense the output voltage of the regulator. The

non−inverting input should be connected to the regulator’s

output voltage. The inverting input should be connected to

the return line of the regulator. Both connection points are

intended to be at a remote point so that the most accurate

reading of the output voltage can be obtained. The amplifier

is configured in a very unique way. First, the gain of the

amplifier is internally set to unity. Second, both the inverting

and non−inverting inputs of the amplifier are summing

nodes. The inverting input sums the output voltage return

voltage with the DAC voltage. The non−inverting input

Precision Oscillator

A programmable precision oscillator is provided. This

oscillator is programmed by the summed resistance of an

oscillator resistor and a current limit resistor. The output

voltage of this pin is 2V used as the reference for the current

limit. The oscillator frequency range is 125 KHz/phase to

1000 KHz/phase. The oscillator frequency is proportional to

the current drawn out of the OSC pin. Connecting a resistor

(R ) from OSC pin to the ground will set the target

osc

oscillator frequency. The relation between the R and F

osc

sw

can be described as below:

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21

NCP5395T

Over Voltage Protection

R

osc

= 15530 x F ^(-1.111)

sw

The output voltage is monitored at the input of the

differential amplifier. During normal operation, if the output

voltage exceeds the DAC voltage by 185 mV, or 285 mV if

in AMD mode, the VR_RDY flag will transition low the

high side gate drivers set to low, and the low side gate drivers

are all brought to high until the voltage falls below the OVP

threshold. If the over voltage trip 8 times the output voltage

will shut down. The OVP will not shut down the controller

if it occurs during soft−start. This is to allow the controller

to pull the output down to the DAC voltage and start up into

a pre−charged output.

PWM Comparators

Four PWM comparators are incorporated within the IC.

The non−inverting input of the comparators is connected to

the output of the error amplifier. The inverting input is

connected to a summed output of the phase current and the

oscillator ramp voltage with an offset. The output of the

comparator generates the PWM control signals.

During steady state operation, the duty cycle will center

on the valley of the saw−tooth waveform. During a transient

event, the controller will operate somewhat hysteretic, with

the duty cycle climbing along either the down ramp, up

ramp, or both.

V_CCPPower ON Reset OVP

The V

power on reset OVP feature is used to protect

CCP

the CPU during start up. When V

is higher than 3.2 V, the

Soft−Start

CCP

Soft−start is implemented internally. A digital counter

steps the DAC up from zero to the target voltage based on the

predetermined rate in the spec table. There are 2 possible

soft start modes: VR11 and AMD. AMD mode simply ramps

gate driver will monitor the switching node SW pin. If

SWNx pin higher than 1.9 V, the bottom gate will be forced

to high for discharge of the output capacitor. This works best

if the 5 volt standby is diode OR’ed into V

with the 12 V

CCP

V

core

from 0 V directly to the DAC setting. The VR11 mode

rail. The fault mode will be latched and the DRVON pin will

ramps DAC to 1.1 V, pauses for 500 ms, reads the DAC

be forced to low, unless V

is reduced below the UVLO

CCP

setting, then ramps to the final DAC setting.

threshold.

Power Saving Mode

Digital Slew Rate Limiter / Soft−Start Block

The controller is designed to allow power saving

operation to maintain a maximum efficiency. When a low

PSI signal from microcontroller is received, the controller

will keep one phase operating while shedding other phases.

The active one phase will operate in diode emulation mode,

minimizing power losses in light load. The device also

maintains an RPM operation in power saving mode. The

12VMON input will be used for two purposes: feedforward

input supply information for RPM mode and secondary

power input voltage UVLO. When the low PSI signal is

de−asserted, the dropped phases will be pulled back in to be

ready for heavy load and the device will be back to regular

PWM mode.

The slew rate limiter and the soft−start block are to be

implemented with a digital up/down counter controlled by

an oscillator that is synchronized to VID line changes.

During soft−start the DAC will ramp at the soft−start rate,

after soft start is complete the ramp rate will follow either the

Intel or the AMD slew rate depending on the mode.

Under Voltage Lockouts

An under voltage circuit senses the V input of the

CC

controller and the V

input of the driver. During power up

CCP

the input voltage to the controller is monitored. The PWM

outputs and the soft start circuit are disabled until the input

voltage exceeds the threshold voltage of the comparators.

Hysteresis is incorporated within the comparators.

Adaptive Non−overlap

The DRVON is held low until V

reaches the start

CCP

The non−overlap dead time control is used to avoid shoot

through damage to the power MOSFETs. When the PWM

signal pull high, DRVL will go low after a propagation

delay, the controller monitors the switching node (SWN) pin

voltage and the gate voltage of the MOSFET to know the

status of the MOSFET. When the low side MOSFET status

is off an internal timer will delay turn on of the high–side

MOSFET. When the PWM pull low, gate DRVH will go low

after the propagation delay (tpdDRVH). The time to turn off

the high side MOSFET is depending on the total gate charge

of the high−side MOSFET. A timer will be triggered once

the high side MOSFET is turn off to delay the turn on the

low−side MOSFET.

threshold during startup. If V

decreases below the stop

CCP

threshold, the output gate will be forced low unit input

voltage V rises above the startup threshold.

CCP

Over Current Latch

A programmable over current latch is incorporated within

the IC. The oscillator pin provides the reference voltage for

this pin. A resistor divider from the OSC pin generates the

ILIM voltage. The latch is set when the current information

on V

exceeds the programmed voltage plus a 1.3 V

droop

offset. DRVON is immediately set low. To recover the part

must be reset by the EN pin or by cycling V

.

CC

UVLO Monitor

Layout Guidelines

Layout is very important thing for design a DC−DC

If the output voltage falls greater than 300 mV below the

DAC voltage for more than 5 ms the UVLO comparator will

trip sending the VR_RDY signal low.

converter. Bootstrap capacitor and V capacitor are most

in

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22

NCP5395T

critical items, it should be placed as close as to the controller

MOSFET source pin. Also, the gate drive trace should be

considered. The gate drives has a high di/dt when switching,

therefore a minimized gate drives trace can reduce the di/dv,

raise and fall time for reduce the switching loss.

IC. Another item is using a GND plane. Ground plane can

provide a good return path for gate drives for reducing the

ground noise. Therefore GND pin should be directly

connected to the ground plane and close to the low−side

1.25 V

ENABLE

VID Captured

VID Valid

1.25 V

VID Not Valid

1 ms − 20 ms

Rise Time

5 V

12 V

1 ms − 20 ms

Rise Time

5 and 12 Good

VR11 Soft−start

Mode Latched

3.5 ms

Calibration Time

DRVON

Soft−start

Slew Rate

DAC Setting

1.10 V

Soft−start

Slew Rate

500 ms

VOUT/DAC

VR_RDY

500 ms

Figure 6. VR11.1 Start Up Timing Diagram

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23

NCP5395T

ENABLE

5 V

VID7/AMD

1 ms − 20 ms

Rise Time

5 V

1 ms − 20 ms

Rise Time

V

CC

12 V

9.5 V

V

CCP

V

CC

and V

CCP

AMD/Legacy Soft Start

Mode Latched

UVLO

3.5 ms

Calibration Time

DRVON

DAC Setting

SS Slew

Rate

VOUT/DAC

VR_RDY

500 ms

Figure 7. AMD / Legacy Start Up Timing Diagram

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NCP5395T

PACKAGE DIMENSIONS

QFN48, 7x7, 0.5P

CASE 485AJ−01

ISSUE O

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

D

A B

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO THE PLATED

TERMINAL AND IS MEASURED ABETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN 1

LOCATION

MILLIMETERS

E

DIM MIN

0.80

A1 0.00

MAX

1.00

0.05

A

2X

L

A3

b

0.20 REF

0.15

C

0.20

0.30

D

7.00 BSC

5.20

7.00 BSC

DETAIL A

OPTIONAL CONSTRUCTION

2X SCALE

D2 5.00

E

E2 5.00

2X

0.15

C

5.20

TOP VIEW

e

K

L

0.50 BSC

0.20

0.30

−−−

0.50

(A3)

0.05

0.08

A

C

SOLDERING FOOTPRINT*

A1

2X

5.20

NOTE 4

SEATING

PLANE

C

SIDE VIEW

D2

DETAIL A

1

K

13

25

12

2X

7.30

48X

0.63

E2

48X

0.30

1

36

0.50 PITCH

48

37

DIMENSIONS: MILLIMETERS

48X

b

0.10 C A B

e

48X

L

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

e/2

NOTE 3

C

0.05

BOTTOM VIEW

The products described herein (NCP5395T), may be covered by one or more of the following U.S. patents; US07057381.There may be other patents pending.

Devices are ESD sensitive, handling precaution recommended.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP5395T/D

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25


型号：	NCP5395T
厂家：	ONSEMI
描述：	2/3/4-Phase Controller with On Board Gate Drivers for CPU Applications 2/3/ 4相控制器与CPU应用在董事会栅极驱动器驱动器栅极栅极驱动控制器
文件：	总25页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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